JP2001035917A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

(57) Abstract: In a semiconductor device having a buried wiring, a diffusion barrier property of wiring constituent elements is improved and a wiring capacitance is reduced. SOLUTION: A second layer wiring 1 having a buried wiring structure is provided.
An insulating film 14 made of a silicon nitride film having a higher dielectric constant than a silicon oxide film is formed so as to surround the surface of the conductor film 13 of the 1L2 and the third layer wiring 11L3, and the insulating film 14 is separated for each wiring. Formed. This prevents the adjacent wirings from being connected by the insulating film 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a technique for manufacturing the same, and more particularly to a technique which is effective when applied to a method for forming a wiring constituting a semiconductor device.

[0002]

2. Description of the Related Art A wiring forming technique studied by the present inventors is a wiring forming technique called, for example, a damascene method or a dual-damascene method.
In the damascene method, after forming grooves for wiring formation in the insulating film,
A conductive film for forming a wiring is applied on the insulating film and in the groove for forming the wiring, and furthermore, for example, a chemical mechanical polishing method (CM) is used to leave the conductive film only in the groove for forming the wiring.
This is a method of forming a buried wiring in a wiring forming groove by polishing by P (Chemical Mechanical Polishing). In addition, the dual damascene method is a method to which the damascene method is applied, and after forming a groove for forming a wiring and a connection hole for making connection with a lower layer wiring and the like in an insulating film,
On the insulating film, a conductor film for forming a wiring is deposited in the groove and the connection hole for forming the wiring, and further polished by CMP so as to leave the conductor film only in the groove and the connection hole. Forming a buried wiring in the forming groove, and
This is a method of forming a plug in a connection hole. In any case, for example, copper (C
Although a low-resistance material such as u) is used, copper is easily diffused into the insulating film due to heat or an electric field. After the formation of the barrier conductor film, the conductor film for forming the wiring is generally formed.

[0003] Further, in one example of a technique for forming a buried wiring studied by the present inventors, in any of the above methods,
On the entire surface on the upper surface of the insulating film in which the trench for wiring formation is formed,
By depositing an insulating film for a barrier made of a high dielectric constant material such as a silicon nitride film so as to cover the upper surface of the embedded wiring, copper in the embedded wiring is removed from the upper surface side of the embedded wiring. Diffusion into the insulating film is prevented.

In one example of a dual damascene method studied by the present inventors, a second damascene method for forming the connection hole is provided on the upper surface of the first insulating film for forming the connection hole. A mask film such as, for example, a silicon nitride film is formed in advance below the second insulating film, and the mask film is used in the etching process for forming a wiring formation groove in the second insulating film. As an etching mask,
The connection hole is formed by etching away the first insulating film exposed from the mask film. The mask film is formed on the entire upper surface of the first insulating film.

The embedded wiring technology is described, for example, in Press Journal Inc., “Monthly Semiconductor World, December 1996”, pp. 129-134, and the current state and problems of dual damascene wiring are described in detail. I have.

[0006]

However, there is the following problem in the technique of forming a barrier insulating film or a mask film made of the above high dielectric constant material so as to overlap a plurality of wirings in a plane. The present inventor has found that.

That is, an electrical path (a relatively large parallel capacitance component) is formed between wirings in the same layer through a barrier insulating film or a mask film made of a high dielectric constant material, and wiring between the wiring layers in the same layer is formed. As a result of the increase in capacitance, signal delay occurs, which hinders improvement in the operation speed of the semiconductor device.

An object of the present invention is to provide a technique capable of improving the diffusion barrier property of wiring constituent elements and reducing the wiring capacity in a semiconductor device having a buried wiring.

Another object of the present invention is to provide a technique capable of improving the operation speed of a semiconductor device having embedded wiring.

Another object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device having embedded wiring.

A further object of the present invention is to provide a technique capable of improving the yield of semiconductor devices having embedded wiring.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, (1) The present invention provides a semiconductor device, comprising: a plurality of grooves or holes formed in a first insulating film; a copper-based conductor film formed in the plurality of grooves or holes; A plurality of second conductors made of a material having a higher dielectric constant than the film and covering the upper surface of each of the copper-based conductor films in the plurality of grooves or holes;
And the plurality of second insulating films are provided so as to be separated from each other.

(2) The present invention provides a semiconductor device, comprising: a plurality of trenches formed in a first insulating film; a copper-based conductor film formed in the plurality of trenches; A plurality of third insulating films formed of a high material, and provided on the bottom surface of each of the copper-based conductor films in the plurality of trenches, wherein the plurality of third insulating films are separated from each other It is provided in a state.

(3) The present invention provides a semiconductor device, comprising: a plurality of grooves or holes formed in a first insulating film; a copper-based conductor film formed in the plurality of grooves or holes; A plurality of second insulating films made of a material having a high dielectric constant, and covering the upper surfaces of the copper-based conductor films in the plurality of grooves or holes in a state of being separated from each other; and the first insulating film And a plurality of third insulating films provided separately from each other on the bottom surface of the copper-based conductor film in the plurality of grooves.

(4) The invention according to (1) or (3), wherein the upper surface of the copper-based conductor film is depressed from the upper surface of the first insulating film, and 2 is formed.

(5) In the present invention, in the above (2) or (4), the third insulating film is used as an etching mask for forming a connection hole in a lower insulating film.

(6) The present invention provides the above (1) to (5)
A fourth insulating film having a higher dielectric constant than the first insulating film is provided on a side surface of the copper-based conductor film.

(7) The present invention provides the above (1) to (6)
A conductive film for suppressing copper diffusion is provided in contact with the surface of the copper-based conductive film.

(8) The present invention provides a semiconductor device, comprising: a plurality of grooves or holes formed in a first insulating film; a copper-based conductor film formed in the plurality of grooves or holes; Covers at least a part of each surface of the copper-based conductor film, and
An insulating film for suppressing the diffusion of copper in the copper-based conductor film,
The insulating film for suppressing the diffusion of copper is formed for each copper-based conductor film and is separated from each other.

(9) The present invention provides (a) a step of forming a plurality of grooves or holes in a first insulating film, and (b) at least wiring in the plurality of grooves or holes in the first insulating film. And (c) embedding a conductive film in the plurality of grooves or holes.

(10) According to the present invention, (a) a third insulating film, which is an etching mask for forming a connection hole, is formed on an insulating film so as to be separated from each other for each wiring, and is then covered. And (b) forming a plurality of grooves or connection holes in the first insulating film by etching, and exposing the third insulating film using the third insulating film as an etching mask. Forming a connection hole in the insulating film by removing the insulating film by etching.

(11) The present invention provides (a) a step of forming a plurality of grooves or holes in a first insulating film, and (b) at least wiring in the plurality of grooves or holes in the first insulating film. Forming a fourth insulating film by nitriding a portion in contact with, a reducing process on a conductor portion exposed from the plurality of grooves or holes, and (d) a process of reducing the conductive portion exposed from the plurality of grooves or holes. Embedding a conductive film in the hole.

(12) In the present invention, in the above (11), the step (b) is a heat treatment or a plasma treatment in an atmosphere of a mixed gas of nitrogen, ammonia or nitrogen-hydrogen, and the step (c) is a hydrogen Alternatively, heat treatment or plasma treatment is performed in an ammonia gas atmosphere.

(13) The present invention relates to the above (1), (3), (4), (5),
(6) or (7), wherein the second insulating film is formed of Six _x
It is made of N _y or SiON.

[0027] (14) The present invention, in the above (8), inhibits the insulating film diffusion of the copper, Si _x N _y or SiON
It consists of

(15) The present invention relates to the above (8) and (14)
A conductive film for suppressing copper diffusion is provided in contact with the surface of the copper-based conductive film.

(16) The present invention relates to the above (2), (3), (4), (5),
(6), (7) or (10), wherein the third insulating film is
It is made of Si _x N _y or SiON.

(17) The present invention relates to the above (6), (7) or (11)
Wherein the fourth insulating film is made of SiN or SiON
It consists of

(18) The invention according to (7) or (15), wherein the conductive film for suppressing the diffusion of copper is made of TiN, TiO.
N, TiSiN, TaN, TaON, TaSiN, W
N, WSiN or WON.

(19) The present invention relates to the above (1) to (18)
The first insulating film is made of an SOG film, a SiOF film, a polyimide film or an insulating film containing carbon, and the second insulating film is made of a TEOS film.

(20) The present invention provides a semiconductor device, comprising: a plurality of grooves or holes formed in a first insulating film; a copper-based conductor film formed in the plurality of grooves or holes; An insulating film that covers at least a part of each surface of the copper-based conductor film in the above, and that suppresses copper diffusion of the copper-based conductor film, wherein the copper-based conductor insulating film suppresses copper diffusion. The films are separated from each other.

[0034]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted. In the present embodiment, a p-channel type MISFET (Me
tal Insulator Semiconductor Field Effect Transisto
r) is abbreviated as pMIS, and an n-channel MISFET is abbreviated as nMIS.

(Embodiment 1) In Embodiment 1, for example, a twin well type CMIS (Compliment
The case where the present invention is applied to a semiconductor device having an ary MIS) circuit will be described. FIG. 1 is a sectional view of a main part of the semiconductor device. The semiconductor substrate 1 is made of, for example, n-type Si single crystal, and has, for example, an n-well 2n and a p-well 2p on its main surface. For example, an n-type impurity such as phosphorus or As is introduced into the n-well 2n, and a p-type impurity such as boron is introduced into the p-well 2p. On the main surface of the semiconductor substrate 1, for example, a groove-shaped separation portion 3 is formed. That is, the separation unit 3 is a semiconductor substrate 1
An insulating film made of, for example, a silicon oxide film is buried and formed in a groove dug in the thickness direction. The separation unit 3 is a LOCOS (Local Oxidization of Silicon)
It may be formed of a field insulating film formed by a method or the like.

An nMISQn and a pMISQp are formed in the active region surrounded by the isolation portion 3. Gate insulating film 4 of nMISQn and pMISQp
Is made of, for example, a silicon oxide film and is formed by a thermal oxidation method or the like. By subjecting the gate insulating film 4 to a nitriding treatment, nitrogen may be segregated at the interface between the gate insulating film 4 and the semiconductor substrate 1. Also, nMISQn
The gate electrode 5 of pMISQp is made of, for example, a single film of low-resistance polysilicon. However, the gate electrode 5
For example, a so-called polycide structure in which a silicide film such as tungsten silicide is provided on a low-resistance polysilicon film may be used, or a barrier layer such as titanium nitride or tungsten nitride may be provided on the low-resistance polysilicon film. A so-called polymetal structure in which a metal film such as tungsten is provided. The nMISQn semiconductor region 6 is formed in a self-aligned manner with respect to the gate electrode 5 by introducing, for example, phosphorus or arsenic into the semiconductor substrate 1 using the gate electrode 5 as a mask by an ion implantation method or the like. The semiconductor region 7 of pMISQp is formed in a self-aligned manner with respect to the gate electrode 5 by introducing, for example, boron into the semiconductor substrate 1 by using the gate electrode 5 as a mask by an ion implantation method or the like.

On the main surface of the semiconductor substrate 1, an interlayer insulating film 8a made of, for example, a silicon oxide film is formed. In the interlayer insulating film 8a, for example, a plurality of connection holes 9a having a substantially circular shape in a plane are formed. A conductor film 10 such as tungsten is buried in each connection hole 9a.
Conductive film 10 is electrically connected to semiconductor regions 6 and 7. On the upper surface of the interlayer insulating film 8a, a first layer wiring 11L1
Are formed. The first layer wiring 11L1 is made of, for example, tungsten, and is patterned by ordinary photolithography and etching. The first layer wiring 11L is electrically connected to the conductor film 10.

On the main surface of the interlayer insulating film 8a, an interlayer insulating film 8b made of, for example, a silicon oxide film is deposited, thereby covering the upper surface and side surfaces of the first layer wiring 11L1. On this interlayer insulating film 8b, an interlayer insulating film 8c made of, for example, a silicon oxide film is deposited. A wiring groove 12a is formed in the interlayer insulating film 8c. The wiring groove 12a is formed, for example, in a flat band shape. A part of the interlayer insulating film 8b exposed from the bottom surface of the wiring groove 12a is provided with, for example, a substantially circular connection hole 9b in a plane. A conductive film 13 made of, for example, copper is buried in the wiring groove 12a and the connection hole 9b to form a second-layer wiring 11L2. Second layer wiring 1
1L2 is electrically connected to the first layer wiring 11L1 through the connection hole 9b. The conductor film 13 in the wiring groove 12a and the connection hole 9b is formed integrally. The surface (bottom, side, and top) of the conductor film 13 is covered with an insulating film 14 made of, for example, a silicon nitride film. This insulating film 14 is formed in a state of directly contacting the surface of the conductor film 13. That is, the surface of the conductor film 13 made of copper constituting the second-layer wiring 11L2 is
The insulating film 14 having a higher dielectric constant than b, 8c, and the like is covered in a contact state. When a substance having a high dielectric constant and a substance having a low dielectric constant are arranged in series, the electric field strength in the substance having a high dielectric constant decreases. Therefore, by forming the insulating film 14 having a high dielectric constant so as to be in contact with the surface of the conductor film 13 made of copper, the electric field intensity on the surface of the conductor film 13 can be weakened. It becomes possible. In addition, since the insulating film 14 is separated for each adjacent wiring, it is possible to prevent a large-capacity path from being formed between the adjacent wirings through the insulating film 14, so that the capacitance between the adjacent wirings can be reduced. Becomes Thus, the operation speed of the semiconductor device can be improved. Further, in the first embodiment, the upper surface of the second-layer wiring 11L2 is formed to be slightly lower than the upper surface of the interlayer insulating film 8c, and the recess formed by the cap insulating film 14 of the insulating film 14 is formed. The film 14c is formed. Thereby, the step due to the cap insulating film 14c can be eliminated and the flatness can be improved, so that the failure rate of the fine wiring due to the step can be reduced. Therefore, it is possible to improve the reliability and yield of the semiconductor device. The dielectric constant of the insulating film 14 is preferably, for example, larger than 5.

On the main surface of the interlayer insulating film 8c, an interlayer insulating film 8d made of, for example, a silicon oxide film is deposited, thereby covering the upper surface of the second layer wiring 11L2. On the interlayer insulating film 8d, an interlayer insulating film 8e made of, for example, a silicon oxide film is deposited. The third-layer wiring 11L3 is formed in the interlayer insulating film 8e.
The structures of the third-layer wiring 11L3 and the copper diffusion barrier are the same as those of the second-layer wiring 11L2. That is, the third layer wiring 11L3 is formed in the wiring groove 1 formed in the interlayer insulating film 8e.
The conductor film 13 is formed so as to be buried in the connection holes 9b and the connection holes 9c, and is electrically connected to the second-layer wiring 11L2 through the connection holes 9b. The surface of the conductor film 13 is covered with an insulating film 14 having a higher dielectric constant than the interlayer insulating films 8d and 8e.

Next, a method of manufacturing the semiconductor device according to the first embodiment will be described. Here, the second layer wiring 11L2 of FIG.
The third layer wiring 11L3 will be described.

FIG. 2 is a partially cutaway perspective view of the essential part during the manufacturing process of the semiconductor device. At this stage, the second layer wiring 1
Although 1L2 is formed, a wiring groove for forming a third-layer wiring is not formed.

First, an insulating film (third insulating film) 14a made of a material having a higher dielectric constant than the interlayer insulating film 8d, such as a silicon nitride film, is formed on the upper surface of the interlayer insulating film 8d by a CVD method or the like. . Subsequently, as shown in FIG. 3, the insulating film 14a is patterned by a photolithography technique and an etching technique. In the first embodiment, the insulating film 14a is a film having a function as an etching stopper as described later, but also has a function of suppressing copper diffusion. Therefore, the manufacturing process can be simplified as compared with the case where the films having the respective functions are separately formed. At this stage, the insulating film 14a is formed in a planar band shape so as to follow the planar shape of the wiring. That is, the insulating film 14a is separated for each wiring. This can prevent a large-capacity path from being formed between the adjacent wirings through the insulating film 14a, thereby reducing the capacitance between the adjacent wirings. However, the insulating film 14
The width a is formed to be wider than the wiring from the viewpoint of securing a margin for alignment with a wiring groove described later. An opening 15 having, for example, a substantially circular shape in a plane is formed in a part of the insulating film 14a in order to form a connection hole with the second layer wiring. Thereafter, as shown in FIG. 4, on the interlayer insulating film 8d,
For example, an interlayer insulating film 8e made of a silicon oxide film is formed by CVD.
It is formed by a method or the like. Thereby, the surface (the upper surface, the side surface, and the inside of the opening 15) of the insulating film 14a is covered.

Next, by performing an etching process using a normal photoresist film as a mask, as shown in FIG. 5, a wiring groove 12b is formed in the interlayer insulating film 8e. In the process of forming the wiring groove 12b, the silicon oxide film is more easily etched and removed than the silicon nitride film, so that the interlayer insulating film 8d exposed from the opening 15 is etched using the insulating film 14a as an etching mask. Remove. Thereby, the connection hole 9c is also formed. At this stage, since the cap insulating film 14c is left at the bottom of the connection hole 9c, the upper surface of the second layer wiring 11L2 is not exposed.
This can solve the problem that the upper portion of the conductor film 13 for buried wiring is shaved when the connection hole 9c is formed and the problem of contamination caused by the shaving. Therefore, the reliability and yield of the semiconductor device can be improved. continue,
As shown in FIG. 6, an insulating film 14b made of a material having a higher dielectric constant than the interlayer insulating films 8d and 8e, such as a silicon nitride film, is formed on the interlayer insulating film 8e, in the wiring groove 12b, and in the connection hole 9c. It is formed by a CVD method or the like. Wiring groove 12
At the bottom of b, the silicon nitride film becomes thicker than the other parts because it becomes an overlapped film of the insulating films 14a and 14b. Thereafter, the insulating film 14b is etched back by performing, for example, anisotropic dry etching, and the connection hole 9c is formed.
The insulating films 14b and 14c at the bottom of the step are removed. By this processing, as shown in FIG. 7, a part of the upper surface of the second layer wiring 11L2 is exposed from the bottom of the connection hole 9c.
An insulating film (fourth insulating film) 14b is left on the inner wall surfaces of the connection holes 9c and the connection holes 9c.

Next, as shown in FIG.
e, a conductor film 13 made of, for example, copper is formed in the wiring groove 12b and the connection hole 9c by sputtering, CVD (Chem).
The film is formed by the ical vapor deposition) method, the plating method, or a combination of these methods. Prior to this step, for example, TiN, TiON, TiSiN, Ta
N, TaON, TaSiN, WN, WSiN or WO
A conductor film serving as a copper diffusion barrier made of N is formed into an interlayer insulating film 8.
e, it may be formed in the wiring groove 12b and the connection hole 9c by the CVD method or the sputtering method. By providing such a barrier conductor film, it is possible to further improve the resistance to copper diffusion. In addition, it is possible to improve the adhesion when depositing copper. After the conductive film 13 is formed, the conductive film 1 is heated.
3 to allow the conductive film 13 to be connected to the connection hole 9c and the wiring groove 1
You may make it flow well in 2b. Thereafter, the conductive film 13 is etched back by a CMP method or the like, so that the conductive film 13 is left only in the wiring groove 12b and the connection hole 9c as shown in FIG. At this time, the conductive film 13
Conditions or post-processing conditions are set such that the upper surface of is slightly lower than the upper surface of the interlayer insulating film 8e. Further, the upper surface of the interlayer insulating film 8e is also ground so as to be flat.

Next, as shown in FIG. 10, an insulating film 14 for forming a cap insulating film made of a material having a higher dielectric constant than the interlayer insulating film 8e, such as a silicon nitride film, is formed on the interlayer insulating film 8e by CVD. After being deposited by a method or the like, the insulating film 14 is etched back by a CMP method or the like, so that a cap insulating film (second insulating film) 14c is formed only on the upper surface of the conductor film 13 as shown in FIG. . The cap insulating film 14c is buried in the depression, and is formed so that the upper surface thereof substantially coincides with the upper surface of the interlayer insulating film 8e. For this reason, flatness can be improved. In this manner, the third layer wiring 11L3 having the buried wiring structure is formed, and the insulating film 14 for preventing the diffusion of copper in the conductive film 13 is formed on the surface (bottom, side, and bottom) of the conductive film 13 of the third layer wiring 11L3. (Upper surface).

Thereafter, a semiconductor device having a multilayer embedded wiring structure is manufactured by repeating the same embedded wiring forming process.

(Embodiment 2) In Embodiment 2, an example of another method for forming a buried wiring will be described. Here, as in the first embodiment, the second layer wiring 11 shown in FIG.
The L2 and the third layer wiring 11L3 will be extracted and described.

FIG. 12 is a cross-sectional view of a principal part in a manufacturing step of a semiconductor device. Unlike the first embodiment, the cap insulating film 14c in the second-layer wiring 11L2 is formed by patterning using ordinary photolithography and etching techniques.

First, an interlayer insulating film 8f made of, for example, a silicon oxide film is formed on the interlayer insulating film 8d by a CVD method or the like. Thus, the cap insulating film 14c is covered with the interlayer insulating film 8f. Subsequently, an insulating film 16 made of, for example, a silicon nitride film or the like is pattern-formed on the interlayer insulating film 8f. The insulating film 16 is a film serving as a mask when forming a wiring groove, and an opening 16a having the same shape as the wiring is formed in the wiring groove forming region. Since the insulating film 16 is removed later, it is not necessary to form the insulating film 16 so as to be separated for each wiring.

Next, as shown in FIG. 13, a photoresist film 17 is patterned on the interlayer insulating film 8f.
The photoresist film 17 is a film serving as a mask when forming a connection hole. In the connection hole formation region, for example, an opening 17a having a substantially circular shape in a plane is formed. Subsequently, by performing an etching process on the interlayer insulating film 8f using the photoresist film 17 as an etching mask, as shown in FIG.
A connection hole 9c is formed. At this time, the second oxide layer 11L is etched by performing the etching process under the condition that the silicon oxide film is more easily etched and removed than the silicon nitride film.
The cap insulating film 14c on the upper surface of the substrate 2 functions as an etching stopper. Therefore, at this processing stage, the cap insulating film 14c is left at the bottom of the connection hole 9c,
The upper surface of the second layer wiring 11L2 is covered. By adopting such etching conditions, it is possible to solve the problem that the conductive film 13 of the second-layer wiring 11L2 is shaved at the time of forming the connection hole 9c and the problem of contamination due to it. Therefore, the reliability and yield of the semiconductor device can be improved. Then, after removing the photoresist film 17 (see FIG. 13), the interlayer insulating film 8f is removed by etching using the insulating film 16 as an etching mask, thereby forming a wiring groove 12b as shown in FIG.
At this time, the depth of the wiring groove 12b is controlled by, for example, time. Also at this stage, the cap insulating film 14c remains at the bottom of the connection hole 9c. After forming the wiring groove 12b, the connection hole 9c can be formed by using the photoresist film as an etching mask.

Next, the insulating film 16 is selectively removed by etching. That is, the etching process is performed under the condition that the silicon nitride film is more easily removed by etching than the silicon oxide film. At this time, the cap insulating film 14c left at the bottom of the connection hole 9c is also made of a silicon nitride film, and thus is simultaneously removed by etching. As a result, as shown in FIG. 16, the upper surface of the conductor film 13 of the second layer wiring 11L2 is also exposed from the bottom of the connection hole 9c. The insulating film 16 may be removed at the time of a CMP process for a conductor film made of copper, which will be described later. Subsequently, the interlayer insulating film 8f is subjected to plasma processing in, for example, a nitrogen or ammonia atmosphere.
The surface of the wiring groove 12b and the inner wall surface of the connection hole 9c are modified to form a nitride film (fourth insulating film) as shown in FIG.
18 are formed. Nitride layer 18 is, for example SiN, Si _x
It is made of _Ny (Si ₃ N ₄ or the like), SiON or the like, and is made of a material having a higher dielectric constant than the interlayer insulating film 8f or the like. That is,
This nitride film 18 is a film that functions as a barrier that suppresses copper diffusion. When a barrier insulating film or a conductor film is deposited by a CVD method, it is necessary to increase the plane dimensions of the wiring groove and the connection hole by the thickness. However, Embodiment 2
According to the method of (1), the portion of the interlayer insulating film 8f exposed on the inner wall surface of the wiring groove or the connection hole is modified to form the barrier nitride film 18, so that the planarization of the wiring groove 12b or the connection hole 9c is performed. It is not necessary to allow for the thickness of the film 18. Therefore, high-density wiring design is possible. Further, since the cross-sectional area of the conductor film made of copper can be increased, the wiring resistance can be reduced.
Further, since the amount of nitrogen in SiON in the nitride film 18 is small, the dielectric constant can be reduced. Therefore, the capacitance between wirings can be reduced.

By the way, at the time of such a surface modification treatment, the exposed surface of the conductor film 13 made of copper (here, the conductor film 13 of the second-layer wiring 11L2) is also nitrided to form a copper nitride film depending on the treatment conditions. . Therefore, in the second embodiment, after the surface modification treatment, the copper nitride film is removed by performing a plasma treatment or a heat treatment in, for example, a hydrogen atmosphere.

Next, a conductor film made of copper is formed in the same manner as in the first embodiment. In the second embodiment, a method for forming a conductive film by, for example, a plating method will be described. First, as shown in FIG. 18, the wiring groove 1 is formed on the interlayer insulating film 8f.
A thin conductor film 13a made of, for example, copper is formed in 2b and the connection hole 9c by a sputtering method or the like. This conductor film 13a becomes a seed film at the time of plating. Note that, similarly to the first embodiment, prior to the formation process of the conductor film 13a, for example, TiN, TiON, TiS
iN, TaN, TaON, TaSiN, WN, WSiN
Alternatively, a conductor film serving as a copper diffusion barrier made of WON is C
It may be formed by a VD method or a sputtering method. Subsequently, after the seed conductor film 13a is formed, as shown in FIG. 19, the seed conductor film 13a is formed on the seed conductor film 13a.
The conductor film 13b made of copper is formed by, for example, an electrolytic plating method. In forming the conductive film 13b, an electroless plating method may be used. In that case, the seed conductive film 13a may not be formed. Conductive film 13
After the film formation process b, heat treatment may be performed to flow the conductor films 13a and 13b so that the conductor films 13a and 13b can flow well into the connection holes 9c and the wiring grooves 12b. Thereafter, the conductive film 13b is etched back by a CMP method or the like, so that the conductive films 13a and 13b are left only in the wiring groove 12b and the connection hole 9c as shown in FIG. In the second embodiment, the CMP conditions are set such that the upper surfaces of the conductor films 13a and 13b substantially coincide with the upper surface of the interlayer insulating film 8e.

Next, an insulating film for forming a cap insulating film made of a material having a higher dielectric constant than the interlayer insulating film 8f, such as a silicon nitride film, is deposited on the interlayer insulating film 8f by a CVD method or the like. By patterning the insulating film by a usual photolithography technique and etching technique, as shown in FIG. 21, a cap insulating film 14c is formed so as to cover the upper surface of the conductor film 13b. Thus, the third layer wiring 11L3 having the buried wiring structure is formed, and the nitride film 18 for preventing the diffusion of copper in the conductor films 13a and 13b is brought into contact with the surface of the conductor film 13 of the third layer wiring 11L3. It is formed in a state where it is formed. The insulating film 18 and the cap insulating film 14c are separated for each wiring. Therefore,
Also in the second embodiment, the same effect as in the first embodiment can be obtained.

Thereafter, a semiconductor device having a multilayer embedded wiring structure is manufactured by repeating the same embedded wiring forming process.

(Embodiment 3) In Embodiment 3, a barrier material for suppressing the diffusion of copper is different from Embodiments 1 and 2. FIG. 22 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step thereof. A connection hole 9 is formed in the interlayer insulating film 8d.
c is perforated, and a conductor film 19 is buried therein. The conductor film 19 is made of, for example, tungsten or the like, and is electrically connected to the second-layer wiring 11L2.
A wiring groove 12b is formed in the interlayer insulating film 8e, and the upper surface of the conductor film 19 is exposed from the bottom surface.

First, on the interlayer insulating film 8e and the wiring groove 12
b, a barrier film 20 made of, for example, tantalum (Ta)
Is formed by a sputtering method, a CVD method, or the like. Subsequently, by performing heat treatment in an oxygen atmosphere, of the barrier film 20, it is partially oxidized tantalum to oxidize the lower part of the barrier of the grain boundary or the like (Ta _x O _y). Thereby, of the barrier films (first films) 20,
Portions having low barrier properties such as grain boundaries are formed by interlayer insulating films 8d and 8e.
It becomes a substance having a higher dielectric constant. That is, the barrier film 2
0 has the function of suppressing the diffusion of copper. The conductivity of the barrier film 20 is ensured. Thereafter, as shown in FIG. 23, a barrier conductor film 21 is formed on the barrier film 20 by a sputtering method, a CVD method, or the like. The conductor film 21 is made of, for example, a film containing TaN, TaON, or both, and has a function of suppressing copper diffusion.
At this time, since the lower barrier film 20 made of tantalum oxide is formed, the conductive film 2 is also formed in the wiring groove 12b.
1 does not impair the adherence. That is, tantalum nitride having a high copper diffusion barrier property and a high adhesion to copper can be satisfactorily applied. In addition, by forming a tantalum nitride film after the tantalum film formation and further performing a heat treatment in an oxygen atmosphere, oxygen reaches the tantalum through a portion where the tantalum nitride is not formed well or through a grain boundary portion, and the tantalum nitride film is formed. By partially oxidizing, tantalum oxide may be partially formed. Thereby, the same effect as described above can be obtained.

Next, as in the first and second embodiments,
After forming the conductor film 13 made of copper, the conductor films 13 and 21 are formed.
By etching back the barrier film 20 by a CMP method or the like, as shown in FIG. 24, the conductor films 13, 21 and the barrier film 20 are left only in the wiring groove 12b, and the third layer wiring 11L3 having the buried wiring structure is formed. To form continue,
The cap insulating film 14c is formed by ordinary photolithography and etching so as to cover only the upper surfaces of the conductor films 13 in the first and second embodiments.

According to the third embodiment, the same effects as those of the first and second embodiments can be obtained. In particular, in the third embodiment, the conductive film 13 is surrounded by the conductive film 21 for the barrier, and the periphery thereof is surrounded by the barrier film 20 having a high dielectric constant and the cap insulating film 14c, so that the copper diffusion barrier property is improved. Can be improved, and
The capacitance between adjacent wirings can be reduced.

(Embodiment 4) In Embodiment 4, as shown in FIG. 26, in a state in which the bottom and side surfaces of the conductor film 13 constituting the buried wiring are in contact with the wiring groove 12b, for example, TiN, TiON, TiSiN, TaN, T
A conductive film 22 serving as a copper diffusion barrier made of aON, TaSiN, WN, WSiN or WON is formed. Then, a cap insulating film 14c is formed so as to cover the upper surface of the conductor film 13. Cap insulating film 1
4c is pattern-formed by ordinary photolithography and etching techniques,
As in the case of No. 3, it is formed separately for each individual wiring. However, similarly to the first embodiment, the cap insulating film 14c may be embedded. Embodiment 4
Also, in the same manner as in the first to third embodiments, the copper diffusion barrier property can be improved, and the capacitance between adjacent wirings can be reduced. FIG. 26 shows only the second layer wiring and the third layer wiring of FIG.

(Fifth Embodiment) In a fifth embodiment, as shown in FIG.
The conductor film 22 is formed in c in a state of being in contact with the surface (excluding the upper surface) of the conductor film 13 constituting the embedded wiring. Further, a cap insulating film 14c is formed on the conductor film 13 as in the second embodiment. However, as in the first embodiment, the cap insulating film 14c
May be embedded. Then, the wiring groove 12a,
An insulating film 14a functioning as a mask when forming the connection hole 9c is formed on the bottom surface of the
Are formed. The cap insulating film 14c and the insulating film 14a are separated for each individual wiring as in the first embodiment. Therefore, also in the fifth embodiment, as in the first to third embodiments, the diffusion barrier property of copper can be improved, and the capacitance between adjacent wirings can be reduced. FIG. 27 shows only the second layer wiring and the third layer wiring of FIG.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. Needless to say,

For example, in the first to fifth embodiments,
Although the case where the barrier insulating film is a silicon nitride film has been described, the present invention is not limited to this.
An iON film can also be used. In this case, the dielectric constant can be reduced because the amount of N in the barrier insulating film is small.

In the first to fifth embodiments,
The case where the interlayer insulating film is made of a silicon oxide film and the insulating film for the barrier is made of a silicon nitride film has been described. However, the present invention is not limited to this. For example, the interlayer insulating film may be made of organic SOG (Spin On Glass). A film, a SiOF film, a polyimide film, or an insulating film containing carbon may be used, and the insulating film for the barrier may be a film having a relatively high dielectric constant such as a TEOS (Tetraethoxysilane) film.

In the above description, the invention made mainly by the present inventor is described in the CMI which is the application field in which the invention is based.
The case where the present invention is applied to a semiconductor device having an S circuit and a method of manufacturing the same has been described. However, the present invention is not limited to this. For example, a dynamic random access memory (DRAM)
y), SRAM (Static Random Access Memory) or flash memory (EEPROM; Electric Erasabl)
e) A semiconductor device having a memory circuit such as Programmable Read Only Memory), a semiconductor device having a logic circuit such as a microprocessor, or a hybrid semiconductor device having the memory circuit and the logic circuit provided on the same semiconductor substrate. Also applicable to

[0066]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1). According to the present invention, in a semiconductor device in which a wiring is provided in a groove or a hole formed in an insulating film, it is possible to improve a diffusion barrier property of a wiring constituent element and to reduce a wiring capacitance. This makes it possible to improve the reliability and yield of the semiconductor device. Further, the operation speed of the semiconductor device can be improved.

(2). According to the present invention, the upper surface of the copper-based conductor film is depressed from the upper surface of the first insulating film, and the second insulating film is formed in the depressed portion.
It is possible to improve the flatness of a wiring layer included in the semiconductor device. Therefore, the yield and reliability of the semiconductor device can be improved.

(3). According to the present invention, the step of forming a plurality of grooves or holes in the first insulating film and the step of forming at least a portion of the plurality of grooves or holes in the first insulating film where the wiring is in contact with the first insulating film By having a step of modifying the insulating film to have a higher dielectric constant and a step of burying a conductive film in the plurality of grooves or holes, the insulating film having a high dielectric constant for suppressing the diffusion of copper is The hole can be formed without increasing the cross-sectional dimension of the hole. For this reason, the wiring density can be improved. In addition, it is possible to increase the cross-sectional area of the copper-based conductor film and reduce the wiring resistance.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of a semiconductor device according to an embodiment of the present invention;

FIG. 2 is a partially cutaway perspective view of the semiconductor device of FIG. 1 during a wiring forming step;

FIG. 3 is a partially cutaway perspective view of the main part of the semiconductor device of FIG. 1 during a wiring forming step following FIG. 2;

FIG. 4 is a perspective view of a partly broken main part of the semiconductor device of FIG. 1 during a wiring forming step following FIG. 3;

FIG. 5 is a partially broken perspective view of the main part of the semiconductor device of FIG. 1 during a wiring forming step following FIG. 4;

6 is a fragmentary perspective view of the main part of the semiconductor device shown in FIG. 1 during a wiring forming step following that of FIG. 5;

7 is a partially broken perspective view of the main part of the semiconductor device of FIG. 1 during a wiring forming step following FIG. 6;

8 is a perspective view of a partly broken main part of the semiconductor device of FIG. 1 in a wiring forming step following FIG. 7;

9 is a perspective view of a partly broken main part of the semiconductor device of FIG. 1 during a wiring forming step following FIG. 8;

FIG. 10 is a perspective view of a partly broken main part of the semiconductor device of FIG. 1 during a wiring forming step following FIG. 9;

11 is a perspective view of a partly broken main part of the semiconductor device of FIG. 1 in a wiring forming step following FIG. 10;

FIG. 12 is a fragmentary cross-sectional view of a semiconductor device according to another embodiment of the present invention during a wiring forming step;

13 is a fragmentary cross-sectional view of the semiconductor device during a wiring formation step following that of FIG. 12;

14 is a fragmentary cross-sectional view of the semiconductor device during a wiring formation step following that of FIG. 13;

15 is a fragmentary cross-sectional view of the semiconductor device during a wiring formation step following that of FIG. 14;

16 is a fragmentary cross-sectional view of the semiconductor device during a wiring formation step following that of FIG. 15;

17 is a fragmentary cross-sectional view of the semiconductor device during a wiring formation step following that of FIG. 16;

18 is a fragmentary cross-sectional view of the semiconductor device during a wiring formation step following that of FIG. 17;

19 is a fragmentary cross-sectional view of the semiconductor device during a wiring formation step following that of FIG. 18;

20 is a fragmentary cross-sectional view of the semiconductor device during a wiring formation step following that of FIG. 19;

21 is a fragmentary cross-sectional view of the semiconductor device during a wiring formation step following that of FIG. 20;

FIG. 22 is a fragmentary cross-sectional view of a semiconductor device according to still another embodiment of the present invention during a wiring forming step;

23 is a fragmentary cross-sectional view of the semiconductor device during a wiring formation step following that of FIG. 22;

24 is a fragmentary cross-sectional view of the semiconductor device during a wiring formation step following that of FIG. 23;

FIG. 25 is an essential part cross sectional view of the semiconductor device during a wiring forming step following FIG. 24;

FIG. 26 is a fragmentary cross-sectional view of a semiconductor device according to another embodiment of the present invention;

FIG. 27 is a fragmentary cross-sectional view of a semiconductor device according to another embodiment of the present invention;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2p p well 2n n well 3 Separation part 4 Gate insulating film 5 Gate electrode 6 Semiconductor region 7 Semiconductor region 8a-8f Interlayer insulating film 9a-9c Connection hole 10 Conductor film 11L1 First layer wiring 11L2 Second layer wiring 11L3 Third layer wiring 12a, 12b Wiring groove 13 Conductive film 13a, 13b Conductive film 14 Insulating film 14a Insulating film (third insulating film) 14b Insulating film (fourth insulating film) 14c Cap insulating film (second insulating film) 15 opening 16 insulating film 16a opening 17 photoresist film 17 opening 18 nitride film (fourth insulating film) 19 conductive film 20 barrier film (first film) 21 conductive film 22 conductive film Qp pMIS Qn nMIS

 ──────────────────────────────────────────────────の Continuing from the front page (72) Inventor Junji Noguchi 3-16-1, Shinmachi, Ome-shi, Tokyo 3 Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Hideki Yamaguchi 6-16, Shinmachi, Ome-shi, Tokyo No. 3 Inside the Hitachi, Ltd. Device Development Center (72) Inventor Nobuo Owada 3-16, Shinmachi, Ome-shi, Tokyo 3 Inside the Hitachi, Ltd. Device Development Center F-term (reference) 5F033 HH11 HH19 HH21 HH27 HH28 HH30 HH32 HH33 HH34 HH35 JJ01 JJ11 JJ19 JJ27 JJ28 JJ30 JJ32 JJ33 JJ34 JJ35 KK01 KK11 KK19 KK27 KK28 KK30 KK32 KK33 KK34 KK35 MM02 MM12 MM13 NN06 NN07 PP06 PP15 PP27 PP28 Q16 Q31 Q28 Q16 Q29 Q16 Q28 XX10 XX25 XX27 XX28

Claims (10)

[Claims] 1. A plurality of grooves or holes formed in a first insulating film, a copper-based conductor film formed in the plurality of grooves or holes, and a dielectric constant higher than that of the first insulating film. A plurality of second insulating films made of a material and covering respective upper surfaces of the copper-based conductor films in the plurality of grooves or holes, wherein the plurality of second insulating films are separated from each other. A semiconductor device characterized by being provided by: A plurality of grooves formed in the first insulating film;
A copper-based conductor film formed in the plurality of grooves, a material having a higher dielectric constant than the first insulating film, and provided on each bottom surface of the copper-based conductor film in the plurality of grooves; A plurality of third insulating films, wherein the plurality of third insulating films are provided separately from each other. 3. A plurality of grooves or holes formed in the first insulating film, a copper-based conductor film formed in the plurality of grooves or holes, and a dielectric constant higher than that of the first insulating film. A plurality of second layers made of a material and covering the upper surfaces of the copper-based conductor films in the plurality of grooves or holes in a state of being separated from each other;
And a plurality of second insulating films made of a material having a higher dielectric constant than the first insulating film, and provided on the bottom surfaces of the copper-based conductor films in the plurality of grooves in a state of being separated from each other. 3. A semiconductor device, comprising: 4. The semiconductor device according to claim 1, wherein an upper surface of the copper-based conductor film is depressed from an upper surface of the first insulating film, and the second insulating film is formed in the depressed portion. A semiconductor device characterized by forming: 5. The semiconductor device according to claim 2, wherein the third insulating film is used as an etching mask when a connection hole is formed in a lower insulating film. 6. The semiconductor device according to claim 1, wherein said first conductive film is formed on a side surface of said copper-based conductor film.
And a fourth insulating film having a higher dielectric constant than the insulating film. 7. A plurality of grooves or holes formed in the first insulating film, a copper-based conductor film formed in the plurality of grooves or holes, and a dielectric constant higher than that of the first insulating film. A first material made of a material and surrounding at least a part of the copper-based conductor film;
Wherein the first film is provided so as to be separated from the first film. 8. The semiconductor device according to claim 1, further comprising: a conductor film that is in contact with a surface of said copper-based conductor film and suppresses copper diffusion. . 9. A step of: (a) forming a plurality of grooves or holes in a first insulating film; and (b) forming at least a portion of the plurality of grooves or holes in the first insulating film which contacts a wiring. A semiconductor device having a step of reforming into a second insulating film having a higher dielectric constant than the first insulating film; and (c) a step of burying a conductive film in the plurality of grooves or holes. Production method. 10. A third insulating film serving as an etching mask for forming a connection hole is formed on an insulating film so as to be separated from each other for each wiring, and then a first insulating film is formed so as to cover the third insulating film. Forming a film, and (b) forming a plurality of grooves or connection holes in the first insulating film by etching, and etching the insulating film exposed therefrom using the third insulating film as an etching mask. Forming a connection hole in the insulating film by removing the insulating film.