JP2001028036A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP2001028036A JP2001028036A JP20008799A JP20008799A JP2001028036A JP 2001028036 A JP2001028036 A JP 2001028036A JP 20008799 A JP20008799 A JP 20008799A JP 20008799 A JP20008799 A JP 20008799A JP 2001028036 A JP2001028036 A JP 2001028036A
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- Prior art keywords
- antenna
- semiconductor device
- substrate
- semiconductor element
- antenna pattern
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Abstract
(57)【要約】
【課題】 通信用のアンテナを備えた小型の半導体装置
を提供し、種々用途に使用可能とする。
【解決手段】 信号授受用のアンテナが半導体素子４０
に電気的に接続されたアンテナ付きの半導体装置であっ
て、前記半導体素子４０の電極端子形成面の平面領域と
略同寸法に形成された絶縁基板２１に前記アンテナとし
て作用するアンテナパターン２６が形成されたアンテナ
基板２８が、前記アンテナパターン２６と半導体素子４
０とが電気的に接続されて半導体素子４０に一体に接着
されている。
(57) [Problem] To provide a small-sized semiconductor device provided with a communication antenna and to be usable for various uses. SOLUTION: An antenna for signal transmission and reception is a semiconductor element 40.
A semiconductor device having an antenna electrically connected to the semiconductor element 40, wherein an antenna pattern 26 acting as the antenna is formed on an insulating substrate 21 having substantially the same size as a plane area of an electrode terminal forming surface of the semiconductor element 40. The antenna substrate 28 that has been mounted is connected to the antenna pattern 26 and the semiconductor element 4.
0 are electrically connected to and integrally bonded to the semiconductor element 40.
Description
【０００１】[0001]
【発明の属する技術分野】本発明は非接触式ＩＣカード
等に使用する半導体装置及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used for a non-contact type IC card and the like and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】非接触式ＩＣカードは図１３に示すよう
に、コイル状に形成したアンテナ１０と、アンテナ１０
に接続された信号授受用の半導体素子１２をカード状に
形成したフィルム１４で挟み、薄いカード状に形成した
ものである。アンテナ１０は、電気的絶縁性を有するフ
ィルムの表面に形成された導体層をエッチングして所定
のコイル状に形成される。半導体素子１２とアンテナ１
０とはワイヤボンディングによって電気的に接続され
る。2. Description of the Related Art As shown in FIG. 13, a non-contact type IC card includes an antenna 10 formed in a coil shape,
The semiconductor device 12 for signal transmission / reception connected to the device is sandwiched by a film 14 formed in a card shape to form a thin card shape. The antenna 10 is formed in a predetermined coil shape by etching a conductor layer formed on a surface of an electrically insulating film. Semiconductor element 12 and antenna 1
0 is electrically connected by wire bonding.
【０００３】[0003]
【発明が解決しようとする課題】従来の非接触式ＩＣカ
ードでは、図１３に示すように、アンテナ１０をカード
の外周近傍に沿って配置している。これは、アンテナ１
０の通信特性がアンテナのループが囲む面積とアンテナ
の巻き線数によって決まることから、アンテナ１０が囲
む面積を広く確保できるようにするためである。カード
形のＩＣカードは携帯等の利便性を考慮してその形状が
考慮されている。しかし、上記のようにアンテナ１０を
配置する広い面積を確保することは、電子機器の小型化
を制約し、他用途への応用を制約することになる。In a conventional non-contact type IC card, as shown in FIG. 13, an antenna 10 is arranged along the vicinity of the outer periphery of the card. This is antenna 1
Since the communication characteristic of 0 is determined by the area surrounded by the loop of the antenna and the number of windings of the antenna, the area surrounded by the antenna 10 can be ensured to be large. The shape of a card-type IC card is considered in consideration of the convenience of carrying and the like. However, securing a large area for disposing the antenna 10 as described above restricts miniaturization of the electronic device and restricts application to other uses.
【０００４】本発明はこのような通信機能を備えた電子
部品の特性に鑑み、これら通信機能を備えた電子部品の
小型化を容易に図ることができ、種々の電子機器への応
用利用が容易に可能な半導体装置及びその好適な製造方
法を提供することを目的とする。[0004] In view of the characteristics of such electronic parts having a communication function, the present invention can easily reduce the size of electronic parts having these communication functions, and can be easily applied to various electronic devices. It is an object of the present invention to provide a semiconductor device which is capable of being manufactured and a preferable manufacturing method thereof.
【０００５】[0005]
【課題を解決するための手段】上記目的を達成するた
め、本発明は次の構成を備える。すなわち、信号授受用
のアンテナが半導体素子に電気的に接続されたアンテナ
付きの半導体装置であって、前記半導体素子の電極端子
形成面の平面領域と略同寸法に形成された絶縁基板に前
記アンテナとして作用するアンテナパターンが形成され
たアンテナ基板が、前記アンテナパターンと半導体素子
とが電気的に接続されて半導体素子に一体に接着されて
いることを特徴とする。また、前記アンテナ基板が、半
導体素子の電極端子形成面の平面領域内に接着されてい
ることを特徴とする。また、前記半導体素子が、アンテ
ナ基板の基板面内に接着されていることを特徴とする。
また、前記アンテナ基板が、アンテナパターンが形成さ
れた面とは反対面を半導体素子の電極端子が形成された
面に接着され、前記電極端子とアンテナパターンとが、
絶縁基板に設けられたビアを介して電気的に接続されて
いることを特徴とする。また、前記アンテナ基板が、ア
ンテナパターンが形成された面とは反対面を半導体素子
の電極端子が形成された面に接着され、前記電極端子と
アンテナパターンとが、ワイヤボンディングにより電気
的に接続されていることを特徴とする。また、半導体素
子が、電極端子を形成した面とは反対面をアンテナ基板
に接着され、前記電極端子と前記アンテナ基板に形成さ
れたアンテナパターンとがワイヤボンディングにより電
気的に接続されていることを特徴とする。また、前記ア
ンテナ基板が、前記アンテナパターンが絶縁層を介して
複数層に積層して形成され、各層に形成されたアンテナ
パターンが電気的に直列に接続された多層のアンテナ基
板であることを特徴とする。また、アンテナパターン
が、隣接する層間のビアを介して電気的に接続されてい
ることを特徴とする。また、アンテナパターンが、ワイ
ヤボンディングにより隣接する層間が電気的に接続され
ていることを特徴とする。To achieve the above object, the present invention comprises the following arrangement. That is, a semiconductor device with an antenna in which a signal transmitting / receiving antenna is electrically connected to a semiconductor element, wherein the antenna is provided on an insulating substrate formed to have substantially the same size as a plane area of an electrode terminal forming surface of the semiconductor element. An antenna substrate on which an antenna pattern acting as a substrate is formed is characterized in that the antenna pattern and the semiconductor element are electrically connected and integrally bonded to the semiconductor element. Further, the antenna substrate is bonded to a plane area of the electrode terminal forming surface of the semiconductor element. Further, the semiconductor element is bonded to a surface of the antenna substrate.
Also, the antenna substrate has a surface opposite to the surface on which the antenna pattern is formed adhered to the surface on which the electrode terminals of the semiconductor element are formed, and the electrode terminal and the antenna pattern are
It is characterized by being electrically connected via a via provided in the insulating substrate. Also, the antenna substrate has a surface opposite to the surface on which the antenna pattern is formed adhered to the surface of the semiconductor element on which the electrode terminals are formed, and the electrode terminals and the antenna pattern are electrically connected by wire bonding. It is characterized by having. Also, the semiconductor element is bonded to the antenna substrate on the surface opposite to the surface on which the electrode terminals are formed, and the electrode terminals and the antenna pattern formed on the antenna substrate are electrically connected by wire bonding. Features. Further, the antenna substrate is a multilayer antenna substrate in which the antenna pattern is formed by laminating a plurality of layers via an insulating layer, and the antenna patterns formed on each layer are electrically connected in series. And Further, the antenna pattern is electrically connected via a via between adjacent layers. Further, the antenna pattern is characterized in that adjacent layers are electrically connected by wire bonding.
【０００６】また、信号授受用のアンテナが半導体素子
に電気的に接続されたアンテナ付きの半導体装置であっ
て、前記半導体素子の電極端子形成面内に、前記アンテ
ナとして、電極端子形成面を被覆する電気的絶縁層を介
して形成した導体層がエッチングされてアンテナパター
ンが形成され、該アンテナパターンと電極端子とが電気
的絶縁層に形成したビアを介して電気的に接続されてい
ることを特徴とする。また、前記アンテナパターンが、
電気的絶縁層を介して複数層に形成されていることを特
徴とする。Also, a semiconductor device with an antenna in which an antenna for signal transmission / reception is electrically connected to a semiconductor element, wherein an electrode terminal forming surface of the semiconductor element covers the electrode terminal forming surface as the antenna. The antenna pattern is formed by etching the conductor layer formed through the electrically insulating layer, and the antenna pattern and the electrode terminals are electrically connected to each other through the via formed in the electrically insulating layer. Features. Also, the antenna pattern is
It is characterized by being formed in a plurality of layers with an electrical insulating layer interposed therebetween.
【０００７】また、半導体装置の製造方法において、半
導体素子が所定配置で形成された半導体ウエハに、電気
的絶縁性を有する絶縁基板に前記各半導体素子の配置に
合わせて信号授受用のアンテナパターンが形成されたア
ンテナ基板を、各半導体素子の電極端子と前記各アンテ
ナパターンとを電気的に接続して接着した後、前記アン
テナ基板が接着された半導体ウエハを半導体装置単位の
個片に切断することを特徴とする。また、半導体素子が
所定配置で形成された半導体ウエハの電極端子形成面に
電気的絶縁層を形成し、該電気的絶縁層に前記電極端子
が底面に露出するビア穴を形成し、該ビア穴の内面およ
び前記電気的絶縁層の表面に導体層を形成し、該導体層
により前記半導体素子の配置位置に合わせてアンテナパ
ターンを形成するとともに、該アンテナパターンと前記
電極端子とを前記ビア穴に形成されたビアを介して電気
的に接続し、該アンテナパターンが形成された半導体ウ
エハを半導体装置単位の個片に切断することを特徴とす
る。In the method of manufacturing a semiconductor device, an antenna pattern for signal transmission / reception is provided on an insulating substrate having electrical insulation on a semiconductor wafer having semiconductor elements formed in a predetermined arrangement according to the arrangement of the semiconductor elements. After the formed antenna substrate is electrically connected and bonded to the electrode terminals of each semiconductor element and each of the antenna patterns, the semiconductor wafer to which the antenna substrate is bonded is cut into individual semiconductor device units. It is characterized by. Further, an electric insulating layer is formed on the electrode terminal forming surface of the semiconductor wafer on which the semiconductor elements are formed in a predetermined arrangement, and a via hole in which the electrode terminal is exposed on the bottom surface is formed in the electric insulating layer. A conductor layer is formed on the inner surface and the surface of the electrical insulating layer, and an antenna pattern is formed by the conductor layer in accordance with an arrangement position of the semiconductor element, and the antenna pattern and the electrode terminal are formed in the via hole. Electrical connection is made through the formed vias, and the semiconductor wafer on which the antenna pattern is formed is cut into individual pieces of semiconductor device units.
【０００８】[0008]
【発明の実施の形態】以下、本発明の好適な実施形態を
添付図面に基づいて詳細に説明する。図１〜３は本発明
に係る半導体装置を製造する際に使用するアンテナ基板
の製造方法を示す。図１(a) は電気的絶縁性を有する絶
縁基板２１の片面に金属箔２２が被着された金属箔付き
絶縁基板２０の断面図である。実施形態では金属箔付き
絶縁基板２０の基材としてポリイミドフィルムを使用し
ている。ポリイミドフィルムの一方の面に銅箔が被着さ
れ、他方の面にポリイミドをＢステージ化した接着層２
４が形成されている。Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. 1 to 3 show a method of manufacturing an antenna substrate used when manufacturing a semiconductor device according to the present invention. FIG. 1A is a cross-sectional view of an insulating substrate 20 with a metal foil in which a metal foil 22 is adhered to one surface of an electrically insulating insulating substrate 21. In the embodiment, a polyimide film is used as a base material of the insulating substrate 20 with a metal foil. An adhesive layer 2 in which a copper foil is adhered to one surface of a polyimide film and B-staged polyimide is applied to the other surface.
4 are formed.
【０００９】図１(b) は金属箔２２をエッチングしてア
ンテナパターン２６を形成した状態を示す。図２はアン
テナパターン２６の平面図である。この実施形態では絶
縁基板２１の表面の全領域を利用してコイル状に形成し
ている。絶縁基板２１の表面に形成するアンテナパター
ン２６の巻き数、パターン幅、パターン配置等は任意に
選択することが可能である。金属箔２２をエッチングし
てアンテナパターン２６を形成する方法は、通常のフォ
トリソグラフィー法によればよい。金属箔２２の表面に
感光性レジストを塗布し、露光・現像してアンテナパタ
ーン２６として残す部位を被覆したレジストパターンを
形成し、レジストパターンから露出している金属箔２２
の部位をエッチングして除去することによりアンテナパ
ターン２６が得られる。FIG. 1B shows a state in which the metal foil 22 is etched to form an antenna pattern 26. FIG. 2 is a plan view of the antenna pattern 26. In this embodiment, the insulating substrate 21 is formed in a coil shape using the entire area of the surface. The number of turns, the pattern width, the pattern arrangement, and the like of the antenna pattern 26 formed on the surface of the insulating substrate 21 can be arbitrarily selected. The method of forming the antenna pattern 26 by etching the metal foil 22 may be a usual photolithography method. A photosensitive resist is applied to the surface of the metal foil 22, and is exposed and developed to form a resist pattern covering a portion to be left as the antenna pattern 26, and the metal foil 22 exposed from the resist pattern is formed.
The antenna pattern 26 is obtained by etching and removing the portion.
【００１０】本発明に係る半導体装置は半導体素子の素
子面と略同サイズにアンテナ基板を形成し、半導体素子
の素子面にアンテナ基板を接合して半導体装置とする。
このように、半導体素子と略同サイズにアンテナ基板を
形成する場合は、アンテナパターン２６をきわめて微細
に形成することが求められる。エッチング法によりアン
テナパターン２６を形成する方法は、アンテナパターン
２６をきわめて微細に形成でき、任意のパターンに容易
に形成することができるという利点がある。In a semiconductor device according to the present invention, an antenna substrate is formed with substantially the same size as an element surface of a semiconductor element, and the antenna substrate is joined to the element surface of the semiconductor element to obtain a semiconductor device.
As described above, when the antenna substrate is formed to have substantially the same size as the semiconductor element, it is required to form the antenna pattern 26 very finely. The method of forming the antenna pattern 26 by the etching method has an advantage that the antenna pattern 26 can be formed extremely finely and can be easily formed into an arbitrary pattern.
【００１１】図１(c) はアンテナパターン２６を形成し
た基板にビア３０を形成したアンテナ基板２８を示す。
ビア３０は層間でアンテナパターン２６を電気的に接続
してアンテナ基板２８を積層するため、また、アンテナ
基板２８を半導体素子に接合した際に半導体素子と電気
的に接続する際の接続端子として形成する。ビア３０
は、パンチング加工によりアンテナ基板２８を貫通する
ビア穴を形成し、貫通穴に導体ぺースト等の導体材を充
填することによって形成できる。また、アンテナパター
ン２６を設けた面と反対側の面からレーザ光を照射して
底面にアンテナパターン２６が露出するビア穴を形成
し、ビア穴に導体材を充填することによってビア３０を
形成することができる。図３にビア３０を形成したアン
テナ基板２８の平面図を示す。ビア３０はコイル状に形
成したアンテナパターン２６の両端に各々形成されてい
る。FIG. 1C shows an antenna substrate 28 in which a via 30 is formed on the substrate on which the antenna pattern 26 is formed.
The via 30 is formed as a connection terminal for electrically connecting the antenna pattern 26 between the layers and stacking the antenna substrate 28, and for connecting electrically to the semiconductor element when the antenna substrate 28 is joined to the semiconductor element. I do. Via 30
Can be formed by forming a via hole penetrating the antenna substrate 28 by punching and filling the through hole with a conductor material such as a conductor paste. Further, a via hole is formed on the bottom surface by irradiating a laser beam from a surface opposite to the surface on which the antenna pattern 26 is provided, and the via hole 30 is formed by filling the via hole with a conductive material. be able to. FIG. 3 shows a plan view of the antenna substrate 28 in which the via 30 is formed. The vias 30 are respectively formed at both ends of the antenna pattern 26 formed in a coil shape.
【００１２】なお、ビア３０を形成する他の方法とし
て、図１(a) に示す金属箔２２が被着された金属箔付き
絶縁基板２０にパンチング加工あるいはレーザ加工を施
してビア３０を形成することも可能である（図１
(d)）。この場合、ビア３０を形成した後、金属箔２２
をエッチングしてアンテナパターン２６を形成する方法
と、金属箔付き絶縁基板２０にビア穴を形成し、金属箔
２２をエッチングしてアンテナパターン２６を形成した
後、ビア穴に導体材を充填してビア３０を形成しアンテ
ナ基板２８を得る方法がある。また、ビア３０を形成す
る他の方法として、接着層２４および絶縁基板２１にビ
ア穴を形成し、金属箔２２に通電して電解めっきを施す
ことによりビア穴を導体材で充填する方法もある。As another method of forming the via 30, a via 30 is formed by performing punching or laser processing on the insulating substrate 20 with the metal foil on which the metal foil 22 shown in FIG. It is also possible (Fig. 1
(d)). In this case, after forming the via 30, the metal foil 22
A via hole is formed in the insulating substrate 20 with metal foil, the metal foil 22 is etched to form the antenna pattern 26, and then the via hole is filled with a conductive material. There is a method of forming the via 30 and obtaining the antenna substrate 28. Further, as another method of forming the via 30, there is a method of forming a via hole in the adhesive layer 24 and the insulating substrate 21, and energizing the metal foil 22 to perform electrolytic plating to fill the via hole with a conductive material. .
【００１３】本発明に係る半導体装置は、上記のアンテ
ナパターン２６が形成されたアンテナ基板２８を半導体
素子に接合し、アンテナパターン２６と半導体素子とを
電気的に接続して得られる。半導体素子としてＩＣカー
ド等の信号授受用の機能を有する素子を使用すれば、半
導体装置内にアンテナを備えた非接触式の通信用の半導
体装置として得られる。A semiconductor device according to the present invention is obtained by bonding an antenna substrate 28 on which the above-described antenna pattern 26 is formed to a semiconductor element and electrically connecting the antenna pattern 26 and the semiconductor element. If an element having a function of transmitting and receiving signals, such as an IC card, is used as the semiconductor element, it can be obtained as a non-contact communication semiconductor device having an antenna in the semiconductor device.
【００１４】図４は半導体素子４０にアンテナ基板２８
を接合して一体に形成した半導体装置の実施形態の斜視
図、図５は断面図を示す。図５に示すように、アンテナ
基板２８の裏面、すなわちアンテナパターン２６を形成
した面とは反対面を半導体素子４０の素子面に接着して
半導体素子４０とアンテナパターン２６とを電気的に接
続する。そのため、半導体素子４０の電極端子４２とア
ンテナ基板２８のビア３０とを位置合わせし、異方導電
性接着フィルム４３を使用してアンテナ基板２８と半導
体素子４０とを接着する。異方導電性接着フィルム４３
を使用することにより、電極端子４２とビア３０とが電
気的に接続されてアンテナ基板２８と半導体素子４０と
が一体に接着される。FIG. 4 shows that the semiconductor substrate 40 is mounted on the antenna substrate 28.
And FIG. 5 is a cross-sectional view of an embodiment of the semiconductor device in which the semiconductor device is integrally formed by bonding. As shown in FIG. 5, the back surface of the antenna substrate 28, that is, the surface opposite to the surface on which the antenna pattern 26 is formed is adhered to the element surface of the semiconductor element 40 to electrically connect the semiconductor element 40 and the antenna pattern 26. . Therefore, the electrode terminals 42 of the semiconductor element 40 are aligned with the vias 30 of the antenna substrate 28, and the antenna substrate 28 and the semiconductor element 40 are bonded using the anisotropic conductive adhesive film 43. Anisotropic conductive adhesive film 43
Is used, the electrode terminals 42 and the vias 30 are electrically connected, and the antenna substrate 28 and the semiconductor element 40 are integrally bonded.
【００１５】なお、異方導電性接着フィルム４３を使用
するかわりに、バンプを介して電極端子４２とビア３０
とを接続し、アンテナ基板２８と半導体素子４０との隙
間に接着剤を充填して一体に接着することも可能であ
る。このように異方導電性接着フィルムあるいは異方導
電性接着剤を使用してアンテナ基板２８を半導体素子４
０に接着する場合は、図１に示すアンテナ基板２８にお
いて接着層２４を形成する必要はない。また、図１に示
すアンテナ基板２８において、接着性を有する導電性樹
脂（導電性接着剤）を使用してビア３０を形成した場合
は、接着層２４を半導体素子４０の能動面に接着し、ビ
ア３０を電極端子４２に接着することにより図４、５に
示す半導体装置を形成することができる。It is to be noted that, instead of using the anisotropic conductive adhesive film 43, the electrode terminals 42 and the vias 30 are connected via bumps.
Can be connected, and a gap between the antenna substrate 28 and the semiconductor element 40 can be filled with an adhesive and adhered integrally. As described above, the antenna substrate 28 is attached to the semiconductor element 4 using the anisotropic conductive adhesive film or the anisotropic conductive adhesive.
In the case of bonding to zero, it is not necessary to form the bonding layer 24 on the antenna substrate 28 shown in FIG. In the case where the via 30 is formed using a conductive resin having a bonding property (conductive adhesive) on the antenna substrate 28 shown in FIG. 1, the bonding layer 24 is bonded to the active surface of the semiconductor element 40, By bonding the via 30 to the electrode terminal 42, the semiconductor device shown in FIGS.
【００１６】図６は半導体装置の他の製造方法として、
アンテナパターン２６を多層化した多層のアンテナ基板
３２を半導体素子４０に接合して半導体装置を製造する
方法を示す。図６(a) は所定のアンテナパターン２６を
形成したアンテナ基板２８を複数枚積層する状態を示
す。各々のアンテナ基板２８には接着層２４が形成され
ているから、アンテナ基板２８を位置合わせして加熱・
加圧することにより、アンテナパターン２６が多層に形
成された多層のアンテナ基板３２が得られる。各々のア
ンテナ基板３２は、積層して一体化した際に層間でアン
テナパターン２６が電気的に接続されるようアンテナパ
ターン２６およびビア３０が設計されている。FIG. 6 shows another method of manufacturing a semiconductor device.
A method for manufacturing a semiconductor device by bonding a multilayer antenna substrate 32 having a multilayer antenna pattern 26 to a semiconductor element 40 will be described. FIG. 6A shows a state in which a plurality of antenna substrates 28 on which a predetermined antenna pattern 26 is formed are stacked. Since the adhesive layer 24 is formed on each antenna substrate 28, the antenna substrate 28 is positioned and
By pressing, a multilayer antenna substrate 32 in which the antenna pattern 26 is formed in multiple layers is obtained. The antenna patterns 26 and the vias 30 are designed such that the antenna patterns 26 are electrically connected between the layers when the respective antenna substrates 32 are stacked and integrated.
【００１７】図７にアンテナ基板２８に設けるアンテナ
パターン２６の例を示す。２６ａ、２６ｂ、２６ｃが各
々１層目、２層目、３層目のアンテナ基板２８に設ける
アンテナパターン２６である。ビア３０はこれらのアン
テナパターン２６ａ、２６ｂ、２６ｃが一筆書き状に接
続されるように配置する。そして、アンテナの両端がビ
ア３０を介して半導体素子４０に電気的に接続される。FIG. 7 shows an example of the antenna pattern 26 provided on the antenna substrate 28. Reference numerals 26a, 26b, and 26c denote antenna patterns 26 provided on the first, second, and third antenna substrates 28, respectively. The via 30 is arranged so that these antenna patterns 26a, 26b, 26c are connected in a one-stroke form. Then, both ends of the antenna are electrically connected to the semiconductor element 40 via the vias 30.
【００１８】図６(b) は多層のアンテナ基板３２を半導
体素子４０に位置合わせして接合する状態を示す。アン
テナ基板３２と半導体素子４０とは、異方導電性接着フ
ィルムあるいはバンプ等を介してビア３０と電極端子４
２とを電気的に接続して一体に接合される。多層のアン
テナ基板３２を半導体素子４０に接合した形態は図４に
示す半導体装置と同様である。半導体素子４０の一方の
面に多層のアンテナ基板３２が接合され、チップサイズ
の半導体装置に形成される。FIG. 6B shows a state in which the multilayer antenna substrate 32 is positioned and joined to the semiconductor element 40. The antenna substrate 32 and the semiconductor element 40 are connected to the via 30 and the electrode terminal 4 via an anisotropic conductive adhesive film or a bump.
2 and are electrically connected to each other. The configuration in which the multilayer antenna substrate 32 is joined to the semiconductor element 40 is the same as the semiconductor device shown in FIG. The multilayer antenna substrate 32 is joined to one surface of the semiconductor element 40 to form a chip-sized semiconductor device.
【００１９】前述したように、アンテナパターン２６は
任意のパターンで、かつきわめて微細なパターンに形成
可能であるから、チップサイズの半導体装置に組み込む
場合のように、アンテナパターン２６を配置する領域が
微小な領域に限られている場合であっても、所要のアン
テナ特性を備えた半導体装置として提供することが可能
である。また、アンテナ基板２８を積層した多層のアン
テナ基板３２の積層数を適宜選択したり、アンテナのパ
ターンを適宜設計したりすることによってさらに製品に
応じた特性を備えた半導体装置として提供することが可
能となる。As described above, since the antenna pattern 26 can be formed in an arbitrary pattern and in an extremely fine pattern, the area in which the antenna pattern 26 is arranged is very small as in the case where the antenna pattern 26 is incorporated in a chip-size semiconductor device. Even when the semiconductor device is limited to a specific area, the semiconductor device can be provided as a semiconductor device having required antenna characteristics. In addition, by appropriately selecting the number of layers of the multilayer antenna substrate 32 in which the antenna substrates 28 are stacked, or by appropriately designing the antenna pattern, the semiconductor device can be provided as a semiconductor device having characteristics further depending on the product. Becomes
【００２０】上記実施形態では、単一の半導体素子４０
に個片に形成した単層のアンテナ基板２８あるいは多層
のアンテナ基板３２を接合して半導体装置とした。この
ように、単体の半導体素子４０とアンテナ基板２８、３
２を取り扱うかわりに、信号授受に使用する半導体素子
を形成した半導体ウエハにあらかじめ所定のアンテナパ
ターンを形成した大判のアンテナ基板を接合し、半導体
ウエハとアンテナ基板の接合体をスライシングして個片
の半導体装置を得ることも可能である。In the above embodiment, the single semiconductor element 40
Then, a single-layer antenna substrate 28 or a multi-layer antenna substrate 32 formed in individual pieces was joined to obtain a semiconductor device. Thus, the single semiconductor element 40 and the antenna substrates 28, 3
Instead of handling 2, a large-sized antenna substrate on which a predetermined antenna pattern is formed in advance is bonded to a semiconductor wafer on which semiconductor elements used for signal transmission / reception are formed, and a bonded body of the semiconductor wafer and the antenna substrate is sliced to form individual pieces. It is also possible to obtain a semiconductor device.
【００２１】半導体ウエハに接合する大判のアンテナ基
板には半導体ウエハに形成された個々の半導体素子に位
置合わせしてアンテナパターンを形成し、半導体ウエハ
にアンテナ基板を接合した際に個々の半導体素子とアン
テナパターンとが電気的に接続して接合されるようにす
る。大判のアンテナ基板であれば、エッチングによって
アンテナパターン２６を形成するといった一連の作業を
効率的に行うことができるという利点があり、スライシ
ングによって図４に示したと同様なチップサイズの半導
体装置を容易に得ることができる。An antenna pattern is formed on a large-sized antenna substrate to be bonded to a semiconductor wafer by aligning the individual semiconductor elements formed on the semiconductor wafer with each other. The antenna pattern is electrically connected and joined. A large-sized antenna substrate has an advantage that a series of operations such as forming the antenna pattern 26 by etching can be efficiently performed, and a semiconductor device having a chip size similar to that shown in FIG. Obtainable.
【００２２】このように、半導体素子とアンテナ基板と
を組み合わせて半導体素子と略同サイズの半導体装置を
形成する方法としては、単一の半導体素子とアンテナ基
板とを組み合わせる他に、以下のような方法が可能であ
る。すなわち、上記例のように半導体ウエハに大判のア
ンテナ基板を組み合わせて製造する方法、半導体ウエハ
に個片に形成したアンテナ基板を組み合わせて製造する
方法、個片の半導体素子に大判のアンテナ基板を組み合
わせて製造する方法等である。As described above, as a method of forming a semiconductor device having substantially the same size as a semiconductor element by combining a semiconductor element and an antenna substrate, in addition to combining a single semiconductor element and an antenna substrate, the following method is used. A method is possible. That is, a method of manufacturing a semiconductor wafer by combining a large-sized antenna substrate with a semiconductor wafer, a method of manufacturing a semiconductor wafer by combining an antenna substrate formed in a piece, and a method of combining a large-sized antenna board with a piece of semiconductor element. And the like.
【００２３】図８は半導体装置のさらに他の製造方法を
示す。本実施形態では絶縁基板２１の両面にアンテナパ
ターン２６を形成したアンテナ基板２８を積層してアン
テナパターン２６を多層化したこと、および半導体素子
４０とアンテナパターン２６とをワイヤボンディングに
よって電気的に接続したことを特徴とする。図８(a) は
絶縁基板２１の両面にアンテナパターン２６を形成した
アンテナ基板２８を接着剤シート３４により接着して多
層のアンテナ基板を形成する方法を示す。アンテナ基板
２８は、絶縁基板２１の両面に金属箔を被着した金属箔
付き絶縁基板の両面の金属箔をエッチングして絶縁基板
２１の両面にアンテナパターン２６を形成し、絶縁基板
２１をパンチングしてビア穴を形成し、ビア穴に導体材
を充填することによって形成できる。FIG. 8 shows still another method of manufacturing a semiconductor device. In the present embodiment, the antenna substrate 28 having the antenna pattern 26 formed on both surfaces of the insulating substrate 21 is laminated to form the antenna pattern 26 in a multilayer structure, and the semiconductor element 40 and the antenna pattern 26 are electrically connected by wire bonding. It is characterized by the following. FIG. 8A shows a method of forming a multilayer antenna substrate by bonding an antenna substrate 28 having an antenna pattern 26 formed on both surfaces of an insulating substrate 21 with an adhesive sheet 34. The antenna substrate 28 is formed by etching the metal foil on both sides of an insulating substrate with a metal foil in which metal foil is applied on both surfaces of the insulating substrate 21 to form antenna patterns 26 on both surfaces of the insulating substrate 21 and punching the insulating substrate 21. The via hole is formed by filling the via hole with a conductive material.
【００２４】アンテナ基板２８を接合する接着剤シート
３４には隣接するアンテナパターン２６を電気的に接続
する部位に貫通孔が設けられ、該貫通孔に導電性接着剤
３６が充填されている。接着剤シート３４を介してアン
テナ基板２８を接合することにより、隣接層のアンテナ
パターン２６は接着剤シート３４を形成した部位のみで
電気的に接続されてアンテナ基板２８が一体に接合され
る。もちろん、接着剤シート３４を使用するかわりに、
前述したと同様に異方導電性接着フィルムを利用してア
ンテナ基板２８、２８を電気的に接続して接合すること
も可能である。The adhesive sheet 34 for bonding the antenna substrate 28 is provided with a through hole at a portion where the adjacent antenna patterns 26 are electrically connected, and the through hole is filled with a conductive adhesive 36. By bonding the antenna substrate 28 via the adhesive sheet 34, the antenna patterns 26 in the adjacent layers are electrically connected only at the portion where the adhesive sheet 34 is formed, and the antenna substrate 28 is integrally bonded. Of course, instead of using the adhesive sheet 34,
As described above, it is also possible to electrically connect and join the antenna substrates 28, 28 using an anisotropic conductive adhesive film.
【００２５】図８(b) はアンテナ基板２８を積層して多
層に形成したアンテナ基板３２に半導体素子４０を搭載
し、半導体素子４０とアンテナ基板３２のアンテナパタ
ーン２６とを電気的に接続した状態である。半導体素子
４０とアンテナパターン２６とはワイヤボンディングに
よって接続する。４４はボンディングワイヤ、３８はア
ンテナ基板２８に設けたボンディングパッドである。ワ
イヤボンディングした後、ボンディングワイヤ４４、ボ
ンディングワイヤ４４とアンテナ基板２８とのボンディ
ング部、半導体素子４０の外面等をポッティング等によ
って封止する。FIG. 8B shows a state in which the semiconductor element 40 is mounted on the antenna substrate 32 formed by laminating the antenna substrates 28 and the semiconductor element 40 is electrically connected to the antenna pattern 26 of the antenna substrate 32. It is. The semiconductor element 40 and the antenna pattern 26 are connected by wire bonding. 44 is a bonding wire, and 38 is a bonding pad provided on the antenna substrate 28. After the wire bonding, the bonding wire 44, the bonding portion between the bonding wire 44 and the antenna substrate 28, the outer surface of the semiconductor element 40, and the like are sealed by potting or the like.
【００２６】図９は図８に示す半導体装置で各層に設け
たアンテナパターン２６のパターンと、半導体素子４０
とアンテナパターン２６とを電気的に接続する構成を示
す。アンテナパターン２６は前述した実施形態と同様に
一筆書き状に接続されている。実施形態では多層のアン
テナ基板３２の外形寸法よりも半導体素子４０が小型に
形成され、半導体素子４０とアンテナパターン２６に設
けられたボンディングパッド３８とをワイヤボンディン
グしている。ワイヤボンディングした後、ボンディング
ワイヤ４４を含めて半導体素子４０の外面に樹脂をポッ
ティングして封止することも可能である。FIG. 9 shows a pattern of the antenna pattern 26 provided on each layer in the semiconductor device shown in FIG.
A configuration for electrically connecting the antenna pattern 26 to the antenna pattern 26 is shown. The antenna pattern 26 is connected in a one-stroke form as in the above-described embodiment. In the embodiment, the semiconductor element 40 is formed smaller than the outer dimensions of the multilayer antenna substrate 32, and the semiconductor element 40 and the bonding pads 38 provided on the antenna pattern 26 are wire-bonded. After the wire bonding, it is also possible to seal the outer surface of the semiconductor element 40 including the bonding wire 44 by potting a resin.
【００２７】半導体素子４０とアンテナ基板３２とを同
一の大きさとした場合には、図６に示す方法と同様に、
異方導電性接着剤あるいはバンプ等により半導体素子４
０とアンテナパターン２６とを電気的に接続して一体に
接合することもできる。また、実施形態ではアンテナ基
板３２で半導体素子４０を搭載する面にはボンディング
パッド３８のみを設けているが、半導体素子４０を搭載
した面にもアンテナパターン２６を引き回し、アンテナ
パターン２６の端部にボンディングパッド３８を設ける
ようにしてもよい。その場合は、積層するアンテナ基板
２８、２８がともに両面にアンテナパターン２６が形成
されたものとなる。When the semiconductor element 40 and the antenna substrate 32 have the same size, similar to the method shown in FIG.
The semiconductor element 4 is formed by using an anisotropic conductive adhesive or a bump.
0 and the antenna pattern 26 can also be electrically connected and integrally joined. In the embodiment, only the bonding pad 38 is provided on the surface of the antenna substrate 32 on which the semiconductor element 40 is mounted. However, the antenna pattern 26 is also routed on the surface on which the semiconductor element 40 is mounted, and A bonding pad 38 may be provided. In this case, the antenna patterns 28 are formed on both sides of the antenna substrates 28 to be stacked.
【００２８】図１０は半導体装置のさらに他の実施形態
を示す。本実施形態の半導体装置は、半導体素子４０の
電極端子形成面にアンテナパターン２６を形成した面を
向けてアンテナ基板２８を接合したことを特徴とする。
半導体素子４０とアンテナ基板２８とをたとえば、異方
導電性接着フィルムを用いて接合することにより、電極
端子４２とアンテナパターン２６の端子２７のみとを電
気的に接続して接合することができる。この半導体装置
の場合はアンテナ基板２８に電気的接続用のビア３０を
形成する必要がないという利点がある。FIG. 10 shows still another embodiment of the semiconductor device. The semiconductor device according to the present embodiment is characterized in that an antenna substrate 28 is joined to an electrode terminal forming surface of a semiconductor element 40 with the surface on which the antenna pattern 26 is formed facing.
By joining the semiconductor element 40 and the antenna substrate 28 using, for example, an anisotropic conductive adhesive film, the electrode terminal 42 and only the terminal 27 of the antenna pattern 26 can be electrically connected and joined. In the case of this semiconductor device, there is an advantage that it is not necessary to form a via 30 for electrical connection in the antenna substrate 28.
【００２９】図１１は本発明に係る半導体装置のさらに
他の構成を示す。図１１(a) は半導体素子４０の電極端
子４２を形成した面に多層のアンテナ基板３２を接合
し、第１層目のアンテナ基板２８のアンテナパターン２
６と電極端子４２とをワイヤボンディングにより接続し
た例である。層間のアンテナパターン２６の電気的接続
にはビア３０を使用している。図１１(b) はアンテナ基
板２８を階段状に積層し、各層ごとにワイヤボンディン
グしてアンテナパターン２６を層間で電気的に接続した
例である。この実施形態でもボンディングワイヤ４４、
ボンディングワイヤ４４とアンテナ基板２８とのボンデ
ィング部等をポッティング等によって封止するようにす
る。FIG. 11 shows still another configuration of the semiconductor device according to the present invention. FIG. 11A shows a case where a multilayer antenna substrate 32 is bonded to the surface of the semiconductor element 40 on which the electrode terminals 42 are formed, and the antenna pattern 2 of the first layer antenna substrate 28 is formed.
This is an example in which the electrode terminals 6 and the electrode terminals 42 are connected by wire bonding. Vias 30 are used to electrically connect the antenna patterns 26 between the layers. FIG. 11B shows an example in which the antenna substrates 28 are stacked in a stepwise manner, and the antenna pattern 26 is electrically connected between the layers by wire bonding for each layer. Also in this embodiment, the bonding wire 44,
The bonding portion between the bonding wire 44 and the antenna substrate 28 is sealed by potting or the like.
【００３０】以上説明したように、アンテナ基板と半導
体素子４０とを接合して半導体装置を得る方法には種々
の方法があり、アンテナ基板またアンテナ基板に形成す
るアンテナパターンも任意の形状に形成することが可能
である。そして、これによって、製品の特性に応じた設
計が可能になる。また、上記例の半導体装置では半導体
装置内に単一の半導体素子４０を搭載しているが、アン
テナ基板２８、３２を中間層に挟むことによって一つの
半導体装置に複数の半導体素子４０を搭載することも可
能である。As described above, there are various methods for joining the antenna substrate and the semiconductor element 40 to obtain a semiconductor device, and the antenna substrate and the antenna pattern formed on the antenna substrate are also formed in an arbitrary shape. It is possible. As a result, a design according to the characteristics of the product becomes possible. Further, in the semiconductor device of the above example, a single semiconductor element 40 is mounted in the semiconductor device, but a plurality of semiconductor elements 40 are mounted in one semiconductor device by sandwiching the antenna substrates 28 and 32 between the intermediate layers. It is also possible.
【００３１】上記実施形態の半導体装置は、いずれも半
導体素子４０の電極端子形成面に半導体素子４０とは別
体に形成したアンテナ基板を接合して信号授受用のアン
テナを備えた半導体装置として得たものである。図１２
は信号授受用のアンテナを備えた半導体装置の他の実施
形態として、半導体素子の電極端子形成面にアンテナパ
ターン２６を直接作り込むことによって半導体装置を製
造する方法を示す。この製造方法では信号授受用の半導
体素子を形成した半導体ウエハ５０に所要の加工を施し
てアンテナパターンを組み込んだ半導体装置を得る。Each of the semiconductor devices of the above embodiments is obtained as a semiconductor device having an antenna for transmitting and receiving signals by bonding an antenna substrate formed separately from the semiconductor element 40 to the electrode terminal forming surface of the semiconductor element 40. It is a thing. FIG.
FIG. 4 shows a method of manufacturing a semiconductor device by directly forming an antenna pattern 26 on an electrode terminal forming surface of a semiconductor element as another embodiment of a semiconductor device having an antenna for transmitting and receiving signals. In this manufacturing method, a required processing is performed on a semiconductor wafer 50 on which a semiconductor element for signal transmission / reception is formed to obtain a semiconductor device in which an antenna pattern is incorporated.
【００３２】図１２(a)は所定配置で半導体素子が形成
された半導体ウエハ５０を示す。５２が各半導体素子で
アンテナパターンと電気的に接続される電極端子であ
る。図１２(b)は電極端子形成面にアンテナパターンを
形成するため、まず、電気的絶縁層５４を形成した状態
を示す。電気的絶縁層５４は半導体ウエハ５０の電極端
子形成面にポリイミド樹脂等の樹脂材をコーティング
し、あるいは接着性を有する樹脂フィルムを接着して形
成することができる。FIG. 12A shows a semiconductor wafer 50 on which semiconductor elements are formed in a predetermined arrangement. Reference numeral 52 denotes an electrode terminal electrically connected to the antenna pattern in each semiconductor element. FIG. 12B shows a state in which an electrical insulating layer 54 is first formed to form an antenna pattern on the electrode terminal formation surface. The electrical insulating layer 54 can be formed by coating a resin material such as a polyimide resin on the electrode terminal forming surface of the semiconductor wafer 50 or by bonding an adhesive resin film.
【００３３】図１２(c)は、電気的絶縁層５４に底面に
電極端子５２が露出するビア穴５６を形成した状態であ
る。ビア穴５６は電気的絶縁層５４にレーザ光を照射す
る方法、化学的エッチングを施す方法等によって形成で
きる。図１２(d)は、次に、ビア穴５６の内面と電気的
絶縁層５４の表面全体に導体層５８を形成した状態であ
る。導体層５８はアンテナパターンの導体部となり、ま
た、ビア穴５６を充填して電極端子５２とアンテナパタ
ーンとを電気的に接続するビア６０となる。したがっ
て、これらの導体部として必要な厚さに導体層５８を形
成する。FIG. 12C shows a state in which a via hole 56 for exposing the electrode terminal 52 is formed on the bottom surface of the electrically insulating layer 54. The via hole 56 can be formed by a method of irradiating the electrical insulating layer 54 with laser light, a method of performing chemical etching, or the like. FIG. 12D shows a state in which the conductor layer 58 is formed on the inner surface of the via hole 56 and the entire surface of the electrically insulating layer 54. The conductor layer 58 becomes a conductor of the antenna pattern, and also becomes a via 60 that fills the via hole 56 and electrically connects the electrode terminal 52 to the antenna pattern. Therefore, the conductor layer 58 is formed to have a thickness necessary for these conductor portions.
【００３４】図１２(e)は、導体層５８をエッチングし
て電気的絶縁層５４の表面にアンテナパターン２６を形
成した状態である。アンテナパターン２６は半導体ウエ
ハ５０での半導体素子の配置位置に合わせて所定のパタ
ーンに形成する。導体層５８の表面にアンテナパターン
２６として残す部位のみを被覆したレジストパターンを
形成し、このレジストパターンをマスクとして導体層５
８をエッチングすることによってアンテナパターン２６
を形成することができる。なお、セミアディティブ法に
よる場合は、めっき給電層として薄い導体層を形成した
後、アンテナパターンとして形成する部位を露出させた
レジストパターンを形成し、電解めっきにより導体部を
盛り上げて形成した後、レジストパターンを除去し、レ
ジストパターンによって被覆されていた薄い導体層をエ
ッチングして除去することにより、所定パターンのアン
テナパターン２６を形成することができる。FIG. 12E shows a state in which the conductor pattern 58 is etched to form the antenna pattern 26 on the surface of the electrically insulating layer 54. The antenna pattern 26 is formed in a predetermined pattern in accordance with the arrangement position of the semiconductor elements on the semiconductor wafer 50. A resist pattern is formed on the surface of the conductor layer 58 so as to cover only the portion to be left as the antenna pattern 26, and the resist pattern is used as a mask to form
8 by etching the antenna pattern 26
Can be formed. In the case of the semi-additive method, after forming a thin conductor layer as a plating power supply layer, forming a resist pattern exposing a portion to be formed as an antenna pattern, forming a conductive portion by electrolytic plating, and then forming a resist. By removing the pattern and etching away the thin conductor layer covered with the resist pattern, the antenna pattern 26 having a predetermined pattern can be formed.
【００３５】半導体素子の表面に設けるアンテナパター
ン２６が１層のみの場合は、図１２(e)の状態、もしく
は、図１２(f)に示すように、アンテナパターン２６の
表面を保護膜６２によって被覆した後、半導体ウエハ５
０を個片にスライシングする。これによって、電極端子
形成面にアンテナパターン２６が形成されたチップサイ
ズの半導体装置が得られる。図１２(f)でＡ−Ａ線が半
導体ウエハ５０を切断する位置である。When only one layer of the antenna pattern 26 is provided on the surface of the semiconductor element, the surface of the antenna pattern 26 is protected by a protective film 62 as shown in FIG. 12E or as shown in FIG. After coating, the semiconductor wafer 5
Slice 0 into pieces. Thus, a chip-sized semiconductor device in which the antenna pattern 26 is formed on the electrode terminal formation surface is obtained. In FIG. 12F, the line AA is a position where the semiconductor wafer 50 is cut.
【００３６】アンテナパターン２６を複数層に積層して
形成する場合には、保護膜６２のかわりに、上記電気的
絶縁層５４と同様な電気的絶縁層を形成し、第１層のア
ンテナパターン２６を形成すると同様にして次層のアン
テナパターンを形成する。すなわち、第２層目の電気的
絶縁層にビア穴を形成し、スパッタリング等により導体
層を形成し、導体層をエッチングして第２層目のアンテ
ナパターンを形成する。第１層と第２層のアンテナパタ
ーン２６は電気的絶縁層に形成したビアを介して電気的
に接続することができる。アンテナパターン２６の形態
および層間の電気的接続は図７に示した形態と同様であ
る。When the antenna pattern 26 is formed by laminating a plurality of layers, an electric insulating layer similar to the electric insulating layer 54 is formed instead of the protective film 62, and the antenna pattern 26 of the first layer is formed. Is formed, an antenna pattern of the next layer is formed in the same manner. That is, a via hole is formed in the second electrically insulating layer, a conductor layer is formed by sputtering or the like, and the conductor layer is etched to form a second antenna pattern. The first and second antenna patterns 26 can be electrically connected via vias formed in the electrically insulating layer. The form of the antenna pattern 26 and the electrical connection between layers are the same as the form shown in FIG.
【００３７】図１２に示すように、半導体ウエハ５０の
電極端子形成面に電気的絶縁層５４を介してアンテナパ
ターン２６を作り込む方法は、アンテナパターン２６を
微細なパターンに形成すること、アンテナパターン２６
を複数層に積層して形成することが容易に可能であるこ
と、半導体ウエハ５０を対象として露光・現像といった
操作を行うことで効率的に半導体装置を製造することが
可能になる等の利点がある。半導体ウエハ５０をスライ
スして得られた半導体装置は半導体素子４０の電極端子
形成面に、電極端子５２と電気的に接続してアンテナパ
ターン２６が形成されたものとなる。As shown in FIG. 12, the method of forming the antenna pattern 26 on the electrode terminal forming surface of the semiconductor wafer 50 via the electrical insulating layer 54 is to form the antenna pattern 26 into a fine pattern, 26
Are easily formed in a plurality of layers, and the semiconductor device can be efficiently manufactured by performing operations such as exposure and development on the semiconductor wafer 50. is there. The semiconductor device obtained by slicing the semiconductor wafer 50 has the antenna pattern 26 formed on the electrode terminal forming surface of the semiconductor element 40 so as to be electrically connected to the electrode terminal 52.
【００３８】以上のように、本発明に係る半導体装置は
半導体素子４０と略同サイズに形成され、信号授受用の
アンテナを備えた半導体装置としてきわめて小型に形成
される。したがって、非接触式のＩＣカードとして使用
するといった場合でも従来のようなカード形とする必要
はなく、切手サイズもしくはさらに小型に形成して使用
することが可能になる。また、アンテナを組み込んだＩ
Ｃとして形成することにより、ＩＣとＩＣとの間で非接
触により信号を授受することが可能となる。これによっ
て、ＩＣとＩＣとを接続する配線が不要になり、ＩＣを
実装する実装基板を小型化することが可能になる等の種
々の用途に利用可能である。As described above, the semiconductor device according to the present invention is formed to have substantially the same size as the semiconductor element 40, and is extremely small as a semiconductor device having an antenna for transmitting and receiving signals. Therefore, even when used as a non-contact type IC card, it is not necessary to use a conventional card shape, and it is possible to use a stamp size or a smaller size. In addition, I
By forming C, signals can be transmitted and received between the ICs in a non-contact manner. This eliminates the need for wiring for connecting the ICs, and can be used for various applications such as miniaturization of the mounting board on which the IC is mounted.
【００３９】[0039]
【発明の効果】本発明に係る半導体装置は、上述したよ
うに、半導体素子と略同寸法のアンテナ基板を半導体素
子に接合して半導体装置としているから、通信用のアン
テナを備えたきわめて小型の半導体装置として提供さ
れ、非接触方式の通信等の用途に好適に使用することが
可能になる。また、本発明に係る半導体装置の製造方法
によれば、アンテナ基板を備えた半導体装置を容易にか
つ効率的に製造することが可能になる。As described above, the semiconductor device according to the present invention is formed by joining an antenna substrate having substantially the same dimensions as the semiconductor element to the semiconductor element to form a semiconductor device. It is provided as a semiconductor device and can be suitably used for applications such as non-contact communication. Further, according to the method of manufacturing a semiconductor device according to the present invention, it is possible to easily and efficiently manufacture a semiconductor device having an antenna substrate.
【図１】本発明に係る半導体装置に使用するアンテナ基
板の製造方法を示す説明図である。FIG. 1 is an explanatory view showing a method for manufacturing an antenna substrate used for a semiconductor device according to the present invention.
【図２】絶縁基板にアンテナパターンを形成した状態の
平面図である。FIG. 2 is a plan view showing a state where an antenna pattern is formed on an insulating substrate.
【図３】アンテナ基板にビアを形成した状態の平面図で
ある。FIG. 3 is a plan view showing a state where vias are formed in an antenna substrate.
【図４】本発明に係る半導体装置の実施形態を示す斜視
図である。FIG. 4 is a perspective view showing an embodiment of a semiconductor device according to the present invention.
【図５】図４に示す半導体装置の断面図である。5 is a cross-sectional view of the semiconductor device shown in FIG.
【図６】多層のアンテナ基板を用いて半導体装置を形成
する方法を示す説明図である。FIG. 6 is an explanatory diagram illustrating a method for forming a semiconductor device using a multilayer antenna substrate.
【図７】アンテナパターンのパターン例を示す説明図で
ある。FIG. 7 is an explanatory diagram showing a pattern example of an antenna pattern.
【図８】本発明に係る半導体装置の他の製造方法を示す
説明図である。FIG. 8 is an explanatory view showing another method of manufacturing the semiconductor device according to the present invention.
【図９】アンテナパターンのパターン例を示す説明図で
ある。FIG. 9 is an explanatory diagram showing a pattern example of an antenna pattern.
【図１０】本発明に係る半導体装置のさらに他の構成例
を示す断面図である。FIG. 10 is a cross-sectional view showing yet another configuration example of the semiconductor device according to the present invention.
【図１１】本発明に係る半導体装置のさらに他の構成例
を示す断面図である。FIG. 11 is a cross-sectional view showing still another configuration example of the semiconductor device according to the present invention.
【図１２】本発明に係る半導体装置のさらに他の製造方
法を示す説明図である。FIG. 12 is an explanatory view showing still another method of manufacturing a semiconductor device according to the present invention.
【図１３】従来のＩＣカードの構成を示す説明図であ
る。FIG. 13 is an explanatory diagram showing a configuration of a conventional IC card.
１０ アンテナ １２ 半導体素子 １４ フィルム ２０ 金属箔付き絶縁基板 ２１ 絶縁基板 ２２ 金属箔 ２４ 接着層 ２６、２６ａ、２６ｂ、２６ｃ アンテナパターン ２８、３２ アンテナ基板 ３０ ビア ３４ 接着剤シート ３６ 導電性接着剤 ３８ ボンディングパッド ４０ 半導体素子 ４２、５２ 電極端子 ４３ 異方導電性接着フィルム４４ ボンディングワイ
ヤ ５０ 半導体ウエハ ５４ 電気的絶縁層 ５６ ビア穴 ５８ 導体層 ６０ ビア ６２ 保護膜DESCRIPTION OF SYMBOLS 10 Antenna 12 Semiconductor element 14 Film 20 Insulated board with metal foil 21 Insulated board 22 Metal foil 24 Adhesive layer 26, 26a, 26b, 26c Antenna pattern 28, 32 Antenna board 30 Via 34 Adhesive sheet 36 Conductive adhesive 38 Bonding pad Reference Signs List 40 semiconductor element 42, 52 electrode terminal 43 anisotropic conductive adhesive film 44 bonding wire 50 semiconductor wafer 54 electrical insulating layer 56 via hole 58 conductive layer 60 via 62 protective film
───────────────────────────────────────────────────── フロントページの続き (72)発明者 樋口 努 長野県長野市大字栗田字舎利田711番地 新光電気工業株式会社内 (72)発明者 赤川 雅俊 長野県長野市大字栗田字舎利田711番地 新光電気工業株式会社内 (72)発明者 西口 愛子 長野県長野市大字栗田字舎利田711番地 新光電気工業株式会社内 Ｆターム(参考） 2C005 NA09 NA31 PA18 TA22 5B035 AA00 BA05 BB09 CA08 CA23 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tsutomu Higuchi Nagano Prefecture Nagano City Oita Kurita-shasha Toshida 711 Shinko Electric Industries, Ltd. (72) Inventor Aiko Nishiguchi, Nagano-shi, Nagano, 711, Kurita-sha, Toda, Shinko Electric Industries Co., Ltd.F-term (reference)
Claims (13)
気的に接続されたアンテナ付きの半導体装置であって、 前記半導体素子の電極端子形成面の平面領域と略同寸法
に形成された絶縁基板に前記アンテナとして作用するア
ンテナパターンが形成されたアンテナ基板が、前記アン
テナパターンと半導体素子とが電気的に接続されて半導
体素子に一体に接着されていることを特徴とする半導体
装置。1. A semiconductor device with an antenna, wherein an antenna for signal transmission / reception is electrically connected to a semiconductor element, wherein the insulating substrate is formed to have substantially the same size as a plane area of an electrode terminal forming surface of the semiconductor element. A semiconductor substrate on which an antenna pattern acting as the antenna is formed, wherein the antenna pattern and the semiconductor element are electrically connected and integrally bonded to the semiconductor element.
形成面の平面領域内に接着されていることを特徴とする
請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the antenna substrate is bonded in a plane area of the electrode terminal forming surface of the semiconductor element.
に接着されていることを特徴とする請求項１記載の半導
体装置。3. The semiconductor device according to claim 1, wherein the semiconductor element is bonded within a substrate surface of the antenna substrate.
成された面とは反対面を半導体素子の電極端子が形成さ
れた面に接着され、 前記電極端子とアンテナパターンとが、絶縁基板に設け
られたビアを介して電気的に接続されていることを特徴
とする請求項２記載の半導体装置。4. An antenna substrate, wherein a surface opposite to a surface on which an antenna pattern is formed is bonded to a surface on which electrode terminals of a semiconductor element are formed, and the electrode terminal and the antenna pattern are provided on an insulating substrate. 3. The semiconductor device according to claim 2, wherein the semiconductor device is electrically connected via a via.
成された面とは反対面を半導体素子の電極端子が形成さ
れた面に接着され、 前記電極端子とアンテナパターンとが、ワイヤボンディ
ングにより電気的に接続されていることを特徴とする請
求項２記載の半導体装置。5. An antenna substrate having a surface opposite to a surface on which an antenna pattern is formed is bonded to a surface on which electrode terminals of a semiconductor element are formed, and the electrode terminals and the antenna pattern are electrically connected by wire bonding. 3. The semiconductor device according to claim 2, wherein the semiconductor device is connected.
は反対面をアンテナ基板に接着され、 前記電極端子と前記アンテナ基板に形成されたアンテナ
パターンとがワイヤボンディングにより電気的に接続さ
れていることを特徴とする請求項３記載の半導体装置。6. A semiconductor element having a surface opposite to a surface on which electrode terminals are formed is bonded to an antenna substrate, and the electrode terminals and an antenna pattern formed on the antenna substrate are electrically connected by wire bonding. 4. The semiconductor device according to claim 3, wherein:
が絶縁層を介して複数層に積層して形成され、各層に形
成されたアンテナパターンが電気的に直列に接続された
多層のアンテナ基板であることを特徴とする請求項１、
２、３、４、５または６記載の半導体装置。7. The antenna substrate is a multilayer antenna substrate in which the antenna pattern is formed by laminating a plurality of layers via an insulating layer, and the antenna patterns formed on each layer are electrically connected in series. Claim 1, characterized in that:
7. The semiconductor device according to 2, 3, 4, 5, or 6.
アを介して電気的に接続されていることを特徴とする請
求項７記載の半導体装置。8. The semiconductor device according to claim 7, wherein the antenna pattern is electrically connected via a via between adjacent layers.
グにより隣接する層間が電気的に接続されていることを
特徴とする請求項７記載の半導体装置。9. The semiconductor device according to claim 7, wherein adjacent layers of the antenna pattern are electrically connected by wire bonding.
電気的に接続されたアンテナ付きの半導体装置であっ
て、 前記半導体素子の電極端子形成面内に、前記アンテナと
して、電極端子形成面を被覆する電気的絶縁層を介して
形成した導体層がエッチングされてアンテナパターンが
形成され、該アンテナパターンと電極端子とが電気的絶
縁層に形成したビアを介して電気的に接続されているこ
とを特徴とする半導体装置。10. A semiconductor device with an antenna, wherein an antenna for signal transmission / reception is electrically connected to a semiconductor element, wherein an electrode terminal forming surface is covered as the antenna in an electrode terminal forming surface of the semiconductor element. The antenna pattern is formed by etching the conductor layer formed through the electrically insulating layer, and the antenna pattern and the electrode terminals are electrically connected to each other through the via formed in the electrically insulating layer. Characteristic semiconductor device.
介して複数層に積層して形成され、各層に形成されたア
ンテナパターンが電気的に直列に接続されていることを
特徴とする請求項１０記載の半導体装置。11. The antenna pattern according to claim 10, wherein the antenna pattern is formed by laminating a plurality of layers via an electrically insulating layer, and the antenna patterns formed on each layer are electrically connected in series. 13. The semiconductor device according to claim 1.
導体ウエハに、 電気的絶縁性を有する絶縁基板に前記各半導体素子の配
置に合わせて信号授受用のアンテナパターンが形成され
たアンテナ基板を、各半導体素子の電極端子と前記各ア
ンテナパターンとを電気的に接続して接着した後、 前記アンテナ基板が接着された半導体ウエハを半導体装
置単位の個片に切断することを特徴とする半導体装置の
製造方法。12. An antenna substrate in which an antenna pattern for signal transmission / reception is formed on an insulating substrate having electrical insulation on a semiconductor wafer on which semiconductor elements are formed in a predetermined arrangement, in accordance with the arrangement of each semiconductor element. After electrically connecting and bonding the electrode terminals of each semiconductor element and each of the antenna patterns, the semiconductor wafer to which the antenna substrate is bonded is cut into individual semiconductor device units. Production method.
導体ウエハの電極端子形成面に電気的絶縁層を形成し、 該電気的絶縁層に前記電極端子が底面に露出するビア穴
を形成し、 該ビア穴の内面および前記電気的絶縁層の表面に導体層
を形成し、 該導体層により前記半導体素子の配置位置に合わせてア
ンテナパターンを形成するとともに、該アンテナパター
ンと前記電極端子とを前記ビア穴に形成されたビアを介
して電気的に接続し、 該アンテナパターンが形成された半導体ウエハを半導体
装置単位の個片に切断することを特徴とする半導体装置
の製造方法。13. An electric insulating layer is formed on an electrode terminal forming surface of a semiconductor wafer on which semiconductor elements are formed in a predetermined arrangement, and a via hole is formed in the electric insulating layer such that the electrode terminal is exposed on a bottom surface. A conductor layer is formed on the inner surface of the via hole and on the surface of the electrically insulating layer. An antenna pattern is formed by the conductor layer in accordance with the arrangement position of the semiconductor element, and the antenna pattern and the electrode terminals are connected to each other. A method for manufacturing a semiconductor device, comprising: electrically connecting via a via formed in a via hole; and cutting the semiconductor wafer on which the antenna pattern is formed into individual pieces of a semiconductor device.
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|---|---|---|---|
| JP20008799A JP3557130B2 (en) | 1999-07-14 | 1999-07-14 | Method for manufacturing semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20008799A JP3557130B2 (en) | 1999-07-14 | 1999-07-14 | Method for manufacturing semiconductor device |
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|---|---|---|---|
| JP2004079712A Division JP4450652B2 (en) | 2004-03-19 | 2004-03-19 | Semiconductor device and manufacturing method thereof |
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