JP2001013968A - Waveform generating method and device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a waveform generating method and a device by which a DCO(Digital Controlled Oscillator) can be synchronized with externally given phase information or a waveform signal. SOLUTION: A frequency calculating means 1 regards an external input signal as phase information, calculates its increment, and outputs frequency information. A reset timing detecting means 2 detects a zero cross point of the external input signal, and outputs a reset timing signal. In a reset phase calculating means 3, a reset phase in reset timing is calculated based on the external input signal and the frequency information, in reset timing, a phase generated by a phase information generating means 4 is set to a reset phase by a changeover switch 22. Therefore, a waveform synchronizing with the external input signal is generated by a waveform generator 5. Aliasing caused by discontinuity of a reset part can be eliminated by multiplying window function.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for generating a waveform synchronized with phase information or a waveform supplied from an external oscillator or the like by digital processing.

[0002]

2. Description of the Related Art Conventionally, an analog synthesizer has two master and slave waveform generators each having a sawtooth wave or a pulse wave (square wave) as a fundamental wave. Some have an oscillator synchronization (oscillator sync) function for resetting the phase of the fundamental wave on the side. Here, the reset of the slave-side oscillator is normally triggered by the input of a pulse output from the master-side oscillator when the phase of the master-side fundamental wave becomes zero. According to the analog synthesizer having such an oscillator synchronizing function, the tone signal of the master-side fundamental frequency is output from the master-side waveform generator, and the slave-side waveform generator corresponds to the master-side fundamental frequency. A tone signal having a pitch and a spectrum envelope shape having a center frequency at a fundamental frequency on the slave side is output.

Generally, an analog synthesizer is apt to be unstable because of analog operation.
Today, most synthesizers have been replaced by digital ones. However, an analog synthesizer has a unique sound quality, and it is desired to accurately simulate a function of the analog synthesizer, such as the oscillator synchronization function, by digital processing.

When the above-described oscillator synchronization function is simply digitized, each signal (data) is output at a predetermined sampling period, so that an ideal reset timing and an actual reset timing are set. And a time lag occurs. This will be described with reference to an example of the waveform shown in FIG. FIG. 11A is a diagram showing the waveform of the phase information Pm of the fundamental wave on the master side. The fundamental wave phase information Pm on the master side is determined by the fundamental frequency information fm on the master side as shown in FIG. And has a waveform that changes in a sawtooth manner in a value range of “−1” to “+1”. That is, -1 to +1 of the amplitude are associated with -π to + π of the phase. Here, in order to process digitally, the phase information Pm is actually output as a value for each sampling period Δt indicated by a circle in the figure. FIG. 11B is a diagram showing the waveform of the phase information Ps of the fundamental wave on the slave side, which has a gradient determined by the fundamental frequency information fs on the slave side,
The waveform has a sawtooth shape in the range of the value of “+1”, and the phase information Ps is similarly output at each sampling period Δt. As shown in the drawing, the master-side fundamental wave phase information Pm is reset to the “−1” level in synchronization with the timing (t0) at which it changes from “+1” to “−1”. Is performed.

[0005] However, the master-side fundamental wave phase information Pm is output at every sampling period Δt as described above, and the phase information Pm falls from “+1” to “−1”. Can be recognized at the timing indicated by t1 in the figure. At this timing, when the fundamental wave phase information Ps on the slave side is reset, FIG.
The fundamental wave phase information P on the slave side as shown in FIG.
s output. That is, Δz in FIG.
A time shift (jitter) indicated by 1 (= t1−t0) will occur. Similarly, the same occurs at the timing indicated by t2, and a time shift indicated by Δz2 occurs.

Accordingly, the present inventors have proposed a tone generating method and apparatus capable of realizing an oscillator synchronization function without causing such a time lag (Japanese Patent Laid-Open No. 10-210).
-198338). First, the principle of the proposed method will be described. As shown in FIG. 11B, the ideal slave-side fundamental wave phase information Ps
Already have a value “ps” different from 0 at t1. Therefore, at the timing of t1 when the reset processing is actually performed, the ideal phase information “ps” is set as the reset phase on the slave side.
It is possible to reduce adverse effects on sound quality due to jitter.
This reset phase “ps” is, as described below,
Master-side fundamental frequency information "fm" and master-side fundamental wave phase information "p" at reset timing t1.
m ", the reset point in time t0 when the sampling frequency is infinite is estimated, and the reset point in time t0 and the fundamental frequency information" fs "on the slave side can be obtained.

The process for obtaining the reset phase "ps" will be specifically described. However, in the following description, it is assumed that 0 <fm <1 and 0 <fs <1. As described above, the frequency ratio and the inclination ratio of the master-side fundamental wave phase information Pm and the slave-side fundamental wave phase information Ps are equal. Also, in FIG. 11B, the time period P0 from the true reset time t0 to the actual reset timing t1 is changed.
The ratio p between the value ps at which s has increased and the value pm 'at which Pm has increased.
s / pm 'is equal to the ratio of the slope of the Ps waveform to the slope of the Pm waveform. Thereby, the following equation (1) is established. ps / pm '= fs / fm (1) From this equation (1), equation (2) is derived, and further pm'
= Pm + 1, the equation (3) is obtained. ps = pm ′ / fm · fs (2) ps = (pm + 1) / fm · fs (3) That is, the ideal ps value at the actual reset timing t1 is fm, fs, and the actual reset timing. It can be calculated from pm at t1.

FIG. 12 is a block diagram showing an example of the configuration of the proposed tone generator. In this figure,
101 is a master side waveform generator, and 102 is a slave side waveform generator. These waveform generators 101 and 102 are, for example, feedback FM type waveform generators. 103 indicates that the operation result is “−1” to “+”.
When the value exceeds the range of "1", a modulo adder that cuts off the excess and outputs an addition result that is folded back from "+1" to "-1". This is a delay circuit that delays by (Δt). The modulo adder 13 and the delay circuit 10
4 constitutes a master-side oscillator that counts the master-side fundamental frequency information fm representing the frequency of the master-side fundamental wave, and outputs sawtooth master-side fundamental wave phase information Pm. The output Pm of the master-side oscillator becomes a sawtooth wave between “−1” and “+1” as shown in FIG. 11A, and the phase information Pm is input to the waveform generator 101. , A master waveform is output from the waveform generator 101.

A reset timing detector 105 detects the above-described reset timing. For example, the reset timing is detected by detecting an overflow of the modulo adder 103. Further, the modulo adder 106 modulo-adds the master-side phase information Pm to a constant “+1”, and outputs an addition result Pm ′ = (1 + Pm). A divider 107 divides the phase information Pm ′ from the modulo adder 106 by the master-side fundamental frequency information fm, and outputs an output p (= pm ′ / fm). On the slave side, a modulo adder 109 and a delay circuit 110 constitute a slave-side oscillator that outputs fundamental-wave phase information on the slave side. Reference numeral 111 denotes a changeover switch for selecting an output of the modulo adder 109 and an output of a multiplier 108 described later and supplying the output to the waveform generator 102 on the slave side. The multiplier 108 multiplies the operation result p (= pm ′ / fm) of the divider 107 by the slave-side fundamental frequency information fs to obtain ps represented by the above equation (3).
(= Fs · pm ′ / fm) is output. The switch 111 is switched to the “1” side only when there is an output from the reset timing detector 105 and supplies the output ps of the multiplier 108 to the waveform generator 102 on the slave side as a reset phase. . As a result, ideal oscillator synchronization as shown in FIG. 11B can be realized in digital processing.

[0010]

According to the above-mentioned proposed tone generating method, it is possible to reliably perform oscillator synchronization in a digitally configured waveform generator (DCO: Digital Controlled Oscillator). However, the proposed method requires that both the phase and frequency signals of the master DCO be available. However, such an oscillator synchronization is performed by the analog VCO as described above on the master side.
Is not limited to the one that simulates
Various sound source outputs such as PCM sound source and physical model sound source,
There is a demand for realizing even more cases in which the output of an electric or electronic musical instrument or the microphone input sound is used as a master. In such a case, there is no problem if the master side can supply the phase information and the frequency information, but since the signal from the external sound source or the like is used as the master phase information and has no frequency information, , Separately,
A means for calculating the frequency from the phase must be provided. However, it is useless to calculate the master frequency information used by the slave DCO one by one on the master side, and passing between the master and the slave by two signals of the phase and the frequency is performed by the register. Consumption also increases and can be burdensome in DSPs that have few resources.

On the other hand, even a simple waveform signal has a DCO
There is also a demand to synch. For example, when adding a DCO sound to an A / D-converted signal, it is often more convenient to match the basic pitch, and such a request is generated. Therefore, the present invention provides DC information to phase information or a waveform signal given from the outside.
It is an object of the present invention to provide a waveform generation method and apparatus capable of synchronizing O.

[0012]

In order to achieve the above object, a waveform generating method according to the present invention is a waveform generating method for generating a waveform synchronized with an external input signal. Detecting a reset timing to reset the phase information of the generated waveform; calculating the information corresponding to the frequency information of the external input signal assuming that the external input signal is a signal corresponding to the phase signal; Calculating the reset phase at the reset timing based on the information corresponding to the external input signal and the fundamental frequency information of the generated waveform, and setting the phase information of the generated waveform at the reset timing to the reset phase. And generating a waveform based on the phase information of the waveform. It is intended.

A step of generating a read signal for reading a window function corresponding to the reset timing based on the external input signal and information corresponding to frequency information of the external input signal; Reading the window function and multiplying the generated waveform by the window function. Or, moreover,
Creating a first read signal for reading a window function corresponding to the reset timing based on the external input signal and information corresponding to frequency information of the external input signal; and discontinuity of the generated waveform. Generating a second read signal for reading a window function corresponding to the portion; and reading a window function based on a read signal obtained by integrating the two read signals, and multiplying the generated waveform by the read function. It is. Further, the step of calculating information corresponding to the frequency information of the external input signal,
Calculating an increment for each sampling cycle of the external input signal.

Further, the waveform generator of the present invention is a waveform generator for generating a waveform synchronized with an external input signal, wherein a reset for resetting phase information of the generated waveform based on the external input signal is provided. Reset timing detecting means for detecting timing, frequency information calculating means for calculating information corresponding to frequency information of the external input signal assuming that the external input signal is a signal corresponding to a phase signal, and corresponding to the frequency information Reset phase calculating means for calculating a reset phase at the reset timing based on the information, the external input signal and the basic frequency information of the generated waveform, and generating phase information based on the basic frequency information of the generated waveform. Setting the phase information to the reset phase at the reset timing. And phase information generating means, and has a waveform generating means for generating a waveform based on the phase information generated by said phase information generating means.

Further, based on the external input signal and information corresponding to frequency information of the external input signal,
Window function reading means for reading a window function in response to the reset timing; and multiplication means for multiplying the waveform generated by the waveform generating means by the window function read by the window function reading means. Alternatively, a means for generating a first read signal for reading a window function corresponding to the reset timing based on the external input signal and information corresponding to frequency information of the external input signal; Means for generating a second read signal for reading a window function corresponding to the discontinuous portion; window function reading means for reading a window function based on a read signal obtained by integrating the first and second read signals; Multiplying means for multiplying the generated waveform by the window function read by the window function reading means. Further, the frequency information calculating means is means for calculating an increment of the external input signal for each sampling cycle.

[0016]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a waveform generating apparatus to which a waveform generating method according to the present invention is applied. It should be noted that the waveform generator of the present invention can not only be realized by hardware,
It can be realized by software or firmware using a DSP (Digital Signal Processor) or the like. The waveform generator of this embodiment is roughly divided into frequency calculating means for obtaining frequency information fx from externally input phase information (external phase input) Px, detecting overflow of the frequency calculating means, and resetting the reset timing. Reset timing detecting means for detecting, reset phase calculating means for calculating an accurate reset phase of the slave DCO from the reciprocal of the phase information and frequency information at the time of reset and the frequency information of the slave DCO, and a phase having a reset mechanism It comprises an information generating means and a waveform generating means for generating a waveform from the phase information. In the present invention, two types of arithmetic units are used. The first type of arithmetic unit has an arithmetic result of “−1” to
If the value exceeds the range of "+1", the excess is truncated to "+".
A modulo operation unit (modulo adder or modulo multiplier, described as mo in the figure) that outputs an operation result folded from “1” to “−1”.
This is an overflow-protection type arithmetic unit (adder or multiplier, described as ov in the figure) in which the calculation result is limited to a range beyond the range of "1" to "+1". An arithmetic unit in which neither mo nor ov is described is an arithmetic unit for storing an intermediate result.

In FIG. 1, Px is an external phase input, and an external waveform input such as an output waveform from another sound source or another DCO, a line input or a microphone input is regarded as phase information, and this external phase input Px can do. 1
Is frequency calculating means for differentiating the external phase input Px to obtain frequency information fx. This frequency calculating means 1 comprises a delay circuit 11 for delaying the input phase information Px by one sampling period and the phase information Px. It comprises a modulo adder 12 for subtracting the output of the delay circuit 11. The modulo adder 12 outputs a differential output of the phase information Px, that is, frequency information fx. Here, as described above, when the operation result exceeds the range of “−1” to “+1”, the modulo adder 12 cuts off the surplus and returns the operation result folded from “+1” to “−1”. The overflow of the modulo adder 12 is detected by the reset timing detecting means 2. The output of the reset timing detecting means 2 is supplied to a phase information generating means 4 having a later-described reset mechanism.

Reference numeral 3 denotes reset phase calculating means. The calculation of the reset phase is basically performed by an external phase input Px, frequency information fx obtained by differentiating the external phase input Px, and a fundamental frequency. Using the information fn,
The reset phase is calculated based on the above equation (3). In the reset phase calculating means 3, the frequency information fx calculated by the modulo adder 12 is input to an absolute value circuit 13, and the absolute value | fx | is output. Here, the absolute value is obtained from the external phase input P
This is so that it is possible to cope with whether the frequency signal obtained by differentiating x is positive or negative. The absolute value | fx | of the frequency is input to the reciprocal table 14,
From the reciprocal table 14, 1 / (| fx | · S) is output. Here, a value obtained by multiplying the reciprocal 1 / | fx | by 1 / S (right-shifted by the number of bits corresponding to S) is output in order to secure the number of significant digits of the operation. The shift amount S determines to what percentage of the maximum oscillation frequency an accurate reset phase can be calculated. The value of the shift amount S is, for example, 8 bits (= 256). ing.

On the other hand, the external phase input Px is input to a modulo adder 15, where it is modulo-added with a constant "-1" to output an output Px '. This output Px '
Is input to the absolute value circuit 16, and | Px '| is output. Here, the reason why the absolute value of Px 'is obtained is to obtain a positive value when multiplied by the output from the reciprocal table 14. The output | Px ′ | of the absolute value circuit 16 is
And the output 1 / (| f
x | · S). Then, the result of the multiplication is multiplied by the shift amount S in the overflow protection type multiplier 18, and the output | Px ′ | / |
fx | is output. This output corresponds to the decimal part of the reset timing (Δz / Δt in FIG. 11).

The output of the multiplier 18 is input to the multiplier 19 and is multiplied by the fundamental frequency information (frequency number) fn of the waveform signal to be generated. As a result, the above-described calculation of the expression (3) is performed. The result of the multiplication is
The modulo adder 20 modulo-adds the initial phase Pi, and the modulo adder 20 outputs (fn · | Px ′
The value of | / | fx | + Pi) modulo, that is, the value of the phase information on the slave side at the reset timing of the external phase input Px is calculated. This phase information is supplied to the contact on the “1” side of the changeover switch 22 in the phase information generating means 4 having the above-described reset mechanism. In the above description, the modulo adder 2
Although the initial phase Pi was added at 0,
It is not necessary to add the initial phase here. Also,
By changing the initial phase Pi with time, a undulating musical sound can be generated.

On the other hand, the frequency number fn is also input to the modulo adder 21 in the phase information generating means 4. The output of the modulo adder 21 is supplied to the contact on the "0" side of the changeover switch 22, and the fixed contact of the changeover switch 22 is connected to the waveform generating means 5 and delays one sampling period. Delay circuit 23
It is connected to the. The output of the delay circuit 22 is connected to the other input of the modulo adder 21.

When the changeover switch 22 is connected to the contact on the "0" side, the phase information generating means 5 outputs phase information in the form of a sawtooth wave having a slope corresponding to the frequency number fn. And the modulo adder 12
When the reset timing signal is output from the reset timing detecting means 2 due to an overflow of the switch, the changeover switch 22 is turned on only during the sampling period.
Is switched to the contact on the “1” side, and the reset phase information (fn · | Px ′ | / | f
x | + Pi) is selected and supplied to the waveform generator 5 and the delay circuit 23. Then, at the next sampling timing, the changeover switch 22 is connected to the contact on the “0” side again. Thus, phase information completely synchronized with the external phase input Px can be supplied to the waveform generator 5, and the waveform generator 5 generates a musical tone synchronized with the external phase input Px. .
In the above description, the zero-cross point of the external phase input Px is detected by detecting the overflow of the modulo adder 12 in the frequency calculating means 1 and is set as the reset timing. However, the present invention is not limited to this. Instead, the reset timing may be detected by detecting the period of the waveform of the external phase input Px or detecting a singular point such as a peak value of the amplitude or a point passing a predetermined threshold value. . As described above, according to this embodiment, it is possible to generate waveform data synchronized with the external input signal by regarding an arbitrary external input signal as phase information.

According to the above-described embodiment,
Since an accurate reset phase can be realized, aliasing (folding distortion) of a generated musical tone can be reduced to some extent, but this may not be enough. Therefore, an embodiment in which a window function is applied to the reset portion to further suppress the occurrence of aliasing will be described. FIG. 2 is a block diagram showing a configuration example of this embodiment. In this embodiment,
The window function is obtained from a window function table that accesses a waveform obtained from the inverse function of phase and frequency as an address.

In FIG. 2, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. This embodiment is different from the embodiment shown in FIG. 1 in that a window function multiplying means 6 for multiplying the reset portion by a window function is provided. That is, in this embodiment, the multiplier 1 in the reset phase calculating means 3
The output of 7 is branched and input to the overflow protection type multiplier 24 in the window function multiplying means 6, where it is multiplied by a coefficient Sw for determining the width of the window function. This output is input to the window function table 25 as an address, and the window function output from the window function table 25 is multiplied by the overflow output type multiplier 26 with the waveform output from the waveform generator 5.

FIG. 3 is a diagram showing an example of the waveform of the main part in FIG. FIG. 3A shows the external phase input P
An example of x is shown, and the modulo adder 15 produces an output Px ′ whose phase is shifted by 180 ° as shown in FIG. Thereby, the zero cross point in the waveform Px is converted into a discontinuous point in the waveform Px ′. This output Px ′ becomes an output * 1 shown in FIG. As is clear from the figure, this output * 1 is a waveform that becomes "0" at the reset timing of the external phase input Px shown in FIG. The output | Px ′ | of the absolute value circuit 16 is multiplied by the output (1 / (| fx | · S)) from the reciprocal table 14 in the multiplier 17 as described above, and the output is branched. It is supplied to the window function multiplying means 6. In the window function multiplying means 6,
The output of the multiplier 17 is multiplied by a coefficient Sw for determining the width of the window function. FIG. 3D illustrates the multiplier 24.
An example of the output * 3 is shown. Here, the slope of the slope of the output * 3 is determined by the coefficient Sw, and the width of the window function can be changed by changing the value of the coefficient Sw. The window function table 25 having the input / output characteristics as shown in FIG.
Is read, a window function output is obtained as shown in FIG. By multiplying this window function output by the overflow protection type multiplier 26 with the waveform output of the waveform generator 5, it is possible to obtain a waveform output in which the reset portion is multiplied by a window function.

In the above description, the output * 2 of the multiplier 17 for multiplying the reciprocal of the frequency fx is supplied to the multiplier 24 of the window function multiplier 6. Therefore, although the width of the window function is constant regardless of the magnitude of the frequency fx, the output * 1 of the absolute value circuit 16 is divided by the multiplier 24.
, A window function having a width proportional to the reciprocal of the frequency fx can be obtained as shown in FIG. In this way, it is possible to limit the band of the discontinuous waveform generated at the time of resetting, and it is possible to prevent aliasing caused by resetting. Also, by actively utilizing this window function, the spectrum envelope or formant of the generated musical tone can be controlled to an arbitrary shape.

The waveform generator 5 uses a feedback FM system, a system that switches and outputs a waveform whose band is limited by PCM, and a system that directly generates a waveform whose band is limited. In the case of the third method for directly generating the generated waveform, the window function applied to the waveform to prevent aliasing and the window function applied to the reset portion can be made common.
Therefore, in an embodiment in which a window function to be applied to the waveform and a window function to be applied to the reset portion in order to prevent the aliasing are common, a block diagram showing a configuration example of this embodiment shown in FIG. 4 and FIG. 5 are shown in FIG. A description will be given with reference to waveform diagrams. In this embodiment, the window function table is accessed by combining the waveform for accessing the window function with respect to the waveform and the waveform for accessing the window function of the reset portion (for example, by a method of obtaining a minimum value). I have to. As a result, the size of the waveform generation portion can be reduced.

In the block diagram shown in FIG.
Alternatively, the same components as those shown in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted. As is clear from this figure, also in this embodiment, the above-described reset timing detecting means 2, reset phase calculating means 3, and phase information generating means 4 are configured in the same manner as in each of the above-described embodiments. Further, since the embodiment shown in this figure directly generates a band-limited waveform as described above, the above-mentioned waveform generator 5 is not provided.
Although FIG. 4 does not describe the frequency calculation means 1 for generating frequency information fx and the modulo adder 15 for modulo-adding "-1" to the external phase input Px and outputting Px ', These may have the same configuration as that shown in FIG. 1 or FIG. 2 described above, or when a VCO or DCO including frequency information and phase information is used as a master side,
The frequency information and the phase information may be used directly.

In FIG. 4, the frequency number fn is also input to the absolute value circuit 31, and the absolute value | fx | is supplied to the reciprocal table 32 as an address.
2 outputs 1 / (| fn | · S). Where S
Is the same shift amount as described above. The output of the phase information generating means 4 is supplied to a modulo adder 33 and an overflow protection type multiplier 39.
The output (* 1, FIG. 5B) of the phase information generating means 4 input to the modulo adder 33 is modulo-added with a constant “−1” by the modulo adder 33, and the phase thereof is 1
Shifted by 80 °. The output of the phase information generating means 4 whose phase has been shifted by 180 ° is supplied to an absolute value circuit 34. The output of the absolute value circuit 34 is multiplied by an overflow protection type multiplier 35 with the output of the reciprocal table 32. Is done. FIG. 5D shows the output * 3 of the multiplier 35. Since the slope of the output * 3 is multiplied by the reciprocal of the frequency information fn, it has the same slope as the output * 2 from the overflow protection type multiplier 17.

Reference numeral 36 denotes a minimum value selection circuit, which is input to the A terminal and output from the overflow protection type multiplier 17 in the reset phase calculating means 3 (* 2 (FIG. 5C)) and input to the B terminal. Of the multiplier 35 ((d) in FIG. 5) and outputs the smaller value. As a result, the output from the multiplier 17 *
2, the master reset timing and the slave reset timing from the multiplier 35 are obtained. Then, the output of the minimum value selection circuit 36 is multiplied by a predetermined coefficient Sw that determines the width of the window in an overflow protection type multiplier 37. FIG. 5E shows the output * 4 of the multiplier 37. As is clear from this figure, an output having a predetermined gradient and having a zero level is obtained at both the master reset timing and the slave reset timing. The output * 4 is input to the window function table 38 as an address. The window function table 38 outputs an output * 5 corresponding to a window function having characteristics as shown in the figure, and outputs the sawtooth wave from the phase information generating means 4 using an overflow protect type multiplier 39. Multiplied by 1 and (g) of FIG.
As a result, a band-limited saw-tooth wave output SAW is output.

Thus, the phase information generating means 4
, A discontinuous portion of the slave waveform itself and the above-described reset portion can be multiplied by using the window function output from the single window function table 38 when generating the sawtooth waveform output directly from Becomes Therefore, the configuration can be simplified.

Although the above-described embodiment is directed to a case where a sawtooth wave is directly generated, this method can be similarly applied to a case where another waveform is directly generated. When a pulse waveform (square wave waveform) is generated, a pulse waveform having a pulse width corresponding to the predetermined time width is obtained by taking a difference between two sawtooth waveforms shifted by a predetermined time width. Can be. FIG. 6 is a block diagram showing components to be added to FIG. 4 when a pulse waveform is directly generated. In the embodiment shown in FIG. 4, the absolute value circuits 31 and 34, the reciprocal table 32, the modulo adder 33, the overflow protection type multipliers 35, 37 and 39, the minimum value selection circuit 3
6. According to the window function table 38, a SAW waveform output * 6 with a predetermined band limitation is obtained. In the modulo adder 41 in FIG. 6, a predetermined coefficient Pw serving as a pulse width is modulo-added to the output * 1 from the phase information generating circuit 4, and the sawtooth wave whose phase is shifted by an amount corresponding to Pw. Occurs. Then, the same processing as the processing in FIG. 4 is performed on the sawtooth wave whose phase has been shifted by an amount corresponding to Pw to generate a band-limited sawtooth wave. That is, the modulo adder 42 and the absolute value circuit 43 in FIG. 6 correspond to the modulo adder 33 and the absolute value circuit 34 in FIG. 4, respectively. Similarly, the overflow protect type multiplier 44, the minimum value selection circuit 45, the overflow protect type multiplier 46, the window function table 47, and the overflow protect type multiplier 48 in FIG. 6 are respectively the overflow protect type multiplier 35 in FIG. , The minimum value selection circuit 36, the overflow protection type multiplier 37, the window function table 38, and the overflow protection type multiplier 39.

Thus, the same operation as described above is performed.
From the overflow protection type multiplier 48, a second SAW waveform output whose phase is shifted by an amount corresponding to Pw is obtained from the SAW waveform output * 6 of FIG. The second SAW waveform output is multiplied by a coefficient -a for determining the duty ratio of the pulse waveform in the multiplier 49, and overflows with the first SAW waveform output * 6 similarly multiplied by the coefficient a in the multiplier 50. The addition is performed in the protect type adder 51. Thereby, a pulse waveform having a time width corresponding to the coefficient Pw is output from the adder 51. In this way, a pulse waveform synchronized with the master waveform and band-limited can be directly output.

The above-described oscillator synchronization method can be applied to a case where a more general waveform is treated as a master. In this case, the input waveform is cut through a DC component by passing through an HPF (high-pass filter) in advance,
Alternatively, in some cases, it is better to perform processing such as removing harmonic components with an LPF (low-pass filter) or the like. An embodiment in which this general waveform is input and a waveform synchronized with the input of the waveform is output will be described with reference to a block diagram shown in FIG. 7 and a main part waveform diagram of FIG. In this embodiment, reset timing detecting means for detecting a singular point such as a zero crossing point or an amplitude peak point of an input waveform to obtain a reset timing, and differentiating the waveform by regarding the input waveform as a phase. Frequency calculation means for obtaining the increment (that is, frequency information in the above-described embodiment), the phase and the increment (frequency) at the time of reset
And the frequency information of the slave DCO,
It comprises reset phase calculating means for calculating an accurate reset phase of the slave DCO, phase information generating means for generating phase information of a generated waveform, and waveform generating means for forming a waveform from the phase information on the slave side. .

In FIG. 7, the same components as those in FIG. 1 described above are denoted by the same reference numerals, and the description will not be repeated. As shown in FIG. 7, also in this embodiment, similarly to the above-described embodiment of FIG. 1, frequency calculation means 1, reset timing detection means 2, reset phase calculation means 3, phase information generation means 4, and It has a waveform generating means 5. And, before the frequency calculating means 1,
LPF for removing harmonic components of external waveform input
A (low-pass filter) 61 and an HPF (high-pass filter) 62 for cutting direct current components and the like are provided as necessary, and an overflow protection type for multiplying an external waveform input by a constant “0.5”. , And a modulo adder 64 for adding a constant “−1” to shift the phase of the multiplication result Wx by 180 °. Further, the output Wx of the overflow protection type multiplier 63 is input to the absolute value circuit 16. Here, the amplitude of the external waveform input is “−1”.
Description will be made assuming that the value is normalized to “+1”.

FIG. 8A shows the case where the HPF 6
8 shows an example of a waveform of an external waveform input * 1 inputted through the input terminal 2, and this waveform is multiplied by a constant “0.5” in an overflow protection type multiplier 63, and FIG. Output Wx shown in FIG. Next, this output Wx
Is modulo-added to the constant "-1" in the modulo adder 64, and becomes an output Wx 'corresponding to a waveform whose phase is shifted by 180 degrees as shown in FIG. Next, in the frequency calculating means 1, the differentiation processing of the waveform Wx ', that is,
Calculate the increment of the waveform from one sampling cycle before,
The differential result dx is obtained. Then, the reset timing detecting means 2 detects a zero crossing point of the external waveform input * 1 by detecting an overflow in which the addition result in the modulo adder 12 becomes smaller than -1. This corresponds to detecting a negative-to-positive zero crossing of the external input waveform * 1. Note that the differential value is +1
If you try to detect that it has become larger,
Positive to negative zero crossing of the waveform can be detected. The reason why the multiplier 63 multiplies the constant "0.5" is to keep the change in the waveform within a predetermined range when the zero-cross detection is performed by the overflow detection.

The output dx of the frequency calculation means 1 represents an increment of the waveform, and corresponds to frequency information (frequency number) when the external input waveform is phase information. Therefore, by treating dx in the same manner as the frequency information fx in the above-described embodiment, the reset phase calculating unit 3 can calculate the reset phase in the same manner as in each of the above-described embodiments. Note that the output Wx 'of the modulo adder 64 corresponds to the external phase input in the above-described embodiment, and the external waveform input Wx whose phase is different from Wx' by 180 ° is directly sent to the absolute value circuit 16 of the reset phase calculator 3. To be entered. In this manner, a waveform synchronized with an external waveform input can be generated.

When a zero-cross from negative to positive occurs, since dx> 0 and Wx ≧ 0, the absolute value circuit 13 for obtaining the absolute value of dx and the absolute value circuit 16 for obtaining the absolute value of Wx It does not necessarily have to be provided. Further, the detection of the zero cross may use a method other than the method described above. For example, a change in the sign bit (usually the MSB) of Wx from 1 (negative) to 0 (positive) may be detected. This method can be easily realized when it is realized by hardware without being executed by the DSP.

In the case where a waveform synchronized with the waveform input as described above is generated, when resetting is performed by detecting a zero cross as described above, usually,
Either an upward or downward zero cross is used. This is because it is common to reset once in one cycle of the waveform. In such a case, it is difficult to use the waveform as it is to create a window function for multiplying the reset portion. This is because when the waveform is shaped and the window function table is read, the window function is applied to both the upward and downward zero crossings. Incidentally, in reality, when the waveform changes in a complicated manner, the zero crossing may occur many times in one cycle.
Since the fundamental period is synchronized with the input signal only by changing the overtone structure of CO, there is often no problem.

Therefore, another embodiment of the present invention which can eliminate the inconvenience that the window function is applied to both the upward and downward zero crossings will be described with reference to the block diagram of FIG. 9 and FIG. A description will be given with reference to waveform diagrams. 9, the same components as those in FIGS. 1 and 7 are denoted by the same reference numerals, and description thereof will be omitted. In this embodiment, an address generator 7 is separately provided, and the window function table 77 is read using the address generator 7. Further, only a predetermined number n of waveform samples are multiplied by the window function,
The width of the window is a fixed number of samples.

The address generator 7 includes an overflow protection type multiplier 1 of the reset phase calculation means 3.
8 (| Wx | / | dx |) is supplied and multiplied by a constant “2 / n” in the multiplier 71. Here, n is the number of samples corresponding to the width of the window, and is usually a power of 2 (n = 4 in the illustrated example).
The output of the multiplier 71 is added to a constant “−1” in an overflow protect type adder 72, and the “1” side of a changeover switch 74 controlled to be switched by a reset timing signal from the reset timing detection means 2. Supplied to the contacts. A delay circuit 75 is connected to the fixed contact of the changeover switch 74.
Is input to an overflow protection type adder 73 and is added to the constant "2 / n". The addition result is connected to a contact on the "0" side of the changeover switch 74.

That is, when the reset timing detection output from the reset timing detection circuit 2 is not input, the changeover switch 74 is connected to the “0” side, and the fixed contact of the changeover switch 74 An output that increases by 2 / n (1/2 in the illustrated example) at each sampling timing is obtained. Then, at the timing when the reset timing detection signal is input from the reset timing detection means 2, the changeover switch 74 is switched to the contact on the “1” side, and the output from the multiplier 18 corresponding to the decimal part of the reset timing ( | Wx | / | dx |) is multiplied by 2 / n (increment of one sampling period), and the output obtained by adding “−1” as the initial value is used as the initial value of the address of the window function at the time of reset. 75 fixed contacts are obtained. FIG. 10C shows the output of the changeover switch 75 * 2
An example is shown. Thus, the signal of * 2 is triggered by the reset timing, and has a slope of 2 / n, -1 to -1.
It becomes a signal that connects between +1 at n points.

The output * 2 from the changeover switch 74 is input to the absolute value circuit 76, and the output of the absolute value circuit 76 is applied to the window function table 77 as an address. As a result, reciprocal readout of movements of +1 to 0 to +1 is performed on the window function table 77, and address folding occurs after the point of n / 2. Therefore, a window function output * 3 corresponding to the window function characteristic illustrated in FIG. 10D is read from the window function table 77, as shown in FIG. FIG. 10B shows an example of a waveform output from the waveform generator 5, and in this example, a case where a pulse waveform is output is shown. As described above, this pulse waveform is a waveform that is reset at the zero cross point of the external input waveform Wx. This waveform is input to a delay circuit 78 of n / 2 stages (two stages in this example),
The waveform output delayed by the sampling period is input to an overflow protection type multiplier 79. The multiplier 79 is supplied with the output (* 3) of the window function table 77, and outputs n samples (4 in this case, 4 in this case) after the reset, as shown in FIG. A waveform output * 4 multiplied by the window function for the period of (sample) is output. As described above, according to this embodiment, since the reset timing output from the reset timing detecting means 2 is provided with the address generating means 7 whose reset phase is controlled, the window function can be reliably applied. become able to.

In the above embodiment, when the reset phase is calculated, the calculation is performed using the reciprocal table, but | Px ′ | / | fx | or | Wx | / |
Since it suffices to calculate dx |, it is natural that a division circuit may be used. Further, in the above embodiment, the reset timing is detected based on the zero crossing point of the input waveform. However, the reset timing is detected based on the peak point of the input waveform amplitude or the timing exceeding a predetermined threshold. The reset timing may be detected.

[0045]

As described above, according to the waveform generating method and apparatus of the present invention, it is possible to generate a waveform completely synchronized with externally applied phase information or an arbitrary waveform signal. In that case, a waveform having ideal characteristics multiplied by the window function can be generated.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of an embodiment of a waveform generation device to which a waveform generation method according to the present invention is applied.

FIG. 2 is a block diagram showing a configuration example of an embodiment in which a reset portion is multiplied by a window function.

FIG. 3 is a waveform chart for explaining the operation of the embodiment shown in FIG. 2;

FIG. 4 is a block diagram showing a configuration example of an embodiment in which both a waveform and a reset portion are multiplied by a window function;

FIG. 5 is a waveform chart for explaining the operation of the embodiment shown in FIG. 4;

FIG. 6 is a diagram showing a modification in which a pulse waveform is generated in the embodiment shown in FIG.

FIG. 7 is a block diagram showing a configuration example of an embodiment synchronized with an external input waveform.

FIG. 8 is a waveform chart for explaining the operation of the embodiment shown in FIG. 7;

9 is a block diagram showing a configuration example of an embodiment in which both the waveform and the reset unit of the embodiment shown in FIG. 7 are multiplied by a window function.

10 is a waveform chart for explaining the operation of the embodiment shown in FIG.

FIG. 11 is a diagram for explaining a problem in a case where oscillator synchronization is performed by digital processing.

FIG. 12 is a diagram showing a configuration of a conventional waveform generator.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 frequency calculating means, 2 reset timing detecting means, 3 reset phase calculating means, 4 phase information generating means, 5 waveform generator, 6 window function multiplying means, 7 address generator, 11, 23, 75, 78 delay circuit, 12 ,
15, 20, 21, 33, 41, 42, 51, 64, 7
2,73 adder, 13,16,31,34,43,7
6 Absolute value circuit, 14, 32 Reciprocal table, 17, 1
8, 19, 24, 26, 35, 37, 39, 44, 4
6, 48, 49, 50, 63, 71, 79 multiplier, 2
2, 74 changeover switch, 25, 38, 47, 77 window function table, 36, 45 minimum value selection circuit, 61 L
PF, 62 HPF

Claims (8)

[Claims] 1. A waveform generating method for generating a waveform synchronized with an external input signal, comprising: detecting a reset timing to reset phase information of a generated waveform based on the external input signal; Calculating the information corresponding to the frequency information of the external input signal assuming that the signal is a signal corresponding to the phase signal; based on the information corresponding to the frequency information, the external input signal and the fundamental frequency information of the generated waveform. Calculating a reset phase at the reset timing, setting phase information of the generated waveform at the reset timing to the reset phase, and generating a waveform based on the phase information of the waveform. A method for generating a waveform, comprising: 2. A step of generating a read signal for reading a window function in response to the reset timing based on the external input signal and information corresponding to frequency information of the external input signal; Reading the waveform and multiplying the generated waveform by the read waveform. Generating a first read signal for reading a window function corresponding to the reset timing based on the external input signal and information corresponding to frequency information of the external input signal; Generating a second read signal for reading a window function corresponding to a discontinuous portion of the waveform, reading a window function based on a read signal obtained by integrating the two read signals, and multiplying the generated waveform by the read function. 2. The method according to claim 1, further comprising the steps of: 4. The method according to claim 1, wherein the step of calculating the information corresponding to the frequency information of the external input signal is a step of calculating an increment of the external input signal for each sampling cycle. A method for generating a waveform according to any one of the preceding claims. 5. A waveform generator for generating a waveform synchronized with an external input signal, comprising: reset timing detecting means for detecting a reset timing at which phase information of a generated waveform should be reset based on the external input signal. Frequency information calculating means for calculating information corresponding to frequency information of the external input signal by regarding the external input signal as a signal corresponding to a phase signal; information corresponding to the frequency information; the external input signal; Reset phase calculation means for calculating a reset phase at the reset timing based on the basic frequency information of the waveform; and generating phase information based on the basic frequency information of the generated waveform, and calculating the phase information at the reset timing. A phase information generating unit configured to set the reset phase; Waveform generating apparatus characterized by having a waveform generating means for generating a waveform based on the phase information generated by the phase information generating means. 6. A window function reading means for reading a window function corresponding to said reset timing based on said external input signal and information corresponding to frequency information of said external input signal, and said window function reading means. 6. The waveform generating apparatus according to claim 5, further comprising a multiplying means for multiplying the waveform generated by said waveform generating means by the window function. 7. A means for generating a first read signal for reading a window function corresponding to the reset timing, based on the external input signal and information corresponding to frequency information of the external input signal; Means for generating a second read signal for reading a window function corresponding to a discontinuous portion of a waveform, and window function reading means for reading a window function based on a read signal obtained by integrating the first and second read signals. 6. The waveform generating apparatus according to claim 5, further comprising: a multiplying unit that multiplies the generated waveform by a window function read by the window function reading unit. 8. The apparatus according to claim 5, wherein said frequency information calculating means is means for calculating an increment for each sampling cycle of said external input signal.
The waveform generator according to the paragraph.