JP4563165B2 - Frequency synthesizer and reference signal phase setting method thereof - Google Patents

Description

  The present invention relates to a frequency synthesizer and its reference signal phase setting method.

  Conventionally, a frequency synthesizer that outputs a signal synchronized with a reference signal using a PLL (Phase Locked Loop) circuit is known. There is also a digital frequency synthesizer using a DDS (Direct Digital Synthesizer). Such a frequency synthesizer stores trigonometric function data in a ROM (Read Only Memory), and reads out this data to directly generate a sine wave.

  Furthermore, there is also a frequency synthesizer that uses a triangular wave data instead of a sine wave and performs linear interpolation to output a signal synchronized with a reference signal without using a ROM (for example, see Patent Document 1).

  In this frequency synthesizer, it is not necessary to provide a ROM, and a folded spectrum is not generated. Therefore, a filter for removing the folded spectrum is also unnecessary. For this reason, this frequency synthesizer is expected to reduce the circuit scale.

  Such a digital frequency synthesizer includes a reference signal generation unit and a PLL circuit. The reference signal generation unit includes a triangular wave conversion circuit, a D / A converter, a linear interpolation circuit, and a comparator. The triangular wave conversion circuit generates triangular wave data corresponding to the phase of the reference signal, and the D / A converter converts the generated differential data between adjacent samples of the triangular wave into analog data.

  The linear interpolation circuit samples and holds this analog data and integrates it. The comparator detects the zero cross timing of the output voltage of the linear interpolation circuit. The PLL circuit compares the phase of the zero cross timing detected by the comparator with the phase of the output signal of the PLL circuit, and outputs a signal having a frequency synchronized with the phase of the reference signal.

A system clock is supplied to the reference signal generator, and the reference signal generator resets the linear interpolation circuit in synchronization with the system clock and cancels the reset.
Japanese Patent Laid-Open No. 5-206732 (page 3-4, FIG. 1)

  However, an offset error may occur in the D / A converter included in the reference signal generation unit. The deviation of the zero-cross timing of the output voltage due to this offset error increases as the time from the reset timing elapses. In the conventional frequency synthesizer, the linear interpolation circuit is reset in synchronization with the system clock. Normally, the relative position between the system clock and the zero cross timing always varies, and therefore the time interval between the reset timing and the zero cross timing also constantly varies. Therefore, the magnitude of the time difference between the zero cross timing obtained when this D / A converter has this offset error and the regular zero cross timing also varies. The VCO (Voltage Controlled Oscillators) control voltage of the PLL circuit controlled by the reference timing signal created from the zero cross timing fluctuates as shown in FIG.

  Along with this, the frequency of the output signal also varies. The simulation result of the frequency fluctuation characteristic at this time is shown in FIG. The simulation conditions are a phase comparison frequency of 8051 kHz, a PLL circuit frequency divided by 50, a D / A converter offset error of 0.3%, and a secondary distortion of 0.3%. The fluctuation range of the frequency is 213 kHz with a period of 2.9 μs. Further, the frequency spectrum at this time has a characteristic as shown in FIG. 9, and the interference (noise) spectrum is included in the frequency characteristic, and the frequency characteristic is lowered.

  Even in a frequency synthesizer using DDS, if a non-linear offset error exists in the D / A converter, a harmonic distortion spectrum is generated. However, this spectrum can be removed by using an analog filter.

  On the other hand, since a frequency synthesizer using triangular wave data cannot use such an analog filter, the nonlinearity of analog data due to an offset error of the D / A converter cannot be corrected. Therefore, in this frequency synthesizer, high accuracy is required for the D / A converter.

  The present invention has been made in view of such conventional problems, and an object of the present invention is to provide a frequency synthesizer and a reference signal phase setting method thereof that can improve frequency characteristics.

In order to achieve this object, a frequency synthesizer according to the first aspect of the present invention provides:
In a frequency synthesizer that outputs a synchronization signal whose phase is synchronized with the phase of the reference signal,
A digital-analog converter that sequentially converts the difference data of the phase data indicating the phase of the reference signal into analog data;
A voltage signal generation unit that generates a voltage signal obtained by interpolating between a signal level corresponding to the phase data and a signal level by integrating the analog data converted by the digital / analog conversion unit;
A reference timing signal output unit that outputs a reference timing signal indicating a specific phase of the reference signal at a crossing timing at which a signal level of the voltage signal generated by the voltage signal generation unit and a preset setting voltage intersect;
A reset control unit that resets the voltage signal generated by the voltage signal generation unit to the set voltage when the reference timing signal output unit outputs the reference timing signal, and is supplied with a reset release signal to release the reset; ,
A timing setting unit that sets the reset release timing based on the reference timing signal output by the reference timing signal output unit so that the time between the intersection timing and the reset release timing for releasing the reset is constant;
A reset release signal supply unit that supplies the reset release signal to the reset control unit at a reset release timing set by the timing setting unit.

A phase difference in which the output timing of the reference timing signal output from the reference timing signal output unit is compared with the output timing of the comparison timing signal generated based on the synchronization signal, and the output timing difference between the two signals is indicated by a signal level A phase comparator that outputs a signal;
A synchronization signal generation unit that corrects and sets a frequency based on a signal level of the phase difference signal output by the phase comparison unit, and generates the synchronization signal of the corrected and set frequency,
The timing setting unit generates the reset release signal based on the synchronization signal generated by the synchronization signal generation unit and supplies the reset release signal to the reset control unit.
The timing setting unit delays the signal generated based on the synchronization signal generated by the synchronization signal generation unit, and outputs the delayed signal as the comparison timing signal to the phase comparison unit, so that the reset release timing May be set a certain time before the intersection timing.

The reference signal phase setting method of the frequency synthesizer according to the second aspect of the present invention includes:
A method of setting a reference signal phase of a frequency synthesizer that outputs a synchronization signal whose phase is synchronized with the phase of the reference signal,
Sequentially converting differential data of phase data indicating the phase of the reference signal into analog data;
Generating a voltage signal obtained by interpolating between a signal level corresponding to the phase data and a signal level by integrating the converted analog data;
Outputting a reference timing signal indicating a specific phase of the reference signal when the generated voltage signal and a preset setting voltage intersect with each other;
Resetting the voltage signal to the set voltage when the reference timing signal is output;
Setting the reset release timing based on the reference timing signal so that the time between the intersection timing and the reset release timing for releasing the reset is constant;
Setting the phase of the reference signal by releasing the reset at the set timing.

  According to the present invention, the frequency characteristics can be improved.

Hereinafter, an apparatus according to an embodiment of the present invention will be described with reference to the drawings.
The configuration of the frequency synthesizer according to this embodiment is shown in FIG.
The frequency synthesizer according to the present embodiment includes a PLL circuit 1 and a reference signal generation unit 2.

  This frequency synthesizer uses a voltage signal as shown in FIG. 2 in which a reference signal is linearly interpolated instead of DDS (Direct Digital Synthesizer), and synchronizes the phase of the clock VCO_CLK as a synchronizing signal with the phase of the reference signal. It is a thing.

  Further, as shown in FIG. 2, the frequency synthesizer is configured to cancel the reset at a time t11 that is a predetermined time TX before the zero cross timing t12.

  That is, the frequency synthesizer is configured to make the time between the reset release timing and the zero cross timing as the cross timing constant, and is not affected by the offset error of the D / A converter 204.

  The PLL circuit 1 shown in FIG. 1 generates a synchronization signal whose phase is synchronized with the phase of the reference signal output from the reference signal generation unit 2. The PLL circuit 1 includes a phase comparator 101, an LPF (Low Pass Filter) 102, a VCO 103, an N frequency dividing counter 104, and a timing setting unit 105.

  The phase comparator 101 compares the output timing of the reference timing signal output from the reference signal generation unit 2 with the output timing of the comparison timing signal output from the timing setting unit 105, and indicates the output timing difference between the two signals as a signal level. Phase difference A phase difference signal is generated.

  The LPF 102 removes a high frequency component from a preset cutoff frequency of the phase difference signal generated by the phase comparator 101.

  The VCO 103 corrects and sets the frequency based on the signal level of the phase difference signal from which the high-frequency component has been removed, and generates a clock VCO_CLK having the frequency fout as a synchronization signal of the corrected and set frequency. The frequency synthesizer The clock VCO_CLK generated by the VCO 103 is output.

  The N-dividing counter 104 counts the clock VCO_CLK output from the VCO 103 and generates the pulse signal Pn every time it counts N, thereby dividing the clock VCO_CLK by N. The N frequency dividing counter 104 supplies the generated pulse signal Pn to the timing setting unit 105. Further, the N frequency dividing counter 104 supplies the pulse signal Pn to the reference signal generation unit 2 as a reset release signal.

  The timing setting unit 105 sets the reset release timing based on the reference timing signal output from the reference signal generation unit 2 so that the time between the zero timing and the reset release timing is constant.

  The timing setting unit 105 delays the pulse signal Pn, and outputs the signal Sv to the phase comparator 101 using the delayed signal as a comparison timing signal. The signal S12 is output at zero cross timing, and the cycle of the pulse signal Pn is determined by the cycle of the signal S12. For this reason, the timing setting unit 105 sets the reset release timing a certain time before the zero cross timing based on the reference timing signal.

  The timing setting unit 105 includes DFFs 5-1 to 5-p (p is a natural number). The DFFs 5-1 to 5-p sequentially delay and output the pulse signal Pn output from the N frequency dividing counter 104 in synchronization with the clock VCO_CLK output from the VCO 103.

  The input terminal of DFF5-1 is connected to the output terminal of the N frequency dividing counter 104, and the input terminals of DFF5-2 to 5-p are sequentially connected to the output terminals of DFF5-1 to 5- (p-1). Is done. The output terminal of DFF5-p is connected to one input terminal of the phase comparator 101.

  When a signal is supplied to the input terminal, each of the DFFs 5-1 to 5-p outputs the signal supplied to the input terminal at the rising timing of the next clock VCO_CLK from the output terminal.

  As described above, the timing setting unit 105 includes the DFFs 5-1 to 5-p, so that when the pulse signal Pn is supplied from the N-dividing counter 104, the pulse signal Pn is delayed by a preset time TX. Let Then, the timing setting unit 105 generates a signal Sv as a comparison timing signal for comparison with the output timing of the signal S12 as the reference timing signal, and supplies the generated signal Sv to the phase comparator 101. Note that the number p of the DFFs 5-1 to 5-p is set in advance based on the time TX and the cycle Tvco of the clock VCO_CLK of the VCO 103.

  The reference signal generator 2 operates in synchronization with the supplied system clock CLK, and generates a reference timing signal to be supplied to the PLL circuit 1. The reference signal generation unit 2 includes a phase generation unit 201, a delay circuit unit 202, a subtractor 203, a D / A converter 204, a current source 205, a linear interpolation circuit 206, a comparator 207, and a reset unit 208. A reset control unit 209, a zero cross detector 210, and a DFF 211.

  The phase generation unit 201 is supplied with the frequency data d1 and the modulation data d2, and generates phase data for generating a reference signal in synchronization with the system clock CLK. The phase generation unit 201 includes a phase accumulator 221 and an adder 222. Become.

  The phase accumulator 221 integrates the supplied frequency data d1, and includes an adder 223 and a delay device 224.

  The adder 223 adds the supplied frequency data d1 and the output data of the delay unit 224 to generate integral data. The delay unit 224 supplies the integration data output from the adder 223 to the adder 223.

  The adder 223 has a preset number of bits, and the integral data overflows when the number of bits is exceeded. Therefore, the waveform of the data output from the phase accumulator 221 is a sawtooth waveform.

  The adder 222 generates phase data d11 based on the frequency data d1 and the modulation data d2. The phase generation unit 201 supplies the generated series of phase data d11 to the delay circuit unit 202 as a phase data string.

  The delay circuit unit 202 delays the phase data in order to make the zero cross timing correspond to the detection timing of the phase inversion of the zero cross detector 210. The delay circuit unit 202 includes registers (denoted as “REG” in the drawing) 231 to 235.

  The registers 231 to 235 output the supplied phase data d11 to d15 as phase data d12 to d16 in synchronization with the next rising edge of the system clock CLK. The input terminal of the register 231 is connected to the output terminal of the adder 222, and the input terminals of the registers 232 to 235 are connected to the output terminals of the registers 231 to 234, respectively.

  The subtracter 203 is for subtracting the phase data d16 output from the register 235 from the phase data d15 output from the register 234 to obtain difference data d17 between the two phase data. The subtracter 203 is connected between the output terminal of the register 234 and the output terminal of the register 235. Then, the subtractor 203 supplies the acquired difference data d17 to the D / A converter 204.

  The D / A converter 204 converts the difference data d17 supplied from the subtracter 203 into analog data.

  The current source 205 and the linear interpolation circuit 206 integrate the analog data converted by the D / A converter 204 to generate a voltage signal obtained by linear interpolation between the signal level corresponding to the phase data d11 and the signal level. Is.

  The current source 205 generates a current having a current value corresponding to the analog data converted by the D / A converter 204 and supplies the current to the linear interpolation circuit 206. The linear interpolation circuit 206 linearly interpolates the signal level of the reference signal on the time axis to generate a signal S11 as a voltage signal.

  The comparator 207 compares the voltage of the signal S11 output from the linear interpolation circuit 206 with a preset zero voltage, and at the zero cross timing at which the signal level of the signal S11 and the zero voltage intersect, The signal S12 is output. This reference timing signal is a signal indicating a specific phase of the reference signal. The comparator 207 outputs an H (high) level signal S12 when the negative voltage of the signal S11 output from the linear interpolation circuit 206 intersects the zero voltage as the set voltage.

  A mask circuit (not shown) for masking the signal S12 is provided at the output terminal of the comparator 207 so that the signal level of the signal S12 does not become H level even if the signal S11 exceeds the zero voltage except near the zero cross timing. Connected.

  The reset unit 208 is turned on to reset the voltage of the signal S11 of the linear interpolation circuit 206 to zero voltage.

  The reset controller 209 resets the signal S11 to zero voltage when the H level signal S12 is output from the comparator 207, and the H level pulse signal Pn is output from the N frequency dividing counter 104 of the PLL circuit 1. The reset is canceled when

  The reset control unit 209 turns on the reset unit 208 to reset the voltage of the signal S11 to zero voltage when the signal S12 output from the comparator 207 becomes H level.

  When the pulse signal Pn output from the N frequency dividing counter 104 of the PLL circuit 1 rises to H level, the reset control unit 209 turns off the reset unit 208 and releases the reset.

  The zero cross detector 210 compares the phase data d12 and d13 and detects the inversion of both phases, thereby predicting the zero cross timing of the signal S11. The zero cross detector 210 predicts that the zero cross timing is reached when the phase data d12 and d13 are positive and negative, respectively.

  The DFF 211 outputs a reset signal to the registers 234 to 235 in synchronization with the next rising edge of the system clock CLK when the zero cross detector 210 predicts the zero cross timing. An input terminal of the DFF 211 is connected to an output terminal of the zero cross detector 210, and an output terminal of the DFF 211 is connected to reset terminals of the registers 234 to 235.

  When the zero cross detector 210 detects the zero cross timing, the zero cross detector 210 resets the registers 234 to 235 via the DFF 211.

Next, the operation of the frequency synthesizer according to this embodiment will be described.
The phase generation unit 201 outputs a data string of phase data d11 as shown in FIG. 3 to the delay circuit unit 202 in synchronization with the system clock CLK. The subscripts _- and ₊ indicate the positive and negative phase data, respectively.

At time t21, the register 232 is phase data d13 = B _- outputs, when the register 231 has output the phase data d12 = _{C +,} zero cross detector 210 detects a zero-cross timing.

  When the system clock CLK rises at time t22, the zero cross detector 210 resets the registers 234 to 235 via the DFF 211. When the D / A converter 204 is reset, the phase data d17 becomes zero.

At time t23, when the system clock CLK rises, the subtractor 203, the phase data d15 = B the register 234 has output _- from the register 235 by subtracting the phase data d16 = 0 outputted difference data d17 = B _- generate To the D / A converter 204. D / A converter 204, phase data d17 = B _- converting the analog data.

  As shown in FIG. 4, the current source 205 supplies a current having a current value corresponding to the analog data to the linear interpolation circuit 206. Since the data B is negative, the voltage of the signal S11 of the linear interpolation circuit 206 decreases.

As shown in FIG. 3, at time t24, when the system clock CLK rises, the subtractor 203, the phase data d16 = B phase data d15 = _{C +} from the register 235 register 234 is output is output _- subtracted, Difference data d17 = C ₊ -B ₋ is generated and supplied to the D / A converter 204. The D / A converter 204 converts the phase data d17 = C ₊ -B ₋ into analog data.

As shown in FIG. 4, the current source 205 supplies a current having a current value corresponding to the phase data d17 = C ₊ -B ₋ to the linear interpolation circuit 206, and the voltage of the signal S11 increases.

  When the voltage of the signal S11 exceeds the zero voltage, the comparator 207 outputs the H-level signal S12 to the phase comparator 101 as a signal indicating a specific phase of the reference signal. The comparator 207 also outputs the H level signal S12 to the reset control unit 209 as a reset signal.

  When the H level signal S12 is supplied from the comparator 207, the reset control unit 209 outputs the H level signal S13 to the reset unit 208, turns on the reset unit 208, and resets the voltage of the signal S11 to zero voltage. . When the voltage of the signal S11 is reset to zero voltage, the comparator 207 sets the signal level of the signal S12 to L level. Accordingly, the comparator 207 outputs the pulsed signal S12 to the phase comparator 101.

  On the other hand, the N frequency dividing counter 104 supplies the H level pulse signal Pn to the reset control unit 209 when the number of clocks of the clock VCO_CLK is counted as N.

  When the H-level pulse signal Pn is supplied from the N-dividing counter 104, the reset control unit 209 supplies the L-level signal S13 to the reset unit 208, turns off the reset unit 208, and cancels the reset of the signal S11. To do.

  Further, the N frequency dividing counter 104 outputs the pulse signal Pn to the timing setting unit 105 when the number of clocks of the clock VCO_CLK is counted as N.

  The timing setting unit 105 outputs an H level signal Sv to the phase comparator 101 when time TX = Tvco × p has elapsed since the pulse signal Pn was supplied.

  The phase comparator 101 compares the rising timing of the signal S12 output from the comparator 207 with the rising timing of the signal Sv. As a result of the comparison, the phase comparator 101 outputs a phase difference signal indicating the timing difference between the two signals as a signal level to the LPF 102. When the phase of the signal S12 is ahead of the phase of the signal Sv, the phase comparator 101 outputs to the LPF 102 a phase difference signal that increases the VCO oscillation frequency and advances the phase of the signal Sv.

  When the phase of the signal Sv is ahead of the phase of the signal S12, a phase difference signal that lowers the VCO transmission frequency and delays the phase of the signal Sv is output to the LPF 102. The LPF 102 removes higher frequency components than the cutoff frequency of the phase difference signal output from the phase comparator 101.

  The VCO 103 sets the frequency fout based on the phase difference indicated by the phase difference signal, and outputs the clock VCO_CLK.

  When the reset of the linear interpolation circuit 206 is released, the signal level of the output signal S11 of the linear interpolation circuit 206 gradually increases due to the error of the D / A converter 204, as shown in FIG. When the signal level of the signal S11 increases, the zero cross timing when there is no error in the D / A converter 204 is set as a normal timing, and the zero cross timing when there is an error in the D / A converter 204 is higher than the normal timing It will be faster.

  However, the amount of deviation from the normal timing of the zero cross timing is constant by canceling the reset of the signal S11 at a timing that is a preset time TX before the zero cross timing when there is an error in the D / A converter 204. become.

  When the frequency fluctuation characteristic in this case is simulated, the frequency fluctuation characteristic becomes a characteristic as shown in FIG. The conditions for this simulation are the phase comparison frequency of 8051 kHz, the PLL circuit frequency divided by 50, the D / A converter offset error of 0.3%, and the secondary distortion of 0.3%, as in the prior art.

  As shown in FIG. 6, the simulation result of the frequency fluctuation of the conventional frequency synthesizer was a maximum of 213 kHz with a period of 2.9 μs, whereas the simulation result of the frequency fluctuation of this embodiment is a maximum of 48 kHz.

  As described above, according to the present embodiment, the N frequency dividing counter 104 outputs the pulse signal Pn for causing the reset control unit 209 to cancel the reset of the signal S11. The timing setting unit 105 delays the pulse signal Pn output from the N-dividing counter 104 at this time for a predetermined time, and outputs the delayed signal Sv to the phase comparator 101.

  Therefore, the reset of the signal S11 is released before this zero cross timing, and the time position between the reset release timing and the zero cross timing is made constant regardless of the error of the D / A converter 204. be able to. For this reason, the interference (noise) spectrum due to fluctuations in the control voltage of the VCO 103 can be reduced, and the frequency characteristics can be improved.

In carrying out the present invention, various forms are conceivable and the present invention is not limited to the above embodiment.
For example, in the above embodiment, the crossing voltage is described as zero voltage. However, the crossing voltage may not be a zero voltage and may be set to a desired voltage.

It is a block diagram which shows the structure of the frequency synthesizer which concerns on embodiment of this invention. It is a figure which shows the outline | summary of operation | movement of the frequency synthesizer which concerns on this embodiment. It is a timing chart which shows operation of a frequency synthesizer concerning this embodiment. It is a timing chart which shows the detailed operation | movement of the frequency synthesizer which concerns on this embodiment. It is a figure which shows the simulation result of the frequency fluctuation of the frequency synthesizer which concerns on this embodiment. It is a figure which shows the simulation result which represented the frequency variation shown in FIG. 5 with the spectrum. It is a figure which shows the control voltage of VCO of the conventional frequency synthesizer. It is a figure which shows the simulation result of the frequency fluctuation of the conventional frequency synthesizer. It is a figure which shows the simulation result which represented the frequency variation shown in FIG. 8 with the spectrum.

Explanation of symbols

1 PLL circuit 2 Reference signal generator 101 Phase comparator 103 VCO
104 N frequency dividing counter 105 Timing setting unit 201 Phase generation unit 202 Delay circuit unit 204 D / A converter 206 Linear interpolation circuit 207 Comparator 208 Reset unit 209 Reset control unit 210 Zero cross detector

Claims (3)

In a frequency synthesizer that outputs a synchronization signal whose phase is synchronized with the phase of the reference signal,
A digital-analog converter that sequentially converts the difference data of the phase data indicating the phase of the reference signal into analog data;
A voltage signal generation unit that generates a voltage signal obtained by interpolating between a signal level corresponding to the phase data and a signal level by integrating the analog data converted by the digital / analog conversion unit;
A reference timing signal output unit that outputs a reference timing signal indicating a specific phase of the reference signal at a crossing timing at which a signal level of the voltage signal generated by the voltage signal generation unit and a preset setting voltage intersect;
A reset control unit that resets the voltage signal generated by the voltage signal generation unit to the set voltage when the reference timing signal output unit outputs the reference timing signal, and is supplied with a reset release signal to release the reset; ,
A timing setting unit that sets the reset release timing based on the reference timing signal output by the reference timing signal output unit so that the time between the intersection timing and the reset release timing for releasing the reset is constant;
A reset release signal supply unit that supplies the reset release signal to the reset control unit at a reset release timing set by the timing setting unit;
With
This is a frequency synthesizer. A phase difference in which the output timing of the reference timing signal output from the reference timing signal output unit is compared with the output timing of the comparison timing signal generated based on the synchronization signal, and the output timing difference between the two signals is indicated by a signal level A phase comparator that outputs a signal;
A synchronization signal generation unit that corrects and sets a frequency based on a signal level of the phase difference signal output by the phase comparison unit, and generates the synchronization signal of the corrected and set frequency,
The timing setting unit generates the reset release signal based on the synchronization signal generated by the synchronization signal generation unit and supplies the reset release signal to the reset control unit.
The timing setting unit delays the signal generated based on the synchronization signal generated by the synchronization signal generation unit, and outputs the delayed signal as the comparison timing signal to the phase comparison unit, so that the reset release timing Is set a certain time before the intersection timing,
The frequency synthesizer according to claim 1. A method of setting a reference signal phase of a frequency synthesizer that outputs a synchronization signal whose phase is synchronized with the phase of the reference signal,
Sequentially converting differential data of phase data indicating the phase of the reference signal into analog data;
Generating a voltage signal obtained by interpolating between a signal level corresponding to the phase data and a signal level by integrating the converted analog data;
Outputting a reference timing signal indicating a specific phase of the reference signal when the generated voltage signal and a preset setting voltage intersect with each other;
Resetting the voltage signal to the set voltage when the reference timing signal is output;
Setting the reset release timing based on the reference timing signal so that the time between the intersection timing and the reset release timing for releasing the reset is constant;
Setting the phase of the reference signal by releasing the reset at the set timing, and
A reference signal phase setting method for a frequency synthesizer.