JP2001008202A - Moving image encoding method, moving image encoding device, and moving image recording device using the same - Google Patents

Abstract

(57) [Summary] [Problem] To convert a non-interlaced video signal to MP
The encoding can be performed correctly according to the EG2 standard. SOLUTION: A vertical synchronization signal detection circuit 1 generates a vertical synchronization pulse v from a vertical synchronization signal of an input moving image signal p, and generates an inverted field pulse f whose level is inverted for each vertical synchronization pulse v. Circuit 3
Generated by The frame synchronization pulse generation circuit 4
Generates a frame synchronization pulse s having a two-field period of the input moving image signal p from the vertical synchronization pulse v and the inverted field pulse f. The encoding processing circuit 5 fetches the input moving image signal p in pairs on the basis of the frame synchronization pulse s in two fields and performs encoding processing. In this case, the two fields forming a pair are coded as a top field and the other as a bottom field according to the level of the inverted field pulse f.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a moving picture coding apparatus for coding a moving picture and a moving picture recording apparatus for recording a code coded by the moving picture coding apparatus. The present invention relates to a technique for encoding a moving image signal.

[0002]

2. Description of the Related Art As a moving picture coding method, MPEG is used.
The two standards are well known, are applied to various applications, and have become international standards for moving picture coding methods. The MPEG2 standard is described in detail, for example, in the Journal of the Institute of Television Engineers of Japan, Vol. 49 No. 4 (1995), pp. 435-458.

[0003] The MPEG2 standard is a general-purpose standard on the premise that it is applied to various applications such as broadcasting, communication, and storage media. However, moving image signals to be encoded are standardized such as the NTSC system and the PAL system. Format.

[0004] On the other hand, there are many moving images that do not conform to a standard format (that is, non-standard type). The reason why such non-standard moving images are widely used is that they can be displayed on a general television monitor even if they do not necessarily conform to a standard format. A typical example is a moving image signal output from a game device. The MPEG2 standard accepts only an interlaced image signal having a field frequency of 60 Hz as a moving image signal that can be displayed on an NTSC television monitor, but a moving image signal output from a game device has a field frequency Is 60Hz
Progressive image signal (an odd-field or even-field continuous image signal and a non-interlaced non-interlaced moving image signal) in which the number of lines in the vertical direction is half that of the interlaced image signal. This is because, depending on the scene, it is easier to see the image when it is progressive.

A recording apparatus that encodes a moving image signal and records it on a recording medium may be used for switching a plurality of moving image sources, such as switching the channel of a tuner. Normally, these moving image sources are not synchronized with each other, so that the synchronization is discontinuous at the time of switching. For this reason, a moving image obtained by switching a plurality of moving image sources does not conform to the standard format, and cannot be coded in the MPEG2 standard as it is.

[0006]

In order to encode a non-standard video signal according to the MPEG2 standard as described above, a frame synchronizer is conventionally provided in front of the encoding means, thereby providing a standard synchronizer. Although the video signal is converted into a standard video signal conforming to the format, the frame synchronizer requires a frame memory, which causes a problem that the circuit scale is increased and the cost is increased.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problem, and to provide a moving picture encoding system capable of encoding a non-standard moving picture signal in accordance with the MPEG2 standard with a simple circuit configuration without using a frame synchronizer. An apparatus and a moving image recording apparatus are provided.

[0008]

In order to attain the above object, the present invention provides an inverted field pulse generating means for generating an inverted field pulse whose level is inverted for each field of an input moving image signal comprising a series of field images. When,
Frame synchronizing pulse generating means for generating a frame synchronizing pulse synchronized with the inversion field pulse; and by using the frame synchronizing pulse, successive fields of the input moving image signal are paired by two fields, and the input moving image signal is paired. And an encoding means for encoding the data.

With this configuration, even if the input moving image signal is a non-interlaced moving image, the coding is performed as a pair of two fields, so that the coding according to the MPEG2 standard can be performed.

Further, according to the present invention, in the above configuration, a field discriminating means for discriminating a type of a field of the input moving image signal and generating a field discriminating pulse of a level corresponding to the type, Encoding start control means for generating an encoding start command prior to the start of the encoding process, wherein the inversion field pulse generating means responds to the level of the field discrimination pulse at the time of generation of the encoding start command. The level of the inversion field pulse is set to the initial level.

With this configuration, even if the input moving image signal is non-interlaced or interlaced, encoding according to the MPEG2 standard can be performed from the start of the encoding operation. In particular, when the input video signal is interlaced, the first field of the pair can be a recording field, and the second field can be an even field, and encoding according to the MPEG2 standard is reliably performed. .

Further, the present invention provides the above-mentioned configuration,
A field discriminating means for discriminating a type of a field of the input moving image signal and generating a field discrimination pulse having a level corresponding to the type; and a polarity between the inverted field pulse and the field discrimination pulse continuously mismatching. The inversion detecting means for detecting that the polarity between the inverted field pulse and the field discriminating pulse are continuously inconsistent with each other. Is temporarily stopped, and when the continuous inversion detecting means does not detect that the polarity between the inverted field pulse and the field discrimination pulse is continuously inconsistent, an encoding start command is issued. Thereafter, an encoding start / stop control unit for canceling the suspension of the encoding processing operation of the encoding unit is provided. Inverted field pulse generating means configured to set the level of the inverted field pulse to an initial level corresponding to the level of the field discrimination pulse generation timing of the coding start command.

With this configuration, when the moving image source is switched to a new input moving image signal, the polarity between the inversion field pulse and the field discrimination pulse may be inverted, but this polarity inversion is continuous. Accordingly, it is determined that the video source has been switched, and the operation of the encoding unit is temporarily stopped. When the polarity between the inverted field pulse and the field discrimination pulse is matched by the encoding start command as described above, the code is output. Since the operation of the demultiplexing means is resumed, even if the moving image source is switched to a new input moving image signal, or if the new input moving image signal is interlaced or non-interlaced, Encoding according to the MPEG2 standard is surely performed.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of a moving picture coding apparatus according to the present invention, wherein 1 is a vertical synchronizing signal detecting circuit, 2 is a horizontal synchronizing signal detecting circuit, 3 is an inverted field pulse generating circuit, Is a frame synchronization pulse generation circuit, and 5 is an encoding processing circuit. FIG. 2 is a timing chart showing the operation of the first embodiment.
Are assigned the same reference numerals.

In FIGS. 1 and 2, an input moving image signal p
Is supplied to the encoding processing circuit 5. Here, it is assumed that the input moving image signal p is a non-interlaced moving image. The vertical synchronizing signal detecting circuit 1 detects a vertical synchronizing signal indicating the head of each field from the input moving image signal p to generate a vertical synchronizing pulse v. The horizontal synchronizing signal detecting circuit 2 The horizontal synchronizing signal is detected from the image signal p to generate a horizontal synchronizing pulse h. The vertical synchronizing pulse v and the horizontal synchronizing pulse h are supplied to the encoding processing circuit 5.

On the other hand, a vertical synchronization pulse v output from the vertical synchronization signal detection circuit 1 is supplied to an inverted field pulse generation circuit 3 and a frame synchronization pulse generation circuit 4.

The inversion field pulse generation circuit 3 generates an inversion field pulse f whose level is inverted to 0 or 1 every time the vertical synchronizing pulse v is supplied.
To supply. This inverted field pulse f has a level of 0 in every other field of the input moving image signal p,
The level is 1 in every other field. In addition,
The inversion field pulse generation circuit 3 can be configured by, for example, a D-type flip-flop circuit that uses the vertical synchronization pulse v as a clock CK and outputs Q as data D latched by the clock CK.

The frame synchronization pulse generation circuit 4 generates a frame synchronization pulse s which is phase-synchronized with the inverted field pulse f in a two-field cycle from the vertical synchronization pulse v and the inverted field pulse f, and supplies the frame synchronization pulse s to the encoding processing circuit 5. . The frame synchronization pulse generation circuit 4 can be constituted by, for example, an AND gate. In this case, after adjusting the phase of the vertical synchronization pulse v by the processing time of the inversion field generation circuit 3, the vertical synchronization pulse v And the inverted field pulse f are supplied to this AND gate. As a result, as shown in FIG. 2, a frame synchronization pulse s is obtained at the head of the inverted field pulse f at level 1.

The coding processing circuit 5 performs coding by taking in the two fields of the input moving picture signal p as a set (hereinafter, the two fields to be combined are referred to as a pair) based on the frame synchronization pulse s. The encoding processing is performed on the captured image data of the input moving image signal p with reference to the vertical synchronization pulse v and the horizontal synchronization pulse h. In this case, the first field in the pair defined by the frame synchronization pulse s is the top field because the level of the inverted field pulse f at this time is 1, and the second field in this pair is Since the level of the inverted field pulse f at this time is 0, encoding processing according to the MPEG2 standard is performed for each pair as a bottom field. Here, since the input moving image signal p is a non-interlaced moving image, the first field of the pair is treated as a pseudo odd field, and the second field is treated as a pseudo even field.

FIG. 3 is a conceptual diagram showing a spatial position of a line for each field of a moving image in the first embodiment.

FIG. 3A shows an input moving picture signal p of a non-interlaced moving picture. The coding is performed in the top field first (the vertical position of the first field is displayed on the upper side of the screen). ). Here, two adjacent fields 0 and 1, 2
, 3, 4, 5,... Form a pair and form a frame unit, every other field 0, 2, 4,. ,
.. Are the second fields of each pair. In such an input moving image signal p, the vertical positions of the lines having the same arrangement order match in all the fields.

FIG. 3B shows an encoded moving image signal obtained by encoding the input moving image signal p by the encoding processing circuit 5. In the encoding processing circuit 5, FIG.
In each pair of the input moving image signals p shown in FIG. 1, the first field is taken as the top field, and the second field is taken as the bottom field, and MPEG2
In order to be encoded according to the standard, the encoded video signal is
As shown in (b), the second field (field 1, field 1)
,...) Are vertically displaced downward by a half of the line interval from the line corresponding to the order of the first field (fields 0, 2, 4,...). That is, in each pair, the first field and the second field have an interlaced relationship.

As described above, in the first embodiment, a non-interlaced moving image can be encoded as an interlaced moving image with a simple circuit configuration.

In the first embodiment, the non-interlaced moving image is formed as an interlaced moving image by shifting the line position of the second field in the vertical direction. Vertical blurring occurs.

FIG. 4 is a block diagram showing a second embodiment of the moving picture coding apparatus according to the present invention which eliminates such vertical blurring of the screen.
Reference numeral 7 denotes a polarity inversion detection circuit, and reference numeral 8 denotes a field interpolation circuit. The same reference numerals are given to portions corresponding to those in FIG. FIG. 5 is a timing chart showing the operation of the second embodiment, and the same reference numerals are given to the signals corresponding to FIG.

In FIGS. 4 and 5, the field discriminating circuit 6 determines the input moving image from the phase relationship between the vertical synchronizing pulse v from the vertical synchronizing signal detecting circuit 1 and the horizontal synchronizing pulse h from the horizontal synchronizing signal detecting circuit 2. The polarity (odd / even field) of each field of the signal p is determined, and a field determination signal f 'is output which has a level 1 if the field is odd and a level 0 if the field is even. Here, since the input moving image signal p is a non-interlaced moving image, the input moving image signal p is composed of a repetition of a field corresponding to one of an odd field and an even field in an interlaced moving image. Here, it is assumed that the field is a repetition of a field corresponding to an odd field, and therefore, the field discrimination signal f 'is fixed at level 1.

In the field discriminating circuit 6, for example, if the cycle of the horizontal synchronizing pulse h is Th,
The pulse width Tv of the vertical synchronization pulse v is set to Th / 2 <Tv <T
By setting h, it is possible to configure a latch circuit using the horizontal synchronization pulse h as a latch pulse and the vertical synchronization pulse v as data.

The polarity reversal detection circuit 7 calculates the inversion field pulse f from the field discrimination signal f ′ and the inversion field pulse f from the inversion field pulse generation circuit 3.
Is determined with respect to the level of the field determination signal f ′ (when the level is inverted between the two pulses, these pulses are said to have inverted polarity). ), And outputs a polarity inversion detection signal i representing the result of the determination. This polarity inversion detection signal i
As shown in FIG. 5, when the inverted field pulse f is at level 1, the level becomes 0 when the inverted field pulse f is at level 0, and when the inverted field pulse f is at level 0, the level becomes 1 with respect to the level 1 field discrimination signal f '. Therefore, the polarity inversion detection circuit 7 can be constituted by, for example, a NAND gate or an ExOR circuit.

Thus, the polarity inversion detection signal i is
The level becomes 1 during the period of the second field of the two fields paired by the frame synchronization signal s in the input moving image signal p. The field interpolation circuit 8 uses the polarity inversion detection signal i as a basis. Thus, the period of the second field is determined for each pair of the input moving image signal p, and this period is subjected to field interpolation. In the field interpolation, a field having a relation of an even field interlaced with the first field is generated from the first field, and the field is interpolated as the second field during this period. The moving image signal p ′ is
This is a pseudo-interlaced moving image. here,
As shown in FIG. 5, the second field as an even field generated for each pair is defined as fields 1 ′, 3 ′,
5 ′,..., And from the field interpolation circuit 8,
A moving image signal p 'which is pseudo-interlaced moving image
Is output in units of pairs, that is, the first field is taken as the top field and the interpolated second field is taken as the bottom field, and is taken into the encoding processing circuit 5 and encoded.

FIG. 6 is a conceptual diagram showing a spatial position of a line for each field of a moving image according to the second embodiment.

FIG. 6A shows an input moving image signal p of a non-interlaced moving image, which is the same as that shown in FIG. 3A in the first embodiment.

FIG. 6B shows a moving image signal p 'of a pseudo interlaced moving image obtained by performing a field interpolation process on the input moving image signal p by the field interpolation circuit 8. As shown in the figure, the field interpolation circuit 8 generates the image data of the line of the second field from the image data of two lines vertically adjacent to the first field in each pair.

FIG. 7 is a block diagram showing a specific example of the field interpolation circuit 8, in which 8a is a field memory,
b is a line memory, 8c is an adder, 8d is a multiplier, 8e
Is a changeover switch.

In the figure, the write / read timing of the field memory 8a and the switching timing of the changeover switch 8e are controlled by the polarity inversion detection signal i from the polarity inversion detection circuit 7 (FIG. 4).

Now, when the polarity inversion detection signal i is at level 0, the changeover switch 8e is closed to the B side, and the input moving image signal p is changed to the moving image signal p 'via the changeover switch 8e.
And is written to the field memory 8a. The field of the moving image signal p 'at this time is treated as an odd field, and is the fields 0, 2, 4,... In FIG.

When the writing of this field in the field memory 8a is completed, as shown in FIG. 5, the polarity inversion detection signal i becomes level 1, the changeover switch 8e is switched to the A side, and at the same time, the reading of the field memory 8a is performed. Starts. The read moving image signal is added to an adder 8c.
And is delayed by one line time in the line memory 8b and supplied to the adder 8b. This adder 8c
Is supplied to a multiplier 8d, where it is multiplied by a multiplier of 1/2. As a result, a line composed of image data obtained by averaging the image data of two consecutive lines is obtained. The moving image signal composed of such lines is output as an even field of the moving image signal p ′ via the changeover switch 8e. Here, the read start timing of the field memory 8a is adjusted so that the odd field and the even field of the moving image signal p 'have an interlaced relationship.

In this way, a moving image signal p 'of an interlaced moving image is obtained as shown in FIG.

As described above, also in the second embodiment, when a non-interlaced moving image is encoded as an interlaced image, an image without vertical blur of the screen can be obtained with a simple circuit configuration. .

FIG. 8 is a block diagram showing a third embodiment of the moving picture encoding apparatus according to the present invention, wherein 3 'is an inverted field pulse generating circuit, 9 is an encoding start control circuit, and FIGS. Parts corresponding to those in FIG. 4 are denoted by the same reference numerals, and redundant description is omitted.

FIG. 9 is a timing chart showing the operation of the third embodiment. The same reference numerals are given to the signals corresponding to FIG.

In the third embodiment, a moving picture signal of a non-interlaced moving picture and an interlaced moving picture can be encoded.
FIG. 9 shows the operation in the case where
This will be described with reference to FIG.

8 and 9 (a), the field discriminating circuit 6 has the polarity of the field of the input moving image signal p (that is, odd,
In this case, since the input moving image signal p is an interlaced moving image, the level 1 is set when the odd fields 0, 2, 4,... At the time of 5,..., A field discrimination signal f ′ which becomes level 0 is generated.

Further, when there is an encoding start command from outside, the encoding start control circuit 9 changes the field initialization command l to
Next, an encoding command e is generated to initialize the inverted field pulse generation circuit 3 ', and the encoding processing circuit 5
Is started.

The inversion field pulse generation circuit 3 generates an inversion field pulse f for inverting the level to 1, 0 every time the vertical synchronization pulse v is supplied from the vertical synchronization signal detection circuit 1, as in the previous embodiment. However, when the field initialization command 1 is supplied from the encoding start control circuit 9, the level of the field discrimination signal f 'at that time is determined, and the inverted field pulse starting with the vertical synchronization pulse v supplied immediately thereafter is determined. The level of f is made to match the level of the field determination signal f '. As a result, before the field initialization command 1 is supplied, the level of the inverted field pulse f is in a relationship in which the polarity is inverted with respect to the field discrimination signal f ′, and is 0 when the input moving image signal p is an odd field. ,
Even if it is 1 in the even field, when the field initialization command 1 is supplied, the level of the inverted field pulse f becomes 1 in the odd field of the input moving image signal p and 0 in the even field. And the field determination signal f '
And the polarities match. That is, the level of the inversion field pulse f is 1 in the odd field as the first field and 0 in the even field as the second field in the input moving image signal p.

FIG. 10 is a block diagram showing a specific example of the inversion field pulse generation circuit 3 'in FIG.
3a and 3b are D-type flip-flop circuits (D-FF),
Reference numeral 3c denotes a changeover switch, and 3d denotes a set / reset type flip-flop circuit (SR-FF).

In the figure, a D-FF 3a latches data D at its leading edge using a vertical synchronization pulse v as a clock CK, and makes its Q output an inverted field pulse f. Further, the D-FF 3b uses the field initialization command l as the clock CK and sets the field discrimination signal f 'to the data D
To latch that level. The Q output of the D-FF 3b and the Q output of the D-FF 3a are connected to a switch 3c
Is selected, and becomes data D of the D-FF 3a. The SR-FF 3d is set by the field initialization command 1 and is reset at the trailing edge of the vertical synchronization pulse v. The Q output of the SR-FF 3d serves as a switching control signal for the changeover switch 3c. When the level of the changeover control signal is 1, the changeover switch 3c selects the Q output of the D-FF 3b. 3c
Selects the Q output of the D-FF 3a and sets it as data D of the D-FF 3a. That is, the changeover switch 3c selects the Q output of the D-FF 3b during the period from the field initialization command 1 to the trailing edge of the immediately following vertical synchronization pulse v, and selects the Q output of the D-FF 3a during other periods. I do.

Therefore, as shown in FIG. 9A, when the field discrimination signal f 'is at level 1 (at this time, the inverted field pulse f is at level 0), the field initialization command l The level of the inverted field pulse f becomes 0 by the vertical synchronization pulse v, and the level 0 continues for two field periods with the inverted field pulse f. As a result, the level of the inverted field pulse f is inverted, and the polarity of the inverted field pulse f matches that of the field discrimination pulse f '.

In FIG. 9A, the field initialization command 1 is generated when the field discrimination signal f 'is at level 1, but as shown by the broken line, the field discrimination signal f' is at level 0. (At this time, the inverted field pulse f is at level 1), the Q output of the D-FF 8b becomes level 0 by this field initialization command l.
As a result, as shown by the broken line in FIG. 9A, the level of the inverted field pulse f is further held at 1, and the level 1 of the inverted field pulse f continues for two field periods. Thus, thereafter, the inverted field pulse f
Means that the polarity has been inverted, and the polarity of the field discrimination pulse f 'matches.

As is apparent from the above operation, in this specific example, when the field initialization command 1 is generated, the level of the field discrimination signal f 'at this time is detected by the D-FF 3b, and the next vertical synchronization pulse v Hold until the timing of
The inverted level of this level is latched by the D-FF 3a. Therefore, an inverted field pulse f having the same polarity as the field discrimination signal f 'is obtained from the Q terminal of the D-FF 3a.

Returning to FIG. 8 and FIG. 9A, the frame synchronization pulse generation circuit 4 is the same as the frame synchronization pulse generation circuit 4 in FIG. f to generate a frame synchronization signal s. Two fields forming a pair in the input moving image signal p are determined based on the frame synchronization signal s. The frame synchronization signal s and the inverted field signal f
As in the previous embodiment, the first field of the pair is an odd field (fields 0, 2, 4,... In FIG. 9A), and the second field is an even field (FIG. 9A). (Fields 1, 3, 5,...) In (a).

After generating the above-described field initialization command 1, the encoding start control circuit 9 sets the inverted field pulse f
, The level 1 encoding command e is generated with a delay of about one field period when the polarity of. When the encoding command e becomes level 1, the encoding processing circuit 5 fetches the input moving image signal p from the immediately following frame synchronization signal s in pairs and starts the encoding process. Therefore, the encoding processing circuit 5 sets the input moving image signal p to the odd field which is the first field as the top field based on the inverted field pulse f,
Encoding processing is performed based on the MPEG2 standard for each pair in which the even field that is the second field is the bottom field.

Next, the operation of the third embodiment when the input moving image signal p is a non-interlaced moving image will be described with reference to FIG.

In FIG. 8 and FIG. 9 (b), the input moving picture signal p is composed of only the same type of field (odd or even field). Shall be equivalent to a field. In this case, the field discriminating circuit 6
Outputs a level 1 field discrimination signal f ', like the field discrimination circuit 6 in FIG. Therefore, when the field initialization command 1 is supplied from the encoding start control circuit 9 as described above, the inversion field generation circuit 3 'determines that the inversion field pulse f Is inverted so that the level becomes 0 with the vertical synchronization pulse v immediately after that.

In the specific example of the inversion field generating circuit 3 shown in FIG. 10, when the inversion field pulse f is at level 0 in FIG. 9B, it is assumed that the field initialization command l is generated as shown by the solid line. Then, the level 1 of the field discrimination signal f 'at the time when the field initialization command 1 is generated is held in the D-FF 3b, and the level 1 is latched in the D-FF 3a by the immediately following vertical synchronization pulse v. Therefore, during one field period from the vertical synchronization pulse v, the inverted field pulse f becomes level 0. Thereafter, the level of the inverted field pulse f is constantly inverted to 1, 0 every time the vertical synchronization pulse v is supplied. In this way, the generation of the field initialization command l results in an inverted field pulse f having the same level 0 for two consecutive field periods and a polarity inversion as compared to before the field initialization command l was supplied.

When the inverted field pulse f is at level 1
At the time, as shown by the broken line, the field initialization command l
Is generated, since the field discrimination signal f 'is at level 1 and the inverted field pulse f becomes level 0 by the immediately following vertical synchronization pulse v, the polarity of the inverted field pulse f is not inverted. In this case, the inverted field pulse f after the field initialization command 1 indicated by the broken line is the level inverted from that shown in FIG. 9B, and as a result, the frame synchronization pulse s is also changed as shown in FIG. Although the phase is advanced by one field period from that shown in FIG. 9B, the combination of the fields to be paired is different from that shown in FIG. It just doesn't matter.

Referring back to FIGS. 8 and 9B, the frame synchronization pulse generation circuit 4 generates the frame synchronization pulse s from the vertical synchronization pulse v and the inverted field pulse f as described above. The phase relationship between the field pulse f and the frame synchronization pulse s is the same as in the previous embodiment. Therefore, as in the previous embodiment, when a coding instruction e of level 1 is supplied from the coding start control circuit 9, the coding processing circuit 5 starts the processing shown in FIG. As in the embodiment described above, the input moving image signal p
, In pairs, fields 0, 2, 4,... When the inverted field pulse f is at level 1 are the first fields (top fields), and fields 1, 3, 5 when the inverted field pulse f is at level 0. ,... Are fetched in pairs as the second field (bottom field), and the encoding process is started.

As described above, also in the third embodiment, a non-interlaced moving image and an interlaced moving image can be encoded with a simple circuit configuration.

In the third embodiment, when the input moving image signal p is a non-interlaced moving image, the field interpolation circuit 8 is used as in the second embodiment shown in FIG. It may be supplied to the encoding processing circuit 5 as an interlaced moving image signal. In this case, for example, it is determined whether or not the field discrimination signal f output from the field discrimination circuit 6 is at a certain level.
May be supplied to the field interpolation circuit 8.

FIG. 11 is a block diagram showing a fourth embodiment of the moving picture coding apparatus according to the present invention, in which 10 is a vertical synchronization mask circuit, 11 is a continuous inversion detecting circuit, and 12 is coding start / stop control. The circuit 12 is the same as that shown in FIG. FIG.
FIG. 14 is a timing chart showing the operation of the fourth embodiment, wherein the signals corresponding to those in FIG. 11 are denoted by the same reference numerals.

In FIG. 11, this fourth embodiment is
Even when the input video source is switched, encoding is enabled. In the third embodiment shown in FIG. 8, the vertical synchronization mask circuit 10 and the continuous inversion detection circuit 11
And an encoding start / stop control circuit 12 is used in place of the encoding start control circuit 9.

Here, the vertical synchronizing mask circuit 10 normally passes the vertical synchronizing pulse v from the vertical synchronizing signal detecting circuit 1, but when the input moving image signal p is switched to another moving image signal p, it is shown in the figure. The control circuit which does not inhibit the passage of the vertical synchronizing pulse v for one field period from the switching time point t ₀ (FIG. 12), and mask so that the period of the vertical synchronizing pulse v is opened by one or more fields. Further, the continuous inversion detecting circuit 11 detects the levels of the inverted field pulse f and the field discrimination signal f ', and when it detects that the polarities of these levels are continuously inverted for two or more fields, the level 1 of the level 1 is detected. It outputs a continuous inversion detection signal c. During the other periods, the continuous inversion detection signal c is maintained at level 1. When the input video source is switched, the control circuit (not shown) controls the field discrimination circuit 6 and forcibly resets the field discrimination signal f to level 0.

Next, the operation of the fourth embodiment when the input moving image signal p is an interlaced moving image will be described with reference to FIG.

Now, it is assumed that a moving image signal p of an interlaced moving image from a certain moving image source has been encoded by the encoding processing circuit 5. At this time, the vertical synchronization mask circuit 10 allows the vertical synchronization pulse v from the vertical synchronization signal detection circuit 1 to pass, and outputs the vertical synchronization signal detection circuit 1, the horizontal synchronization signal detection circuit 2, the inverted field pulse generation circuit 3 ', the frame synchronization pulse The generation circuit 4 and the field discrimination circuit 6 operate in the same manner as in the third embodiment shown in FIG. Further, the determination field pulse f from the inversion field pulse generation circuit 3 'and the field determination signal f' from the field determination circuit 6 have the same polarity, and therefore, the continuous inversion detection signal output from the continuous inversion detection circuit 11 c is kept at level 0. Further, the encoding start / stop control circuit 12 generates an encoding instruction e of level 1 and supplies it to the encoding processing circuit 5 to set the encoding processing circuit 5 to an operation state. At this time, the coding stop command p generated by the coding start / stop control circuit 12 is kept at level 0.

In this state, at the time t ₀ when the odd field 0 and the even field 1 forming a pair of the moving image signal p are input and the odd field 2 of the next pair is input, the input moving image of another moving image source is input. when switched to the image signal p (at this time, since an odd field period, the inverted field pulse f is level 1), a vertical synchronizing pulse v and horizontal synchronization of a new input video signal p from the point t ₀ pulse h Togaotto s vertical synchronizing signal detecting circuit 1, output from the horizontal synchronizing signal detection circuit 2, a vertical synchronizing pulse mask circuit 10 masks the one field period vertical synchronizing pulses v from time t _0. Therefore, the inverted field pulse f
Are held at level 1 for longer than one field period. In the field discrimination circuit 6, the field discrimination signal f 'is forcibly reset to level 0.

Thereafter, the vertical synchronization pulse mask circuit 10
Is released, and immediately after that, when a new input moving image signal p, for example, an odd field (this is referred to as a field 3) is input, the inverted vertical field pulse generation circuit v generates the inverted field pulse generation circuit. 3 changes from level 1 to level 0, and the field discrimination signal f 'changes from level 0 to level 1 because it is an odd field. Thereafter, the fields of the moving image signal p are input in the order of even, odd, even,..., So that the level of the field discrimination signal f ′ is 0, 1, 0,. The level of the inverted field pulse f is inverted to 1, 0, 1,.... Therefore, these field discrimination signals f '
And the inversion field pulse f have a relationship in which the polarity is inverted.

The continuous inversion detecting circuit 11 constantly monitors the relationship between the polarity of the field discrimination signal f 'and the polarity of the inverted field pulse f. The inversion detection signal c is inverted from level 0 to level 1 (time t ₁ ).

Note that this "two fields" is not necessarily the time length of the two-field period, but when the level of the field discrimination signal f 'and the inverted field pulse f is inverted twice, these two levels are inverted. Means that the polarities of the field discrimination signal f 'and the inversion field pulse f are in a mutually inverted relationship. When such two fields elapse, the field discrimination signal f' and the inversion field pulses f and 3 In the second level inversion (this time is t ₁ , and the period from time t ₀ to time t ₁ is the above-described two fields T).
Changes from level 0 to level 1.

When the continuous inversion detection signal c becomes level 1,
The encoding start / stop control circuit 12 changes the encoding stop command q from level 0 to level 1 and temporarily stops the encoding processing operation of the encoding processing circuit 5. Thereafter, the encoding start / stop control circuit 12 generates a field initialization command 1 and supplies it to the inverted field pulse generation circuit 3 '(at time t).
₂ ). Thereby, the inverted field pulse generation circuit 3 '
Is as described in FIGS. 8 to 10 above, to inverted field pulse f and the field determination pulse f 'same polarity (time t _3). Upon detecting this, the continuous inversion detection circuit 11 changes the continuous inversion detection signal c from level 1 to level 0
And the encoding start / stop control circuit 12
Reverses the encoding stop command q from level 1 to level 0. Then, the encoding processing circuit 5 restarts the operation of the code,
The input moving image signal p is fetched in pairs of odd and even fields from the first frame synchronization pulse s (time t ₄ ) thereafter, and encoding processing is performed with the odd field as the top field and the even field as the bottom field.

Next, referring to FIG. 12B, when the input moving image signal p is a non-interlaced moving image,
The operation of the embodiment will be described.

In this case, assuming that the input moving picture signal p is composed of only odd fields of the interlaced moving picture, the field discrimination signal f 'is inverted to level 0 when the moving picture source is switched (time t ₀ ). Returns to the original level 1 by the first vertical synchronizing pulse v from the new input moving image signal p after the masking is released by the vertical synchronizing mask circuit 10, and thereafter, the next moving image source is switched. Until level 1 is held. On the other hand, the inversion field pulse generation circuit 3 'changes the inversion field pulse f to the same level until the first vertical synchronization pulse v from the new input moving image signal p after the masking by the vertical synchronization mask circuit 10 is released is supplied. (In this case, level 1), but the level is alternately inverted to 0 and 1 from the first vertical synchronization pulse v.

In this way, the polarity of the inverted field pulse f after the switching of the moving image source is inverted with respect to that before the switching, but 0, 0 for each vertical synchronization pulse v.
The level is inverted to 1 and the level inversion of the two fields in the above sense does not occur between the level 1 field discrimination pulse f '. Accordingly, the continuous inversion detection signal c output from the continuous inversion detection circuit 11 is maintained at the level 0 as it is, whereby the encoding start / stop control circuit 12 sets the encoding stop command q to the level 1. Therefore, the encoding processing circuit 5 outputs a new input moving image signal p
Is immediately performed for each pair of correct field combinations. Even if the encoding process of the new input moving image signal p is performed as described above, since this input moving image signal p is a non-interlaced moving image, it does not pose a separate problem.

As is apparent from the above operation, the same applies to the case where the source of the interlaced moving image is switched to the source of the non-interlaced moving image and vice versa. The encoding process of the image signal p is immediately performed for each pair of correct field combinations.

As described above, in the fourth embodiment as well, with a simple circuit configuration, even if the video source is switched in the middle, the encoding processing circuit 5 converts the input video signal p into a correct pair. An encoding process can be performed.

FIG. 13 is a block diagram showing a specific example of the continuous inversion detection circuit 11 in FIG.
An xOR circuit, 11b and 11c are D-FFs, and 11d is an inverter.

In the figure, an inverted field pulse f and a field discrimination pulse f 'are supplied to an ExOR circuit 11a, and their polarity relationship is discriminated. This ExOR
The output of the circuit 11a is supplied to the D-FF 11b as data D, and is latched at the trailing edge of the vertical synchronization pulse v. The Q output of the D-FF 11b is D-FF as data D.
It is supplied to the FF 11c and is latched at the trailing edge of the vertical synchronization pulse v. The Q output of the D-FF 11c becomes the continuous inversion detection signal c. The output of the ExOR circuit 11a is inverted in level by an inverter 11d.
The D-FF 11c is reset at the rising edge of the output so that its Q output becomes level 0.

In such a configuration, when the polarity of the inverted field pulse f and the polarity of the field discrimination pulse f 'coincide with each other, the output of the ExOR circuit 11a is at level 0, and therefore the Q output of the D-FF 11b is -FF1
The Q output of 1c is also at level 0.

If the polarity of the inverted field pulse f and the polarity of the field discrimination pulse f ′ do not match from time t _{0 in} FIG. 12 due to the switching of the moving image source, the output of the ExOR circuit 11 a becomes level 1 from time t _0. Then, at the trailing edge of the first vertical synchronization pulse v, this level 1 becomes D-
It is latched by the FF 11b. Therefore, the Q output of the D-FF 11b becomes level 1, and this level 1 is latched by the D-FF 11c at the trailing edge of the next vertical synchronization pulse v. As a result, the continuous inversion detection signal c, which is the Q output of the D-FF 11c, is inverted from level 0 to level 1, but at the time of this level inversion, the polarity of the inverted field pulse f and the field discrimination pulse f 'do not match. 12, after the above two fields T, as shown in FIG.

Thereafter, when the polarity of the inverted field pulse f and the polarity of the field discrimination pulse f 'become identical (time t _{3 in} FIG. 12A), the output of the ExOR circuit 11a is inverted from level 1 to level 0. However, at the same time, the output of the inverter 11d is also inverted from level 0 to level 1, and at the rising edge, the D-FF 11c is reset, and the continuous inversion detection signal c is inverted from level 1 to level 0.

In each of the above embodiments, the input moving image signal p of a non-interlaced moving image is composed of a field corresponding to an odd field of an interlaced moving image. It may be. In this case, the field discriminating signal f 'at level 0 is output from the field discriminating circuit 6 in the embodiment shown in FIGS. 4, 8 and 11, but the operation of these embodiments is different from that described above. is not.

FIG. 14 is a block diagram showing an embodiment of a moving picture recording apparatus according to the present invention for recording an encoded moving picture signal from the moving picture encoding apparatus shown in FIG.
Is a packet processing circuit, and 14 is a recording medium, and portions corresponding to FIG.

In the figure, the encoded moving image signal obtained from the encoding processing circuit 5 as described with reference to FIGS. 11 to 13 is processed by the packetization processing circuit 13 and converted into recordable packet data. Are recorded on the recording medium 14 by recording means (not shown).

As described above, in this embodiment, the encoded moving image signal obtained by encoding the moving image signal p of the interlaced or non-interlaced moving image according to the MPEG2 standard can be recorded on the recording medium 14.

Here, the moving picture coding apparatus of the embodiment shown in FIG. 11 is used, but other embodiments, that is, the embodiments shown in FIG. 1, FIG. 4 or FIG. It can also be used.

[0084]

As described above, according to the present invention,
With a simple circuit configuration, it is possible to correctly encode not only interlaced video but also non-interlaced video, and even at the start of such a video, even when the video source is switched. The encoding is performed correctly, and the obtained encoded moving image signal can also be recorded on a recording medium.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a moving picture coding apparatus according to the present invention.

FIG. 2 is a timing chart showing an operation of the first embodiment of the moving picture coding apparatus shown in FIG.

3 is a conceptual diagram showing a spatial position of a line in each field of an input moving image and an encoded moving image in the first embodiment of the moving image encoding device shown in FIG.

FIG. 4 is a block diagram showing a second embodiment of the moving picture coding apparatus according to the present invention.

FIG. 5 is a timing chart showing an operation of the video encoding device shown in FIG. 4 according to a second embodiment;

FIG. 6 is a conceptual diagram showing a spatial position of a line in each field of an input moving image and an encoded moving image in a second embodiment of the moving image encoding device shown in FIG.

FIG. 7 is a block diagram showing a specific example of a field interpolation circuit in FIG. 4;

FIG. 8 is a block diagram showing a third embodiment of the video encoding device according to the present invention.

FIG. 9 is a timing chart showing an operation of the third embodiment of the moving picture coding apparatus shown in FIG. 7;

FIG. 10 is a block diagram showing a specific example of an inverted field pulse generation circuit in FIG. 8;

FIG. 11 is a block diagram showing a fourth embodiment of the moving picture coding apparatus according to the present invention.

FIG. 12 is a timing chart showing an operation of the fourth embodiment of the video encoding device shown in FIG.

FIG. 13 is a block diagram showing a specific example of a continuous inversion detection circuit in FIG. 11;

FIG. 14 is a block diagram showing an embodiment of a moving image recording apparatus according to the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 vertical synchronization detection circuit 2 horizontal synchronization detection circuit 3, 3 ′ automatic inversion field generation circuit 4 frame synchronization generation circuit 5 encoding processing circuit 6 field discrimination circuit 7 polarity inversion detection circuit 8 field interpolation circuit 9 encoding start control circuit 10 vertical Synchronization mask circuit 11 Continuous inversion detection circuit 12 Encoding start / stop control circuit 13 Packetization processing circuit 14 Recording medium

Continued on the front page (72) Inventor Yukito Tsuboi 5-2-1, Kamizuhoncho, Kodaira-shi, Tokyo F-term in the System LSI Development Center of Hitachi, Ltd. 5C059 KK00 MA00 PP04 SS06 UA02 UA31

Claims (12)

[Claims] 1. A non-interlaced input video signal consisting of a series of field images is paired for every two fields, and for each pair, a first field of the pair is a top field and a second field is a bottom field. A moving picture coding method characterized by: 2. The input video signal according to claim 2, wherein an inverted field pulse whose level is sequentially inverted for each vertical synchronization signal of the input video signal is generated, and a field of the input video signal during one level period of the inverted field pulse is generated. Is the first field,
A moving picture coding method comprising coding the input moving picture signal using a field of the input moving picture signal in the other level period of the inverted field pulse as the second field. 3. The method according to claim 1, wherein the second field as the bottom field is interpolated from the first field as the top field to form the same pair of the top field and the bottom field. A moving picture coding method characterized by coding in an interlaced relationship. 4. A method for encoding a non-interlaced or interlaced input video signal comprising a series of field images, wherein the type of the field of the input video signal is sequentially detected, and the field type is detected at the time of a coding start command. Generating an inversion field pulse, which is initialized to a level corresponding to the type of the field and whose level is inverted for each field of the input video signal, the input video signal during one level period of the inversion field pulse; Is a first field, a field of the input moving image signal during the other level period of the inverted field pulse is a second field, and two consecutive fields of the input moving image signal are the first and second fields. A moving image code, wherein the input moving image signal is encoded in pairs. Method. 5. The apparatus according to claim 4, wherein when the input moving image signal is an interlaced moving image signal, the first field in the pair is an odd field, and the second field is an even field. Moving image encoding method. 6. A method for encoding a non-interlaced or interlaced input video signal comprising a series of field images, comprising: an inverted field pulse whose level is inverted for each vertical synchronizing signal of the input video signal; And a field discrimination pulse of a level corresponding to the type of the field, and switching to a video signal of a new video source,
The level inversion of the inverted field pulse accompanying the first vertical synchronization signal after the switching is inhibited, and the level of the field discrimination pulse is initialized. The period between the inverted field pulse and the field discrimination pulse is two fields. When the polarity is inverted, the encoding process is stopped, and a coding start command is generated during the stop period of the coding process, and the field type indicated by the field discrimination pulse at the time of the generation of the coding start command is determined. A moving image encoding method, comprising: initializing the inverted field pulse to a corresponding level, matching the polarity of the inverted field pulse with the polarity of the field discrimination pulse, and restarting the encoding process. 7. An inversion field pulse generating means for generating an inversion field pulse of which level is inverted for each field of an input moving image signal comprising a series of field images, and generating a frame synchronization pulse synchronized with the inversion field pulse Frame synchronizing pulse generating means, and encoding means for forming a pair of successive fields of the input moving image signal by the frame synchronizing pulse, and encoding the input moving image signal in pairs. A video encoding device characterized by the above-mentioned. 8. The moving picture coding apparatus according to claim 7, wherein the input moving picture signal is a non-interlaced moving picture signal. 9. The input video signal according to claim 7, wherein the input video signal is an interlaced or non-interlaced video signal, and a type of a field of the input video signal is determined, and the input video signal is determined according to the type. Field discriminating means for generating a level field discriminating pulse, and encoding start control means for generating an encoding start command prior to the start of the encoding process of the encoding means, wherein the inverted field pulse generating means, A moving picture coding apparatus, wherein the level of the inverted field pulse is set to an initial level corresponding to the level of the field discrimination pulse at the time when the coding start command is generated. 10. The input moving image signal according to claim 7, wherein the input moving image signal is any one of an interlaced and a non-interlaced moving image signal, and a type of a field of the input moving image signal is determined. A field discriminating means for generating a level field discriminating pulse, and detecting that the polarity between the inverted field pulse from the inverted field generating means and the field discriminating pulse from the field discriminating means is continuously inconsistent. A continuous inversion detecting means for detecting, when the continuous inversion detecting means detects that the polarity between the inverted field pulse and the field discriminating pulse is continuously inconsistent, an encoding processing operation of the encoding means; Is temporarily stopped, and the inversion field pulse and the field determination are performed by the continuous inversion detection means. When it is no longer detected that the polarity between the pulse and the pulse does not match continuously, a coding start command is generated, and thereafter, the coding start for releasing the pause of the coding processing operation of the coding means is started. A stop control unit, wherein the inversion field pulse generation unit sets the level of the inversion field pulse to an initial level corresponding to the level of the field discrimination pulse at the time of generation of the encoding start command. Video encoding device. 11. The method according to claim 8, 9 or 10, wherein for each pair of the non-interlaced input video signals, two non-interlaced two
Converting means for converting the non-interlaced input moving image signal into an interlaced moving image signal by converting one field into two fields interlaced with each other; A moving picture coding apparatus for coding a signal. 12. A moving picture recording apparatus comprising a recording means for recording a moving picture signal encoded by the moving picture encoding apparatus according to claim 7 on a recording medium. apparatus.