JP2000347929A - Memory ic - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate discontinuous address areas and effectively utilize limited memory resources by remapping calculation to an inputted address on the basis of prescribed information from a non-volatile memory. SOLUTION: At the time of initial setting, an address bus 10 is connected to a non-volatile memory 12 by a select signal 14. Then, a control signal 15 is made active and a leading address, block size and empty area information are written by using a data bus 17 and a write signal 19. At the time of operation, a signal inputted through the address bus 10 to a memory IC is inputted through a selector 13 to an address translating circuit 11 by the select signal 14. In the address translating circuit 11, the address is remapped on the basis of information for skipping the read of unnecessary addresses from the non- volatile memory 12 and inputted to an internal RAM 16 later. Thus, the read of unnecessary memory spaces is skipped and unnecessary memory spaces can be saved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory IC (integrated circuit) according to the present invention, and more particularly to a memory IC suitable for a peripheral circuit of a processing device such as a microprocessor (MPU).

[0002]

2. Description of the Related Art With the spread of personal computers using MPUs and their high performance, memories (storage circuits or elements) used therewith have been increasing in capacity and speed.

A memory control device for controlling an access operation from a processing device such as an MPU to a storage device composed of a plurality of memories generally comprises the following means. That is, a memory configuration recognizing means for recognizing a memory configuration of the storage device,
Determining means for determining an operation mode suitable for each memory based on the stored memory configuration, determining means for each memory based on the determined operation mode, and generating an address signal corresponding to the determined operation mode; Is output to the corresponding memory.

[0004] The decoding means is characterized in that the mapping for each memory is determined so that addresses are continuous based on the determined operation mode. That is, a plurality of memories (built-in memory,
When an additional memory is connected to a microprocessor or the like, all the memory seen from the microprocessor appears to be mapped to a series of continuous address spaces.

Further, the related art of such a memory control device or memory management device is also disclosed in Japanese Patent Application Laid-Open No. 5-216745.

[0006]

In the above-mentioned prior art, it is possible to create a variable length buffer by making the free space continuous by managing the buffer. At the time of software design, a redundant area is provided. Then, when it is desired to use a redundantly vacant area in an actual operation stage, there is a problem that a great deal of change occurs.

Further, the RA required in software design
If the capacity of M (random access memory) cannot be determined, more RAM than necessary must be installed in advance.
However, this is wasteful because it includes many unnecessary areas.
Therefore, the actual operation including the redundant memory is inconvenient in terms of the device (system) cost, and a large amount of space is required for the means for mounting the memory on the board.

An object of the present invention is to provide a memory IC which can use an address map constructed at a software design stage in actual operation and can save space and cost by eliminating discontinuous areas. To provide.

[0009]

In order to solve the above-mentioned problems, a memory IC according to the present invention employs the following characteristic configuration.

(1) RAM having a large number of storage addresses
In a memory IC including: a non-volatile memory for storing information for skipping an unnecessary address area in advance, and an address conversion for calculating remapping for an input address based on the information from the non-volatile memory A memory IC comprising a circuit.

(2) The memory IC according to (1), wherein a selector is further arranged at a stage preceding the address conversion circuit, and an address from an address bus is input to the address conversion circuit via the selector.

(3) The memory IC according to (1) or (2), wherein the information stored in the nonvolatile memory includes a start address, a block size, and a free area.

(4) The memory IC according to (3), wherein the address conversion circuit includes a head address register, a block size register, and a free area register for holding information for address conversion.

(5) The memory IC according to (1), wherein the information in the nonvolatile memory is written from outside using a control signal, a data bus and a write signal.

(6) The memory IC according to (1), wherein a data bus, a write signal, and a read signal are commonly connected to the RAM and the nonvolatile memory from the outside.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a memory IC according to the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the internal configuration of a preferred embodiment of a memory IC according to the present invention. This memory IC includes a nonvolatile memory 12, an address conversion circuit 11, a selector 13, and an internal RAM 16. The nonvolatile memory 12 holds discontinuous information. The address conversion circuit 11 converts an address based on the discontinuity information described above. Data is actually written in the internal RAM 16.

The nonvolatile memory 12 and the internal RAM 16 include:
A data bus 17, a write (write) signal 19, and a read (read) signal 20 are input / output from outside. The control signal 15 is input to the nonvolatile memory 12. The address bus 10 is connected to the selector 13.
The select signal 14 is input to the selector 13 and the nonvolatile memory 12. Further, the output of the selector 13 is input to the address conversion circuit 11 and the internal address 21 is input to the nonvolatile memory 12. The output of the address conversion circuit 11 is input to the address bus of the internal RAM 16. The polling signal 22 and the data bus 23 are connected between the address conversion circuit 11 and the nonvolatile memory 12. Also,
The internal RAM 16 has an external chip select signal 18
Is input to the CSB terminal.

FIG. 4 is a detailed block diagram of the address conversion circuit 11. The address conversion circuit 11 includes a selector 4
2, 46, the start address register 43, the block size register 44, the free area information register 45, the subtraction circuits 47 and 51, the addition circuits 48 and 50, the subtraction and counting circuit 49, the timing generation circuit 52, the P / S (parallel / serial). ) A conversion shift register 53 and a non-volatile memory write monitor 57 are provided.

The subtraction circuits 47 and 51 have the input address 4
0 is input. The timing generation circuit 52 receives the external clock input 54, the trigger signal 55 from the nonvolatile memory writing monitor 57, the count signal 70 from the subtraction and count circuit 49, and receives the P / S conversion clock 60, the select signal 61 and the address 69. Output. The P / S conversion shift register 53 receives the PS conversion clock 60 from the timing generation circuit 52 and the input 56 from the non-volatile memory 12 as inputs, and inputs a serially converted signal 62 to the selector 42. The selectors 42 and 46 select the input signals 62 and 60 based on the selector signal 61 from the timing generation circuit 52, and select the registers 43, 44 and
5, the registers 43 to 45 subtract the information 63 to 65 set in the respective registers into subtraction circuits 47 and 4.
Enter 8 The information 65 from the free area information register 45 is input to the adding circuit 50, and the output 65 of the free area result is input to the subtracting circuit 51, and the converted address 41 is output.

Next, the operation of the memory IC shown in FIGS. 1 and 4 will be described. As an initial setting operation, it is necessary to write each information to the nonvolatile memory 12 from an external control device (such as a microprocessor). This operation is performed when select signal 1
4 connects the address bus 10 to the nonvolatile memory 12. Then, the control signal 15 is activated,
The head address, block size, and free area information are written using the data bus 17 and the write signal 19 (see FIG. 5).

Referring to FIG. 2, the initial setting operation is performed in four steps of writing a head address into the nonvolatile memory 12, writing a block size write free area information, and writing an OK flag register. When the block sizes are not uniform, the block size register 44
And writes it in the free area information register 45.

Referring to FIG. 4, the initialization of the address conversion circuit 11 will be described. The non-volatile memory write monitor 57 monitors the writing of the OK flag of the non-volatile memory using the polling signal 58, and outputs a trigger signal 55 to the timing generation circuit 52 when it is found that 1 has been written. Based on the timing of the trigger signal 55, the timing generation circuit 52 outputs an address 69 to the P / S conversion clock 60, the select signal 61, and the nonvolatile memory 12 in synchronization with the external clock 54.

The signal 62 converted to a serial signal by the P / S conversion shift register 53 is set in each of the registers 43 to 45 via the selector 42 based on the selector signal 61.

In operation, referring to FIG. 1, a signal input to the memory IC via the address bus 10 is input to the address conversion circuit 11 via the selector 13 by the select signal 14. Then, after the address is remapped by the address conversion circuit 11, the internal RA
It is input to M16. The following address conversion method will be described.

Referring to FIG. 4, the subtraction circuit 4 uses information 63 to 65 set in registers 43 to 45, respectively.
In step 7, subtraction of input address 40-head address 63 is performed. The adder circuit 48 adds the block size 64 + the free area information 65, subtracts the output signals 66 and 67 by the subtraction and count circuit 49, and determines which block the input address corresponds to. Signal 66-signal 67
Is positive, the count signal 7 used to change the addresses of the block size information and the free area information
The signal 67 is changed to the next block by adding 1 to 0.
The adding circuit 50 adds the free area information 65 + the free area result 68. This calculation is performed until the result of the signal 66-signal 67 becomes negative. When the result is negative, the empty area result 68 is the address to be skipped, so that by performing the input address 40-the empty area result 68, the converted address 41 whose address is remapped is output.

Next, a system using the memory IC 101 according to the present invention will be described with reference to FIG. This system includes a memory IC 101, a CPU (central processing unit) 100, and a pair of peripheral circuits 102, 103 according to the present invention. An address bus 110, a data bus 111, a write signal 112, and a read signal 113 are provided between the CPU 100, the memory IC 101, and the peripheral circuits 102 and 103.
Connected to each other. The memory IC 101 and the peripheral circuit 102 are connected by a select signal 114 and a control signal 115. On the other hand, the memory IC 101 and the peripheral circuit 103 are connected by a chip select signal 116.

FIG. 6 shows an example of an address map by the memory IC of the present invention. As an example, a 512 Kbit address space is divided into three blocks and used. FIG.
As shown in (A), the size of block 0 is 30,000,
Empty area is 10000, block 1 size is 400
00, free area 10000, block 2 size is 1
0000 and the empty area 2 are 60000.

The operation will be described with reference to FIGS.
The memory IC 101 according to the present invention includes an initialization mode,
It operates in two modes, the operation mode.

In the initial setting mode, information is set from the CPU 100 to the nonvolatile memory (12 in FIG. 1) in the memory IC 101. Using the address map of FIG. 6,
The start address is 0000h and the size of block 0 is 10.
000h, the size of the free area 0 is 10000h, the size of the free area 1 is 10,000h, and the size of the free area 2 is 60,000h. Fig. 2
Is written in the nonvolatile memory 12 as shown in the flowchart of FIG. That is, it is determined whether the setting has not been made in step S1 or whether the setting should be reset. If YES, the process proceeds to step S2, and if NO, the process ends. In step S2, the head address is written to address 0 of the nonvolatile memory. Next, in step S3, it is determined whether the free area of the block size is uniform. If YES (uniform), step S4
Then, the block size (uniform) is written to the nonvolatile memory. Next, the empty area (uniform) is written in the nonvolatile memory (step S5), and the process proceeds to step S9 described later.

Next, if NO in step S3, that is, if it is determined to be non-uniform, the process proceeds to step S6, where 0 is written in the block size and the empty area (uniform). Next, step S7
Then, the block size (n) is written in the nonvolatile memory. Then, in step S8, the free area information (n) is written in the nonvolatile memory. Steps S7 and S8 are looped n times, and finally, in step S9, a write OK flag is written in the nonvolatile memory.

As shown in FIG. 5, after writing all the information, 1 is written to the OK bit register of the nonvolatile memory in order to set the write OK bit to 1. This writing is monitored by the nonvolatile memory writing monitor 57 in FIG. After writing,
The timing generation circuit 52 generates an address 69 for the nonvolatile memory, and at the same time, the select signal 61 and the P signal
By generating the / S clock 60, each register 4
Each information is set in 3-45. When setting again, the same operation needs to be performed. The information set once can be used even after the power is turned on again. In this case, the nonvolatile memory write monitor 57 determines whether or not to perform the automatic setting based on whether or not 1 is written in the OK flag register after the power is turned on.

Next, the memory IC according to the present invention has
The conversion operation when 0h is input will be described (see the flowchart of FIG. 3).

FIG. 3 is a flowchart for explaining an operation of converting an address input to the memory IC of the present invention by using the address conversion circuit 11. First, as additionally shown in FIG. 3, n, a, and Atemp are the contents of a block calculation temporary register, an area calculation temporary register, and a free area calculation temporary register, respectively. Size (n) and Area (n) are block size and free area information, respectively.

In step S10, each calculation register is initialized. That is, n = 0, a = 0, and Atemp = 0. Subsequently, in step S11, an address is input, and (input address-head address) is calculated. Next, in step S12, it is determined whether (input address-a) is correct (> 0). In the case of Yes, the process proceeds to step S13,
Calculate a + Size (n) + Area (n) and calculate the result as a
And Next, n is incremented by one in step S14, and the process returns to step S12. In the case of No,
Proceeding to step S15, it is determined whether the input address is 0. In the case of Yes, the conversion ends, and in the case of No, the process proceeds to step S16, where n-1 is performed, and the result is substituted for n. Thereafter, it is determined in step S17 whether n is positive. In the case of Yes, the process proceeds to step S18, and Atemp + Are
a (n) is calculated, and the result is set to Atemp. Thereafter, the process proceeds to step S19, where n is decremented by one, and then returns to step S17. On the other hand, in the case of No, the process proceeds to step S20, where (input address-Atemp) is calculated, and the process ends.

Initialization is performed by substituting 0 into each of the calculation registers n, a, and Atemp (A). Start address register 43
From the input address, and the input address-head address is calculated (B). Here, the input address-area calculation temporary register is calculated (C). In order to make the result positive, the calculation of the calculation temporary register a + block size 30000h + free area 10000h is performed, and this is set as a (D), and n is counted up by 1 (E). It is determined again whether the calculation of the temporary register a for input address-area calculation is above 0. 60
000-40000 = 20,000, and it is found that it is still positive (F). Therefore, the area calculation temporary register a + the block 1 size 10000h + the free area 1 size 10000h is calculated, and this is set to a (G). Then, n is incremented by one (H).

Next, the input address-area calculation temporary register a is calculated.
−60000, which does not satisfy the condition (I). Therefore,
Move on to the next condition. Since the input address is not 0 (J), the calculation of n-1 is performed and it is set as n (k).
Then, a determination is made that the block calculation temporary register n> 0 (L). Since n is currently 1, the calculation of the free area calculation temporary register Atemp + the free area (1) is performed, the result is set to n (N), and the determination of n> 0 is performed again (0). Here, since n is currently 0, the condition is not satisfied. Therefore, from the input address 60000h to Atemp
The value obtained by subtracting the value of 10000h is output as an address after remapping (P). The above description is expressed by the following equations. n = 0, a = 0, Atemp = 0 ... (A) 60000-0 = 60000 ... (B) The result of 60000-0> is positive, and the following formula is calculated ... (C) 0 + 30000 + 10000 = 40000 → a (D) 0 + 1 = 0 → h is substituted (E) The result of 60000-40000> 0 is positive, and the following formula is calculated ... (F) 40000 + 10000 + 10000 = 60000 → a is substituted (G) Substituting for 1 + 1 = 2 → n ... (H) 60000-60000 = 0, not satisfying the condition ... (I) Since 60000 ≠ 0, go to the next condition. ... (J) Substitute for n-1 = 2-1-1 → n ... (K) Since n = 1> 0, the following equation is calculated. .. (L) 0 + 10000 = 10000 → substituted into Atemp (M) n−1 = 0 → substituted into n (N) The determination of n> 0 is NO. ... (O) 60000-10000 = 50000 ... Output address ... (P)

Although the preferred embodiment of the memory IC according to the present invention has been described above, this is merely an example, and it goes without saying that various modifications can be made in accordance with the specific application.

[0039]

As can be understood from the above description, according to the memory IC of the present invention, by eliminating discontinuous address areas, limited memory resources can be effectively used and software design can be improved. It can respond flexibly. The reason is that addresses are remapped according to the information set in the non-volatile memory, unnecessary memory space can be skipped, and useless memory space can be omitted.

[Brief description of the drawings]

FIG. 1 is an internal block diagram of a preferred embodiment of a memory IC according to the present invention.

FIG. 2 is a flowchart for setting information in a non-volatile memory in the initial setting of the memory IC shown in FIG. 1;

FIG. 3 is a flowchart of an operation for converting an address input to the memory IC shown in FIG. 1;

FIG. 4 is a detailed internal block diagram of an address conversion circuit constituting the memory IC shown in FIG. 1;

FIG. 5 is a diagram showing an internal address space map of a nonvolatile memory included in the memory IC shown in FIG. 1;

FIG. 6 shows an example of an address map, (A) is a conventional example, and (B) is a diagram showing an example converted by the present invention.

FIG. 7 is a configuration diagram of a system using the memory IC shown in FIG. 1;

[Explanation of symbols]

 Reference Signs List 10 address bus 11 address conversion circuit 12 nonvolatile memory 13 selector 15 control signal 16 RAM 17 data bus 19 write signal 20 read signal 43 start address register 44 block size register 45 free area information register

Claims (6)

[Claims] 1. A memory IC including a RAM having a large number of storage addresses, a nonvolatile memory for storing information for skipping an unnecessary address area in advance, and an input based on the information from the nonvolatile memory. A memory IC, comprising: an address conversion circuit that performs a remapping calculation on an address. 2. The memory IC according to claim 1, wherein a selector is further arranged at a stage preceding the address conversion circuit, and an address from an address bus is input to the address conversion circuit via the selector. 3. The information stored in the nonvolatile memory is:
3. The memory IC according to claim 1, comprising a start address, a block size, and a free area. 4. The memory IC according to claim 3, wherein said address conversion circuit includes a head address register, a block size register, and a free area register for holding information for address conversion. 5. The memory according to claim 1, wherein said information in said nonvolatile memory is written from outside using a control signal, a data bus and a write signal.
C. 6. The memory I according to claim 1, wherein a data bus, a write signal, and a read signal are externally connected to the RAM and the nonvolatile memory in common.
C.