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JP2000347420A5 - - Google Patents

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Publication number
JP2000347420A5
JP2000347420A5 JP1999157470A JP15747099A JP2000347420A5 JP 2000347420 A5 JP2000347420 A5 JP 2000347420A5 JP 1999157470 A JP1999157470 A JP 1999157470A JP 15747099 A JP15747099 A JP 15747099A JP 2000347420 A5 JP2000347420 A5 JP 2000347420A5
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JP
Japan
Prior art keywords
substrate
negative resist
holes
hole
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1999157470A
Other languages
Japanese (ja)
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JP2000347420A (en
Filing date
Publication date
Application filed filed Critical
Priority to JP11157470A priority Critical patent/JP2000347420A/en
Priority claimed from JP11157470A external-priority patent/JP2000347420A/en
Publication of JP2000347420A publication Critical patent/JP2000347420A/en
Publication of JP2000347420A5 publication Critical patent/JP2000347420A5/ja
Pending legal-status Critical Current

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Description

【発明の名称】半導体装置の製造方法Patent application title: METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

【０００１】
【発明の属する技術分野】
本発明は、微細な幅（径）でアスペクト比の高い溝や孔を有する基板へ良好なパターン形成が行える半導体装置の製造方法に関する。[0001]
Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device capable of performing good pattern formation to a substrate having a high grooves or holes of an aspect ratio in the fine pore width (diameter).

【００３８】
【発明の効果】
本発明により、所望の開口を有するレジストパターンを形成することが可能となる。レジスト残り不良が発生しないことから歩留まりが向上する。[0038]
【Effect of the invention】
The present invention, it is possible to form a resist pattern having an opening Nozomu Tokoro. The yield is improved because no remaining resist failure occurs.

Claims (6)

孔あるいは溝パターンが形成された基板の、一部の上記孔あるいは溝の部分に
開口を持つレジストパターンを形成する半導体装置の製造方法において、上記基板あるいは上記開口部の孔や溝に近接して配置された物質が、露光光の透過を妨げる性質を持ち、上記孔あるいは溝パターンが形成された基板上にネガレジストを形成する工程と、所望の開口部以外を露光する工程、および現像する工程からなることを特徴とした半導体装置の製造方法。In a method of manufacturing a semiconductor device in which a resist pattern having an opening is formed in a part of the hole or groove of the substrate on which the hole or groove pattern is formed, in proximity to the hole or groove of the substrate or the opening A process of forming a negative resist on a substrate having the above-mentioned hole or groove pattern, which has the property of preventing transmission of exposure light, and a process of exposing other than the desired opening, and a process of developing A method of manufacturing a semiconductor device comprising: 請求項１において、上記基板に形成された孔あるいは溝パターンの最小幅が、
上記露光を行なうときの露光光の波長と同じかそれより小さいことを特徴とする
半導体装置の製造方法。In claim 1, the minimum width of the hole or groove pattern formed in the substrate is
Characterized in that it is the same as or smaller than the wavelength of exposure light when performing the exposure
Semiconductor device manufacturing method . 請求項１において、上記基板に形成された孔あるいは溝パターンのアスペクト
比が３以上であることを特徴とする半導体装置の製造方法。The method of manufacturing a semiconductor device according to claim 1, wherein an aspect ratio of the hole or groove pattern formed in the substrate is 3 or more. 表面が酸化膜であり、径が露光波長よりも小さい孔がマトリクス状に配置された基板を準備する工程と、前記孔を有する前記基板表面にネガレジストを塗布して塗膜を形成する工程と、前記塗膜を露光、現像し、ライン状に前記孔が露出するネガレジストパターンを形成する工程と、その後前記ネガレジストパターンをマスクとして前記基板をエッチングする工程とを有することを特徴とする半導体装置の製造方法。Preparing a substrate having an oxide film on the surface and a matrix of holes having a diameter smaller than the exposure wavelength, and applying a negative resist on the surface of the substrate having the holes to form a coating film. And a step of exposing and developing the coating film to form a negative resist pattern in which the holes are exposed in a line, and then etching the substrate using the negative resist pattern as a mask. Device manufacturing method. 前記孔のアスペクト比は３以上であることを特徴とする請求項４記載の半導体装置の製造方法。5. The method of manufacturing a semiconductor device according to claim 4, wherein an aspect ratio of the hole is 3 or more. 表面が酸化膜であり、径が露光波長よりも小さく、アスペクト比が３以上の孔が複数設けられた基板を準備する工程と、前記孔を有する前記基板表面にネガレジストを塗布して塗膜を形成する工程と、前記塗膜を露光、現像し、複数の前記孔の内所望の幾つかが露出するネガレジストパターンを形成する工程と、その後前記ネガレジストパターンをマスクとして前記基板をエッチングし、所望の前記孔を深孔にする工程とを有することを特徴とする半導体装置の製造方法。Preparing a substrate having an oxide film on the surface, a diameter smaller than the exposure wavelength, and a plurality of holes with an aspect ratio of 3 or more, and applying a negative resist on the surface of the substrate having the holes to form a coating film Forming a negative resist pattern, exposing and developing the coating film to form a negative resist pattern in which desired ones of the plurality of holes are exposed, and then etching the substrate using the negative resist pattern as a mask. And D. making the desired holes deep.
JP11157470A 1999-06-04 1999-06-04 Formation of resist pattern Pending JP2000347420A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11157470A JP2000347420A (en) 1999-06-04 1999-06-04 Formation of resist pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11157470A JP2000347420A (en) 1999-06-04 1999-06-04 Formation of resist pattern

Publications (2)

Publication Number Publication Date
JP2000347420A JP2000347420A (en) 2000-12-15
JP2000347420A5 true JP2000347420A5 (en) 2004-09-02

Family

ID=15650388

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11157470A Pending JP2000347420A (en) 1999-06-04 1999-06-04 Formation of resist pattern

Country Status (1)

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JP (1) JP2000347420A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101172313B1 (en) 2006-02-23 2012-08-14 에스케이하이닉스 주식회사 Method for fabricating the same of semiconductor device
KR102545448B1 (en) * 2015-02-21 2023-06-19 도쿄엘렉트론가부시키가이샤 Patterning method including misalignment error protection
US9633847B2 (en) * 2015-04-10 2017-04-25 Tokyo Electron Limited Using sub-resolution openings to aid in image reversal, directed self-assembly, and selective deposition

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