JP2000341554A - Synchronous signal processing circuit - Google Patents

Abstract

(57) Abstract: In a synchronization signal processing circuit for generating an internal horizontal synchronization signal synchronized with a horizontal synchronization signal of a video signal, all horizontal synchronization signals are not once subjected to A / D conversion as in the related art. Even so, the phase difference between the two synchronization signals is eliminated by accurately detecting the phase difference between the two synchronization signals. SOLUTION: An internal horizontal synchronization signal HD is generated based on an internal clock signal CLK1 synchronized with a phase of a color burst signal included in a video signal, and a horizontal synchronization signal Hsync and an internal horizontal synchronization signal separated from the video signal are generated. HD, and detects the phase difference between the two synchronous signals Hsync and Hsync.
When the phase control is performed so that the phase difference of D disappears, the horizontal synchronization signal Hsync, the internal horizontal synchronization signal HD, the internal clock signal CLK1, the reverse phase clock signal CLK2 obtained by inverting the level of the internal clock signal CLK1, and the internal A phase difference detection circuit 4 is provided for calculating a phase difference between the horizontal synchronization signal Hsync and the internal horizontal synchronization signal HD based on a phase comparison reference signal B generated based on the horizontal synchronization signal HD.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a synchronization signal processing circuit for generating an internal horizontal synchronization signal synchronized with a horizontal synchronization signal of a video signal using a system clock synchronized with a color burst signal of a video signal. In particular, the present invention relates to a phase difference detection circuit.

[0002]

2. Description of the Related Art Generally, in a vehicle-mounted liquid crystal television or the like,
An internal horizontal synchronizing signal is generated based on a horizontal synchronizing signal separated from a video signal, and an image is displayed in synchronization with the internal horizontal synchronizing signal, thereby reducing the influence of external noise and the like.

Incidentally, the internal horizontal synchronizing signal needs to be in phase with the horizontal synchronizing signal separated from the video signal. It is premised that the internal horizontal synchronizing signal is separated from the video synchronizing signal. Needs to be detected.

For this purpose, conventionally, a synchronization signal processing circuit using a system clock synchronized with a color burst signal of a video signal compares data of a horizontal synchronization signal after A / D conversion with a predetermined synchronization separation level. Then, the horizontal synchronization area at a level lower than the synchronization separation level is subjected to addition / subtraction processing using two control pulses, and is further subjected to predetermined arithmetic processing to perform phase correction, and to reduce the phase difference of one clock or less. Detected.

[0005]

As described above, the conventional synchronous signal processing circuit performs A / D conversion processing on all input video signals and then calculates area to calculate phase difference data. I have to. Therefore, an A / D converter is indispensable, and all processes before calculating the phase difference data need to be handled as digital data, so that the overall circuit scale is large.

According to the present invention, the input video signal is synchronized with the horizontal synchronizing signal included in the video signal and the color burst signal included in the video signal without performing all A / D conversion processing as in the prior art. An object of the present invention is to make it possible to reliably detect a phase difference between a horizontal synchronization signal and an internal horizontal synchronization signal using an internal clock signal, and to reduce the circuit scale of a synchronization signal processing circuit as compared with the related art.

[0007]

In order to solve the above-mentioned problems, a synchronous signal processing circuit according to the present invention is configured as follows.

That is, the synchronization signal processing circuit according to the first aspect generates an internal horizontal synchronization signal based on an internal clock signal synchronized with the phase of a color burst signal included in a video signal, and separates the internal horizontal synchronization signal from the video signal. A synchronization signal processing circuit that detects a phase difference between the horizontal synchronization signal and the internal horizontal synchronization signal and performs phase control so that the phase difference between the two synchronization signals is eliminated. A phase difference between the horizontal synchronizing signal and the internal horizontal synchronizing signal based on a signal, an antiphase clock signal obtained by inverting the level of the internal clock signal, and a phase comparison reference signal generated based on the internal horizontal synchronizing signal. A phase difference detection circuit to be obtained is provided. This makes it possible to accurately detect a phase difference in clock units and a phase difference of 1 clock or less without performing A / D conversion and digital processing on all horizontal synchronization signals separated from a video signal as in the related art. it can.

According to a second aspect of the present invention, in the synchronous signal processing circuit according to the first aspect, the phase difference detecting circuit includes a period from a leading edge of the horizontal synchronizing signal to a rising edge of the reference signal for phase comparison, By detecting the period from the rising edge of the reference signal for comparison to the trailing edge of the horizontal synchronization signal using the internal clock signal,
A phase difference in clock units between the horizontal synchronizing signal and the internal horizontal synchronizing signal is obtained.

According to a third aspect of the present invention, in the synchronous signal processing circuit according to the first or second aspect, the phase difference detecting circuit is configured to detect the front and rear edges of the horizontal synchronizing signal with the internal clock signal and the opposite phase clock signal. The phase difference between the horizontal synchronizing signal and the internal horizontal synchronizing signal by one clock or less is determined by using the above-mentioned method.

According to a fourth aspect of the present invention, in the synchronous signal processing circuit according to any one of the first to third aspects, the phase difference detecting circuit comprises an internal horizontal synchronizing signal according to a degree of the detected phase difference. Is changed.

[0012]

Embodiments of the present invention will be described below.

In FIG. 1, 1 is a synchronization separation circuit, 2 is a horizontal synchronization extraction section, 3 is a synchronization signal edge detection circuit, 4 is a phase difference detection circuit, 5 is an internal synchronization generation circuit, and 6 is a phase difference detection flag creation circuit. , 7 are a jitter correction circuit, 8 is a clock phase correction circuit, and 9 is a division circuit.

The sync separation circuit 1 separates and extracts the composite sync signal from the video signal, and supplies the composite sync signal to the horizontal sync extractor 2 at the next stage.

The horizontal synchronizing extractor 2 separates only the horizontal synchronizing signal Hsync from the composite synchronizing signal, and outputs the horizontal synchronizing signal Hsync to the synchronizing signal edge detecting circuit 3, the phase difference detecting circuit 4, and the phase difference detecting flag creating circuit 6. Respectively.

On the other hand, the clock phase correction circuit 8 includes an internal clock signal CLK1 synchronized with the phase of the color burst signal included in the input video signal and this signal C1.
An inverted phase clock signal CLK2 obtained by inverting the level of LK1
Is created together. And each of these clock signals CL
Both K1 and CLK2 are input to the synchronization signal edge detection circuit 3 and the phase difference detection circuit 4, and the internal clock signal CLK1 is applied to the internal synchronization generation circuit 5.

Here, each edge before and after the low level period of the horizontal synchronizing signal Hsync is a reference position for examining the phase difference from the internal horizontal synchronizing signal HD. Need to be kept. Therefore, in this embodiment, the synchronization signal edge detection circuit 3 uses the two clock signals CLK1 and CLK2 output from the clock phase correction circuit 8 to use the front edge (from high level to low level) of the horizontal synchronization signal Hsync. By detecting the falling edge of the internal clock signal CLK1 and the trailing edge (rising edge from a low level to a high level).

That is, the synchronization signal edge detection circuit 3
As shown in FIGS. 2A and 2B, it is detected whether the leading edge of the horizontal synchronization signal Hsync is recognized first by the internal clock signal CLK1 or the antiphase clock signal CLK2.
Further, as shown in FIGS. 3A and 3B, the synchronizing signal edge detection circuit 3 recognizes the trailing edge of the horizontal synchronizing signal Hsync first by using either the internal clock signal CLK1 or the antiphase clock signal CLK2. Or to detect. Then, each time an edge before or after the horizontal synchronizing signal Hsync is detected, the detection signals Sf and Sb are output in response to the detection.

For example, when the leading edge of the horizontal synchronizing signal Hsync is detected by the internal clock signal CLK1 as shown in FIG. 2A, a high level is output as the detection signal Sf. ), The horizontal synchronization signal Hsyn
When the leading edge of c is detected by the opposite phase clock signal CLK2, a low level is output as the detection signal Sf. Further, as shown in FIG. 3A, the horizontal synchronizing signal Hsyn
When the trailing edge of c is detected by the internal clock signal CLK1, a high level is output as the detection signal Sb, and as shown in FIG. When detected by CLK2, a low level is output as the detection signal Sb.

On the other hand, as shown in FIG. 4, the phase difference detection flag creation circuit 6 has a constant pulse width T ₀ synchronized with the horizontal synchronization signal Hsync extracted by the horizontal synchronization extraction section 2 based on the horizontal synchronization signal Hsync. A phase difference detection flag F is created. The pulse width T ₀ is set so as to have a time sufficient to cover the low level period of the horizontal synchronization signal Hsync. Then, the phase difference detection flag F is provided to the phase difference detection circuit 4.

The internal synchronization generating circuit 5 receives the internal clock signal CLK1 output from the clock phase correction circuit 8, and based on the internal clock signal CLK1, as shown in FIG. A horizontal synchronizing signal HD is generated. Then, the internal horizontal synchronization signal H
D is supplied to a video signal processing circuit (not shown). Further, the internal synchronization generation circuit 5 has a predetermined pulse width T ₂ whose phase is delayed by a predetermined time T ₁ (for example, 2.7 μs) from the leading edge (falling edge) of the internal horizontal synchronization signal HD. A phase comparison reference signal B having a width of, for example, 30 μs is created.

In the above-described phase delay time T ₁ , the rising edge of the phase comparison reference signal B corresponds to the internal horizontal synchronization signal H
It is set in advance so as to be located exactly at the center of the low level period of D. Further, the pulse width T ₂ of the phase comparison reference signal B is set to a period that is about half of one cycle of the horizontal synchronization signal Hsync, which is about 63.5 μm.

As described above, the phase difference detection circuit 4 applies both clock signals C output from the clock phase correction circuit 8
LK1, CLK2, the horizontal synchronizing signal Hsync separated by the horizontal synchronizing extraction unit 2, the two types of detection signals Sf and Sb detected by the synchronizing signal edge detection circuit 3, and the reference signal for phase comparison generated by the internal synchronization generation circuit 5. B and the phase difference detection flag F created by the phase difference detection flag creation circuit 6 are both input.

Next, in the phase difference detection circuit 4, the phase difference in clock units between the horizontal synchronizing signal Hsync and the internal horizontal synchronizing signal HD (that is, 1 of the internal clock signal CLK1).
The operation in the case of detecting a phase difference in units of a cycle) and a phase difference of one clock or less will be described.

The phase difference detection circuit 4 is provided when the detection signal Sf at the time when the synchronization signal edge detection circuit 3 detects the leading edge of the horizontal synchronization signal Hsync is at a high level, ie, in the state shown in FIG. , Df1 = 0.25 is set as phase difference data (evaluation value) of one clock or less of the leading edge, and the detection signal S
When f is at a low level, that is, in the state of FIG.
Df1 = 0.75 is set as phase difference data (evaluation value) of one clock or less of the leading edge.

The reason is that when the leading edge of the horizontal synchronizing signal Hsync is detected by the internal clock signal CLK1, a period from the falling edge of the half cycle before the internal clock signal CLK1 to the present rising edge, that is, the internal clock signal In terms of the number of clocks of the signal CLK1, it is estimated that there is an edge of the horizontal synchronizing signal Hsync in the range of the phase difference of 0 to 0.5 clocks, so that an intermediate value of 0.25 can be evaluated as the phase difference. Because.
When the leading edge of the horizontal synchronizing signal Hsync is detected by the anti-phase clock signal CLK2, the internal clock signal CLK1 is output from the falling edge one half cycle before the anti-phase clock signal CLK2 to the present rising edge. In this case, from the rising edge one cycle before the rising edge of the internal clock signal CLK1 to the current falling edge, and if this is expressed by the number of clocks of the internal clock signal CLK1, it is 1.0 to 1.0.
This is because it is estimated that there is an edge of the horizontal synchronization signal Hsync in the range of the phase difference of 0.5 clocks, so that an intermediate value of 0.75 can be evaluated as the phase difference.

Similarly, when the detection signal Sb at the time when the trailing edge of the horizontal synchronizing signal is detected is at a high level, that is, in FIG.
3b, Db1 = 0.25 is set as the phase difference data (evaluation value) below the clock of the trailing edge, and if the detection signal Sb is at the low level, that is, if the state shown in FIG. Db1 = 0.75 is set as phase difference data (evaluation value) below the clock of the trailing edge.

As described above, since the phase comparison reference signal B is generated with reference to the leading edge of the internal horizontal synchronization signal HD, the phase of the internal horizontal synchronization signal HD is different from that of the horizontal synchronization signal Hsync. When shifted by Δ, the rising edge of the reference signal B for phase comparison also shifts by Δ in which the phase shift occurs.

Therefore, as can be seen from FIG. 4, when the phases of the horizontal synchronizing signal Hsync and the internal horizontal synchronizing signal HD match, the rising edge of the phase comparison reference signal B is equal to either of the signals Hsync and HD. Is located at the center of the low level period, but both signals Hsync, Hsync
When the phase of D is shifted, the phase comparison reference signal B
Is located at the center of the low level period of the internal horizontal synchronizing signal HD, but the horizontal synchronizing signal Hsync
Is not located at the center of the low level period.

Therefore, using the internal clock signal CLK1, the period Tf from the detection of the leading edge of the horizontal synchronizing signal Hsync to the rising edge of the phase comparison reference signal B, and the rise of the phase comparison reference signal B By measuring both the period Tb from the edge to the trailing edge of the horizontal synchronization signal Hsync, it is possible to detect the phase difference in clock units between the horizontal synchronization signal Hsync and the internal horizontal synchronization signal HD.

Therefore, the phase difference detection circuit 4 calculates the number of clocks of the internal clock signal CLK1 included in the low-level period Tf and the high-level period Tb of the phase comparison reference signal B in the horizontal synchronization signal Hsync, respectively. Count. Here, the count value during the period Tf is Df2, and the count value during the period Tb is Db2. In this case, the phase difference detection circuit 4 performs the phase comparison in clock units only during the period when the phase difference detection flag F is at the high level.

Subsequently, the phase difference detection circuit 4 counts the count value Df2 during the low level period Tf of the phase comparison reference signal B.
Then, a value Df is obtained by adding the phase difference data (evaluation value) Df1 set based on the detection signal Sf of the front edge of the horizontal synchronization signal Hsync. Therefore, Df = Df2 + Df1. Further, a value Db is obtained by subtracting the value Db1 set based on the detection signal Sb of the trailing edge of the horizontal synchronization signal Hsync from the count value Db2 of the high-level period Tb of the phase comparison reference signal B. Therefore, Db = Db2-Db1. Subsequently, the phase difference detection circuit 4 obtains and outputs a value D obtained by subtracting both Df and Db. Therefore, D = D
f-Db = (Df2 + Df1)-(Db2-Db1).

Since the value of D, which is the phase difference data calculated by the phase difference detection circuit 4 in this manner, is twice the actual phase difference, this value D is calculated by the division circuit 9 in the next stage. D / 2 is further calculated by 1/2. Here, this D /
An integer value of the two values is a phase difference in clock units, and a value after the decimal point indicates a phase difference of one clock or less.

Thus, the D / 2 obtained by the dividing circuit 9
The integer part (that is, the data of the phase difference in clock units) of the values of is input to the internal synchronization generation circuit 5, and the internal horizontal synchronization signal HD is adjusted in phase in clock units. On the other hand, in the value of D / 2, a portion below the decimal point (that is, data of a phase difference below the clock) is input to the jitter correction circuit 7 and a video signal processing unit (not shown) processes the video signal. Is used as data for jitter correction.

As described above, the phase of the internal horizontal synchronization signal HD can be controlled according to the state of the phase difference detected by the phase difference detection circuit 4.

In the above description of the embodiment,
And a relatively small phase difference between the internal horizontal synchronizing signal HD to the horizontal synchronizing signal Hsync, if the rising edge of the phase comparison reference signal B is always fall within a high level period T ₀ of the phase difference detection flag F (see FIG. 4) Although there was a, when the phase difference between the internal horizontal synchronizing signal HD to the horizontal synchronization signal Hsync becomes large, the rising edge of the phase comparison reference signal B fall within a high level period T ₀ of the phase difference detection flag F It may disappear. In such a case, the phase difference detection circuit 4 performs the following processing operation.

FIG. 5 shows the phase relationship between the phase difference detection flag F created by the phase difference detection flag creation circuit 6 and the phase comparison reference signal B generated by the internal synchronization generation circuit 5. In FIG. 7A, as in the description of the above embodiment,
In this state, the rising edge of the phase comparison reference signal B exists within the high-level period T ₀ of the phase difference detection flag F. In this case, the phase difference detection circuit 4 operates as follows:
Df-Db is output.

FIG. 3B shows a state in which the phase of the internal horizontal synchronizing signal HD is delayed and the rising edge of the phase comparison reference signal B does not exist within the high level period T _{0 of the} phase difference detection flag F. Yes, the phase difference detection circuit 4 in this case
Outputs D = Df-0 = Df.

In FIG. 3C, the phase of the internal horizontal synchronizing signal HD is advanced, and the rising edge of the phase comparison reference signal B does not exist within the high level period T _{0 of the} phase difference detection flag F. Yes, the phase difference detection circuit 4 in this case
Outputs D = 0−Db = −Db.

In FIG. 4D, the phase shift of the internal horizontal synchronizing signal HD is extremely large, and the falling edge of the phase comparison reference signal B falls within the high-level period T _{0 of the} phase difference detection flag F. In this case, the phase difference detection circuit 4 determines that D = maximum value (+2 in the case of 8 bits).
55) is output.

As shown in FIG. 7E, if there is no high-level period for the phase difference detection flag F, it is considered that the horizontal synchronization signal Hsync has not been input from the outside. The phase difference detection circuit 4 calculates D =
Outputs 0.

As described above, if the phase control amount for the internal horizontal synchronizing signal HD is changed in accordance with the detected phase difference as shown in FIG. 5, the phase pull-in speed is improved.

[0043]

According to the synchronization signal processing circuit according to the present invention, the following effects can be obtained.

(1) Even if all the video signals are once A / D-converted and the phase difference is not determined as in the prior art, the clock processing can be performed so that the position of the clock unit between the horizontal synchronizing signal and the internal horizontal synchronizing signal is obtained. The phase difference and the phase difference of one clock or less can be accurately detected. For this reason, the circuit scale of the synchronization signal processing circuit can be reduced as compared with the related art.

(2) In particular, by detecting the leading and trailing edges of the horizontal synchronizing signal using the internal clock signal and the inverted phase clock signal whose level is inverted, the internal horizontal synchronizing signal with respect to the horizontal synchronizing signal is detected. The phase difference can be detected more accurately.

(3) Further, if the phase control amount for the internal horizontal synchronizing signal is changed according to the detected phase difference, the phase pull-in speed is increased and the input horizontal synchronizing signal is lost. Phase can be stabilized during the operation.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a synchronization signal processing circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing an operation when a leading edge of a horizontal synchronization signal is detected by an internal clock signal and an opposite-phase clock signal in the embodiment of the present invention;

FIG. 3 is a timing chart showing an operation when a trailing edge of a horizontal synchronization signal is detected by an internal clock signal and an opposite-phase clock signal in the embodiment of the present invention;

FIG. 4 is a timing chart showing respective relationships among an internal clock signal, a phase difference detection flag, a horizontal synchronization signal, an internal horizontal synchronization signal, and a phase comparison reference signal input to a phase difference detection circuit in the embodiment of the present invention. chart

FIG. 5 is a timing chart showing a relationship between a phase comparison reference signal input to a phase difference detection circuit and a phase difference detection flag in the embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Synchronization separation circuit, 2 ... Horizontal synchronization extraction part, 3 ... Synchronization signal edge detection circuit, 4 ... Phase difference detection circuit, 5 ... Internal synchronization generation circuit, 6 ... Phase difference detection flag creation circuit, 7 ... Jitter correction circuit, 8: clock phase correction circuit, 9: division circuit.

Continued on the front page F term (reference) 5C020 AA16 AA32 AA35 CA15 5C066 AA03 CA17 DA08 EB11 EC06 EG02 GA04 GA13 GA20 JA07 KA05 KA13 KB03 KB05 KD03 5C080 AA10 BB05 DD22 EE29 FF09 GG08 GG09 JJ02 JJ04

Claims (4)

[Claims] An internal horizontal synchronizing signal is generated based on an internal clock signal synchronized with a phase of a color burst signal included in a video signal, and a horizontal synchronizing signal separated from the video signal and the internal horizontal synchronizing signal are generated. A synchronous signal processing circuit that detects the phase difference between the two synchronous signals and performs phase control so that the phase difference between the two synchronous signals is eliminated. The level of the horizontal synchronous signal, the internal horizontal synchronous signal, the internal clock signal, and the internal clock signal is inverted. A synchronization signal processing circuit including a phase difference detection circuit that calculates a phase difference between a horizontal synchronization signal and an internal horizontal synchronization signal based on an anti-phase clock signal and a reference signal for phase comparison generated based on the internal horizontal synchronization signal. . 2. The phase difference detection circuit according to claim 1, wherein a period from a leading edge of the horizontal synchronization signal to a rising edge of the reference signal for phase comparison and a period from a rising edge of the reference signal for phase comparison to a trailing edge of the horizontal synchronization signal. 2. The synchronous signal processing circuit according to claim 1, wherein a phase difference in clock units between the horizontal synchronizing signal and the internal horizontal synchronizing signal is obtained by detecting the internal clock signal and the internal clock signal. 3. The phase difference detecting circuit detects one of the leading and trailing edges of a horizontal synchronizing signal using the internal clock signal and the anti-phase clock signal, thereby detecting one clock of the horizontal synchronizing signal and the internal horizontal synchronizing signal. 3. The synchronization signal processing circuit according to claim 1, wherein the following phase difference is obtained. 4. The synchronizing signal according to claim 1, wherein said phase difference detecting circuit changes a phase control amount for an internal horizontal synchronizing signal in accordance with a degree of the detected phase difference. Processing circuit.