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JPS60229590A - Timing pulse generating circuit - Google Patents

Timing pulse generating circuit

Info

Publication number
JPS60229590A
JPS60229590A JP59085491A JP8549184A JPS60229590A JP S60229590 A JPS60229590 A JP S60229590A JP 59085491 A JP59085491 A JP 59085491A JP 8549184 A JP8549184 A JP 8549184A JP S60229590 A JPS60229590 A JP S60229590A
Authority
JP
Japan
Prior art keywords
signal
horizontal
synchronizing signal
synchronization signal
timing pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59085491A
Other languages
Japanese (ja)
Inventor
Toshihiko Tsuru
鶴 敏彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59085491A priority Critical patent/JPS60229590A/en
Publication of JPS60229590A publication Critical patent/JPS60229590A/en
Pending legal-status Critical Current

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  • Television Systems (AREA)
  • Pulse Circuits (AREA)

Abstract

PURPOSE:To simplify the circuit and to improve the stability and precision by controlling the start of counting with a vertical synchronizing signal, counting a horizontal synchronizing signal and comparing the counted horizontal synchronizing signal with a horizontal line set externally, and outputting a timing pulse when they coincide with each other. CONSTITUTION:When a composite video signal (a) is inputted from a composite video signal input 2, a synchronous separating circuit 3 separates and outputs its synchronizing signal. Therefore, the synchronizing signal is inputted to a horizontal synchronizing signal generating circuit 4 and a vertical synchronizing signal generating circuit 5 to generate a horizontal synchronizing signal (e) and a vertical synchronizing signal (d). A monostable multivibrator circuit 6 expands the vertical synchronizing signal (d) like a signal (g). A counter 7 starts counting the horizontal synchronizing signal (e) after the signal (g) is outputted and supplies the result to a comparator 8. The comparator 8 compares the count signal with the horizontal line set with a line setting signal from a line setting signal input 1 and outputs the timing pulse signal (h) for the horizontal line when they coincide with each other.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、特にテレビジョン信号の特定の水平ラインを
選択するだめのタイミングノ(ルスの発生回路に関する
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention particularly relates to a timing pulse generation circuit for selecting a particular horizontal line of a television signal.

〔従来技術及びその問題点〕[Prior art and its problems]

一般に、テレビジョン信号において、垂直消去期間内の
特定の水平ラインに種々のイa@を重畳させる場合があ
る。この場合、重畳ラインを決定するのに、垂直のタイ
ミングと水平のタイミングを決める同期信号が必要であ
るが、外部との接続の容易さから外部同期を不要とする
べく、複合映像信号の入力から同期を分離する方式がよ
く用いられる。
In general, in a television signal, various types of Ia@ may be superimposed on a specific horizontal line within a vertical erasing period. In this case, a synchronization signal that determines the vertical timing and horizontal timing is required to determine the superimposition line, but in order to eliminate the need for external synchronization for ease of external connection, we A method of separating synchronization is often used.

ここで第1図(4)〜(ト)は従来例の信号波形を示す
タイムチャート図である。上記の如く、入力された複合
映像信号a(第1図(4)参照)は切替器等(図示せず
)により平均映像レベルの異なる信号が切替られる。こ
の切替は一般に、垂直同期信号d(同図(ハ)参照)の
付近の切替タイミングエムで行なうので、信号aの波形
は第1図(4)の如くなシ、同期分離回路では第1図0
3)に示す信号すの如く応答が追いつかず、第1図(C
)の如く分離同期信号Cが欠ける場合があった。これは
平均映像レベルの差が大きい程顕著となる。
Here, FIGS. 1(4) to 1(g) are time charts showing signal waveforms in the conventional example. As described above, the input composite video signal a (see FIG. 1 (4)) is switched between signals having different average video levels by a switch or the like (not shown). This switching is generally performed at the switching timing M near the vertical synchronization signal d (see (c) in the same figure), so the waveform of the signal a is as shown in Fig. 1 (4). 0
3), the response could not keep up with the signal shown in Figure 1 (C
), there were cases where the separated synchronization signal C was missing. This becomes more noticeable as the difference in average video level increases.

このため、垂直同期信号dの後の水平同期信号e(第1
図面参照)の欠けによシ、単純に水平同期を計算してい
ると、第1図(ト)の如くタイミングパルス信号fは実
線が正規のタイミングであるにかかわらず、同図(ト)
中破線で示す信号f′の如くタイミングがずれることが
あるという欠点があった。
Therefore, the horizontal synchronization signal e (first
However, if you simply calculate the horizontal synchronization, the timing pulse signal f will be as shown in Figure 1 (G), even though the solid line is the normal timing, as shown in Figure 1 (G).
There is a drawback that the timing may be shifted as shown by the signal f' indicated by the middle broken line.

これを避ける手段としては、分離同期信号により発振器
を制御して同期の再生を行なう方法もあるが、回路が複
雑化すると共に、ジッター等の特性的な問題も生ずると
いう欠点があった。
One way to avoid this is to regenerate synchronization by controlling the oscillator using a separate synchronization signal, but this method has the drawbacks of complicating the circuit and causing characteristic problems such as jitter.

又単に垂直同期信号をトリガーとするモノマルチ回路の
出力では水平ラインのタイミングを決めるには安定度及
び精度の点で不十分であるという欠点があった。
Another disadvantage is that the output of a mono multi-circuit that is simply triggered by a vertical synchronization signal is insufficient in terms of stability and accuracy to determine the timing of a horizontal line.

〔発明の目的〕[Purpose of the invention]

本発明は、入力の複合映像信号より分離した同期信号よ
り、水平同期信号及び垂直同期14号を生成し、前記垂
直同期信号をモノマルチ回路によシ一定幅に延ばす、垂
直同期信号後の安定した時点から水平同期信号を計数す
る様にカウンターを制御して、比較器で設定ラインと一
致した水平ラインのタイミングを作り出すことにより、
垂直同期信号付近での映像信号の切替に対し、安定な水
平ラインのタイミングパルスを発生させるようにし、上
記欠点を除去したタイミングパルス発生回路を提供する
ことを目的とする。
The present invention generates a horizontal synchronizing signal and a vertical synchronizing signal No. 14 from a synchronizing signal separated from an input composite video signal, and extends the vertical synchronizing signal to a constant width using a mono multi-circuit. By controlling the counter to count horizontal synchronization signals from the point in time, and using a comparator to create a horizontal line timing that matches the set line,
It is an object of the present invention to provide a timing pulse generation circuit which generates a stable timing pulse of a horizontal line when switching a video signal near a vertical synchronization signal, and which eliminates the above-mentioned drawbacks.

〔発明の構成〕[Structure of the invention]

そのための本発明の構成は、複合映像信号から同期信号
を分離する手段と、前記分離した同期信号から水平同期
信号を発生する手段と、前記分離した同期信号から垂直
同期信号を発生する手段と、前記垂直同期信号をトリガ
ーとして信号を出力するモノマルチ手段と、前記信号に
より計数の開始を制御され、前記水平同期信号を割数す
る手段と、前記計数された水平同期信号と外部で設定さ
れた水平ラインとを比較し、−iしたときにタイミング
パルスを出力する比較手段とよシ構成してなるものであ
る。
To achieve this, the configuration of the present invention includes means for separating a synchronization signal from a composite video signal, means for generating a horizontal synchronization signal from the separated synchronization signal, and means for generating a vertical synchronization signal from the separated synchronization signal. monomulti means for outputting a signal using the vertical synchronization signal as a trigger; means for controlling the start of counting by the signal and dividing the horizontal synchronization signal; It is constructed with a comparison means that compares the horizontal line and outputs a timing pulse when -i.

〔発明の実施例〕[Embodiments of the invention]

次に、その一実施例を図面と共に説明する。 Next, one embodiment will be described with reference to the drawings.

第2図は本発明になるタイミングパルス発生回路の一実
施例のブロック図であり、その動作を第1図(A)−■
、 (G) 、 lυを適宜使用して説明する。
FIG. 2 is a block diagram of an embodiment of the timing pulse generation circuit according to the present invention, and its operation is illustrated in FIGS.
, (G), and lυ as appropriate.

第2図中、lはライン設定信号入力、2は複合映像信号
入力であシ、又3は同期分離回路、4は水平同期信号発
生回路、5は垂直同期信号発生回路、6はモノマルチ回
路、7はカウンタ、8は比較器、9はタイミングパルス
信号出力である。
In Figure 2, l is a line setting signal input, 2 is a composite video signal input, or 3 is a sync separation circuit, 4 is a horizontal sync signal generation circuit, 5 is a vertical sync signal generation circuit, and 6 is a mono multi circuit. , 7 is a counter, 8 is a comparator, and 9 is a timing pulse signal output.

次に、その動作につき説明する。複合映像信号人力2か
ら複合映像信号a(第1図囚参照)が入力すると、同期
分離回路3はこれから同期信号を分離して出力する。従
って水平同期信号発生回路4及び垂直同期信号発生回路
5では上記同期信号を入力されて、夫々第1図■、(1
)>の如く水平同期信号e1垂直同期信号dを発生する
。モノマルチ回路6は、垂直同期信号dを入力され、こ
れを第1図(G)に示す信号gの如く引延ばす。従って
カウンタ7では、前記信号gの出力の後から水平同期信
号eを計数開始することになり、これを比較器8に供給
する。従って、比較器8では、ライン設定信号人力1か
らのライン設定信号で設定された水平ラインと上記計数
信号とを比較し、一致したところで、該当の水平ライン
のタイミングパル信号h (第1図I参照)を出力する
Next, the operation will be explained. When a composite video signal a (see FIG. 1) is input from the composite video signal input 2, the synchronization separation circuit 3 separates and outputs a synchronization signal from it. Therefore, the horizontal synchronization signal generation circuit 4 and the vertical synchronization signal generation circuit 5 receive the synchronization signal as shown in FIG.
)>, a horizontal synchronizing signal e1 and a vertical synchronizing signal d are generated. The monomulti circuit 6 receives the vertical synchronizing signal d and stretches it as a signal g shown in FIG. 1(G). Therefore, the counter 7 starts counting the horizontal synchronizing signal e after the output of the signal g, and supplies this to the comparator 8. Therefore, the comparator 8 compares the horizontal line set by the line setting signal from the line setting signal 1 with the above count signal, and when they match, the timing pulse signal h of the corresponding horizontal line (I reference) is output.

以上の如く、切替の影響にある付近TAではモノマルチ
回路6によシ粗いタイミングを出し、その袋を水平同期
信号eの計数によシ水平ラインを決定するようにしてい
るので、安定した水平ラインのタイミングパルス信号り
を得ることができる。
As mentioned above, in the vicinity TA affected by switching, rough timing is output to the mono multi circuit 6, and the horizontal line is determined by counting the horizontal synchronization signal e, so that stable horizontal Line timing pulse signals can be obtained.

〔発明の効果〕 以上説明した如く、本発明に係るタイミングパルス発生
回路によれば、入力の複合映像信号より分離した同期信
号よシ水平同期信号及び垂直同期信号を生成し、帥記垂
直同期信号をモノマルチ回路により一定幅に延ばし、垂
直同期信号後の安定した時点から水平同期信号を計数す
るようにカウンタを制御して、比較器で設定ラインと一
致した水平ラインのタイミングを作り出すようにしてい
るため、垂直同期信号付近での映像の切替に対し、水平
同期に一致した水平ラインのタイミングパルスを発生さ
せることができ、しかも回路構成も簡単でおるという利
点がある。
[Effects of the Invention] As described above, the timing pulse generation circuit according to the present invention generates a horizontal synchronization signal and a vertical synchronization signal from a synchronization signal separated from an input composite video signal, and generates a horizontal synchronization signal and a vertical synchronization signal. is extended to a certain width using a mono multi-circuit, the counter is controlled to count horizontal synchronization signals from a stable point after the vertical synchronization signal, and a comparator is used to create the timing of the horizontal line that matches the set line. Therefore, it is possible to generate a horizontal line timing pulse that matches horizontal synchronization when switching images near a vertical synchronization signal, and the circuit configuration is also simple.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(4)〜■は夫々従来又は本発明になるタイミン
グパルス発生回路の各種信号のタイムチャート図、第2
図は本発明になるタイミングノ(ルス発生回路の一実施
例のブロック図である。 l・・・ライン設定信号入力 2・・・複合映像信号入力 3・・・同期分離回路 4・・・水平同期信号発生回路 5・・・垂直同期信号発生回路 6・・・モノマルチ回路 7・・・カウンタ 8・・・比較器 9・・・タイミングパルス信号出力 出願人 日本電気株式会社
Figures 1 (4) to (2) are time charts of various signals of the conventional timing pulse generation circuit or the present invention, respectively;
The figure is a block diagram of an embodiment of the timing pulse generation circuit according to the present invention. l...Line setting signal input 2...Composite video signal input 3...Synchronization separation circuit 4...Horizontal Synchronization signal generation circuit 5...Vertical synchronization signal generation circuit 6...Monomulti circuit 7...Counter 8...Comparator 9...Timing pulse signal output Applicant: NEC Corporation

Claims (1)

【特許請求の範囲】[Claims] 複合映像信号から同期信号を分離する手段と、前記分離
した同期信号から水平同期信号を発生する手段と、前記
分離した同期信号から垂直同期信号を発生する手段と、
前記垂直同期信号をトリガーとして信号を出力するモノ
マルチ手段と、前記信号により計数の開始を制御され、
前記水平同期信号を計数する手段と、前記計数された水
平同期信号と外部で設定された水平ラインとを比較し、
一致したときにタイミングパルスを出力する比較手段と
より構成してなることを特徴とするタイミングパルス発
生回路。
means for separating a synchronization signal from a composite video signal; means for generating a horizontal synchronization signal from the separated synchronization signal; and means for generating a vertical synchronization signal from the separated synchronization signal;
mono-multi means for outputting a signal using the vertical synchronization signal as a trigger, and the start of counting is controlled by the signal;
means for counting the horizontal synchronization signal; comparing the counted horizontal synchronization signal with an externally set horizontal line;
1. A timing pulse generation circuit comprising: comparison means that outputs a timing pulse when a match occurs.
JP59085491A 1984-04-27 1984-04-27 Timing pulse generating circuit Pending JPS60229590A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59085491A JPS60229590A (en) 1984-04-27 1984-04-27 Timing pulse generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59085491A JPS60229590A (en) 1984-04-27 1984-04-27 Timing pulse generating circuit

Publications (1)

Publication Number Publication Date
JPS60229590A true JPS60229590A (en) 1985-11-14

Family

ID=13860397

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59085491A Pending JPS60229590A (en) 1984-04-27 1984-04-27 Timing pulse generating circuit

Country Status (1)

Country Link
JP (1) JPS60229590A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5453795A (en) * 1991-07-02 1995-09-26 Thomson Consumer Electronics, Inc. Horizontal line counter insensitive to large phase shifts of video
US5619275A (en) * 1992-09-01 1997-04-08 Thomson Consumer Electronics, Inc. TV line and field detection apparatus with good noise immunity

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5453795A (en) * 1991-07-02 1995-09-26 Thomson Consumer Electronics, Inc. Horizontal line counter insensitive to large phase shifts of video
US5619275A (en) * 1992-09-01 1997-04-08 Thomson Consumer Electronics, Inc. TV line and field detection apparatus with good noise immunity

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