JP2000340674A - Mos capacitor and manufacture of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the breakdown voltage of a MOS capacitor formed in a CMOS device and to facilitate manufacturing of the MOS capacitor. SOLUTION: In this manufacturing method of MOS capacitors 42 and 43 formed in a CMOS device having a P-channel MOS transistor 41 and an N- channel MOS transistor 40, channel stopper regions 9 and 10 which interrupt influence between the transistors 40 and 41 are installed on the surface of a semiconductor substrate 1, and a CMOS transistor is formed. Also electrodes 18 and 19 are formed on the one conductivity-type region of the semiconductor substrate 1 via an insulating film 12. The region 27 and 28 of high concentration in the same conductivity-type are formed in a region adjacent to the insulating film 12 in the one conductivity-type region in a process similar to the forming process for the channel stopper regions 9 and 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a P-channel MOS
The present invention relates to a MOS capacitor formed in a complementary (C) MOS device in which a transistor and an N-channel MOS transistor are formed on the same semiconductor substrate, and a method of manufacturing the MOS capacitor.

[0002]

2. Description of the Related Art In a MOS structure, an oxide film 33 is interposed between a metal electrode 32 and a semiconductor substrate 31, as shown in FIG. Since the oxide film 33 is a dielectric, a MOS
The structure can be operated as a capacitance. Under the voltage condition in which the storage layer is formed, since there is no depletion layer, the capacitor has only the capacitance Co and has no voltage dependency.
When a negative voltage is applied to the metal electrode 32 when the semiconductor substrate 3 is n-type, the depletion layer 34 expands and a capacitance value Cs is generated as shown in FIG.

FIG. 10 shows a CV characteristic curve of a MOS capacitor when the semiconductor substrate 31 is a p-type. It is a curve obtained by measuring a capacitance while applying a DC bias voltage for a MOS structure. The horizontal axis is the voltage V, and the vertical axis is the capacitance C. As the DC bias voltage V is increased, C-V
(Capacity) curves are very different like C1 or C2. Here, the curve C1 is a case where the impurity concentration of the semiconductor substrate is lower than that of the curve C2, and when the same voltage is applied, the depletion layer 34 has a large spread.

[0004]

However, when the MOS capacitor is formed in a CMOS device, a semiconductor substrate or a well formed on the semiconductor substrate is used. However, these semiconductor substrates or wells have a low impurity concentration. Therefore, there is a problem that the voltage dependency of the MOS capacitor is large.

The present invention has been made in view of the above circumstances, and has as its object to provide a MOS capacitor formed in a CMOS device and having reduced voltage dependency.

Another object of the present invention is to provide a MOS capacitor for easily forming the MOS capacitor.

[0007]

SUMMARY OF THE INVENTION A MOS capacitor according to the present invention is a P-channel MOS transistor for solving the above problems.
In a MOS capacitor formed in a CMOS device having both an S transistor and an N-channel MOS transistor, a high-concentration region of the same conductivity type as that of the semiconductor region is formed in a semiconductor region located below an insulating film constituting the MOS capacitor. Formed adjacently.

Further, a method of manufacturing a MOS capacitor according to the present invention is directed to a P-channel MOS
In a method of manufacturing a MOS capacitor formed in a COMS device having both an S transistor and an N-channel MOS transistor, a CMOS transistor is formed by providing a channel stopper region on a surface of a semiconductor substrate to block an influence between the two transistors. An electrode is formed on a region of one conductivity type of the semiconductor substrate via an insulating film to form a MOS capacitor, and a high-concentration region of the same conductivity type is formed in a region adjacent to the insulating film in the region of one conductivity type. The region is formed in the same step as the channel stopper region forming step.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for manufacturing a MOS capacitor according to the present invention will be described with reference to the drawings.
What is manufactured by this method of manufacturing a CMOS device is
This is a CMOS device having a capacitor element.
In this CMOS device, an n-type silicon single crystal is cut into a wafer, the surface is mirror-polished, the wafer is exposed to a high-temperature oxygen atmosphere, and a silicon oxide film is grown. A p-well region is formed, and a p-well impurity is doped and thermally diffused to form a p-well (p-well forming step).
Then, it is manufactured through the steps shown in FIG.

As shown in FIG. 1, a pad oxide film 50 is formed on a semiconductor substrate 1 and wells 2 and 3, and the oxide film 5
The resist 20 is formed on the zero. Then, in order to form a channel stopper region in the p-type well 2 and a first capacitor region in the p-type well 3 formed in the conductive substrate 1, as shown by arrows from the opening of the resist 20,
B (boron) ions are implanted through the oxide film 50. Then, as shown in FIG. 2, the resist 20 is removed, and P (P) is passed through the oxide film 50 from the opening of the resist 21 in order to form a channel stopper and a second capacitor region at necessary places on the surface of the semiconductor substrate 1. Phosphorus) implant ions. Next, as shown in FIG. 3, the resist 21 is removed, and a nitride film 22 is formed on the drain and source formation regions and the first and second capacitor regions. Next, as shown in FIG. 4, the field oxide film 11 for separating elements is formed by applying heat using the nitride film 22. At the same time, the implanted ions B and P are diffused to form the channel stopper 9, the channel stopper 10, the first capacitor region 27, and the second capacitor region 28.

Next, as shown in FIG. 5, after removing the nitride film 22, removing the pad oxide film 50 and forming the gate oxide film 12, a conductive polycrystalline silicon layer 15 is formed on the upper surface. Next, as shown in FIG. 6, an N-MOS gate electrode 1 is formed.
6. The gate electrode 17 of the P-MOS, the extraction electrode 18 of the first capacitor, and the extraction electrode 19 of the second capacitor are formed.

Next, as shown in FIG. 7, the drain region (N + type) 5, the source region (N + type) 6, and the
The drain region (P + type) 7 and the source region (P + type) 8 of the MOS region are formed by ion implantation using boron or phosphorus. Next, as shown in FIG. 8, an insulating film 24 is laminated, and thereafter, a metal wiring layer 15A, 15B, 15C, 15D,
15E, 15F, 15G, and 15H are stacked. The metal wiring layers 15A, 15B, 15C, and 15D are connected to the drain / source regions 5, 6, 7, and 8 through contact windows formed in the film 24 and a part of the oxide film thereunder. Then, the metal wiring layers 15E, 15F, 15G, 15
H is connected to the extraction electrodes 18 and 19 of the first and second capacitors 42 and 43 and the capacitor regions 27 and 28. By the above manufacturing process, the N-MOS 40, the P-MO
A CMOS device including S41 and capacitors 42 and 43 is formed.

The first capacitor 42 includes the electrode 18, the oxide film 12, and the P-type region 27, and the second capacitor 43 includes the electrode 19, the oxide film 12, and the N-type region 28. Here, the P-type region 27 and the N-type region 28
The impurity concentration of the well 3 and the semiconductor substrate 1 is higher than that of the well, and the voltage dependency of the capacitor is reduced.

Further, compared to the conventional MOS capacitor manufacturing process, the manufacturing can be performed without increasing the number of steps for forming the high-concentration P-type region 27 and the N-type region 28. That is, the conventional channel stopper regions 9 and 10 are formed after forming the nitride film 22 shown in FIG. 3, but in the present invention, as described above, the channel stopper regions 9 and 10 are It is formed before forming (steps in FIGS. 1 and 2). As a result, the high-concentration region 27 of the MOS capacitor 42 is formed in advance by using the channel stopper region 9 and the high-concentration region 28 of the MOS capacitor 43 is formed by using the channel stopper region 10.

In the above description, the oxide film 12 may be an insulating film, and is not limited to this. Further, both the first and second capacitors 42 and 43 may be provided, or either one may be provided.

[0016]

According to the device of the present invention, since the high-concentration capacitor region is provided, the fluctuation of the CV characteristic can be suppressed, and the high-concentration region uses the channel stopper layer of the CMOS device. And can be easily formed.

[Brief description of the drawings]

FIG.

FIG. 2

FIG. 3

FIG. 4

FIG. 5

FIG. 6

FIGS. 1 to 7 are views for explaining a method of manufacturing a CMOS device according to the present invention.

FIG. 8 is a diagram for explaining a CMOS device formed by the method for manufacturing a CMOS device according to the present invention.

FIG. 9 is a diagram for explaining the principle of the MOS capacitor structure.

FIG. 10 is a diagram showing a CV characteristic curve of a MOS capacitor.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 n-type semiconductor substrate 2, 3 p-well 9 n-channel stopper 10 p-channel stopper 27, 28 capacitor region 40 N-MOS transistor 41 P-MOS transistor 42, 43 MOS capacitor

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 27/092 29/94

Claims (2)

[Claims] In a MOS capacitor formed in a COMS device having both a P-channel MOS transistor and an N-channel transistor, a semiconductor region located below an insulating film forming the MOS capacitor has a high conductivity type of the same conductivity type as the semiconductor region. A MOS capacitor, wherein a region is formed adjacent to the insulating film. 2. A method of manufacturing a MOS capacitor formed in a COMS device having both a P-channel MOS transistor and an N-channel MOS transistor, wherein a CMOS is provided by providing a channel stopper region on the surface of the semiconductor substrate for blocking the influence between the two transistors. A transistor is formed, an electrode is formed on the one conductivity type region of the semiconductor substrate via an insulating film to form a MOS capacitor, and a region adjacent to the insulating film in the one conductivity type region is A method for manufacturing a MOS capacitor, wherein a high-concentration region of the same conductivity type is formed in the same step as the channel stopper region forming step.