JP2000330500A - Liquid crystal display device and its applied equipment - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To reduce the frequency of an input data signal by dividing it and simultaneously input it to a plurality of driver circuits to cope with higher resolution of a high frequency. Due to the increase in resolution, the frequency cannot be supported by the source driver IC alone. SOLUTION: Asynchronous reading with frequency dividing means 22 and data storing means 24 by dividing and dividing a data bus,
By combining the division of the source driver, the simultaneous driving of a plurality of the source drivers, and the division of the source driver substrate, the source driver IC supports high resolution and high frequency which are not individually supported.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and its applied equipment.

[0002]

2. Description of the Related Art A display method of a conventional liquid crystal display device is shown in FIG.
This will be described with reference to FIG. FIG. 18 is a view showing a conventional liquid crystal display device. In FIG. 18, 201 is a liquid crystal panel,
202 is a display control board, 203 is a signal line electrode drive circuit board or a source driver board (hereinafter described as a source driver board), and 204 is a scan line electrode drive circuit board or a gate driver board (hereinafter described as a gate driver board). ) And 205 are means for connecting the source driver IC and the liquid crystal panel, 206 is means for connecting the gate driver IC and the liquid crystal panel, 207 is a connection cable between the source driver board and the display control board, and 208 is a connection between the gate driver board and the display control board Cable. FIG. 19 is a diagram showing a main configuration of a display control board portion of a conventional liquid crystal display device. In FIG. 19, 211 is an input terminal, 212 is a display control means, and 213 is an output terminal. FIG. 20 shows a panel and a source driver substrate of a conventional liquid crystal display device. In FIG. 20, 221 is a liquid crystal panel, and 222 is a source driver substrate. The source driver board 222
It is composed of one sheet.

[0003]

In recent years, there has been remarkable progress in increasing the resolution of displays. When color displays began to spread, the resolution was VGA (Video
o Graphics Array)
The display was 0 pixels and 480 vertical lines. This is SV
It is called GA (Super VGA), which has 800 horizontal pixels and 600 vertical pixels, and has an XGA (Extended G
1024 pixels in width and 768 in height, which is called a graphics architecture (SXGA).
upper XGA), 1280 horizontal pixels, 1 vertical
024 pixels or UXGA (Ultra XGA), 1600 horizontal pixels, 1200 vertical pixels, HDTV (Hi
gh Definition Television)
It has a resolution of 1920 horizontal pixels and 1080 vertical lines, and a resolution called QXGA (Quadruple XGA) of 2048 horizontal pixels and 1536 vertical lines. FIG. 21 shows examples of these resolutions. In FIG. 21, 231 is VGA, 232 is SVGA, 233 is XGA, 234 is SXGA, 235 is UXGA, 236
Indicates HDTV and 237 indicates QXGA. Furthermore, high-resolution ones, resolutions in which the flatness ratio of 4: 3 or 5: 4 is widened (widened) to 16: 9, etc., and broadcasting standards (N
Some resolutions depend on TSC, PAL, SECAM, etc. and computer standards (computers manufactured by International Business Machines, Sun Microsystems, Apple Computer, etc.). Such a progress in higher resolution, on the other hand, raises the problem of higher clock frequency of the drive circuit, while improving the performance of higher definition. The total number of pixels at each resolution is: Total_Pixel = Horizontal_Dot × Vertical_Line (Equation 1) Here, Total_Pixel: number of pixels, Horizontal_Pixel: number of horizontal pixels, Vertical_Line: number of vertical lines. Equation 1
Therefore, in VGA (640 × 480), 307,200
Pixel, 480,00 for SVGA (800 × 600)
0 pixels, 786,4 for XGA (1024 × 768)
For 32 pixels, SXGA (1280 × 1024), 1,
310,720 pixels, UXGA (1600 × 1200)
Then, 1,920,000 pixels, HDTV (1920 ×
1080), 2,073,600 pixels, QXGA
In (2048 × 1536), it is 3,145,728 pixels.

[0004] At present, even in a liquid crystal display,
Similar to a CRT (Cathode RayTube) display, driving is often performed in consideration of a blank period. Here, for the sake of simplicity, a trial calculation is first performed excluding the blank period. Next, as the blank period, a value obtained by adding 40% is shown as an example. This allows for about 30% of the horizontal blank period and about 10% of the vertical blank period. The following are all clock frequencies when the frame frequency is 60 Hz. For each resolution given above, the resolution, the clock frequency without a blank period, and the clock frequency with a blank period are listed. Here, Frequency_Without_Blanking: Clock frequency without blanking period, Frequency_With_Blanking:
Clock frequency with blanking period, Frame: number of frames per second, Blanking_Rate: coefficient of blank period (here, 1.4).

From equations (2) and (3), VGA (640 × 48
0), 18.4 MHz, 25.8 MHz, SVGA
(800 × 600), 28.8 MHz, 40.3 M
Hz, XGA (1024 × 768), 47.2 MH
z, 66.1 MHz, SXGA (1280 × 1024)
Then, 78.6 MHz, 110 MHz, UXGA (16
00 × 1200), 115 MHz, 161 MHz,
In HDTV (1920 × 1080), 124 MHz,
At 174 MHz, QXGA (2048 × 1536),
189 MHz and 264 MHz.

At the time of writing this specification, available source driver ICs have a specification of 2 pixels / clock (data of 2 pixels can be input per clock), a clock frequency of about 65 MHz, and data transfer. When converted to a rate, it is 130 MHz, but the data transmission path as it is cannot support a resolution of UXGA, QXGA or higher including a blank period.

[0007] In addition, in many cases, high resolution is not simply high definition but is accompanied by enlargement of the screen. This is because the added value is more easily understood by the consumer when the resolution is increased and the screen is enlarged than when the definition is increased with the same screen size. In this case, it is attached around the LCD panel,
There is a problem that the length of the printed circuit board becomes long. As an example, when the pixel pitch is 0.3 mm for each of the above-mentioned resolutions, the length of the source driver substrate and the length of the gate driver substrate can be roughly described as: Length_Of_SourcePCB = Horizontal_Pixel_Pitch × Horizontal_Pixel 4) Here, Length_Of_SourcePCB: length of source driver board, Horizontal_Pixel_Pitch: horizontal pixel pitch, Hori
zontal_Pixel: The number of horizontal pixels. Length_Of_GatePCB = Vertical_Pixel_Pitch × Vertical_Line (Equation 5) where Length_Of_GatePCB: length of gate driver substrate, Vertical_Pixel_Pitch: vertical pixel pitch, Vertical
_Line: Number of vertical lines.

From equations 4 and 5, VGA (640 × 48
0), 192 mm and 144 mm, SVGA (8
00 × 600), 240 mm and 180 mm, X
307.2 mm and 230.4 mm for GA (1024 × 768), 384 mm and 307.2 mm for SXGA (1280 × 1024), UXGA (16
00 × 1200), 480 mm and 360 mm,
For HDTV (1920 × 1080), 576 mm and 324 mm, and for QXGA (2048 × 1536),
614.4 mm and 460.8 mm. However, this is calculated using only pixels, and there is a difference in practice.

In the above example, the SXGA, UXGA, HDT,
With a resolution of V, QXGA or higher, the length of a single substrate is long, so when connecting the liquid crystal panel and the source driver IC, the printed circuit board contracts, which may cause a defect and decrease the yield. is there. For the gate driver substrate, the TCP (T
Since the output pin pitch and the pin width of the ape carrier package are several times wider than the source driver IC, this problem is less likely to occur than the source driver substrate. However, in the above example, care must be taken at a resolution exceeding UXGA.

(Definition of Terms) The definitions of some terms used in the present specification are clarified here.

"Pixels" and "pixels" represent points, areas, and the like having all color information. "Dot" is the three primary colors of light R,
A point, area, or the like having only one of the color information G and B is represented. In the liquid crystal display described in this specification, unless otherwise specified, a color display is described, and the above “pixel” and “pixel” are a set of three “dots” of R, G, and B. "Pixel", "pixel" and "dot" for monochrome displays
Is synonymous. FIG. 22 shows pixels, pixels, and dots in a color display. In FIG. 22, reference numeral 241 denotes a liquid crystal panel. FIG. 22 shows an example in which the number of horizontal pixels is four and the number of vertical lines is four. A portion surrounded by a dotted line at 242a is a pixel, which is a pixel. 242A is an enlarged view of this 242a. The part of 242A is 243,
It is composed of three dots 244 and 245, 243 is an R dot, 244 is a G dot, and 245 is a B dot. FIG. 23 shows pixels, pixels, and dots on a monochrome display. In FIG. 23, reference numeral 251 denotes a liquid crystal panel. FIG.
This is an example in which the number of horizontal pixels is four and the number of vertical lines is four. The portion of a circle surrounded by a dotted line in 252a is a pixel,
Pixel. FIG. 252a is an enlarged view of 252a.
A. 243 is a single dot.

[0012] The "dot clock" and "pixel clock" are frequency units for displaying the above "pixel" or "pixel". The term “dot clock”, which is a pixel unit, is used as a standard term for a display signal source device. In this specification, a portion that does not require special attention is described as “dot clock” or “dot clock (pixel clock)”.

[0013]

In order to solve such a problem, according to the first aspect of the present invention, after inputting an image signal, the liquid crystal display control circuit divides input image data into n (n) signals by frequency dividing means. Is a natural number), and then transmits the n-divided data to k (k is a natural number) divided signal line electrode drive circuit boards.

According to a second aspect of the present invention, after inputting an image signal, the liquid crystal display control circuit divides the input image data into n (n is a natural number) by frequency dividing means, and then divides the n-divided data into one unit. A liquid crystal display device characterized by transmitting the signal to a signal line electrode drive circuit board.

According to a third aspect of the present invention, the input image data is divided into n (n is a natural number) by the frequency dividing means by the liquid crystal display control circuit after the image signal is input, and is temporarily stored by the storage means. A liquid crystal display device characterized in that data is transmitted at a frequency h times (h is a real number) to a signal line electrode driving circuit substrate divided into k units (k is a natural number).

According to a fourth aspect of the present invention, the input image data is divided into n (n is a natural number) by a frequency dividing means by a liquid crystal display control circuit after an image signal is inputted, and is temporarily stored by a storing means. A liquid crystal display device characterized in that data is transmitted to one signal line electrode drive circuit board at a frequency h times (h is a real number). Claim 5 of the present application
According to the invention, the liquid crystal display control circuit after inputting the image signal,
A liquid crystal display device characterized in that input image data is transmitted to a signal line electrode drive circuit board divided into k units (k is a natural number).

According to a sixth aspect of the present invention, the input image data is temporarily stored by the storage means by the liquid crystal display control circuit after the input of the image signal, and the stored data is divided into k units (k is a natural number). A liquid crystal display device characterized in that the signal is transmitted to the signal line electrode drive circuit board at a frequency h times (h is a real number).

According to the invention of claim 7 of the present application, the input image data is temporarily stored by the storage means by the liquid crystal display control circuit after the image signal is input, and the stored data is stored in one signal line electrode driving circuit board. A liquid crystal display device characterized by transmitting at a frequency twice (h is a real number).

The invention according to claim 8 of the present application is a liquid crystal display device application device using the liquid crystal display device according to any one of claims 1 to 7.

[0020]

(Embodiment 1) A liquid crystal display device according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a liquid crystal display device of the present embodiment. As shown in FIG. 1, the liquid crystal display device includes a liquid crystal panel 1, a display control board 2, a source driver board 3, a gate driver board 4, a connection means 5 between the source driver IC and the liquid crystal panel, and a connection between the gate driver IC and the liquid crystal panel. It comprises a connecting means 6, a connecting means 7 between the source driver substrate and the display control board, and a connecting means 8 between the gate driver board and the display control board. For details of the display control board 2,
This will be described with reference to FIG. FIG. 2 is a diagram showing the display control board 2 of the liquid crystal display device of the present embodiment. Display control board 2
Is composed of an input terminal 11, a frequency division unit 12, a display control unit 13, a storage unit 14, and an output terminal 15. The signal of the bus width w (bit) input at the frequency f (Hz) from the input terminal 11 is divided into n frequencies by the frequency dividing means 12, and the frequency becomes f / n (Hz).
The bus width becomes n × w (bits) and is input to the display control means 13. Thereafter, through a write / read operation to the storage means 14, the signals are divided and output to k output terminals 15 in order to transmit signals to the k source driver substrates.

The k output terminals 15 are sequentially output terminal 15
-1, output terminal 15-2 (omitted in the middle), output terminal 15
Call it -k.

FIG. 3 shows a liquid crystal display device according to the present embodiment.
FIG. 6 is a diagram illustrating another example of the display control board 2. The display control board 2 includes an input terminal 21, a frequency dividing unit 22, a display control unit 23, a storage unit 24, and an output terminal 25. The signal of the bus width w (bit) input at the frequency f (Hz) from the input terminal 21 is divided into n frequencies by the frequency dividing means 22, and the frequency becomes f / n (Hz).
The bus width becomes n × w (bits) and is input to the display control means 23. Thereafter, through a write / read operation to the storage means 24, the signals are divided and output to k output terminals 25 in order to transmit the signals to the k source driver substrates. It is adjusted twice. As a result, the bus width remains unchanged, and only the frequency is (a
× f) / n (Hz).

The k output terminals 25 are sequentially output terminal 25
-1, output terminal 25-2 (omitted midway), output terminal 25
Call it -k.

For details of the source driver board 4,
This will be described with reference to FIG. FIG. 4 is a diagram showing the source driver substrate 4 of the liquid crystal display device of the present embodiment. The source driver board 4 is divided into k pieces such as a source driver board 32-1, a source driver board 32-2 (omitted in the middle), and a source driver board 32-k.

Now, as an example, two pixels / clock (two pixels (RGB × 2) are inputted in one clock cycle)
Assuming that a source driver IC with an operating frequency of 65 MHz (Max.) Is used in the specification, one pixel (RG
The transfer frequency per B) is 65 MHz × 2 = 130 MH
z.

This is shown in FIG. 5 and FIG. FIG. 5 is a diagram illustrating a driver IC used in the present embodiment. In FIG.
41 is a source driver IC, 42 is a liquid crystal panel, and 43 is data input per operation clock. The source driver IC 41 according to the present embodiment has an
Data of two pixels, that is, data of 6 dots is input. FIG.
The frequency of the portion indicated by a becomes 65 MHz (Max.). FIG. 6 is a diagram in which the operation of this driver is rewritten as the operation of one pixel. In FIG. 6, reference numeral 51 denotes a source driver IC, 52 denotes a liquid crystal panel, and 53 denotes data input per operation clock. Source driver IC of FIG.
Reference numeral 51 inputs data of one pixel, that is, data of three dots per operation clock. In FIG. 6, the frequency of the portion indicated by b is reduced to half the data amount by the conversion of the number of dots in the case of FIG. 5, so the frequency is doubled to 65 × 2 = 13.
0 MHz (Max.).

Next, assuming that the frame frequency of the high-resolution display with a blank period is 60 Hz, according to Equation 3, UXGA (1600 × 1200)
At 161 MHz and HDTV (1920 × 1080),
174 MHz, WUXGA (Wide-UXGA, 19
20 × 1200), 194 MHz, QXGA (20
In the case of (48 × 1536), since the frequency is 264 MHz, even if the source driver IC is connected as it is, the operation is inconvenient due to an excessive frequency. Therefore, when these clock frequencies are divided by 130 MHz and rounded up to the nearest whole number (using the ROUNDUP function), the UXGA
OUNDUP (161 ÷ 130) = 2, R for HDTV
OUNDUP (174 @ 130) = 2, ROUNDUP (194 @ 130) = 2 in WUXGA, ROUNDUP (264 @ 130) = 3 in QXGA, and it is good to divide into two, two, and three, respectively. I understand that. Similarly, it can be easily considered that the same calculation is performed for other resolutions, the number of divisions is obtained by Expression 6, and the source driver substrate is divided. n = roundup (dclk / pclk) (Equation 6) Here, n is the number of driver IC divisions, dclk is a dot clock (or pixel clock) for display, pclk.
Is the operating frequency of the driver IC (converted per pixel).

As an example, if the resolution is UXGA (1600
A color liquid crystal display device in the case of (pixels × 1200 scanning lines) will be described. The UXGA has a resolution as shown in FIG.

When the resolution is UXGA, the number of divisions of the source driver IC becomes two by the calculation of Expression 6. At this time, the following processing is sequentially performed on the input image data signal. First, during one frame period, the input data signal is set as R (0,0), G as a valid data signal.
(0,0), B (0,0), R (1,0), G (1,
0), B (1, 0), (omitted on the way), R (x, y), G
(X, y), B (x, y), (omitted midway), R (159
8, 1199), G (1598, 1199), B (15
98, 1199), R (1599, 1199), G (1
599, 1199), B (1599, 1199) 5,
760,000 dots (the dots described here are
(Independent dots of R, G, B, not pixels)
It is assumed that R, G, and B dots are sequentially input as a set in synchronization with the dot clock dclk. However,
x is a horizontal pixel number starting from 0 to 1599, and y is a vertical scanning line number starting from 0 to 1199. FIG.
FIG. 5 is a diagram showing a valid data signal of UXGA.

When the input data is sequentially received, the input data is stored in the storage means. Now, the output number of the driver to be used is 3
Assuming 84 outputs, UXGA uses 1600 × RGB
(= 3) ÷ 384 = 12.5, so a minimum of 13 drivers are required. D0, D1, D1
2, (omitted in the middle), D12.

The source driver board is composed of two boards. One board has six source driver ICs D0, D1, (omitted in the middle), D4, D5, and the other board has D6, D7,
(Omitted on the way), seven source driver ICs D11 and D12 are mounted. FIG. 9 is a diagram showing a form of the source driver substrate. In FIG. 9, reference numerals 81 and 82 denote source driver substrates. 81 is equipped with six source driver ICs,
Reference numeral 82 includes seven source driver ICs. 83 is a source driver IC. 84 and 85 are connectors for receiving data from the display control board.

The size of the board on which seven are mounted is about 270 mm. At the time of displaying an image, the image data is output from the storage means to the driver. At this time, R (0,0), G
(0,0), B (0,0), (omitted midway), R (12
7,0), G (127,0) and B (127,0) to D0
To R (128,0), G (128,0), B (12
8,0), (omitted on the way), R (255,0), G (25
5,0) and B (255,0) are output simultaneously to D1 with the same clock, but this clock is dclk / 2. This simultaneous output to the two drivers with the same clock is described in
Divided into individual pieces ".

Further, following the output to D0 and D1, R
(256,0), G (256,0), B (256,0)
0), (omitted on the way), R (383, 0), G (383,
0), B (383,0) to D2, R (384,0),
G (384, 0), B (384, 0), (omitted midway),
R (511, 0), G (511, 0), B (511, 0)
0) to D3 simultaneously with the same clock.

Hereinafter, similarly, D4 and D5, D6 and D7,
The image data is output from the storage means to D8 and D9 and to D10 and D11. Following output to D10 and D11, R (1536,0), G (1536,0), B (1
536, 0), (omitted on the way), R (1599, 0), G
(1599,0) and B (1599,0) are output to D12 with the same clock as described above.

FIG. 10 shows a method of outputting the above data. In FIG. 10, reference numeral 91 denotes data (part 1) output simultaneously. When the data of 91 has been output to D0 and D1, then the data of 92 (same as the second) and
The data of two driver ICs are sequentially output simultaneously with the same clock in the order of (No. 3, No. 4, 94, No. 4, No. 5, No. 5, 96, No. 6, No. 6).
Is independently output to D12.

Thus, the output for one scanning line is completed, and the process proceeds to the next scanning line. When this is repeated for 1200 scanning lines, U
This is equivalent to one frame of XGA effective image data.

The frequency and bus width at this time are considered as follows. First, the input dot clock of the image signal to the input terminal 11 is 161 MHz as described above.
The bus width at this time is 24 bits. This is divided by 2 by the frequency dividing means 12. At this point the frequency is 8
0.5 MHz. The bus width doubles to 48 bits. When the image data is temporarily stored in the storage means 14 via the display means 13 and the image data is output, the data is output to the two output terminals 15 at the same time. Therefore, the frequency can be finally reduced to 40.25 MHz. The bus width is further doubled to 96 bits. Since 40.25 MHz is lower than the clock frequency 65 MHz of the source driver IC to be used, there is no problem in operation.

The output of image data from the storage means to the source driver is not limited to simultaneous output with the same clock as in the above-described example. It can be easily understood that the same effect can be obtained if the operating frequency of the driver is reduced.

In the above example, the output order of the image data from the storage means is described as D0 and D1, D2 and D3, D4 and D5, D6 and D7, D8 and D9, D10 and D11, and D12. However, this order is not uniquely determined, and as another example, the output order of the image data from the storage unit is D0 and D6, D1 and D7, D2 and D8, D3 and D3.
9, D4 and D10, D5 and D11, D12,
Further, as another example, the output order of the image data from the storage means is D12 and D10, D8 and D6, D4 and D2, D0 and D11, D9 and D7, D5 and D3, D1, and other combinations. The same effect can be obtained.
D12 is unique with respect to the amount of data,
There is no problem if data is output simultaneously in combination with other drivers D0 to D11.

In the above example, the UXGA resolution has been described. However, by performing the same processing for other resolutions, the source driver IC can be divided and the frequency can be easily reduced. It can be understood.

In the above example, 384 outputs and an operating frequency of 6
5 MHz (2 pixels / clock) source driver I
Although this example uses C, even if the number of output terminals and the operating frequency are changed, the present example can be applied by recalculating each item.

If the configuration of the display control board 2 includes the frequency adjusting means 26 as shown in FIG. 3, the frequency of the output signal to the output terminal 25 is adjusted to be higher than 40.25 MHz, for example, the operation of the source driver. The upper limit of the clock can be raised to about 65 MHz, and as a result, the refresh rate can be improved and the display quality can be further improved.

(Embodiment 2) A liquid crystal display device according to Embodiment 2 of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing a liquid crystal display device of the present embodiment. As shown in the figure, the liquid crystal display device has a liquid crystal panel 1,
Display control board 2, source driver board 3, gate driver board 4, source driver IC-to-liquid crystal panel connection means 5, gate driver IC-to-liquid crystal panel connection means 6, source driver board-to-display control board connection means 7, gate It comprises a connecting means 8 for connecting a driver board and a display control board. Details of the display control board 2 will be described with reference to FIG.

FIG. 2 is a view showing the display control board 2 of the liquid crystal display device of the present embodiment. The display control board 2 includes an input terminal 11, a frequency division unit 12, a display control unit 13, a storage unit 14, and an output terminal 15. The signal of the bus width w (bit) input from the input terminal 11 at the frequency f (Hz) is divided into m frequencies by the frequency dividing means 12, the frequency is f / m (Hz), and the bus width is m ×
w (bit) and is input to the display control means 13.
After that, through a write / read operation to the storage means 14,
It is divided and output to k output terminals 15. The k output terminals 15 include an output terminal 15-1, an output terminal 15-2,
(Omitted in the middle), and is referred to as an output terminal 15-k.

FIG. 3 shows a liquid crystal display device according to the present embodiment.
FIG. 6 is a diagram illustrating another example of the display control board 2. The display control board 2 includes an input terminal 21, a frequency dividing unit 22, a display control unit 23, a storage unit 24, and an output terminal 25. The signal of the bus width w (bit) input at the frequency f (Hz) from the input terminal 21 is divided into m frequencies by the frequency dividing means 22, and the frequency is changed to f / m (Hz).
The bus width becomes m × w (bits) and is input to the display control unit 23. After that, through a write / read operation to the storage means 24, it is divided and output to k output terminals 25,
Here, the frequency is adjusted by a times by the frequency adjusting means. As a result, the bus width remains unchanged, and only the frequency is (a
× f) / m (Hz).

The k output terminals 25 are sequentially output terminal 25
-1, output terminal 25-2,..., Output terminal 25-k.

For details of the source driver board 4,
This will be described with reference to FIG. FIG. 4 is a diagram showing the source driver substrate 4 of the liquid crystal display device of the present embodiment. The source driver board 4 is divided into k pieces such as a source driver board 32-1, a source driver board 32-2 (omitted in the middle), and a source driver board 32-k.

Now, as an example, two pixels / clock (two pixels (RGB × 2) are input in one clock cycle)
Assuming that a source driver IC with an operating frequency of 65 MHz (Max.) Is used in the specification, one pixel (RG
The transfer frequency per B) is 65 MHz × 2 = 130 MH
The clock frequency with a blank period for high-resolution display is expressed by the following equation (3), where the frame frequency is 60 Hz.
Therefore, in UXGA (1600 × 1200), 161M
Hz, HDTV (1920 × 1080), 174M
Hz, WUXGA (Wide-UXGA, 1920 × 1
200), 194 MHz, QXGA (2048 × 1
In 536), since the frequency is 264 MHz, even if the source driver IC is connected as it is, there is a problem in operation due to excessive frequency. For this reason, these clock frequencies are each divided by 130 MHz and rounded up to the nearest whole number (ROU
NDUP function) and ROUND in UXGA
UP (161 ÷ 130) = 2, ROUND in HDTV
UP (174 ÷ 130) = 2, ROUX in WUXGA
DUP (194 ÷ 130) = 2, ROX in QXGA
DUP (264 ÷ 130) = 3 is calculated,
It can be seen that it is better to divide into two, two, and three, respectively. Similarly, it can be easily considered that the above calculation is similarly performed for other resolutions, the number of divisions is obtained by Expression 6, and the source driver substrate is divided.

As an example, if the resolution is UXGA (1600
A color liquid crystal display device in the case of (pixels × 1200 scanning lines) will be described. When the resolution is UXGA, the number of divisions of the source driver IC becomes two by the calculation of Expression 1. At this time, the following processing is sequentially performed on the input image data signal.

First, during one frame period, the input data signal is set as R (0,0), G (0,
0), B (0,0), R (1,0), G (1,0), B
(1, 0), (omitted on the way), R (x, y), G (x,
y), B (x, y), (omitted on the way), R (1598, 1)
199), G (1598, 1199), B (1598,
1199), R (1599, 1199), G (159)
9,1199) and 5,76 of B (1599,1199)
000 dots (dots described here are R,
G and B are independent dots, not pixels), and R, G, and B dots are sequentially input as a set in synchronization with the dot clock dclk. Here, x is a horizontal pixel number starting from 0 to 1599, and y is a vertical scanning line number starting from 0 to 1199.

When the input data is sequentially received, the input data is stored in the storage means. Now, the output number of the driver to be used is 3
Assuming 84 outputs, UXGA uses 1600 × RGB
(= 3) ÷ 384 = 12.5, so a minimum of 13 drivers are required. D0, D1, D1
2, (omitted in the middle), D12.

The source driver board is composed of a single board.
13 source driver ICs 0, D1, (omitted in the middle) and D12 are mounted. FIG. 11 is a diagram showing a form of the source driver substrate. In FIG. 11, reference numeral 101 denotes a source driver substrate. 102 is a source driver IC. 1
03 is a connector for receiving data from the display control board.

At the time of displaying an image, the image data is output from the storage means to the driver. At this time, R (0,
0), G (0,0), B (0,0), (sometimes omitted), R
(127,0), G (127,0), B (127,0)
To D0, R (128,0), G (128,0), B
(128,0), (omitted midway), R (255,0), G
(255,0) and B (255,0) to D1, the same clock, but this clock is dclk /
2 and output simultaneously. This simultaneous output to two drivers with the same clock is described in "Source Driver I
C is divided into two ". Following the output to D0 and D1, R (256,0), G (25
6,0), B (256,0), (omitted midway), R (38
3,0), G (383,0) and B (383,0) to D2
To R (384,0), G (384,0), B (38
4,0), (omitted on the way), R (511, 0), G (51
1, 0) and B (511, 0) are simultaneously output to D3 with the same clock.

Similarly, D4 and D5, D6 and D7,
The image data is output from the storage means to D8 and D9 and to D10 and D11. Following output to D10 and D11, R (1536,0), G (1536,0), B (1
536, 0), (omitted on the way), R (1599, 0), G
(1599,0) and B (1599,0) are output to D12 with the same clock as described above.

FIG. 12 shows a method of outputting the above data. In FIG. 12, reference numeral 111 denotes data (part 1) output simultaneously. When the data of 111 has been output to D0 and D1, then the data of 112 (the same, part 2), and
113 (same, 3), 114 (same, 4), 115
(Same, No. 5), 116 (Same, No. 6) and data for two driver ICs are sequentially output simultaneously with the same clock,
Finally, the data of 117 is independently output to D12.

Thus, the output for one scanning line is completed, and the process proceeds to the next scanning line. When this is repeated for 1200 scanning lines, U
This is equivalent to one frame of XGA effective image data.

The frequency and bus width at this time are considered as follows. First, the input dot clock of the image signal to the input terminal 11 is 161 MHz as described above.
The bus width at this time is 24 bits. This is divided by 2 by the frequency dividing means 12. At this point the frequency is 8
0.5 MHz. The bus width doubles to 48 bits. When the image data is temporarily stored in the storage means 14 via the display means 13 and the image data is output, the data is output to the two output terminals 15 at the same time. Therefore, the frequency can be finally reduced to 40.25 MHz. The bus width is further doubled to 96 bits. Since 40.25 MHz is lower than the clock frequency 65 MHz of the source driver IC to be used, there is no problem in operation.

The output of image data from the storage means to the source driver is not limited to the case of simultaneous output with the same clock as in the above-described example. It can be easily understood that the same effect can be obtained if the operating frequency of the driver is reduced.

In the above example, the output order of the image data from the storage means is described as D0 and D1, D2 and D3, D4 and D5, D6 and D7, D8 and D9, D10 and D11, and D12. However, this order is not uniquely determined, and as another example, the output order of the image data from the storage unit is D0 and D6, D1 and D7, D2 and D8, D3 and D3.
9, D4 and D10, D5 and D11, D12,
Further, as another example, the output order of the image data from the storage means is D12 and D10, D8 and D6, D4 and D2, D0 and D11, D9 and D7, D5 and D3, D1, and other combinations. The same effect can be obtained.
D12 is unique with respect to the amount of data,
There is no problem if data is output simultaneously in combination with other drivers D0 to D11.

In the above example, the UXGA resolution has been described. However, by performing the same processing for other resolutions, it is easy to divide the source driver IC and reduce the frequency. It can be understood.

In the above example, 384 outputs and an operating frequency of 6
5 MHz (2 pixels / clock) source driver I
Although this example uses C, even if the number of output terminals and the operating frequency are changed, the present example can be applied by recalculating each item.

If the configuration of the display control board 2 includes the frequency adjusting means 26 as shown in FIG. 3, the frequency of the output signal to the output terminal 25 is adjusted to be higher than 40.25 MHz, for example, the operation of the source driver. The upper limit of the clock can be raised to about 65 MHz, and as a result, the refresh rate can be improved and the display quality can be further improved.

(Embodiment 3) A liquid crystal display device according to Embodiment 3 of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing a liquid crystal display device of the present embodiment. As shown in the figure, the liquid crystal display device has a liquid crystal panel 1,
Display control board 2, source driver board 3, gate driver board 4, source driver IC-to-liquid crystal panel connection means 5, gate driver IC-to-liquid crystal panel connection means 6, source driver board-to-display control board connection means 7, gate It comprises a connecting means 8 for connecting a driver board and a display control board.

Now, as an example, 2 pixels / clock (2 pixels (RGB × 2) are input in one clock cycle)
Assuming that a source driver IC with an operating frequency of 65 MHz (Max.) Is used in the specification, one pixel (RG
The transfer frequency per B) is 65 MHz × 2 = 130 MH
z, and the clock frequency with a blank period for high-resolution display is UXG when the frame frequency is 60 Hz.
A (1600 × 1200), 161 MHz, HDT
V (1920 × 1080), 174 MHz, WUX
In the case of GA (Wide-UXGA, 1920 × 1200), the frequency is 194 MHz, and in the case of QXGA (2048 × 1536), it is 264 MHz.
MHz and round up to the nearest whole number (ROUNDUP
UXGA) and ROUNDUP (1
61 ÷ 130) = 2, ROUNDUP (1
74 ÷ 130) = 2, ROUNDUP in WUXGA
(194 ÷ 130) = 2, ROUNDUP for QXGA
(264 ÷ 130) = 3, 2
It is necessary to divide into two, three and two.

Similarly, for the other resolutions, the above-described calculation is similarly performed, the number of divisions is obtained by Expression 6, and a configuration in which the source driver substrate is divided can be easily considered.

As an example, if the resolution is HDTV (1920
A case of a color liquid crystal display device having (pixels × 1080 scanning lines) will be described. HDTV is a resolution as shown in FIG. When the resolution is HDTV, the number of divisions of the source driver IC is two by the calculation of Expression 1.

However, in the case of HDTV, since the horizontal resolution is 1920 pixels, the total number of source driver ICs is 1920 × RGB (= 3) ÷ 384 = 15.
A scheme of three divisions can also be considered. In the case of two divisions, the same processing as in the first embodiment may be performed, and therefore, description of this example will be omitted.

At this time, for the input image data signal,
The following processing is sequentially performed. First, the input data signal is used as a valid data signal during one frame period.
(0,0), G (0,0), B (0,0), R (1,
0), G (1,0), B (1,0), (omitted midway), R
(X, y), G (x, y), B (x, y), (omitted midway), R (1918, 1079), G (1918, 10)
79), B (1918, 1079), R (1919, 1)
079), G (1919, 1079), B (1919,
1079) (dots described here are independent dots of R, G, and B, not pixels) in synchronization with the dot clock dclk,
It is assumed that R, G, and B dots are sequentially input as a set. Here, x is a horizontal pixel number starting from 0 and 1920.
And y is the vertical scanning line number, starting from 0 and up to 1080. FIG. 14 is a diagram showing a valid data signal of HDTV.

The input data is sequentially stored in the storage means at the time of reception. Now, the number of source drivers to be used is fifteen, and the fifteen drivers are arranged in the order of D0, D1, D2,.
(Sometimes omitted), referred to as D14.

The source driver board is composed of three boards. One board has five source driver ICs D0, D1, (not shown in the middle) and D4, and the other board has D5, D6, (not shown in the middle), D9. 5 source driver ICs, and D10, D11 (omitted in the middle), D14
The source driver ICs are mounted. FIG. 15 is a diagram showing a form of the source driver substrate. In FIG.
1 is a source driver board. Each of the three 141s has five source driver ICs mounted thereon. 142 is a source driver IC. 143 is a connector for receiving data from the display control board.

At the time of displaying an image, the image data is output from the storage means to the driver. At this time, R (0,
0), G (0,0), B (0,0), (sometimes omitted), R
(127,0), G (127,0), B (127,0)
To D0, R (128,0), G (128,0), B
(128,0), (omitted midway), R (255,0), G
(255,0), B (255,0) to D1, R (25
6,0), G (256,0), B (256,0), (omitted midway), R (383,0), G (383,0), B
(383, 0) to D2 and the same clock, but this clock is output simultaneously at dclk / 3. This simultaneous output to the three drivers with the same clock means "split the source driver IC into three". Also, following output to D0, D1, and D2, R (384,0), G (384,0),
B (384, 0), (omitted on the way), R (511, 0),
G (511,0), B (511,0) to D3, R (5
12,0), G (512,0), B (512,0),
(Omitted on the way), R (639,0), G (639,0),
B (639,0) to D4, R (640,0), G (6
40,0), B (640,0), (omitted midway), R (7
67,0), G (767,0) and B (767,0) to D
5 and are output simultaneously with the same clock.
Hereinafter, similarly, D6, D7, and D8, D9, D10, and D1
1. Image data is output from the storage means to D12, D13 and D14.

FIG. 16 shows a method of outputting the above data. In FIG. 16, reference numeral 151 denotes data (part 1) output simultaneously. When the output of the data 151 is completed to D0, D1, and D2, the data 152 (the same, No. 2) is then output to the data 153 (the third), 154 (the fourth), and 155.
(Same as No. 5) and data for three driver ICs are sequentially output at the same clock. FIG. 17 shows an example in which the data output order is changed. Data having the same reference numerals 161 to 165 are data output to the driver IC at the same time.

Thus, the output for one scanning line is completed, and the process proceeds to the next scanning line. When this is repeated for 1080 scanning lines, H
One frame of DTV effective image data.

The output of image data from the storage means to the source driver is not limited to the case of simultaneous output with the same clock as in the above example. It can be easily understood that the same effect can be obtained if the operating frequency of the driver is reduced.

In the above example, the resolution of the HDTV has been described. However, it is easily understood that the source driver IC can be divided and the frequency can be reduced by performing the same processing for the other resolutions. it can.

In this embodiment, the HDTV (1920 × 108)
0), W-UXGA (1920 × 1
200), the number of scanning lines is from 1080 to 1200
It can be considered in the same way, considering that it has increased.

[0077]

The signal data bus is divided into n parts (n parts) after the input.
Is a natural number), the frequency f becomes f / n, and the processing clock frequency can be reduced.

Further, since the data is transmitted to the source driver divided into k (k is a natural number), it is possible to design the liquid crystal module to easily absorb the deformation due to the heat of the substrate during the production of the liquid crystal module.

Further, the frequency can be changed by a factor h (h is a real number) by temporarily holding the signal data in the storage means and reading it out with a clock different from that used for writing.
It is possible to adjust the design so as to output in accordance with the drive frequency of the source driver IC.

By combining the above effects, in designing and developing a high-resolution liquid crystal display device, a source driver IC having insufficient frequency performance for a target resolution.
Can be used, and the capability of the source driver IC can be maximized. Further, it is possible to cope with the deformation of the circuit board accompanying the enlargement of the screen in conjunction with the higher resolution.

By using the liquid crystal display device of the present invention as an application device of the liquid crystal display device, it is possible to obtain a higher resolution and a larger screen, which is of great industrial value.

[Brief description of the drawings]

FIG. 1 illustrates a liquid crystal display device according to an embodiment.

FIG. 2 is a diagram showing a display control substrate of the liquid crystal display device of the embodiment.

FIG. 3 is a diagram illustrating another example of the display control substrate of the liquid crystal display device according to the embodiment.

FIG. 4 is a diagram showing a source driver substrate of the liquid crystal display device according to the embodiment;

FIG. 5 is a diagram showing a driver IC used in the embodiment;

FIG. 6 is a diagram in which the driver IC used in the embodiment is rewritten to operate per pixel.

FIG. 7 is a diagram showing a resolution UXGA;

FIG. 8 is a diagram showing a valid data signal of UXGA;

FIG. 9 illustrates an example of a mode of a source driver substrate in Embodiment 1.

FIG. 10 illustrates a method for outputting data to a source driver in Embodiment 1.

FIG. 11 illustrates an example of a mode of a source driver substrate in Embodiment 2.

FIG. 12 is a diagram illustrating a method for outputting data to a source driver according to the second embodiment.

FIG. 13 is a diagram showing a resolution HDTV.

FIG. 14 is a diagram showing an effective data signal of HDTV.

FIG. 15 illustrates an example of a mode of a source driver substrate in Embodiment 3.

FIG. 16 illustrates a method for outputting data to a source driver in Embodiment 2.

FIG. 17 is a diagram showing another example of a method for outputting data to a source driver in the second embodiment.

FIG. 18 illustrates a conventional liquid crystal display device.

FIG. 19 is a diagram showing a main configuration of a display control board portion of a conventional liquid crystal display device.

FIG. 20 is a diagram showing a panel and a source driver substrate of a conventional liquid crystal display device.

FIG. 21 is a diagram illustrating an example of resolution.

FIG. 22 is a diagram showing pixels, pixels, and dots of a color display;

FIG. 23 is a diagram showing pixels, pixels, and dots of a monochrome display.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Liquid crystal panel 2 Display control board 3 Source driver board 4 Gate driver board 5 Connection means of a source driver IC and a liquid crystal panel 6 Connection means of a gate driver IC and a liquid crystal panel 7 Connection means of a source driver board and a display control board 8 Gate driver board And display control board connection means 11 input terminal 12 frequency division means 13 display control means 14 storage means 15 output terminal 21 input terminal 22 frequency division means 23 source driver board 24 storage means 25 output means 26 frequency adjustment means 31 liquid crystal panel 32 source Driver board 41 Source driver IC 42 Liquid crystal panel 43 Data input per operation clock 51 Source driver IC 52 Liquid crystal panel 53 Data input per operation clock 81 Source driver board 82 Source driver Substrate 83 Source driver IC 84 Connector for receiving data from display control board 85 Connector for receiving data from display control board 91 Data output simultaneously (No. 1) 92 Data output simultaneously (No. 2) 93 Output simultaneously Data to be output (No. 3) 94 Data to be output simultaneously (No. 4) 95 Data to be output simultaneously (No. 5) 96 Data to be output simultaneously (No. 6) 97 Data to be output alone 101 Source driver IC 103 Display Connector for receiving data from control board 111 Simultaneously output data (No. 1) 112 Simultaneously output data (No. 2) 113 Simultaneously output data (No. 3) 114 Simultaneously output data (No. 4) 115 Data Output Simultaneously (Part 5) 116 Data output at the time (No. 6) 117 Data output alone 141 Source driver board 142 Source driver IC 143 Connector for receiving data from display control board 151 Data output at the same time (No. 1) 152 Output simultaneously Data (No. 2) 153 Simultaneously output data (No. 3) 154 Simultaneously output data (No. 4) 155 Simultaneously output data (No. 5) 161 Simultaneously output data (No. 1) 162 Simultaneously output Data (No. 2) 163 Simultaneously output data (No. 3) 164 Simultaneously output data (No. 4) 165 Simultaneously output data (No. 5) 201 Liquid crystal panel 202 Display control board 203 Source driver board 204 Gate driver board 205 Source Driver Connection means between C and liquid crystal panel 206 Connection means between gate driver IC and liquid crystal panel 207 Connection means between source driver board and display control board 208 Connection means between gate driver board and display control board 211 Input terminal 212 Display control means 213 Output terminal 221 Liquid crystal panel 222 Source driver board 231 VGA resolution 232 SVGA resolution 233 XGA resolution 234 R dots 244 G dots 245 B dots 251 Liquid crystal panel 252 pixels, pixels 253 dots

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] March 16, 2000 (200.3.1.1)
6)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0015

[Correction method] Change

[Correction contents]

According to a third aspect of the present invention, the input image data is divided into n (n is a natural number) by the frequency dividing means by the liquid crystal display control circuit after the image signal is input, and is temporarily stored by the storage means. when transmitting data k stand (k is a natural number) in the divided signal line electrode driving circuit board
The frequency of the input image data is frequency-divided.
To a frequency (a is a real number)
A liquid crystal display device characterized by transmitting at a frequency of ( number) .

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0017

[Correction method] Change

[Correction contents]

According to a sixth aspect of the present invention, the input image data is temporarily stored by the storage means by the liquid crystal display control circuit after the input of the image signal, and the stored data is divided into k units (k is a natural number). Send to signal line electrode drive circuit board
The input image data to a frequency obtained by frequency division.
The frequency is adjusted to a times (a is a real number) and a times (a is
(Real number) frequency.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0022

[Correction method] Change

[Correction contents]

FIG. 3 shows a liquid crystal display device according to the present embodiment.
FIG. 6 is a diagram illustrating another example of the display control board 2. The display control board 2 includes an input terminal 21, a frequency dividing unit 22, a display control unit 23, a storage unit 24, and an output terminal 25. The signal of the bus width w (bit) input at the frequency f (Hz) from the input terminal 21 is divided into n frequencies by the frequency dividing means 22, and the frequency becomes f / n (Hz).
The bus width becomes n × w (bits) and is input to the display control means 23. Here, from the display control means 23 to the storage means 2
The output frequency to 4 is f / n (Hz). Thereafter, through a write / read operation to the storage means 24, the signals are divided and output to k output terminals 25 in order to transmit signals to the k source driver substrates.
By this, the frequency is adjusted to a times. First, the display control hand
The output frequency from the stage 23 to the frequency adjusting means 26 is f / n
It is. Then, from the frequency adjusting means 26 to the storage means 24
Output frequency is a times (a ×
f) / n (Hz), and receives a clock of this frequency.
The image data from the storage means 24 is output frequency (a ×
f) / n (Hz) is read out to the display control means 23.
As a result, the output from the display control means 23 to the output terminal 25
For, the bus width is unchanged and only the frequency is (a ×
f) / n (Hz).

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0079

[Correction method] Change

[Correction contents]

Further, the frequency can be changed by a times ( a is a real number) by temporarily storing the signal data in the storage means and reading it out with a clock different from that at the time of writing.
Rukoto tone pollock designed to output in harmony with the driving frequency of the source driver IC becomes possible.

Continued on the front page F-term (reference) 2H093 NC13 NC16 NC21 NC29 NC49 ND37 ND60 5C006 AA01 AA02 AA16 AA22 AC21 AF04 AF42 BB11 BC12 BC23 BF02 FA12 FA15 5C080 AA10 BB06 CC03 DD07 DD08 EE29 EE30 FF12 GG02 GG01 GG12 GG12 GG12 GG08

Claims (8)

[Claims] 1. A semiconductor device comprising: two opposing substrates in each of which a liquid crystal material is sealed; and a plurality of pixel electrodes arranged in a matrix on one of the substrates. A liquid crystal display device having a plurality of drive electrodes orthogonal to each other for driving, having a drive integrated circuit for supplying a signal to the drive electrodes, and having a liquid crystal display control circuit for controlling the drive integrated circuit, After inputting the image signal, the liquid crystal display control circuit divides the input image data into n (n is a natural number) by a frequency dividing unit, and then divides the n-divided data into k (k is a natural number) signal line electrode drive. A liquid crystal display device, which transmits the liquid crystal display to a circuit board. 2. The liquid crystal display device according to claim 1, wherein the signal line electrode drive circuit board is not divided (k = 1). 3. A semiconductor device comprising: two substrates facing each other in which a liquid crystal substance is sealed; and a plurality of pixel electrodes arranged in a matrix on one of the substrates. A liquid crystal display device having a plurality of drive electrodes orthogonal to each other for driving, having a drive integrated circuit for supplying a signal to the drive electrodes, and having a liquid crystal display control circuit for controlling the drive integrated circuit, After the image signal is input, the input image data is divided into n (n is a natural number) by the frequency dividing means by the liquid crystal display control circuit and temporarily stored by the storage means, and the stored data is divided into k units (k is a natural number). A liquid crystal display device, wherein the signal is transmitted to the signal line electrode drive circuit board at a frequency h times (h is a real number). 4. The liquid crystal display device according to claim 3, wherein the signal line electrode drive circuit board is not divided (k = 1). 5. A semiconductor device comprising: two substrates facing each other in which a liquid crystal substance is sealed; and a plurality of pixel electrodes arranged in a matrix on one of the substrates. A liquid crystal display device having a plurality of drive electrodes orthogonal to each other for driving, having a drive integrated circuit for supplying a signal to the drive electrodes, and having a liquid crystal display control circuit for controlling the drive integrated circuit, A liquid crystal display device, comprising: after inputting an image signal, transmitting, by a liquid crystal display control circuit, input signal data to k (where k is a natural number) divided signal line electrode drive circuit boards. 6. A semiconductor device comprising: two opposing substrates in each of which a liquid crystal material is sealed; and a plurality of pixel electrodes arranged in a matrix on one of the substrates. A liquid crystal display device having a plurality of drive electrodes orthogonal to each other for driving, having a drive integrated circuit for supplying a signal to the drive electrodes, and having a liquid crystal display control circuit for controlling the drive integrated circuit, After the image signal is input, the liquid crystal display control circuit temporarily stores the input image data by the storage means, and stores the stored data in k units (k is a natural number)
A liquid crystal display device, wherein the signal is transmitted at a frequency h times (h is a real number) to the signal line electrode driving circuit substrate divided into two. 7. The liquid crystal display device according to claim 6, wherein the signal line electrode drive circuit board is not divided (k = 1). 8. A liquid crystal display device-applied device using the liquid crystal display device according to claim 1.