JP2000299447A - Semiconductor integrated circuit device and method of manufacturing the same - Google Patents

Abstract

[PROBLEMS] To provide a technique capable of realizing a semiconductor integrated circuit device having a highly reliable MISFET. SOLUTION: The boron concentration of the threshold voltage control layers 33, 34 at the center of the channel of the MISFET is set higher than the boron concentration of the threshold voltage control layers 33, 34 at the end of the channel.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and its manufacturing technique, and more particularly to a DRAM (Dynami
The present invention relates to a semiconductor integrated circuit device having a memory in which a memory circuit and a logic circuit are provided on the same semiconductor substrate, and a technology effective when applied to a manufacturing method thereof. is there.

[0002]

2. Description of the Related Art MISFE for selecting a memory cell of a DRAM
T (Metal Insulator Semiconductor Field Effect Tran
Several methods have been proposed for controlling the threshold voltage of the sistor.
No. 976 discloses a method of introducing a p-type impurity, for example, boron (B) into the entire surface of a semiconductor substrate before forming a gate insulating film.

Japanese Patent Laid-Open Publication No. Hei 10-56147 discloses that a p-type impurity, for example, boron is introduced only into a semiconductor substrate on the side to which a bit line is connected (bit line side) to reduce the impurity concentration of the semiconductor substrate. An asymmetrical method has been proposed in which the impurity concentration is set higher than the impurity concentration of the semiconductor substrate on the side to which the information storage capacitor is connected (capacitor side). A method is described in which the increase in the junction electric field strength is suppressed to reduce the rate of occurrence of refresh failure.

[0004]

However, according to the study by the present inventors, it has been found that when a semiconductor substrate is subjected to a thermal oxidation treatment to form a gate insulating film on the surface of the semiconductor substrate into which boron has been introduced, boron diffusion is difficult. Alternatively, it has been clarified that boron segregation in the gate insulating film causes a problem that the concentration of boron introduced into the semiconductor substrate decreases. In particular, buried shallow trench isolation (Shallow Groo
In the case where ve Isolation (SGI) is used, it is considered that boron segregation into the buried insulating film on the side wall of the SGI causes a significant decrease in boron concentration, and the drain current flowing in this portion lowers the threshold voltage. .

When the boron concentration on the bit line side is increased, the junction electric field strength on the bit line side is increased, and electrons accelerated by the electric field form fixed charges at the interface between the gate insulating film and the semiconductor substrate. It has been considered that a problem that characteristics are deteriorated occurs. When the interface characteristic deteriorates, the sub-threshold characteristic of the memory cell selecting MISFET deteriorates, so that the pause refresh characteristic deteriorates, and the operation gradually progresses as the operation time becomes longer.
It degrades the reliability of AM.

An object of the present invention is to provide a highly reliable MISFET.
It is an object of the present invention to provide a technique capable of realizing a semiconductor integrated circuit device having the following.

[0007] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. That is, (1) In the semiconductor integrated circuit device of the present invention, the impurity concentration of the threshold voltage control layer at the center of the channel is relatively smaller than the impurity concentration of the threshold voltage control layer at the end of the channel. The MISFET has a high MISFET.

(2) A semiconductor integrated circuit device according to the present invention comprises a plurality of MISFs having relatively different gate lengths on a semiconductor substrate.
ET and a first MI having a first gate length.
The impurity concentration of the first threshold voltage control layer at the center of the channel of the SFET is the center of the channel of the second MISFET having a second gate length relatively longer than the first gate length. Is relatively higher than the impurity concentration of the second threshold voltage control layer.

(3) The semiconductor integrated circuit device according to the present invention is the semiconductor integrated circuit device according to (2), wherein the first MIS
The impurity concentration of the first threshold voltage control layer at the center of the channel of the FET is relatively lower than the impurity concentration of the first threshold voltage control layer at the end of the channel of the first MISFET. The impurity concentration of the second threshold voltage control layer at the center of the channel of the second MISFET is higher than that at the end of the channel of the second MISFET.
Is relatively higher than the impurity concentration of the threshold voltage control layer.

(4) In the semiconductor integrated circuit device according to the present invention, in the semiconductor integrated circuit device according to (1), the impurity concentration of the threshold voltage control layer at one end of the channel is:
This is relatively higher than the impurity concentration of the threshold voltage control layer at the other end of the channel.

(5) The semiconductor integrated circuit device according to the present invention is the semiconductor integrated circuit device according to the above (2) or (3).
The impurity concentration of the first threshold voltage control layer at the end of the channel of the first MISFET and the second MISFET
Are almost equal to the impurity concentration of the second threshold voltage control layer at the end of the channel.

(6) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, when forming a MISFET on a semiconductor substrate, a step of sequentially forming a gate insulating film and a gate electrode on the semiconductor substrate; Direction, and at an angle to the direction in which the gate electrode extends.
The method includes a step of obliquely implanting impurity ions into a channel from a direction, and a step of forming a semiconductor region forming a source and a drain.

(7) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, in the method of manufacturing a semiconductor integrated circuit device of (6), the angle with respect to the direction in which the gate electrode extends is 45 degrees.

(8) The method for manufacturing a semiconductor integrated circuit device according to the present invention is the method for manufacturing a semiconductor integrated circuit device according to (6), wherein the ion species, dose amount, and implantation energy of impurity ions implanted into the channel from four directions are provided. Are the same.

According to the above-described means, by implanting impurity ions into the channel of the MISFET in an oblique direction, the threshold voltage having an impurity concentration distribution that is highest at the center of the channel and decreases as approaching the edge of the channel. A control layer is obtained. Accordingly, since the threshold voltage is equal to the space charge amount of the depletion layer of the channel, the desired threshold voltage of the MISFET is substantially increased by the high concentration region of the threshold voltage control layer provided at the center of the channel. In addition, the junction field can be reduced by the low-concentration region of the threshold voltage control layer provided at the end of the channel, and good refresh characteristics can be obtained. further,
When the gate length of the gate electrode is shortened, the impurity concentration of the threshold voltage control layer at the center of the channel increases and the threshold voltage increases, so that the variation in the threshold voltage due to the variation in the gate length is reduced. As a result, a MISFET with small characteristic fluctuation can be obtained.

Further, according to the above-mentioned means, since the impurity concentration of the threshold voltage control layer at the end of the channel is low, the resistance of the semiconductor region forming the source and drain can be reduced, and the drain current can be increased. can do.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

Embodiment 1 FIG. 1 shows a MISFET for selecting a memory cell of a DRAM according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view of a main part of the semiconductor substrate, showing a calculation result of a concentration distribution of boron introduced into the semiconductor substrate to control a threshold voltage.

As shown in FIG. 1, a memory cell selecting MI
The boron concentration at the center of the channel of the SFET is set higher than the boron concentration at the end of the channel.

That is, while a desired threshold voltage is obtained by increasing the boron concentration at the center of the channel, the boron concentration at the end of the channel in contact with the source and drain on the bit line side and the capacitor side is obtained. , The junction electric field strength is kept low, and the formation of fixed charges or the deterioration of refresh characteristics due to electrons accelerated by the electric field is suppressed.

Next, the DRA according to an embodiment of the present invention will be described.
The method of manufacturing M will be described in the order of steps with reference to FIGS. Qs is a memory cell selecting MISFET formed in the memory array, and Qn and Qp are an n-channel MISFET and a p-channel MISFET formed in peripheral circuits, respectively.

First, as shown in FIG. 2, a trench type element isolation insulating film 2 made of a silicon oxide film is formed on a p-type semiconductor substrate 1 having a specific resistance of about 10 Ωcm. Next, an n-type impurity, for example, phosphorus (P) is ion-implanted into the semiconductor substrate 1 of the memory array to form an n-type buried well 3.
To form an n-channel MI of the memory array and peripheral circuits.
A p-type impurity, for example, boron is ion-implanted in a region where the SFET Qn is formed to form a p-type well 4, and an n-type well is formed in a region where a p-channel MISFET Qp of a peripheral circuit is formed.
An n-type well 5 is formed by ion implantation of a type impurity, for example, phosphorus.

After the impurity ions are implanted into the semiconductor substrate 1, the semiconductor substrate 1 is subjected to 1000 ° C. in order to activate the impurity ions, recover crystal defects generated in the semiconductor substrate 1 or obtain an optimum impurity concentration distribution. For about 30 minutes.

Next, although not shown, the n-channel MISFET Qn and the p-channel MISF
A p-type impurity for adjusting the threshold voltage of ETQp,
For example, boron ions are added to p-type well 4 and n-type well 5
Inject into

Next, as shown in FIG. 3, a clean gate insulating film 6 having a thickness of about 7 nm is formed on each surface of the p-type well 4 and the n-type well 5 by using a hydrogen combustion method. An n-type impurity, for example, about 5
A polycrystalline silicon film having a thickness of 0 nm, a tungsten silicide film having a thickness of about 120 nm, and a silicon nitride film 7 having a thickness of about 200 nm are sequentially deposited, and then these films are processed using a photoresist pattern as a mask. Thereby, a gate electrode 8 composed of a tungsten silicide film and a polycrystalline silicon film is formed. The gate length of the gate electrode 8 of the memory cell selection MISFET Qs is 0.2 μm.
m, and a MISFET for selecting an adjacent memory cell
The interval between the gate electrodes 8 of Qs is about 0.2 μm.

Next, a peripheral circuit is covered with a photoresist pattern 9 and a p-type impurity, for example, boron ions is implanted into the p-type well 4 of the memory array using the mask as a mask to form a threshold voltage control layer 10. .

At this time, as shown in FIG. 4, boron ions are implanted obliquely at an angle of, for example, 60 degrees with respect to the normal direction of the semiconductor substrate 1. However, a desired density distribution cannot be obtained by oblique driving from one direction. Thus, as shown in FIG. 5, boron ions are p The mold well 4 is injected obliquely from four directions. That is, boron ions are implanted into the p-type well 4 at the center of the channel from four directions. However, the p-type well 4 at the end of the channel is implanted from two directions by the shadowing of the silicon nitride film 7 and the gate electrode 8. Is implanted.

As a result, as shown in FIG.
The concentration of boron introduced into the p-type well 4 at the center of the channel is higher than the concentration of boron introduced into the p-type well 4 at the end of the channel. By the heat treatment performed on the semiconductor substrate 1 until the DRAM is completed, the implanted boron diffuses into the semiconductor substrate 1, but is introduced into the p-type well 4 at the center of the channel as shown in FIG. The boron concentration maintained is higher than the boron concentration introduced into the p-type well 4 at the end of the channel.

FIG. 7 shows the threshold voltage, the junction electric field, and the ion implantation of boron ions of the memory cell selecting MISFET having the threshold voltage control layer 10 having the boron concentration distribution shown in FIG. This shows the relationship with the dose. The implantation energy is about 60 keV. According to the study by the present inventors, in the conventional method in which boron ions are uniformly implanted into the channel, when a threshold voltage of 1.0 V is obtained, the junction electric field becomes about 0.5 MV / cm. However, as shown in FIG. 7, in the first embodiment,
At a dose where the threshold voltage becomes 1.0 V, the junction electric field is about 0.5.
4 MV / cm, about 0.1 MV / c compared to the conventional method
m can be reduced. As a result, the refresh time, which is about 100 ms in the conventional method, is reduced to 20 times.
It can be as long as about 0 ms.

Next, as shown in FIG. 8, after removing the photoresist pattern 9, the memory cell selecting MIS is removed.
A p-type well 4 on both sides of the gate electrode 8 of the FET Qs;
P on both sides of the gate electrode 8 of the channel type MISFET Qn
An n-type impurity, for example, phosphorus ions,
About 2 × 10 ¹³ cm ^{−2 is} implanted at an acceleration energy of V to form an n ⁻ -type semiconductor region 11a. Further, a p-type impurity, for example, is added to the n-type well 5 on both sides of the gate electrode 8 of the p-channel MISFET Qp. Boron ions are implanted to form the p ^- type semiconductor region 12a. After that, the semiconductor substrate 1 is subjected to a heat treatment at 950 ° C. for about 20 seconds.

Next, a CVD (Chemic) is formed on the semiconductor substrate 1.
After a silicon nitride film having a thickness of about 40 nm is deposited by an Al Vapor Deposition method, the silicon nitride film is anisotropically etched to form sidewall spacers 13 on the side walls of the silicon nitride film 7 and the gate electrode 8.
To form

Next, as shown in FIG. 9, an n-type impurity, for example, arsenic (As) ion is implanted into the p-type well 4 of the peripheral circuit, thereby forming n-type MISFET Qn.
⁺ -Type semiconductor region 11b is formed, to form a p-channel type MISFETQp the p ⁺ -type semiconductor region 12b by implanting p-type impurities into the n-type well 5 of the peripheral circuit, for example, boron ions. After that, the semiconductor substrate 1 is
For about 60 seconds.

Thus, the n-channel type MI is provided in the peripheral circuit.
An SFET Qn and a p-channel MISFET Qp are formed.

Next, after depositing a silicon oxide film on the semiconductor substrate 1, the surface of the silicon oxide film is polished by chemical mechanical polishing (CMP) to flatten the surface. Then, an interlayer insulating film 14 composed of a silicon oxide film is formed. The silicon oxide film is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

Next, the insulating film of the same layer as the interlayer insulating film 14 and the gate insulating film 6 is sequentially removed by dry etching using a photoresist pattern as a mask, so that one n ^{− of the} MISFET Qs for memory cell selection is removed.
A contact hole 15a reaching the n ^- type semiconductor region 11a is formed, and a contact hole 15b reaching the other n ⁻ -type semiconductor region 11a is formed.

This etching is performed under the condition that the silicon nitride film forming the side wall spacer 13 is anisotropically etched, and the memory cell selecting MISFET Qs
The silicon nitride film is left on the side wall of the gate electrode 8. Thereby, contact holes 15a and 15b having a fine diameter equal to or smaller than the resolution limit of photolithography are obtained.
Are formed in self-alignment with the gate electrode 8 of the memory cell selecting MISFET Qs.

Next, contact holes 15a, 15b
The plugs 16a and 16b are respectively formed inside. The plugs 16a and 16b are formed by depositing a polycrystalline silicon film to which an n-type impurity, for example, phosphorus at about 1 × 10 ²⁰ cm ^{−3 is} added by an CVD method on the upper layer of the interlayer insulating film 14, and then removing the surface of the polycrystalline silicon film Polished by CMP method, contact hole 1
It is formed by leaving a polycrystalline silicon film inside 5a, 15b.

Thereafter, the semiconductor substrate 1 is heated at 800.degree.
Heat treatment. By this heat treatment, the plug 16
a, n-type impurities are contact holes 15a of the polycrystalline silicon film constituting the 16b, from the bottom of 15b of the memory cell selecting MISFET Qs n ^- diffused into the semiconductor region 11a, high concentration n ⁺ -type semiconductor region 11c It is formed. Next, as shown in FIG. 10, a silicon oxide film 17 is deposited on the interlayer insulating film. Silicon oxide film 1
7 is deposited by, for example, a plasma CVD method using O ₃ and TEOS as a source gas.

Next, the silicon oxide film 17 on the contact hole 15a is removed by dry etching using a photoresist pattern as a mask to remove the contact hole 18a.
is formed to expose the surface of the plug 16a. At the same time, a contact hole 18b reaching the n ⁺ -type semiconductor region 11b of the n-channel MISFET Qn is formed by sequentially removing the insulating film of the same layer as the silicon oxide film 17, the interlayer insulating film 14, and the gate insulating film 6 of the peripheral circuit. Then, a contact hole 18c reaching the p ⁺ type semiconductor region 12b of the p-channel type MISFET Qp is formed.

Next, the bit line BL of the memory array in contact with the plug 16a through the contact hole 18a and the n-channel MISFE through the contact hole 18b.
First layer wiring 1 in contact with n ⁺ type semiconductor region 11b of TQn
9 and a p-channel type M through a contact hole 18c.
The first contacting the p ⁺ type semiconductor region 12b of the ISFET Qp
The layer wiring 19 is formed. The bit line BL and the first layer wiring 19 are formed by depositing a conductive film on the silicon oxide film 17 and then processing the conductive film using a photoresist pattern as a mask.

Next, as shown in FIG. 11, after a silicon oxide film is deposited on the bit line BL and the first layer wiring 19, the surface of the silicon oxide film is polished by a CMP method and the surface is polished. After planarization, an interlayer insulating film 20 is formed.
Next, the interlayer insulating film 20 and the silicon oxide film 17 on the plug 16b are sequentially removed by dry etching using a photoresist pattern as a mask, and a through hole 21 reaching the plug 16b is formed.

Thereafter, as shown in FIG. 12, an n-type impurity, for example, phosphorus is added to the upper layer of the interlayer insulating film 20 at 1 × 10 ²⁰ cm.
After depositing a polycrystalline silicon film to which about ^{-3 is} added, the polycrystalline silicon film is processed by dry etching using a photoresist pattern as a mask to form the storage electrode 22 of the information storage capacitor C. Next, after the surface of the storage electrode 22 is nitrided or oxynitrided, a tantalum oxide film is deposited, and then this heat-treated tantalum oxide film is crystallized to crystallize the tantalum oxide film to form the capacitor insulating film 23. Thereafter, after depositing a titanium nitride film, the titanium nitride film is patterned and a plate electrode 24 is formed to form a DRAM.

In the conventional method in which boron ions are uniformly implanted into the channel, the memory cell selecting MISFE
The gate length of the gate electrode 8 of TQs may be shortened due to processing fluctuation, and the threshold voltage may fluctuate. Unnecessary boron ions are implanted into the channel to prevent this, but the refresh time may be shortened by the excess boron concentration.

However, in the first embodiment, since boron ions are implanted into the p-type well 4 by oblique implantation, the boron concentration in the central portion of the channel increases as the gate length of the gate electrode 8 becomes shorter, and the threshold is increased. The value voltage can be prevented from lowering.

For example, FIG. 13A shows a semiconductor substrate of a memory cell selecting MISFET having a gate electrode whose gate length is relatively short as compared with the gate electrode of the memory cell selecting MISFET shown in FIG. FIG. 13 (b) shows a calculation result of the concentration distribution of boron introduced into the MISFET for memory cell selection shown in FIG. 4 shows calculation results of a concentration distribution of boron introduced into a semiconductor substrate of a memory cell selecting MISFET having the same. When the gate length is short, the region where boron ions implanted from four directions overlap increases, and the boron concentration at the center of the channel increases. On the other hand, when the gate length is long, the region where boron ions implanted from four directions overlap decreases, and the boron concentration at the center of the channel decreases.

Therefore, even if the gate length of the gate electrode varies in the manufacturing process, the dependence of the threshold voltage on the gate length can be almost eliminated by optimizing the implantation conditions, for example, the implantation angle or the implantation energy. it can. For example, as shown in FIG. 14, when the gate length is 0.2 μm and the variation is ± 0.03 μm, in the conventional method in which boron ions are uniformly implanted into the channel, the threshold voltage is reduced by about 0.20 V. In the first embodiment, the decrease in threshold voltage can be reduced to about 0.08 V.

Thus, the memory cell selecting MISF can be performed without implanting excessive boron ions into the channel.
Variations in the threshold voltage due to variations in the gate length of the ET gate electrode can be suppressed.

In the first embodiment, as shown in FIG. 1 or FIG. 13, the boron concentration at the end of the channel on the bit line side and the boron concentration at the end of the channel on the capacitive element side are different from each other. However, the boron concentration at the end of the channel on the bit line side may be relatively higher than the boron concentration at the end of the channel on the capacitor element side.

As described above, according to the first embodiment, boron ions are obliquely implanted into the channel of the MISFET Qs for memory cell selection from four directions, so that the center is highest at the center of the channel and is directed to the end of the channel. As a result, a threshold voltage control layer 10 having a boron concentration distribution that becomes lower as it approaches is obtained. Therefore, since the threshold voltage matches the space charge amount of the depletion layer of the channel, the threshold voltage is substantially determined by the boron concentration of the threshold voltage control layer 10 at the center of the channel, The junction electric field can be reduced by the boron concentration of the threshold voltage control layer 10 in the portion, and good refresh characteristics can be obtained. Furthermore, when the gate length of the gate electrode 8 is reduced, the boron concentration of the threshold voltage control layer 10 at the center of the channel is increased and the threshold voltage is increased. Can be reduced,
The MISFET Qs for memory cell selection with small characteristic fluctuation is obtained. Further, since the boron concentration of the threshold voltage control layer 10 at the end of the channel is low, the n ⁻ -type semiconductor region 11 a and the n ⁺ -type semiconductor region 1
1c can be reduced, and the drain current can be increased.

(Embodiment 2) A CMOSFET (Complementary Metal Oxide Sem) according to another embodiment of the present invention
A method of manufacturing the semiconductor FET will be described with reference to FIGS. Q ₁ is an n-channel type M having a gate length of 0.2 μm
ISFET and Q ₂ are p-channel MISFETs having a gate length of 0.25 μm.

First, as shown in FIG. 15, a trench type element isolation insulating film 26 made of a silicon oxide film is formed on a semiconductor substrate 25 made of an n-type silicon single crystal. An n-type well 28 is formed.
The p-type well 27 has a driving energy of 250 keV,
Dose amount 1 × at 150 keV and 40 keV respectively
10 ¹³ cm ^-2 , 1 × 10 ¹² cm ^-2 and 5 × 10 ¹¹ cm
It is formed by implanting boron ions into the semiconductor substrate 25 under the condition of ^-2 . Further, the n-type well 28 has a implantation energy of 200 keV and a dose of 1 × 10 ¹³ cm.
It is formed by implanting arsenic ions into the semiconductor substrate 25 under the condition of ^-2 . After that, 100
A heat treatment is performed at 0 ° C. for about 30 minutes.

Next, as shown in FIG.
5, a gate insulating film 29 having a thickness of about 6 nm is formed on the surface of the semiconductor substrate 25, and a polycrystalline silicon film (not shown) doped with phosphorus by a CVD method and a silicon nitride film 30 are formed on the semiconductor substrate 25.
Are sequentially deposited. The thickness of the polycrystalline silicon film is, for example, 5
0 nm, and the thickness of the silicon nitride film 30 is, for example, 1
00 nm. Next, the silicon nitride film 30 and the polycrystalline silicon film are sequentially etched to form a gate electrode 31 composed of the silicon nitride film 30 and the polycrystalline silicon film.

Next, as shown in FIG. 17, a light oxidation process is performed to form a light oxide film 32 on the side wall of the polycrystalline silicon film constituting the gate electrode 31. Thereafter, the n-type well 28 is covered with a resist, and the p-type well 2
7 is implanted with boron ions to form a threshold voltage control layer 33. Boron ions are obliquely implanted at an angle of 60 degrees with respect to the normal direction of the semiconductor substrate 25 and at an angle of 45 degrees with respect to the direction in which the gate electrode 30 extends.
Injected from the direction. The implantation of boron ions from one direction is performed, for example, under the conditions of an implantation energy of 60 keV and a dose of 5 × 10 ¹² cm ⁻² .

Subsequently, using the silicon nitride film 30 and the gate electrode 31 as a mask, an n-type impurity
For example, arsenic ion implantation energy 20 keV, and implanted at a dose of 2 × 10 ¹⁴ cm ^-2, a low concentration of n constituting the n-channel type MISFET Q ₁ source, a portion of the drain ^- -type semiconductor regions 35a .

Next, after removing the resist covering the n-type well 28, the p-type well 27 is covered with the resist, and phosphorus ions are implanted into the n-type well 28 to form a threshold voltage control layer 34. Phosphorus ions are implanted from four directions by oblique implantation at an angle of 60 degrees with respect to the normal direction of the semiconductor substrate 25 and at an angle of 45 degrees with respect to the direction in which the gate electrode 30 extends. The implantation of phosphorus ions from one direction is performed, for example, under the conditions of an implantation energy of 150 keV and a dose of 8 × 10 ¹² cm ⁻² .

Subsequently, using the silicon nitride film 30 and the gate electrode 31 as a mask, a p-type impurity
For example implanted boron ion energy 3 keV, and implanted at a dose of 1 × 10 ¹⁴ cm ^-2, a low concentration of p constituting the source of the p-channel type MISFET Q _2, a portion of the drain ^- -type semiconductor regions 36a .

Thereafter, the resist covering the p-type well 27 is removed, and then, for activation of impurity ions, etc.
The semiconductor substrate 25 is subjected to a heat treatment at 950 ° C. for about 20 seconds.

Next, as shown in FIG.
A silicon nitride film having a thickness of 50 nm deposited by CVD on the silicon nitride film 5 is anisotropically etched by RIE (Reactive Ion Etching) to form sidewall spacers 37 on the side walls of the silicon nitride film 30 and the gate electrode 31.

Next, after the n-type well 28 is covered with a resist, the p-type well 27 is masked by using the silicon nitride film 30, the gate electrode 31, and the sidewall spacer 37 as a mask.
An n-type impurity, for example, arsenic ion is implanted under the conditions of an implantation energy of 60 keV and a dose of 2 × 10 ¹⁵ cm ⁻² , and a high-concentration n ⁺ forming another part of the source and the drain of the n-channel MISFET Q _1. Type semiconductor region 35b
To form

Subsequently, after removing the resist covering the n-type well 28, the p-type well 27 is covered with the resist, and the p-type well 27 is covered with the silicon nitride film 30, the gate electrode 31 and the sidewall spacer 37 as a mask. Type impurity, for example, boron ion implantation energy of 5 ke
V, implanted at a dose of 2 × 10 ¹⁵ cm ^-2, to form a high-concentration p ⁺ -type semiconductor region 37b constituting the p-channel type MISFET Q ₂ source, the other part of the drain. Thereafter, a heat treatment is performed on the semiconductor substrate 25 at 950 ° C. for about 20 seconds for activation of impurity ions and the like.

Thereafter, as shown in FIG. 19, an interlayer insulating film 38 is formed on the semiconductor substrate 25, and the interlayer insulating film 38 is formed.
Is etched to form a contact hole 39,
The metal film deposited on the interlayer insulating film 38 is processed to form the wiring layer 4.
By forming 0, a CMOSFET is formed.

As described above, according to the second embodiment, the n-channel type M
The variation in the threshold voltage of ISFETQ ₁ and p-channel type MISFET Q _2, it is possible to reduce about 25% to 35%, it is possible to realize a small circuit configuration variation in characteristics.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

[0066]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, a desired threshold voltage can be obtained, a junction electric field can be reduced, good refresh characteristics can be obtained, and a threshold voltage due to variation in gate length of a gate electrode can be obtained. Since the voltage fluctuation can be reduced, it is possible to obtain a MISFET with a small characteristic fluctuation. Furthermore, since the resistance of the semiconductor region forming the source and the drain can be reduced and the drain current can be increased, a semiconductor integrated circuit device having a highly reliable MISFET can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a concentration distribution of boron introduced into a channel of a MISFET according to an embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 6 is a graph showing a concentration distribution of boron introduced into a channel of a memory cell selecting MISFET of a DRAM according to an embodiment of the present invention. (A) is a boron concentration distribution immediately after ion implantation, and (b) is a DRA
7 is a boron concentration distribution after M is completed.

FIG. 7 is a graph showing the dependence of the threshold voltage and the junction electric field on the implantation dose of boron ions.

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 13 is a diagram showing a concentration distribution of boron introduced into a channel of the MISFET according to the embodiment of the present invention. (A) is a boron concentration distribution diagram of a MISFET having a relatively short gate length, and (b) is a boron concentration distribution diagram of a MISFET having a relatively long gate length.

FIG. 14 is a graph showing a relationship between a threshold voltage and a gate length of a MISFET.

FIG. 15 shows a CMOSFE according to another embodiment of the present invention.
FIG. 9 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing T.

FIG. 16 shows a CMOSFE according to another embodiment of the present invention.
FIG. 9 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing T.

FIG. 17 shows a CMOSFE according to another embodiment of the present invention.
FIG. 9 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing T.

FIG. 18 shows a CMOSFE according to another embodiment of the present invention.
FIG. 9 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing T.

FIG. 19 shows a CMOSFE according to another embodiment of the present invention.
FIG. 9 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing T.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate 2 trench-type element isolation insulating film 3 n-type buried well 4 p-type well 5 n-type well 6 gate insulating film 7 silicon nitride film 8 gate electrode 9 photoresist pattern 10 threshold voltage control layer 11 an n ^- type Semiconductor region 11b n ⁺ type semiconductor region 11c n ⁺ type semiconductor region 12a p ⁻ type semiconductor region 12b p ⁺ type semiconductor region 13 sidewall spacer 14 interlayer insulating film 15a contact hole 15b contact hole 16a plug 16b plug 17 silicon oxide film 18a contact Hole 18b Contact hole 18c Contact hole 19 First layer wiring 20 Interlayer insulating film 21 Through hole 22 Storage electrode 23 Capacitive insulating film 24 Plate electrode 25 Semiconductor substrate 26 Groove type element isolation insulating film 27 P-type well 28 N-type well 29 Over gate insulating film 30 a silicon nitride film 31 gate electrode 32 light oxidation layer 33 threshold voltage control layer 34 threshold voltage control layer 35a n ^- -type semiconductor region 35b n ⁺ -type semiconductor region 36a p ^- -type semiconductor regions 36b p ⁺ Type semiconductor region 37 sidewall spacer 38 interlayer insulating film 39 contact hole 40 wiring layer BL bit line C information storage capacitor element Qs memory cell selection MISFET Qn n-channel MISFET Qp p-channel MISFET Q ₁ n-channel MISFET Q ₂ p-channel type MISFET

Continued on the front page (72) Inventor Tsutomu Okazaki 3-16, Shinmachi, Shinmachi, Ome-shi, Tokyo F-term in the Device Development Center, Hitachi, Ltd. (Reference) 5F040 DA06 DB03 DB09 EA08 EC01 EC07 EC13 EE05 EF02 EH03 EK05 FA07 FA16 FA18 FB02 FB04 FC11 FC13 FC21 FC22 5F083 AD01 AD10 AD42 AD48 GA05 GA21 GA27 GA30 JA06 JA32 JA35 JA40 JA56 MA06 MA17 NA01 PR03 PR21 PR29 PR33 PR36 PR37 PR40 PR43 PR53 ZA12

Claims (8)

[Claims] 1. An impurity concentration of a threshold voltage control layer at a center of a channel of a MIS transistor is relatively higher than an impurity concentration of a threshold voltage control layer at an end of the channel. Semiconductor integrated circuit device. 2. A semiconductor integrated circuit device having a plurality of MIS transistors having relatively different gate lengths on a semiconductor substrate, wherein a first gate at a central portion of a channel of the first MIS transistor having a first gate length is provided. A second threshold voltage control at a central portion of the channel of the second MIS transistor having a second gate length having an impurity concentration of a threshold voltage control layer relatively longer than the first gate length; A semiconductor integrated circuit device characterized by having a higher impurity concentration than a layer. 3. The semiconductor integrated circuit device according to claim 2, wherein the impurity concentration of the first threshold voltage control layer at the center of the channel of the first MIS transistor is:
A second threshold voltage at a central portion of the channel of the second MIS transistor, which is relatively higher than an impurity concentration of the first threshold voltage control layer at an edge portion of the channel of the first MIS transistor; A semiconductor integrated circuit device, wherein the impurity concentration of the value voltage control layer is relatively higher than the impurity concentration of the second threshold voltage control layer at the end of the channel of the second MIS transistor. 4. The semiconductor integrated circuit device according to claim 1, wherein the impurity concentration of the threshold voltage control layer at one end of the channel is lower than that of the threshold voltage control layer at the other end of the channel. A semiconductor integrated circuit device having a relatively higher impurity concentration. 5. The semiconductor integrated circuit device according to claim 2, wherein an impurity concentration of a first threshold voltage control layer at an end of a channel of said first MIS transistor and said second MIS transistor. Wherein the impurity concentration of the second threshold voltage control layer at the end of the channel is substantially equal. 6. A method of manufacturing a semiconductor integrated circuit device for forming an MIS transistor on a semiconductor substrate, comprising: (a) a step of sequentially forming a gate insulating film and a gate electrode on the semiconductor substrate; Implanting impurity ions obliquely into the channel from four directions at an angle to the normal direction of the semiconductor substrate and at an angle to the direction in which the gate electrode extends; and (c) forming a source and a drain. Forming a semiconductor region to be formed. 7. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein the angle of the step (b) with respect to the extending direction of the gate electrode in the step (b) is 45 degrees. Production method. 8. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein the ion species, dose and implantation energy of the impurity ions implanted into the channel from the four directions of the step (b) are the same. A method for manufacturing a semiconductor integrated circuit device, comprising: