JP2000286701A - Phase locked loop circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify a circuit configuration of a PLL circuit that selects a 1st or a 2nd VCO whose oscillated frequency band duffers to process a reference signal over a wide frequency range and to allow the circuit to supply a stable system clock SCK externally. SOLUTION: The phase locked loop circuit consists of a phase comparator 16, an LPF 17, 1st and 2nd VCOs 18, 19, a changeover device 20, a frequency divider 22, and a lock unlock detection circuit 32. This detection circuit 32 consists of a lock unlock discrimination circuit 33 and an integration circuit 34, this discrimination circuit 33 discriminates lock unlock based on whether or not a phase difference between a burst signal (an example of a reference signal) (1) and a recovered burst signal (an example of a comparison signal) (2) is less than 2 ck (clock), the integration circuit 34 counts up number of discrimination times in the case of discrimination of locking and counts down the number of discrimination times in the base of discrimination of unlocking. The detection circuit 32 detects a lock unlock state on the basis of the count and outputs a detection signal to switch the changeover device 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock (video signal) used for digitally processing video signals such as a TV signal (video signal from a television broadcasting station) and a VTR signal (video signal from a video tape recorder). For example, the present invention relates to a phase locked loop circuit (hereinafter, simply referred to as a PLL circuit) that generates a system clock.

[0002]

2. Description of the Related Art As a thin and lightweight display device,
A display device using a PDP (plasma display panel) or an LCD (liquid crystal display) panel has attracted attention. Since such a display device is a direct drive system using digital signals, when an analog composite video signal is input, a PLL circuit that generates a system clock for digital processing such as A / D (analog / digital) conversion is used. Required. Such a PLL circuit is desired to have a wide lock range. Conventionally, as this kind of PLL circuit, a burst lock PLL circuit as shown in FIG. 10 and a line lock PLL circuit as shown in FIG. 11 are known.

The burst lock PLL circuit shown in FIG. 10 is configured as follows. That is, the DC level of the video signal (for example, a TV signal) input to the input terminal 10 is fixed at a predetermined level by the clamp circuit 11, amplified by the amplifier circuit 12, cut off by the comparator 13 at a predetermined level or more, and burst-cut out. Input to the circuit 14. The synchronization separation circuit 15 separates the horizontal synchronization signal HD and the vertical synchronization signal VD from the input video signal and outputs the signals to the burst extraction circuit 14. The burst cutout circuit 14 cuts out a color burst signal (hereinafter, simply referred to as a burst signal) based on the video signal output from the comparator 13 and the horizontal synchronization signal HD and the vertical synchronization signal VD output from the synchronization separation circuit 15. And a burst cutout period signal (hereinafter simply referred to as a burst period signal).
Is output. The phase comparator 16 compares the burst signal with a reproduced color burst signal (hereinafter, simply referred to as a reproduced burst signal) (an example of a comparison signal) while the burst period signal is being output, using the burst signal as a reference signal. A signal corresponding to the phase difference is output, and an LPF (low-pass filter) 17 outputs a phase error voltage obtained by integrating the output of the phase comparator 16 as a control voltage to first and second VCOs (voltage controlled oscillators) 18 and 19. I do. First and second VCO 18,
Numeral 19 is provided to widen the entire oscillation frequency band (to widen the lock range), and outputs two types of pulses having different oscillation frequency bands for the same control voltage. Is one of the two types of output pulses
System clock SCK (hereinafter simply referred to as SCK)
That. ) Is output from the first output terminal 21. The frequency divider 22 divides the frequency of the SCK by a factor of 1 and outputs a subcarrier SCa (hereinafter simply referred to as SCa) from the second output terminal 23.
That. ), And the SCa is fed back to the phase comparator 16 as a reproduction burst signal. The A / D (analog / digital) converter 24 is
The output voltage (phase error voltage) of the LPF 17 is converted into a digital signal and output to the microcomputer 25.
Is a phase comparator 1 based on the output voltage of the LPF 17.
6, a lock of a PLL circuit 26 comprising an LPF 17, first and second VCOs 18 and 19, a switch 20 and a frequency divider 22,
Unlock is detected, and switching of the switch 20 is controlled.

A line lock PLL shown in FIG.
The circuit includes a video signal (for example, TV) input to the input terminal 10.
Signal), a horizontal sync separation circuit 27 for separating the horizontal sync signal HD from the signals, a phase comparator 31, an LPF 17, a VCO 28,
A PLL circuit 30 including a 1/2 frequency divider 29, a switch 20, and a frequency divider 22, an A / D converter 24, and a microcomputer 25
And consisted of The phase comparator 31 outputs the horizontal synchronizing signal H
The LPF 17 integrates the output of the phase comparator 31 to output a phase error voltage (control voltage) to the VCO 28, and the 1/2 frequency divider 29 outputs the VCO
The frequency of the pulse output from 28 is divided by two and output. The switch 20 includes a VCO 28 and a 1/2 frequency divider 29
Select one of the two types of pulses output from
It outputs from the first output terminal 21 as K. The frequency divider 22 divides the frequency of the SCK by a factor of 1 and feeds it back to the phase comparator 31 as a comparison signal. A / D converter 24
Converts the output voltage of the LPF 17 into a digital signal and outputs the digital signal to the microcomputer 25.
7, the lock and unlock of the PLL circuit 30 are detected, and the switching of the switch 20 is controlled.

[0005]

However, FIG.
Also, in the conventional example shown in FIG. 11, since the lock and unlock of the PLL circuits 26 and 30 are detected by using the A / D converter 24 and the microcomputer 25, there is a problem that the circuit configuration becomes complicated. Was. SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems. In a PLL circuit that handles a reference signal in a wide frequency range by switching a plurality of pulse signals having different oscillation frequency bands, the circuit configuration is simplified and stable. The purpose of this is to supply a clock that has been adjusted.

[0006]

A PLL circuit according to the present invention includes a phase comparator for comparing a reference signal and a comparison signal and outputting a signal corresponding to a phase difference, and a voltage corresponding to a signal output from the phase comparator. A voltage-controlled oscillator that outputs a plurality of pulse signals having different oscillation frequency bands based on an output voltage of the low-pass filter;
A switch for switching and outputting one pulse signal from a plurality of pulse signals output from the voltage controlled oscillator;
A frequency divider that divides the frequency of the pulse signal output from the switch and feeds it back to the phase comparator as a comparison signal, and detects lock and unlock based on the reference signal and the comparison signal, and detects the lock of the switch with the detection signal. And a lock / unlock detection circuit for controlling switching. The lock / unlock detection circuit is configured to control the lock / unlock detection circuit by n clocks (n is a clock) in which the phase difference between the reference signal and the comparison signal is set to a frequency higher than the frequency of the reference signal. A lock / unlock determination circuit that determines lock / unlock based on whether it is less than 1 or an integer), and counts up the number of times of determination in one of the lock determination and the unlock determination of the lock / unlock determination circuit. And an integration circuit that counts down the number of times of judgment at the time of the other judgment and detects lock / unlock based on the count value. Characterized in that it comprises Te.

In the lock / unlock determination circuit, the phase difference between the reference signal and the comparison signal is n clocks (for example, 2 clocks).
The lock / unlock state is determined based on whether or not the lock state is less than the threshold value, and the integration circuit determines whether one of the lock state and the unlock state of the lock / unlock state determination circuit (for example, the lock state).
The number of times of determination is counted up at the same time, and the number of times of determination is down-counted at the time of the other determination (for example, at the time of unlock determination), and lock and unlock are detected based on the count value. The switch selects and outputs one pulse signal from a plurality of pulse signals output from the voltage controlled oscillator based on a lock / unlock detection signal output from the integration circuit. The lock / unlock detection circuit is composed of a lock / unlock determination circuit and an integration circuit which can be configured by logic. The configuration can be simplified. Even if the lock / unlock determination circuit determines lock / unlock, the PLL circuit is not locked / unlocked immediately, but the PLL circuit is locked / unlocked with hysteresis by the integration circuit, so it is more stable. Clock can be supplied.

In order to simplify the configuration of the lock / unlock determination circuit, the lock / unlock determination circuit detects a rising (or falling) of a reference signal and outputs a pulse having a fixed time width synchronized with a clock. A first edge detector, a two-clock width conversion circuit for converting a pulse width of an output pulse of the first edge detector into two clocks for measurement, and a rising (or falling) of a comparison signal
A second edge detector that outputs a pulse having a fixed time width synchronized with the clock and outputs a pulse, and a one-clock delay device that delays the output pulse of the second edge detector by one clock.
Within the pulse width of the output pulse of the 2-clock width
And a gate circuit that outputs a lock / unlock determination signal based on whether a detection signal of the edge detector or an output signal of the one-clock delay unit appears.

In order to simplify the configuration of the integrating circuit, an up / down counter for counting the detection signal of the first edge detector using the determination signal of the lock / unlock determination circuit as an up / down control signal, When the count value of the up / down counter increases and reaches the first set value, lock is detected, and the count value of the up / down counter decreases and reaches the second set value (a value smaller than the first set value). And a detection circuit that detects unlocking when it is done.

In order to further stabilize the operation of the integration circuit, the pulse width of the detection signal output from the first edge detector is increased between the first edge detector and the up / down counter, and is output to the up / down counter. A one pulse width enlarging circuit is provided, and a second pulse width enlarging circuit is provided between the gate circuit and the up / down counter to increase the pulse width of the determination signal output from the gate circuit and output the result to the up / down counter.

In order to use the burst lock PLL circuit, the reference signal is a color burst signal cut out from the composite video signal by a burst cutout circuit.

In order to use the reference signal in a line lock PLL circuit, the reference signal is a horizontal synchronization signal separated from a composite video signal by a horizontal synchronization separation circuit.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows an embodiment of a PLL circuit according to the present invention, and the same parts as those in FIG. In FIG. 1, 10 is an input terminal, 11 is a clamp circuit, 12 is an amplifier circuit, 13 is a comparator, 14 is a burst cutout circuit, 15 is a synchronization separation circuit, 16 is a phase comparator, 17 is an LPF, 18 is a first VCO, 19 is the second
VCO, 20 is a switch, 21 is a first output terminal for outputting SCK, 22 is a frequency divider, and 23 is a second output terminal for outputting SCa. Reference numeral 32 denotes a lock / unlock detection circuit peculiar to the present invention. The lock / unlock detection circuit 32 includes a lock / unlock determination circuit 33 and an integration circuit 34, as shown in FIG. It has two pulse width expansion circuits 35 and 36 and a clock generation circuit 37. Reference numeral 38 denotes a PLL circuit. The PLL circuit 38 includes the phase comparator 16, LP
F17, first and second VCOs 18 and 19, switch 20, and frequency divider 22.

The clock generation circuit 37 generates a clock ck (hereinafter simply referred to as ck) having a frequency eight times the frequency Fsc of the burst signal (Fsc 3.58 MHz) and outputs it as a clock for measurement. As shown in FIG. 2, the lock / unlock determination circuit 33 includes first and second edge detectors 40 and 41, a two-clock width circuit 42, a one-clock delay device 43, and a gate circuit 44. . The first edge detector 40 operates when the burst period signal is at the H level, detects a rising edge of a burst signal as a reference signal, and outputs a pulse having a clock width (hereinafter, simply referred to as 1ck width) synchronized with ck. Output. The second edge detector 41 detects a rising edge of a reproduction burst signal as a comparison signal and outputs a pulse having a 1 ck width synchronized with ck. The two-clock width conversion circuit 42 outputs a signal obtained by converting the pulse width of the output pulse of the first edge detector 40 into two clock widths (hereinafter, simply referred to as 2ck width). The one-clock delay unit 43 outputs a signal obtained by delaying the output pulse of the second edge detector 41 by one clock. The gate circuit 44 includes two-input AND gates 45 and 46 and a NOR gate 47. One AND gate 45 outputs a logical product signal of the signal and the other AND gate 46.
Outputs the AND signal of the signals and the NOR gate 4
7 outputs a signal obtained by inverting the logical sum signal of the output signal of the AND gate 45 and the output signal of the AND gate 46.

The first pulse width expanding circuit 35 comprises a NAND gate 50, a 4-bit counter 51, and a one-clock delay unit 52. The NAND gate 50 outputs an output signal of the first edge detector 40 to an inverter 53.
A logical product signal of the inverted signal and the RCO (ripple carry out) of the counter 51 is inverted and output to the ENP (enable terminal) of the counter 51. The counter 51 uses the signal obtained by inverting the output signal of the first edge detector 40 by an inverter 53 as an input to an LD (load terminal) and outputs data “Dh” (1 in a 4-bit display).
It corresponds to 101. ) Is counted, and ck is counted at the H level of ENP, and the counted value is “Fh” (11 bits of 4-bit display).
It corresponds to 11. ), The RCO goes high.
The one-clock delay unit 52 is connected to the RC
A signal obtained by delaying O by one clock is output to the clock terminal of the integration circuit 34 as BCLKX.

The second pulse width expanding circuit 36 comprises a NAND gate 54, a 4-bit counter 55, and a one-clock delay unit 56. The NAND gate 54 inverts the logical product signal of the signal obtained by delaying the output signal of the gate circuit 44 by 1 clock by the one-clock delay device 57 and the RCO of the counter 55, and outputs the inverted signal to the ENP of the counter 55. The counter 55 loads data “Dh” by using a signal obtained by delaying the output signal of the gate circuit 44 by 1 ck by a 1-clock delay device 57 as an input to the LD,
The ck is counted at the H level of the ENP, and when the count value becomes “Fh”, the RCO becomes the H level. The one-clock delay unit 56 outputs a signal obtained by delaying the output signal of the NAND gate 54 by one clock ck to the U / D (up / down) control terminal of the integration circuit 34 as BLOCK.

The integration circuit 34, as shown in FIG.
It comprises an 8-bit up / down counter 60 and a detection circuit 61. The up / down counter 60 receives the BLOCK output from the second pulse width expansion circuit 36 as an input to a U / D control terminal, and its RC (ripple carry) output as an input to an EN (enable) terminal. The BCLKX output from the one-pulse width enlarging circuit 35 is counted, and the counting is stopped when the counted value reaches “FFh” or “00h”. The detection circuit 61 includes an AND gate 62,
NOR gate 63 and JK-FF (flip-flop) 6
4. The AND gate 62 outputs an AND signal of Q7 (first most significant bit) output and Q6 (second most significant bit) output of the up / down counter 60, and the NOR gate 63 outputs the up / down counter A signal obtained by inverting the logical sum signal of the Q7 output and the Q6 output of 60 is output. The JK-FF 64 receives the output signal of the AND gate 62 as an input to a J terminal, the output signal of the NOR gate 63 as an input to a K terminal,
Count CLKX. For this reason, when the count value of the up / down counter 60 increases and reaches “C0h” (Q7
= 1, Q6 = 1), the J terminal input of the JK-FF 64 becomes H level, the Q output becomes H level (lock) in synchronization with BCLKX, and the count value of the up / down counter 60 decreases. And reached “3Fh” (Q7
= 0, Q6 = 0), the input of the K terminal of the JK-FF 64 goes high, and its Q output goes low (unlocked) in synchronization with BCLKX.

Next, the operation of the embodiment will be described with reference to FIGS.
Will be described together. (1) A video signal (for example, a TV signal) input to the input terminal 10 has a DC level fixed to a predetermined level by a clamp circuit 11, is amplified by an amplifier circuit 12, is cut by a comparator 13 to a predetermined level or more, and is a burst cutout circuit. Input to 14. The horizontal synchronization signal HD and the vertical synchronization signal V separated from the input video signal by the synchronization separation circuit 15
D is input to the burst extraction circuit 14.

(2) The burst extraction circuit 14 outputs a burst signal and a burst period signal based on the video signal input from the comparator 13 and the horizontal synchronization signal HD and the vertical synchronization signal VD input from the synchronization separation circuit 15. This burst signal is used as a reference signal by the PLL circuit 2.
6 and the burst period signal is input to the phase comparator 16 as an enable signal.

(3) The phase comparator 16 compares the burst signal with the reproduced burst signal as a comparison signal and outputs a signal corresponding to the phase difference during the period when the burst period signal is being output. The first and second VCs use the phase error voltage obtained by integrating the output of the
Output to O18 and O19. First and second VCOs 18, 19
Is output from the first output terminal 21 as the SCK selected by the switch 20 and divided by the frequency divider 22 to a second integer. The signal SCa is output from the output terminal 23, and this SCa is fed back to the phase comparator 16 as a reproduction burst signal.

(4) In the above (3), the switch 20 selects which of the two pulse signals output from the first and second VCOs 18 and 19 to use as the SCK.
It is determined by the detection signal of the unlock detection circuit 32, and this detection signal is determined by the phase difference between the burst signal and the reproduced burst signal. Therefore, the case where the phase difference is 0 (A), the case where the phase difference is less than 2ck (B) and (C), and the case where the phase difference is 2ck or more (D) will be described separately.

(A) For convenience of explanation, the switch 20 is a first switch.
A case where the first VCO 18 of the second VCOs 18 and 19 is selected and the phase of the burst signal matches the phase of the reproduced burst signal (when the phase difference is 0) will be described with reference to FIGS. (i) ck output from clock generation circuit 37 (frequency 8
4A, the burst signal of the frequency Fsc is a pulse signal having one cycle of 8ck as shown in FIG. 4C, and the reproduced burst signal is shown in FIG. 4D.
As shown in FIG.

(Ii) During the period in which the burst period signal output from the burst cutout circuit 14 is at the L level (the period shown on the left side of FIG. 4B), the first edge detector 40 does not operate, so the first edge The detection signal and the 2ck width signal are at the L level as shown in FIGS. 7E and 7F, the count value of the first counter 51 is "Fh" as shown in FIG.
The RCO and BCLKX of the counter 51 are as shown in FIGS.
The H level is continued as shown in FIG. The L level 2ck width signal is input to the AND gates 45 and 46 of the gate circuit 44, and the H level signal as shown in FIG.
Since the signal is input to the LD terminal of the counter 55, the count value of the second counter 55 is "Fh" as shown in FIG.
The RCO of the counter 55 keeps the H level as shown in FIG. 3M, and the BLOCK keeps the L level as shown in FIG.

(Iii) During the period in which the burst period signal is at the H level (the period shown on the right side of FIG. 4B), the first edge detector 40 operates to detect the rise of the burst signal. A first edge detection signal having a 1ck width synchronized with ck as shown in e) is output. This signal is inverted by the inverter 53 and input to the LD terminal of the first counter 51 to load the initial value “Dh”.
The count value of 1 changes as shown in FIG. That is, at the time of loading, the count value changes from "Fh" to "Dh", and as shown in FIG. 4 (k), the RCO changes to L level, ENP becomes H level, the first counter 51 is enabled, and the counting is started. start. And the first counter 5
When the count value of 1 reaches “Fh”, the RCO changes to the H level, sets ENP to the L level, and disables the first counter 51. For this reason, BCLKX is as shown in FIG.
As shown in the figure, the signal is obtained by delaying the RCO of FIG.

(Iv) The second edge detector 41 detects the rising edge of the reproduction burst signal and outputs a second edge detection signal as shown in FIG.
The clock delay unit 43 delays the second edge detection signal by one clock and outputs a 1ck delay signal as shown in FIG. The two-clock width circuit 42 doubles the pulse width of the signal and outputs a 2ck width signal as shown in FIG. 4F to the AND gates 45 and 46. For this reason,
A signal as shown in FIG. 4 (i) is input to the NAND gate 54 and to the LD terminal of the second counter 55. This signal is a signal obtained by inverting a signal which becomes H level only during a period when the signal is at H level and one of the signals is at H level and delayed by 1 ck.

(V) The LD of the second counter 55 is
When the terminal goes to the L level, the second counter 55 loads the initial value "Dh" during this L level (2ck period), so that the count value of the second counter 55 changes as shown in FIG. . That is, the count value changes from "Fh" to "Dh" at the time of loading, and as shown in FIG. 4 (m), the RCO changes to L level, ENP is set to H level, the second counter 55 is enabled, and counting is performed. start. When the count value of the second counter 55 reaches “Fh”, RC
O changes to H level, ENP is set to L level, and the second counter 55 is disabled. For this reason, BLO
As shown in FIG. 4 (o), CK is at the H level at the rise of BCLKX, and becomes a pulse signal having an H level period of 4ck and an L level period of 4ck.

(Vi) The up / down counter 60 in the integration circuit 34 operates as an up counter when BLOCK is at the H level and counts the rising edge of BCLKX. For this reason, as shown in FIG. 8, when the count value (number of determinations) of the up / down counter 60 increases and reaches “C0h” as the first set value,
The Q output of the JK-FF 64 changes from L level to H level. That is, when the count value reaches “C0h”, the up / down counter 60 becomes Q7 = 1, Q6 = 1, the output of the AND gate 62 becomes H level (the output of the NOR gate 63 is L level), and the JK-FF 64 J Since the signal is input to the terminal, the Q output changes from the L level to the H level, and a lock detection signal is output to the switch 20. Therefore, the switch 2
0 is one of the first and second VCOs 18 and 19 (for example,
The state of selecting the output of CO18) and outputting it from the first output terminal 21 as SCK continues. This SCK is frequency-divided by the frequency divider 22 to one-integral, and fed back to the phase comparator 16 as a reproduction burst signal to perform phase synchronization control.

(B) Next, the switch 20 is switched to the first VCO 1
8, the reproduced burst signal is delayed in phase from the burst signal but the phase difference is less than 2ck.
This will be described with reference to FIGS. For convenience of explanation, a burst signal and a reproduced burst signal appear at timings as shown in FIGS. 5C and 5D, and a burst period signal is at H level as shown in FIG.
A case where 0 is operating will be described.

(I) The first edge detector 40 detects the rising edge of the burst signal, and outputs the signal ck as shown in FIG.
Outputs a first edge detection signal having a 1ck width in synchronization with the first edge detection signal. This signal is inverted by the inverter 53 and input to the LD terminal of the first counter 51 to load the initial value “Dh”, so that the count value of the first counter 51 changes as shown in FIG. That is, the count value is "Fh" at the time of loading.
To "Dh", and as shown in FIG. 5 (k), the RCO changes to L level, ENP is set to H level, the first counter 51 is enabled, and counting is started. When the count value of the first counter 51 reaches “Fh”, R
CO changes to H level and ENP is changed to L level.
The counter 51 is disabled. For this reason, BC
LKX is, as shown in FIG. 5 (n), the RC of FIG.
This is a signal obtained by delaying O by 1 ck.

(Ii) The second edge detector 41 detects the rising edge of the reproduction burst signal and outputs a second edge detection signal as shown in FIG.
The clock delay unit 43 delays the second edge detection signal by one clock and outputs a 1ck delay signal as shown in FIG. The two-clock width circuit 42 doubles the pulse width of the signal and outputs a 2ck width signal as shown in FIG. 5F to the AND gates 45 and 46. For this reason,
A signal as shown in FIG. 5 (i) is input to the NAND gate 54 and to the LD terminal of the second counter 55. This signal is a signal obtained by inverting a signal which becomes H level only during a period when the signal is at H level and one of the signals is at H level and delayed by 1 ck.

(Iii) The L of the second counter 55 is
When the D terminal goes to L level, during this L level (1ck)
(Period) Since the second counter 55 loads the initial value “Dh”, the count value of the second counter 55 changes as shown in FIG. That is, the count value is "Fh" at the time of loading.
To "Dh", and as shown in FIG. 5 (m), the RCO changes to L level, ENP is set to H level, the second counter 55 is enabled and counting starts. When the count value of the second counter 55 reaches “Fh”, R
CO changes to H level and ENP is changed to L level.
The counter 55 is disabled. Therefore, BL
OCK is in the H level state at the rise of BCLKX as shown in FIG. 5 (o), and is a pulse signal having an H level period of 3ck and an L level period of 5ck.

(Iv) The up / down counter 60 in the integration circuit 34 operates as an up counter when BLOCK is at the H level and counts the rise of BCLKX. Therefore, as shown in FIG. 8, when the count value (number of times of determination) of the up / down counter 60 increases and reaches “C0h”, the Q output of the JK-FF 64 changes from the L level to the H level. That is,
When the counted value reaches “C0h”, the up / down counter 60
Becomes Q7 = 1, Q6 = 1, and the output of the AND gate 62 becomes H level (the output of the NOR gate 63 becomes L level) and is input to the J terminal of the JK-FF 64.
The level changes from the level to the H level, and a lock detection signal is output to the switch 20. Therefore, the switch 20 is connected to the first VCO 1
No. 8 is selected, and the state of outputting as SCK from the first output terminal 21 continues. This SCK is the frequency divider 2
The signal is frequency-divided by 2 and divided by 1 and fed back to the phase comparator 16 as a reproduction burst signal. For this reason, by the phase synchronization control by the first VCO 18 selected by the switch 20, control is performed to advance the phase of the reproduced burst signal, and the phase of the reproduced burst signal matches the phase of the burst signal.

(C) Further, the switch 20 is connected to the first VCO 18
Is selected, and the reproduced burst signal has a phase lead from the burst signal. If the phase difference is less than 2 ck, the operation is the same as in the case (B). That is, the timings at which the first edge detection signal and the second edge detection signal appear are opposite to those in the case of (B), and accordingly, the subsequent signals, the count values of the first and second counters 51 and 55, and the RCO The appearance timing is different from the case of the above (B), but BCLKX is generated at the timing as shown in FIG. 6 (n), and BLOCK is generated as shown in FIG. 6 (o).
At the time of rising of CLKX, the pulse signal is in the H level state, and the H level period is 3 ck and the L level period is 5 ck. Therefore, as in the case of (B), the up / down counter 60 in the integration circuit 34 sets the H level of BLOCK.
Since it operates as an up counter at the level and counts the rise of BCLKX, the count value (number of times of judgment) of the up / down counter 60 increases as shown in FIG.
When "h" is reached, the Q output of the JK-FF 64 changes from the L level to the H level, and outputs a lock detection signal to the switch 20. For this reason, the state where the switch 20 selects the output of the first VCO 18 and outputs it from the first output terminal 21 as SCK continues. This SCK is frequency-divided by a frequency divider 22 into a fraction of an integer, and the phase comparator 16
Will be fed back. Therefore, by the phase synchronization control by the first VCO 18 selected by the switch 20, control for delaying the phase of the reproduced burst signal is performed, and the phase of the reproduced burst signal matches the phase of the burst signal.

(D) Further, the switch 20 is connected to the first VCO 18
And the reproduced burst signal is 2
The case of a phase delay equal to or longer than ck will be described with reference to FIGS. For convenience of explanation, a burst signal and a reproduced burst signal appear at timings as shown in FIGS. 7C and 7D, and a burst period signal becomes H as shown in FIG.
A case where the first edge detector 40 operates at the level will be described.

(I) The first edge detector 40 detects the rising edge of the burst signal, and outputs the signal ck as shown in FIG.
Outputs a first edge detection signal having a 1ck width in synchronization with the first edge detection signal. This signal is inverted by the inverter 53 and input to the LD terminal of the first counter 51 to load the initial value “Dh”, so that the count value of the first counter 51 changes as shown in FIG. That is, the count value is "Fh" at the time of loading.
To Dh, and as shown in FIG. 7 (k), the RCO changes to L level, ENP is set to H level, the first counter 51 is enabled, and counting is started. When the count value of the first counter 51 reaches “Fh”, R
CO changes to H level and ENP is changed to L level.
The counter 51 is disabled. For this reason, BC
LKX is, as shown in FIG. 7 (n), the RC of FIG.
This is a signal obtained by delaying O by 1 ck.

(Ii) The second edge detector 41 detects the rising edge of the reproduction burst signal and outputs a second edge detection signal as shown in FIG.
The clock delay unit 43 delays the second edge detection signal by one clock and outputs a 1ck delay signal as shown in FIG. Further, the two-clock width circuit 42 doubles the pulse width of the signal and outputs a 2ck width signal to the AND gates 45 and 46 as shown in FIG. For this reason,
As shown in FIG. 7 (i), a signal that continues to be at the H level is input to the NAND gate 54 and the second counter 55
Input to the LD terminal. This signal is a signal obtained by inverting a signal which becomes H level only during a period when the signal is at H level and one of the signals is at H level, and further delays by 1 ck, so that the phase difference between the burst signal and the reproduction burst signal is 2 ck. During this period, the H level is maintained.

(Iii) When the signal continues at the H level, the LD terminal of the second counter 55 also keeps the H level and does not load the initial value "Dh", so that the count value of the second counter 55 is as shown in FIG. "Fh" is continued as shown in
(M), the H level is continued, and the second counter 55 is disabled. For this reason, BLOC
K also keeps the L level as shown in FIG.

(Iv) The up / down counter 60 in the integration circuit 34 operates as a down counter when BLOCK is at the L level and counts the rising edge of BCLKX. For this reason, as shown in FIG. 8, when the count value (the number of determinations) of the up / down counter 60 decreases to “3Fh”, the Q output of the JK-FF 64 changes from the H level to the L level. That is,
When the counted value reaches “3Fh”, the up / down counter 60
Becomes Q7 = 0 and Q6 = 0, and the output of the NOR gate 63 becomes H level (the output of the AND gate 62 becomes L level) and is input to the K terminal of the JK-FF 64.
The level changes from the level to the L level, and an unlock detection signal is output to the switch 20. For this reason, the switch 20 is connected to the second VC
The output of O19 is selected and output from the first output terminal 21 as SCK. For example, when the phase difference changes from the lock detection state to the unlock detection state and becomes 2 ck or more, the VCO
Is switched from the first VCO 18 to the second VCO 1 by the switch 20.
9 is switched. SC output from second VCO 19
K is frequency-divided by the frequency divider 22 to be a fraction of an integer, and is fed back to the phase comparator 16 as a reproduction burst signal. For this reason, by the phase synchronization control by the second VCO 19, control is performed to advance the phase of the reproduced burst signal, and the phase of the reproduced burst signal matches the burst signal.

In the above embodiment, the lock / unlock determination circuit determines lock / unlock based on whether the phase difference between the burst signal and the reproduced burst signal is less than 2ck, but the present invention is not limited to this. The phase difference between the burst signal and the reproduced burst signal is not limited to nck (n
Is an integer of 1 or more including 2).

In the above embodiment, when the count value of the up / down counter increases and reaches the first set value "C0h", lock is detected by the detection circuit, and the count value of the up / down counter decreases. The unlocking is detected by the detection circuit when the second set value reaches “3Fh”, but the present invention is not limited to the case where the first set value is “C0h” and the second set value is “3Fh”. , The first set value to the second
It can be used for the case where the hysteresis effect is provided by setting the value larger than the set value.

In the above embodiment, the case where the voltage controlled oscillators for outputting two pulse signals having different oscillation frequency bands are constituted by the first and second VCOs has been described. However, the present invention is not limited to this. As in the conventional example shown in FIG. 11, a VCO for outputting a pulse signal in a predetermined oscillation frequency band, a 1/2 frequency divider for outputting the frequency of the pulse signal output from the VCO divided by 1/2 It can also be used in the case where it is configured with.

In the above embodiment, the burst lock PL
Although the case where the present invention is used for the L circuit has been described, the present invention is not limited to this, and can be used for a line lock PLL circuit.

In the embodiment, in order to further stabilize the operation of the integrating circuit, the first pulse width expanding circuit is provided between the first edge detector and the up / down counter, and the first pulse width expanding circuit is provided between the gate circuit and the up / down counter. Although the case where the second pulse width enlarging circuit is provided has been described above, the present invention is not limited to this, and can be used even when the first and second pulse width enlarging circuits are omitted.

In the above embodiment, the case where the integration circuit is constituted by an up-down counter and a detection circuit has been described in order to simplify the construction of the integration circuit. However, the present invention is not limited to this. At the time of one of the lock determination and the unlock determination of the lock determination circuit (for example, at the time of lock determination), the number of determinations is counted up, and at the time of the other determination (for example, at the time of unlock determination), the number of determinations is down-counted. Lock based on that count,
What is necessary is just to detect unlocking.

In the above embodiment, in order to simplify the configuration of the lock / unlock determination circuit, the lock / unlock determination circuit is composed of a first edge detector, a two-clock width circuit, a second edge detector, and one clock. Although the description has been given of the case where the delay circuit and the gate circuit are used, the present invention is not limited to this case. What is necessary is just to determine whether to lock or unlock based on whether or not.

In the above embodiment, the case where the voltage controlled oscillator outputs two pulse signals having different oscillation frequency bands has been described, but the present invention is not limited to this.
The present invention can also be used when outputting three or more pulse signals having different oscillation frequency bands. For example, as shown in FIG. 9, first, second, third, and fourth output four pulse signals having different oscillation frequency bands at the output voltage of the LPF 17.
The fourth VCOs 71, 72, 73 and 74 constitute a voltage controlled oscillator, and are arranged at regular intervals (for example, “C0h” in FIG. 8).
A switching time setting counter (for example, a 10-bit counter) 75 for outputting one pulse every sufficiently longer period (equivalent to 192 ck) and a 2-bit ring counter 76 for outputting a switching signal are provided. The ring counter 76 is enabled with a signal obtained by inverting the unlock detection signal (L level signal) output from the integration circuit 34 of the unlock detection circuit 32 by the inverter 77, and the counter 75 outputs 00 each time one pulse is output. 0
The present invention can also be used when the switching signals 1, 10, and 11 are cyclically switched and output to the switch 78. In this case, since a reference signal in a wide frequency range can be handled with a simple configuration, NTSC, PAL,
Compatible with SECAM color decoder.

[0047]

The PLL circuit according to the present invention includes a phase comparator, a low-pass filter, a voltage controlled oscillator, a switch, a frequency divider, and a lock / unlock detection circuit.
The unlock detection circuit comprises a lock / unlock determination circuit and an integration circuit, and the lock / unlock determination circuit locks based on whether the phase difference between the reference signal and the comparison signal is less than n clocks (for example, 2 clocks), Unlocking is determined, and the integration circuit counts up the number of times of determination of one of the lock determination and unlock determination of the lock / unlock determination circuit (for example, lock determination) and performs the other determination (for example, unlock). At the time of judgment), the number of times of judgment is counted down, lock and unlock are detected based on the counted value, and the voltage is output from the voltage controlled oscillator by the switch based on the lock / unlock detection signal output from the integration circuit. One pulse signal is switched and output from a plurality of pulse signals having different oscillation frequency bands. For this reason, the lock / unlock detection circuit can be constituted by a lock / unlock determination circuit and an integration circuit which can be constituted by logic, and the lock / unlock detection circuit is constituted by an A / D converter and a microcomputer. The circuit configuration can be simplified as compared with. Furthermore, even if the lock / unlock determination circuit determines lock / unlock, instead of immediately locking / unlocking, the integration circuit locks / unlocks with hysteresis. Can be supplied.

When the lock / unlock determination circuit is composed of a first edge detector, a two-clock width circuit, a second edge detector, a clock delay unit and a gate circuit, the configuration of the lock / unlock determination circuit Can be simplified.

An up / down counter for counting the detection signal of the first edge detector by using the judgment signal of the lock / unlock judgment circuit as an up / down control signal;
When the count value of the up / down counter increases and reaches the first set value, lock is detected, and the count value of the up / down counter decreases and reaches the second set value (a value smaller than the first set value). When it is configured with a detection circuit that detects unlocking when this is done, the configuration of the integration circuit can be simplified.

A first pulse width enlargement circuit is provided between the first edge detector and the up / down counter to increase the pulse width of the detection signal output from the first edge detector and to output the detected signal to the up / down counter. In the case where a second pulse width enlarging circuit is provided between the down counter and the pulse width of the determination signal output from the gate circuit and output to the up / down counter, the operation of the integrating circuit can be further stabilized.

When the reference signal is a color burst signal cut out from the composite video signal by the burst cutout circuit, the present invention can be applied to a burst lock PLL circuit.

When the reference signal is a horizontal synchronization signal separated from the composite video signal by the horizontal synchronization separation circuit,
The present invention can be applied to a line lock PLL circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a PLL circuit according to the present invention.

FIG. 2 is a block diagram showing a lock / unlock detection circuit in FIG. 1;

FIG. 3 is a block diagram showing an integration circuit in FIG. 1;

FIG. 4 is a timing chart for explaining the operation when the phase difference between the reproduced burst signal and the burst signal is 0 in FIG.

FIG. 5 is a timing chart for explaining the operation when the reproduction burst signal is behind the burst signal in phase but less than 2ck in FIG.

FIG. 6 is a timing chart for explaining the operation when the reproduction burst signal is advanced in phase from the burst signal in FIG. 1, but the phase difference is less than 2ck.

FIG. 7 is a timing chart for explaining the operation when the reproduction burst signal has a phase delay from the burst signal and a phase difference of 2 ck or more in FIG.

8 is an explanatory diagram showing the operation of the integration circuit in FIG.

FIG. 9 is a block diagram showing a main part when the present invention is used when a voltage controlled oscillator that outputs four pulse signals having different oscillation frequency bands is used.

FIG. 10 is a block diagram showing Conventional Example 1.

FIG. 11 is a block diagram showing Conventional Example 2.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Input terminal, 11 ... Clamp circuit, 12 ... Amplification circuit, 13 ... Comparator, 14 ... Burst cutout circuit, 15 ... Synchronization separation circuit, 16 ... Phase comparator,
17: LPF (low-pass filter), 18: 1st VC
O (voltage controlled oscillator), 19 ... second VCO, 20,
78: switch, 21: first output terminal, 22: frequency divider,
23 ... second output terminal, 26 ... PLL circuit, 32 ...
Lock / unlock detection circuit, 33: lock / unlock determination circuit, 34: integration circuit, 35: first pulse width expansion circuit, 36: second pulse width expansion circuit, 37 ...
clock generating circuit for generating ck; 38: PLL circuit; 40: first edge detector; 41: second edge detector; 42: two-clock width generating circuit;
6, 57 ... 1 clock delay device, 44 ... Gate circuit,
45, 46, 62 ... AND gate, 47, 63 ... NOR gate, 50, 54 ... NAND gate, 51 ... first counter, 53, 77 ... inverter, 55 ... second counter, 60 ... up-down counter, 61 ... detection circuit, 64: JK-FF; 71 to 74: individual voltage controlled oscillators constituting voltage controlled oscillators for outputting pulse signals in four kinds of oscillation frequency bands; 75: counter for setting switching time; 76: 2-bit ring counter ,
… Burst signal (an example of a reference signal)… Reproduction burst signal (an example of a comparison signal)… Burst period signal ck Clock (clock for measurement) HD
Horizontal sync signal, SCK ... system clock, SCa ...
Subcarrier, VD: vertical synchronization signal.

Continued on the front page F term (reference) 5C020 AA16 AA31 AA32 AA35 CA13 CA15 5D044 AB07 DE32 GM12 GM14 GM15 GM16 GM17 5J106 AA04 CC20 CC21 CC38 CC41 CC52 CC58 DD04 DD05 DD06 DD09 DD17 DD43 DD46 EE01 EE09 FF10 GG39 H01

Claims (8)

[Claims] 1. A phase comparator for comparing a reference signal with a comparison signal and outputting a signal corresponding to a phase difference, a low-pass filter for outputting a voltage corresponding to a signal output from the phase comparator, and a low-pass filter. A voltage-controlled oscillator that outputs a plurality of pulse signals having different oscillation frequency bands based on an output voltage, a switch that selects and outputs one pulse signal from a plurality of pulse signals output from the voltage-controlled oscillator, A frequency divider that divides the frequency of the pulse signal output from this switch and feeds it back to the phase comparator as a comparison signal, and detects lock and unlock based on the reference signal and the comparison signal, and detects the lock with the detection signal. A lock / unlock detection circuit for controlling switching of the switch, wherein the lock / unlock detection circuit detects a phase difference between the reference signal and the comparison signal. A lock / unlock determination circuit for determining lock / unlock based on whether or not a clock set to a frequency higher than the frequency of the reference signal is less than n clocks (n is an integer of 1 or more); An integration circuit that counts up the number of times of determination in one of the lock determination and the unlock determination of the circuit and counts down the number of determinations in the other determination, and detects lock and unlock based on the count value. A phase-locked loop circuit characterized by comprising. 2. A lock / unlock determination circuit comprising: a first edge detector for detecting a rising edge (or a falling edge) of a reference signal and outputting a pulse having a fixed time width synchronized with a clock; Clock width conversion circuit for converting the pulse width of the output pulse of the detector into the clock width of two clocks, and a second circuit for detecting a rise (or fall) of the comparison signal and outputting a pulse having a fixed time width synchronized with the clock. An edge detector; a one-clock delay device for delaying the output pulse of the second edge detector by one clock; and a pulse width of the second edge detector within a pulse width of the output pulse of the two-clock widening circuit. 2. A phase locked loop according to claim 1, further comprising a gate circuit for outputting a lock / unlock determination signal based on whether a detection signal or an output signal of said one-clock delay unit appears. Flop circuit. 3. An up / down counter for counting a detection signal of a first edge detector by using a determination signal of a lock / unlock determination circuit as an up / down control signal, and an integration circuit.
When the count value of the up / down counter increases and reaches the first set value, lock is detected, and the count value of the up / down counter decreases to a second set value (a value smaller than the first set value). 3. The phase-locked loop circuit according to claim 1, further comprising a detection circuit that detects unlocking when the voltage has reached. 4. A first pulse width expanding circuit for expanding a pulse width of a detection signal output from the first edge detector and outputting the detected signal to the up / down counter is provided between the first edge detector and the up / down counter. 4. The phase synchronization according to claim 3, further comprising a second pulse width expanding circuit for expanding a pulse width of a determination signal output from the gate circuit and outputting the pulse width to the up / down counter between the gate circuit and the up / down counter. Loop circuit. 5. The phase locked loop circuit according to claim 1, wherein the reference signal is a color burst signal cut out from the composite video signal by a burst cut out circuit. 6. The phase locked loop circuit according to claim 3, wherein the reference signal is a color burst signal cut out from the composite video signal by a burst cutout circuit. 7. The phase-locked loop circuit according to claim 1, wherein the reference signal is a horizontal sync signal separated from the composite video signal by a horizontal sync separation circuit. 8. The phase locked loop circuit according to claim 3, wherein the reference signal is a horizontal sync signal separated from the composite video signal by a horizontal sync separation circuit.