JP2000286339A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restrain short-circuiting from occurring between wirings by a method, where etching is prevented from proceeding beyond the lower wiring when a contact is formed so as to connect an upper wiring and a lower wiring together, even if the contact is designed in a case where the allowance of the overlap of a contact with the lower wiring is small. SOLUTION: A contact 312 is formed extending from an upper second wiring pattern 311, so as to be connected to a lower first wiring pattern 314 penetrating through a second insulating layer 313. Even if the contact 312 is positioned off the lower first wiring pattern 315, a first insulating film 314 which is slower in etching rate than the second insulating film 313 functions as a stopper to overetching of a contact hole. Therefore, the lower edge of the contact 312 is checked by the first insulating film 314, and advance to the lower wiring pattern 316 is deterred.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device having a multilayer wiring structure using a conductive metal film.

[0002]

2. Description of the Related Art Conventionally, as LSIs have been miniaturized, not only the gate electrode width of a MOS transistor but also the space between gate electrodes has been significantly reduced in order to shrink the memory cell size and the like. For this reason, the wiring pitch (line / space) of the metal wiring for connecting and wiring the MOS transistors must be reduced. On the other hand, in the conventional device, as shown in FIG. 4, when forming the contact 402 for connection with the upper layer, the lower wiring layer 401 and the contact 402 can be properly connected in the etching for forming the contact. ,
In order to prevent short-circuiting with other layers, the wiring layer 401 is designed to have a margin 403 in advance at the portion to which the contact is connected. This portion determines the pitch between adjacent wirings.

However, in recent LSIs, as described above, with miniaturization, it is becoming difficult to provide a margin at a portion where a contact is connected. Therefore, as shown in FIG. 5, the margin is reduced or eliminated entirely. That is, in FIG. 5, the connection region 413 of the contact 412 of the lower wiring layer 411 is formed to have the same width as the lower wiring layer 411, so that there is no margin.

FIG. 6 and FIG. 7 are process diagrams showing a manufacturing process of such a conventional multilayer wiring structure on a semiconductor substrate. Here, already MOS transistors and capacitors,
It is assumed that other structures have been formed, and a description will be given starting from the formation of the first-layer metal film 201 at the beginning of the multilayer wiring process. In the current state, an interlayer insulating film is formed on a device such as a MOS transistor in the lowermost layer by CVD or the like, flattened by a reflow method, an etch back (EB) method, a CMP method, or the like, and is connected to a silicon substrate. After the contact is formed.

First, in FIG. 6A, a first-layer metal film (eg, Al or Cu) 201 is formed to a thickness of, for example, about 500 nm on a layer already formed as described above.
Further, in FIG. 6B, the SiO ₂ -based insulating film 20 is formed.
2 is formed to a thickness of, for example, about 150 nm by CVD or the like.
Next, a resist pattern is formed by a lithography method, and the oxide film 202 on the metal film 201 is selectively dry-etched and removed (DE) by RIE (reactive ion etching) using the mask as a mask. The film 201 is selectively removed by dry etching (DE) to form a pattern 203 as shown in FIG.

Next, in FIG. 6D, an interlayer insulating film 204 is formed on the first wiring pattern 203 by CVD. At this time, according to the high-density plasma technology, the embedding property between wirings and the like is good. Then, the insulating film 204 formed by CVD is polished and flattened by a CMP method (FIG. 6E). After this planarization, an inter-wiring contact 205 for connecting the lower first wiring pattern 203 and an upper wiring pattern 209 described later is formed.
First, a mask pattern of a contact hole is formed on the planarized interlayer insulating film 204 by a lithography technique, and the oxide film 204 is etched away to reach a lower wiring layer (first wiring pattern 203). Is formed (FIG. 7F). At this time, CM
Even if planarization is performed by the P method, over-etching will be applied so that the contact can be properly reached even at the deepest position because global steps and variations in the film thickness between wafers between lots can be considered. Not shown).

After that, a barrier metal (TiN / Ti) is formed by sputtering (not shown) for the purpose of securing adhesion between the contact and the lower wiring layer (first wiring pattern 203) and suppressing an increase in resistance. Tungsten for forming the plug 206 is formed by CVD, and is etched away by etching back or polishing by a CMP method, leaving only the plug portion (FIG. 7G). Next, an upper second-layer metal film (for example, Al or Cu) 207 is, for example, 50
Deposited at about 0 nm (Fig. 7 (H)), further, SiO ₂
System insulating film 208 is formed to a thickness of, for example, 150 nm by CVD or the like.
A film is formed to a degree (FIG. 7 (I)). Next, after patterning by lithography, the insulating film 208 and the second layer metal film 207 are removed by etching, and the second wiring pattern 2 is removed.
09 (FIG. 7 (J)). Thereafter, a multilayer wiring is formed by repeating the above.

[0008]

However, in the above-mentioned prior art, as shown in FIG. 5, if the margin of the portion to which the contact is connected is reduced or eliminated altogether, as shown in FIG. Problems occur. FIG. 8 is a cross-sectional view exemplifying a connection failure state that occurs in the above-described conventional multi-layer wiring structure when a margin to cover a portion to which a contact is connected is eliminated. Note that, in this figure, a MOS which is a lower layer than the illustrated multilayer wiring structure is shown.
Illustration of transistors, resistors, capacitors, and other structures is omitted.

[0009] As shown in FIG.
01 through the insulating layer 303 and the underlying wiring pattern 3
When the position of the contact 302 connected to the contact 04 is shifted from the wiring pattern 304, the lower end of the contact 302 is further etched to the lower wiring pattern 305 by the above-described over-etching, and the contact 302 And the wiring pattern 305 is 30
Short circuit occurs at 6 In particular, when etching a contact, the depth can be accurately controlled at a shallow position, but when etching to a deep position, over-etching is performed twice or three times as long as the lamination interval. In a state where there is no margin, the possibility of occurrence of a short circuit is increased.

Accordingly, an object of the present invention is to provide a method of forming a contact for connecting an upper layer wiring and a lower layer wiring, in which the etching is performed below the lower layer wiring even when the contact is designed to have no margin with the lower layer wiring. It is an object of the present invention to provide a method of manufacturing a semiconductor device which can prevent the semiconductor device from proceeding and prevent a short circuit between wirings.

[0011]

According to the present invention, there is provided a method of manufacturing a semiconductor device having a multi-layer wiring structure using a conductive metal film, wherein the multi-layer wiring structure is formed by using a multi-layer wiring structure. A first insulating film buried in an inter-wiring space for insulating in a pitch direction and a second insulating film formed between each layer for insulating a multilayer wiring in a film thickness direction are formed by films having different etching rates from each other. It is characterized by having been formed.

In the method for manufacturing a semiconductor device according to the present invention,
When forming a contact hole for providing a contact for connecting the upper wiring and the lower wiring, etching is performed from the upper wiring to the lower wiring, and the contact hole penetrates the second insulating film formed between the respective layers. To form At this time, over-etching is applied so that the contact can be reliably connected to the lower wiring. If the position of this etching is shifted from the position of the lower wiring pattern, the etching reaches the first insulating film embedded in the space between the wirings of the lower wiring pattern.

[0013] However, the first insulating film has a second insulating film between the respective layers.
An insulating film having a different etching rate with respect to the insulating film and having a lower etching rate than the second insulating film is selected. This second insulating film functions as a stopper, so that the etching does not proceed to the lower wiring. Therefore, when forming a contact that connects the upper layer wiring and the lower layer wiring, even if the contact is designed so that there is no margin with the lower layer wiring, the etching should not be allowed to proceed below the lower layer wiring, and Can be avoided.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the method for manufacturing a semiconductor device according to the present invention will be described below. 1 and 2
FIG. 9 is a process chart showing a manufacturing process of the multilayer wiring structure in the semiconductor substrate according to the present embodiment. Here, MO
It is assumed that the S transistor, the capacitor, and other structures have been formed, and the description will be made from the point of forming the first-layer metal film 101 at the beginning of the multilayer wiring process. In the current state, an interlayer insulating film is formed on a device such as a MOS transistor in the lowermost layer by CVD or the like, flattened by a reflow method, an etch back (EB) method, a CMP method, or the like, and is connected to a silicon substrate. After the contact is formed.

First, in FIG. 1A, a first-layer metal film (eg, Al or Cu) 101 is formed on a layer already formed as described above by CVD, sputtering, or the like.
Is formed to a thickness of, for example, about 500 nm.
In this case, an SiO ₂ -based insulating film 102 is formed to a thickness of, for example, about 150 nm by CVD or the like. In addition, as long as an SiO ₂ -based film can be formed, for example, P-TEOS, O-
A TEOS, HDP film or the like can be employed. next,
A resist pattern is formed by a lithography method, and the oxide film 102 on the metal film 101 is selectively dry-etched and removed (DE) by RIE (reactive ion etching) using the mask as a mask.
1 was selectively dry-etched (DE) to obtain FIG.
A pattern 103 as shown in FIG. Here, for example, a C ₂ F ₈ gas is used for etching SiO _{2, and} a Cl gas is used for etching Al.

Next, an insulating film that insulates each wiring of the first wiring pattern 103, that is, the first wiring pattern 103
A first insulating film 104 buried in a space between wirings for insulating the wirings in the pitch direction is formed. First, in FIG. 1D, a film 104A of an insulating material to be the first insulating film 104 is formed on the upper surface of the first wiring pattern 103 by C
The film is formed by VD or the like. As the insulating material, for example, a Si ₃ N ₄ -based film (for example, a P-
(SiN) or the like to completely fill the space between the wirings. Thereafter, in FIG. 1E, the Si ₃ N ₄ -based insulating film 104A is polished by a CMP method, and is polished to about half of the above-described insulating film 102 formed on the first-layer metal film 101 to be flattened. . Thereby, the first wiring pattern 10
The first insulating film 104 buried in the space between the wirings for insulating the wirings in the pitch direction from each other can be formed.

Next, a second insulating film 105 for insulating the upper layer and the lower layer in the thickness direction is formed on the flattened upper surfaces of the first insulating film 104 and the insulating film 102. In this method, a SiO ₂ -based film (such as an HDP film) is formed by CVD so as to completely cover the entire surface (FIG. 1F). FIG. 1 (D) to above
By the step (F), the insulating film between the upper layer and the lower layer is formed into two types of films (Si ₃ N ₄ based film and SiO ₂
System film). That is, the Si ₃ N ₄ based film is a film type having a lower etching rate than the SiO ₂ based film. In this case, assuming that the SiO ₂ -based film corresponds to the film to be etched and the Si ₃ N ₄ -based film corresponds to the mask material, the “etching speed a of the film to be etched” and the “etching speed b of the mask material etc.” The “etching selectivity a / b” defined by the ratio of “SiO ₂ based film etching rate” /
"The etching rate of the Si ₃ N ₄ based film” is obtained. As described above, since the etching rate of the Si ₃ N ₄ based film is lower than that of the SiO ₂ based film, the etching selectivity a / b becomes large.

Next, in order to form an inter-wiring contact 107 for connecting a lower first wiring pattern 103 to an upper wiring pattern 110 described later, first, a planarized interlayer insulating film (second insulating film) is formed. 2) A mask pattern of the contact hole 106 is formed on the 105 by a lithography technique, and the oxide film 105 is removed by etching until reaching the lower wiring layer (the first wiring pattern 103), thereby forming the contact hole 106 (FIG. G)). For example,
Etching is performed under conditions of a pressure of 5.3 Pa or the like using a gas having a ratio of C ₂ F ₈ : Co: Ar = 1: 15: 20.
The composition of this gas is set such that the etching rate for an oxide film is high and the etching rate for a nitride film is low. At this time, even if the surface is flattened by the CMP method, since global steps and variations in film thickness between wafers between lots can be considered, over-etching is performed so that the contact can be properly reached even at the deepest position. (Not shown).

Thereafter, a barrier metal (TiN / Ti) is formed by sputtering (not shown) for the purpose of ensuring adhesion between the contact and the lower wiring layer (first wiring pattern 103) and suppressing an increase in resistance. Tungsten for forming the plug 107 is formed by CVD, and is etched and removed by etching back or polishing by a CMP method while leaving only the plug portion (FIG. 2H). Next, an upper second-layer metal film (eg, Al or Cu) 108 is
Deposited at about 0 nm (Fig. 2 (I)), further, SiO ₂
System insulating film 109 is, for example, 150 nm
A film is formed to a degree (FIG. 2 (J)).

Next, after patterning by lithography, the insulating film 109 and the second layer metal film 108 are removed by etching to form a second wiring pattern 110 (FIG. 2K). Thereafter, a multilayer wiring is formed by repeating the above. FIG. 3 shows the operation of the first insulating film when the position of the contact is shifted from the position of the first wiring pattern in the lower layer in the multilayer wiring structure according to the present embodiment when the margin of the portion to which the contact is connected is eliminated. FIG. In this drawing, MOS transistors, resistors, capacitors, and other structures below the multilayer wiring structure shown in the figure are omitted.

As shown in FIG. 3, the position of the contact 312 penetrating from the second wiring pattern 311 in the upper layer to the first wiring pattern 315 in the lower layer through the second insulating layer 313 is changed to the first wiring pattern in the lower layer. Even when the position is shifted from the position 315, the first insulating film 31 having an etching rate lower than that of the second insulating film
4 acts as a stopper, stops the lower end of the contact 312 at 317, and further lowers the wiring pattern 3
Proceeding to 16 is prevented. Therefore, there is no short circuit between the contact 312 and the lower wiring pattern 316.

In the above description, the first insulating film 1
04, 314 and the second insulating films 105, 313 are Si ₃ N ₄ and SiO _2. However, if the etching rates are different from each other and the etching selectivity is high, the combination can function as an interlayer insulating film. , And other combinations. Also, the first wiring pattern 103,
The materials of the 315 and the second wiring patterns 110 and 311 are not limited to the above-described example.

In the above-described example, the first insulating film is formed of C
A film is formed on the upper surface of the wiring pattern 103 by a film forming process such as VD, a part of the film is buried in the space between the wirings, and a portion remaining on the upper surfaces of the wiring patterns 103 and 315 is formed. , Wiring pattern 10
A structure in which a first insulating film is formed by applying a liquid of an insulating material to the upper surface of 3, and a second insulating film is formed thereon by coating. That is, the wiring pattern 103
A part of the insulating material is buried in the inter-wiring space by applying a liquid of the insulating material to the upper surface of
03, 315, the insulating material slightly remains on the upper surface. Next, a portion of the insulating material remaining on the upper surfaces of the wiring patterns 103 and 315 is polished and removed by a CMP method, so that a space between wirings for insulating the respective wirings of the first wiring patterns 103 and 315 in a pitch direction. The first insulating film embedded in the first insulating film can be formed. And this first
A second insulating film may be formed over the insulating film, and this portion may be perforated by contact hole mask etching to provide the contacts 107 and 312. When the portion of the insulating material remaining on the upper surfaces of the wiring patterns 103 and 315 is removed by polishing by a CMP method,
The removal and flattening of the oxide film formed on the metal film of the wiring patterns 103 and 315 to about half the same as in the above-described embodiment is performed.

[0024]

As described above, in the method of manufacturing a semiconductor device according to the present invention, when a multilayer wiring structure is formed, a first insulating film embedded in a space between wirings for insulating a multilayer wiring in a pitch direction; The second insulating film formed between each layer for insulating the multilayer wiring in the film thickness direction was formed of films having different etching rates from each other. For this reason, the second insulating film functions as a stopper even when the contact for connecting the upper layer wiring and the lower layer wiring is formed in a state where there is no margin with the lower layer wiring. It is possible to prevent the wiring from going below the wiring and prevent a short circuit between the wirings.

[Brief description of the drawings]

FIG. 1 is a process chart showing a manufacturing process of a multilayer wiring structure in a semiconductor substrate according to an embodiment of the present invention.

FIG. 2 is a process chart showing a manufacturing process of a multilayer wiring structure in a semiconductor substrate according to an embodiment of the present invention.

FIG. 3 is a diagram showing a first insulating film in a case where a contact position is shifted from a position of a lower first wiring pattern in a multilayer wiring structure according to an embodiment of the present invention when a margin of a portion to which the contact is connected is eliminated; It is sectional drawing which shows the effect | action of.

FIG. 4 is a plan view showing a specific example of a wiring pattern in which a margin is provided at a connection portion of a contact.

FIG. 5 is a plan view showing a specific example of a wiring pattern in which no margin is provided in a connection portion of a contact.

FIG. 6 is a process diagram showing a manufacturing process of a multilayer wiring structure in a semiconductor substrate according to a conventional example.

FIG. 7 is a process diagram showing a manufacturing process of a multilayer wiring structure in a semiconductor substrate according to a conventional example.

FIG. 8 is a cross-sectional view showing a state in which a position of a contact is shifted from a position of a lower wiring pattern and short-circuited with a lower wiring pattern in a multilayer wiring structure according to a conventional example.

[Explanation of symbols]

103, 313: second insulating film, 104, 314: first insulating film, 105, 315: first wiring pattern, 11
0, 311 ... second wiring pattern, 106 ... contact hole.

Claims (5)

[Claims] 1. A method of manufacturing a semiconductor device having a multi-layer wiring structure using a conductive metal-based film, wherein, when forming the multi-layer wiring structure, the multi-layer wiring is embedded in an inter-wiring space for insulating in a pitch direction. 1. A method for manufacturing a semiconductor device, comprising: forming an insulating film and a second insulating film formed between layers for insulating a multilayer wiring in a film thickness direction from films having different etching rates. 2. When the multilayer wiring structure is formed, the contact connecting the wiring has no or little margin at the connection portion with the lower wiring layer, and the contact between the contact and the lower wiring layer is aligned. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is designed in a state where a margin for deviation is not sufficient. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating film is formed of a film type having a lower etching rate than the second insulating film. 4. The first insulating film is formed by a film forming process from an upper surface of the wiring pattern having the inter-wiring space, a part of the first insulating film is embedded in the inter-wiring space, and remains on the upper surface of the wiring pattern. 2. The method according to claim 1, wherein the semiconductor device is formed by removing a portion. 5. The wiring pattern according to claim 1, wherein a part of the insulating material is embedded in the inter-wiring space by applying a liquid of an insulating material from an upper surface of the wiring pattern having the inter-wiring space. 2. The method according to claim 1, wherein the semiconductor device is formed by removing a portion of the insulating material remaining on the upper surface of the semiconductor device.