JP2000276889A - Non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory in which an arbitrary bit can be rewritten without increasing area. SOLUTION: Control gates CG of a memory transistor MT are commonly connected in each row, potentials supplied to these control gate lines, bit lines, word lines are controlled by a potential control means (30, 40, 60, 100). Thereby, a switch transistor having large area is omitted, rewriting data can be performed with less area and with an arbitrary bit unit or a bite unit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory, and more particularly to an EEPROM which can be rewritten in small units of about one byte to several bytes.

[0002]

2. Description of the Related Art FIG. 10 is a circuit diagram showing an example of a conventional EEPROM cell matrix which can be rewritten in 1-byte units. In the same row, cells of 8 bits (1 byte) from bit 0 to bit 7 are provided as one storage unit, and each cell partially has a thin tunnel oxide film,
It comprises a memory transistor MT having a floating gate FG and a control gate CG, and a select transistor ST having a source connected to the memory transistor MT. The drain of the select transistor is arranged corresponding to each cell arranged in the column direction. Connected to the bit line BL. Also,
The other end (source) of the memory transistor for one byte is commonly connected. The gates of the select transistors belonging to the same row are connected to the word line WL, the control gates of the memory transistors belonging to the same row are commonly connected for each byte, and the control gate switch transistor SWT whose gate is connected to the word line WL. Connected to the drain of The source of this transistor is connected to a program line PL provided in byte units.

The erasing and writing operations in the cell matrix shown in FIG. 10 will be described with reference to FIGS. In the following operation diagrams, regarding the selection transistor and the control gate switch transistor, the transistor encircled by a solid line indicates that the transistor is on, and the transistor marked with x indicates the off state. further,
Of the memory cells, those surrounded by a broken-line circle are cells to be erased or written. It is assumed that all selections are made in block 1.

FIG. 11 is a diagram showing a potential relationship of each part when erasing data in a conventional byte unit. A high voltage (Vpp) of about 20 V for applying a tunnel current is applied to the selected word line WL1 and program line PL1, and the unselected word lines, unselected program lines, all bit lines, and the source of the memory transistor Is a ground potential, that is, 0V.

By applying such a potential, the control gate of the selected byte is supplied with a higher voltage (Vpp) than the program line via the control gate switch transistor.
Is applied, the drain of the memory transistor becomes the ground potential, and the eight cells included in the selected byte are erased. At this time, the control gate of the unselected byte is not erased because it is at the ground potential or floating.

FIG. 12 shows the same conventional example as FIG.
FIG. 3 is a diagram illustrating a potential relationship of each unit when writing is performed in byte units. A high voltage (Vp) is applied to the selected word line WL1 and the bit line connected to the cell for writing.
p) is applied, the unselected word lines, the bit lines connected to the cells where no writing is performed, and all the program lines are set to the ground potential, and the sources of the memory transistors are set to be floating.

By applying such a potential, a high voltage is applied to the drain of the memory transistor of the cell selected and the control gate is at the ground potential.
Writing is performed on the selected cell. At this time, since the bit line connected to the unselected cell is at the ground potential, writing to the unselected cell is not performed.

As described above, in the conventional example shown in FIGS. 11 and 12, since the control gate of the 1-byte memory transistor is connected to the program line via the switch transistor, data is erased and rewritten in 1 byte. Performed in units. In order to increase the unit of erasing and rewriting to several bytes, the control gates of the memory transistors may be connected to the program lines via switch transistors for desired bytes.

In the conventional example described above, in order to realize rewriting every byte or every several bytes, the control gate is divided into every one byte or every few bytes, and the control gate switch transistor is divided into one byte or several bytes. One is always necessary.

[0010]

However, since this control gate switch transistor usually requires an area of about 1 to 2 times that of a 1-bit cell, the cell matrix size is about 10 to 20% of the pure cell area. There is a problem that it increases. In addition, since the cell pattern is divided for each byte, and the control gate switch is inserted between the bytes, a complete repetition pattern is not obtained, and the process conditions change within one byte, and There is also a problem that the characteristics vary greatly.

An object of the present invention is to solve such a problem, and an object of the present invention is to provide a nonvolatile semiconductor memory device which can rewrite an arbitrary bit without increasing an area.

[0012]

According to the nonvolatile semiconductor memory device of the present invention, there is provided a nonvolatile memory transistor having a control gate and a floating gate, and a memory cell comprising a selection transistor having one end connected in series to the nonvolatile memory transistor. A memory cell array arranged in a matrix, a control gate line commonly connecting the control gates of the memory transistors in each row, a word line commonly connecting the gates of the select transistors in each row, and the memory cells in each column And a first potential supply means for selectively applying a desired potential to the bit line, and a first potential supply means for selectively applying a desired potential to the bit line. A second potential supply means, and a third potential supply means for selectively applying a desired potential to the control line. And wherein the door.

The first to third potential supply means apply a program voltage to a selected control gate line, a selected word line and a non-selected bit line, and apply a program voltage near the ground potential to the selected bit line. By applying a potential,
A device that supplies a potential so that data is erased in an arbitrary number of bits equal to or greater than the number of bits, a high voltage is applied to the selected control gate line, and a voltage near the power supply voltage is applied to the selected word line and unselected bit lines. By applying a potential near the ground potential to a selected bit line, a potential is supplied so that data is erased in an arbitrary bit number unit of one bit or more, and a potential is supplied to a selected control gate line. High voltage,
Applying a potential near the high voltage or the power supply voltage to the selected word line, and a potential near the ground voltage to the selected bit line,
By setting the unselected bit lines to a floating state, the potential can be supplied so that data is erased randomly in units of one or more bits.

Further, the first potential supply means includes a program voltage generation means and a column decoder, the second potential supply means includes the program voltage generation means and a row decoder, and the third potential supply means comprises , A program voltage generating means and a control decoder.

By adopting such a configuration, the control gate line can be shared in one row by omitting the switch transistor for the control line, so that a rewriting function in a byte unit or a bit unit is provided. The cell matrix size can be reduced by 10 to 20% as it is. In addition, the continuity (uniformity) of the cell pattern is increased, the process conditions are stabilized, and variations in cell characteristics are reduced.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a nonvolatile semiconductor memory device according to the present invention.

The input address data is held in the address register 20, and the row decoder 30 and the column decoder 4
0, which is decoded by the control decoder 60 and supplied to the cell array 10 characteristic of the present invention. That is, the row selection signal output from the row decoder 30 is applied to the word line of the cell array 10, the control line selection signal output from the control decoder 60 is applied to the control gate line of the cell array 10,
The column selection signal output from the column decoder 40 is applied to a Y selection circuit 5
0 is supplied to the bit line of the cell array 10 via 0. The bit line is also supplied to the cell array 10 via the Y selection circuit 50 because the bit line is also a read line for storage data as well as cell selection.

As for data input / output, data input from the input / output buffer 90 is transmitted to the data input register 70.
Then, the data is supplied to the cell array 10 via the Y selection circuit 50, and the data output from the cell array 10 is output to the outside via the Y selection circuit 50, the sense amplifier 80, and the input / output buffer 90.

In a nonvolatile semiconductor memory, it is necessary to supply a high program voltage of about 20 V to bit lines and the like for erasing and writing data. For this purpose, a program voltage generating circuit 100 is provided. The signals are supplied to the row decoder 30, the column decoder 40, and the control decoder 50, respectively.

FIG. 2 is a circuit diagram showing a part of the configuration of the cell array 10 in FIG. 1. Here, a matrix portion (blocks 1 to 4) of 2 rows and 2 columns is shown. Unlike the conventional case of FIG. 10, there is no control gate switch transistor, and the control gates of the memory transistors in each row are commonly connected to a control gate line. For example, focusing on the blocks 1 and 2, the control gates of the memory transistors MT10 to MT17 of the block 1 and the memory transistors MT20 to MT27 of the block 2 are commonly connected and connected to the control gate line CG1.

The operation of the cell array having such a configuration will be described. In the following drawings, the meanings of solid circles, broken circles, and crosses attached to transistors are the same as those of the conventional example in FIGS.

(1) Erasing Operation 1 FIG. 3 is a diagram showing the potential relationship of each part in the first example of the erasing operation in byte units in the block 1 of FIG.

The selected word line WL1, the selected control gate line CG1, and the unselected bit lines BL20 to BL20
A high voltage (Vpp) of about 20 V is applied to L27, and the unselected word line WL2, the unselected control gate line CG2, and the selected bit lines BL10 to BL17 are set to the ground potential. The sources of the memory transistors commonly connected for each byte are floating.

FIG. 4 shows a state in which an unselected bit line and a selected control gate rise simultaneously and reach the same Vpp.

By giving such a potential relation, the potential of each part of the selected block (byte) becomes the same as that of the conventional example, cells in the same block are erased, and cells of unselected bytes in other blocks are erased. Is not erased.

For example, in FIG. 4, the control gate of the cell of the non-selected byte indicated by "block 2" is high voltage (Vp
p), a high voltage is also applied to the bit lines BL20 to BL27, and a high voltage is also transmitted to the drain of the memory transistor in the same byte, so that the potential difference between the drain and the control gate is almost eliminated, and erasure is not performed. Not done.
In the “block 4”, although a high voltage is applied to the bit line, the word line is at the ground potential, so that the drain of the memory transistor is floating and neither erasing nor writing is performed. Further, in the non-selected byte described as “block 3”, neither the bit line nor the control gate line is at the ground potential, so that neither erase nor write is performed.

As described above, in the first embodiment, erasing in units of bytes is realized by setting the non-selected bit lines to a high voltage (Vpp) during erasing. Also, erasing in 1-bit units is possible by the same method.

In the case of this embodiment, it is necessary that the unselected bit lines and the selected control gate rise completely at the same time as shown in FIG. Meanwhile, there is a problem that unselected cells are erased or written.

FIG. 5 shows the potential relationship of each part when writing is performed in byte units in the first embodiment of the present invention. A high voltage (Vpp) is applied to a selected word line and a bit line connected to a cell to be written, for example, BL10 and BL17, and an unselected word line, a bit line connected to a cell not to be written, and All control gate lines are set to the ground potential, and the sources of the memory transistors of the cells are set to be floating. At this time, the voltage applied to each cell is exactly the same as in the conventional example shown in FIG. 12, and the write operation is performed on the selected cell by the same operation as the conventional example. This writing operation can be combined with the following erasing operations.

(2) Erasing Operation 2 FIG. 6 is a diagram showing the potential relationship of each part when performing erasing in byte units in the second erasing operation example of the nonvolatile semiconductor memory according to the present invention.

In this example, the selected control gate line CG
1 is applied with a high voltage (Vpp) of about 20 V to select a selected word line WL1 and unselected bit lines BL20 to BL20.
L27 to the power supply potential (Vcc) and the selected bit line B
L10 to BL17, the unselected word line WL2 and the unselected control gate line CG2 are set to the ground potential. The source of the cell is floating.

With such a potential relationship, the potential of the selected byte is the same as the conventional example except that the word line potential is the power supply potential. Even if the word line potential is the power supply potential, the selection transistor of the cell is turned on, so that the voltage applied to the memory transistor of the cell is exactly the same as in the conventional example, and the cell in the same byte is erased.

Next, the operation of an unselected byte indicated as "block 2" in FIG. 6 will be described with reference to FIG.

The upper half of FIG. 7 shows a state in which the potential shown in FIG. 6 is applied. That is, when the power supply potential Vcc is applied to the unselected bit line and the selected word line, the voltage at the intermediate node between the selection transistor and the memory transistor does not rise to the power supply potential. Become. When the program voltage Vpp is supplied to the selection control gate line at a certain time,
Accordingly, the intermediate node potential rises, but becomes a value (Vpp-α) slightly lower than the program voltage.

When the power supply potential is a sufficiently high voltage such as 5 V, there is no problem even if the voltage drops by Vth of about 1 V, for example. Has also appeared in the case of 1.8 V, and the decrease by the threshold voltage Vth of the selection transistor cannot be ignored.
In some cases, stable erasing and writing cannot be achieved.

The lower half of FIG. 7 shows an operation in a case where such a problem is improved. For example, a precharge potential Vprch which is a power supply potential Vcc is applied to an unselected bit line.
And the threshold voltage Vth of the selection transistor is higher than the precharge potential Vprch on the selected word line.
A voltage higher by the amount, that is, a potential of (Vprch + Vth) is applied. Thus, the intermediate node between the selection transistor and the memory transistor, which is on the drain side of the memory transistor, reliably rises to the precharge potential Vprch. The potential of the selected word line is then reduced by the threshold voltage Vth of the selected transistor, so that the potential becomes Vp.
rch (Vcc).

Thereafter, when the program voltage Vpp is supplied to the selection control gate line, the memory transistor is turned on,
Due to the coupling capacitance between the control gate and the memory transistor channel region via the floating gate, the potential of the channel region increases. Since the channel region and the memory transistor drain have the same potential, the potential of the memory transistor drain, which is an intermediate node between the selection transistor and the memory transistor, also increases at the same time. When the potential of the intermediate node slightly rises above the precharge potential Vprch, the selection transistor is completely turned off. Since the source of the cell is floating, the drain, channel, and source of the memory transistor are all floating at this time, and thereafter, the potential of these regions also rises with the rise of the control gate potential. Therefore, finally, the control gate is driven to a high voltage (V
pp), the potential of the intermediate node is a value lower by a slight potential α than this, the potential difference is small, and the erasing operation is not performed.

In this example, the threshold voltage V of the selection transistor
Regardless of the value of th, the potential of the selected word line is maintained at the precharge potential Vprch, and is not affected by the threshold voltage Vth of the selection transistor even when the power supply voltage is low.

In the non-selected bytes described as "block 3" and "block 4," neither the erasing nor the writing is performed because the selection transistor of the cell is off and the control gate line is at the ground potential.

As described above, in this operation example, at the time of erasing, the potential of the selected word line and the unselected bit line is set to the power supply potential, the potential of the channel and drain region of the unselected cell is raised by capacitive coupling with the control gate, and Achieve unit erasure. Further, erasing in 1-bit units is possible by the same method.

In the first operation example, both the drain and the control gate of the non-selected cell are set to a high potential so that unnecessary erasing and writing do not occur, so that the erasing operation does not occur. In the operation example, if the drain is first set to the power supply potential and then a high voltage is applied to the control gate, the unselected cells are not erased by mistake.

(3) Erase Operation 3 FIG. 8 shows a second example of the nonvolatile semiconductor memory device according to the present invention.
FIG. 13 is a diagram showing a potential relationship of each unit when erasing in byte units in the erasing operation example of FIG.

A high voltage (Vpp) of about 20 V is applied to the selected control gate line CG1, and the selected word line W
L1 is set to a power supply potential (Vcc) or a high voltage, unselected bit lines BL20 to BL27 are floated, selected bit lines BL10 to BL17, unselected word line W
L2 and the unselected control gate line CG2 are set to the ground potential. The source of the cell is floating. With such a potential relationship, the potential of the selected byte is the same as that of the conventional example, and the cells in the byte are erased.

The bit lines BL20 to BL27 of the unselected bytes described as "block 2" are temporarily raised to the power supply potential as shown in FIG. Therefore, as in the second operation example, the drain, channel, and source of the cell in the same byte are all in a floating state, and the potential of these regions also rises with the rise of the control gate potential. Therefore, even if the control gate eventually becomes a high voltage (Vpp), the potential difference between the control gate and the drain of the memory transistor is small, and the erase operation is not performed.

In the unselected bytes described as "block 3" and "block 4," neither the erasing nor the writing is performed because the selection transistor of the cell is off and the control gate line is at the ground potential.

As described above, in this operation example, the non-selected bit line is floated at the time of erasing, and the potential of the channel and drain region of the non-selected cell is increased by capacitive coupling with the control gate to realize erasing in byte units. In this case, it is not necessary to strictly set the timing of applying a high voltage to the control gate. Further, erasing in 1-bit units is possible by the same method as described above.

[0047]

As described above, according to the nonvolatile semiconductor memory of the present invention, the control gates of the memory transistors in each row are commonly connected, and the potential supplied to this line, bit line and word line is controlled. Thus, a switch transistor having a large area can be omitted, and data can be rewritten in an arbitrary bit or byte unit with a small area.

Further, since the uniformity of the cell pattern is improved, variations in cell characteristics can be suppressed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a nonvolatile semiconductor memory according to the present invention.

FIG. 2 is a circuit diagram showing a configuration of a part of a cell array in FIG.

FIG. 3 is a diagram showing a first operation example of the nonvolatile semiconductor memory according to the present invention and showing a potential relationship at the time of byte erasing;

FIG. 4 is an explanatory diagram showing a change in potential in FIG.

FIG. 5 is a diagram showing a potential relationship at the time of byte writing in the nonvolatile semiconductor memory according to the present invention.

FIG. 6 is a diagram showing a potential relationship, showing a second operation example of byte erasing of the nonvolatile semiconductor memory according to the present invention.

FIG. 7 is an explanatory diagram showing a change in potential in FIG. 6;

FIG. 8 is a diagram illustrating a potential relationship, showing a third operation example of byte erasure of the nonvolatile semiconductor memory according to the present invention.

FIG. 9 is an explanatory diagram showing a change in potential in FIG.

FIG. 10 is a circuit diagram showing a cell matrix of a conventional byte rewrite type EEPROM.

FIG. 11 is a diagram showing a potential relationship at the time of byte erasing of a conventional EEPROM.

FIG. 12 is a diagram showing a potential relationship at the time of byte writing in a conventional EEPROM.

[Explanation of symbols]

 Reference Signs List 10 cell array 20 address register 30 row decoder 40 column decoder 50 Y selection circuit 60 control decoder 70 data input register 80 sense amplifier 90 input / output buffer 100 program voltage generation circuit

Claims (7)

[Claims] 1. A memory cell array in which memory cells each comprising a nonvolatile memory transistor having a control gate and a floating gate and a select transistor having one end connected in series thereto are arranged in a matrix, A control gate line for commonly connecting the control gates; a word line for commonly connecting the gates of the select transistors in each row; and a bit provided for the memory cells in each column and connected to the other end of the select transistor. A first potential supply means for selectively applying a desired potential to the bit line; a second potential supply means for selectively applying a desired potential to the word line; and a desired potential selectively to the control line. A non-volatile semiconductor memory comprising: 2. The nonvolatile semiconductor memory according to claim 1, wherein the sources of the nonvolatile memory transistors in each row of the memory cell array are commonly connected in units of eight. 3. The first to third potential supply means applies a program voltage to a selected control gate line, a selected word line and an unselected bit line, and supplies a ground potential to a selected bit line. By giving a nearby potential,
2. The nonvolatile semiconductor memory according to claim 1, wherein a potential is supplied such that data is erased in an arbitrary number of bits of 1 bit or more. 4. The first to third potential supply means selects a high voltage on a selected control gate line and a potential near a power supply voltage on a selected word line and an unselected bit line. 2. The nonvolatile memory according to claim 1, wherein a potential near ground potential is applied to the bit line to supply the potential so that data is erased in an arbitrary number of bits of one bit or more. Semiconductor memory. 5. The nonvolatile semiconductor memory according to claim 4, wherein the potential applied to the selected word line is a potential higher by a threshold voltage of a selection transistor. 6. The first to third potential supply means: applying a high voltage to a selected control gate line, a high voltage or a potential near a power supply voltage to a selected word line, and a selected bit line to a selected bit line. By applying a potential near the ground voltage and floating the unselected bit lines, the potential is supplied such that data is erased randomly in arbitrary units of one or more bits. The nonvolatile semiconductor memory according to claim 1, wherein 7. The first potential supply means includes a program voltage generation means and a column decoder, the second potential supply means includes the program voltage generation means and a row decoder, and the third potential supply means comprises 7. The nonvolatile semiconductor memory according to claim 1, further comprising: the program voltage generating means and a control decoder.