JP2000260190A - Non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory of dual work which has interchangeability of arrangement of pins between a normal storage device and it, and requires no external decoder circuit. SOLUTION: When a normal flash memory is constituted using one chip of a non-volatile semiconductor memory, an input buffer 13 and an address signal A19 processing logic circuit 14 are set to a disable-state. An internal control signal/CEgenerating circuit 16 inputs externally only a control signal /CE from a pin/ce through an input buffer 12, responding to only this control signal/CE, and sets one chip to an operable state. When a flash memory of dual work is constituted using two chips of the memory device, the input buffer 13 and an address signal A19 processing logic circuit 14 are set to a enable-state. The internal control signal/CE generating circuit 16 selects either of two chips responding to 'H' and 'L' of an address signal A19 through the input buffer 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device used for a computer or a portable information device, and more particularly to a nonvolatile semiconductor storage device capable of writing and erasing data and having two or more chips in one package. Related to the device.

[0002]

2. Description of the Related Art A conventional nonvolatile semiconductor memory device is an EPROM (Erasable Programmable Read-Only).
Memory). In this EPROM, data can be written on the user side, and when erasing data, all data stored in the entire memory array is erased collectively by irradiating ultraviolet rays.

Although this EPROM is suitable for increasing the capacity because of the small area of the memory cell, it has been necessary to provide a window through which ultraviolet rays pass in order to erase data by irradiating the ultraviolet rays. Further, since data is written by a writing device called a writer, it is necessary to remove the EPROM from the substrate every time data is erased or rewritten.

On the other hand, an EEPROM (Electrically Eras)
In the programmable programmable read-only memory, although data can be electrically erased and rewritten, the area of the memory cell is 1.5 to 2 times larger than that of the EPROM. Cost is also high.

For this reason, recently, a so-called flash memory (or flash EEPROM) has been developed as an intermediate nonvolatile semiconductor memory device between the two. In this flash memory, the area of a memory cell is substantially equal to that of an EPROM, which is suitable for increasing the capacity. In addition to batch erasure of data in the entire memory cell array, any area (referred to as a sector or a block) can be used. The data in the memory cells in the memory cell can be electrically erased.

Conventional flash memories include those disclosed in, for example, US Pat. No. 5,249,158 and US Pat. No. 5,245,570. As shown in FIG. 7, a memory cell 70 of this type of flash memory is a floating gate type field effect transistor, stores one bit of data with one element, and enables high integration of a memory array.

Writing of data to the memory cell 70 is performed as follows.
For example, a voltage of 12 V is applied to the control gate electrode 71, a voltage of 7 V is applied to the drain 74, a voltage of 0 V is applied to the source 73, and hot electrons generated near the drain junction are injected into the floating gate electrode 72. This writing increases the threshold voltage of the control gate electrode 71.

For reading data from the memory cell 70, for example, a voltage of 0 V is applied to the source 73, a voltage of 1 V is applied to the drain 74, a voltage of 5 V is applied to the control gate electrode 71, and the magnitude of the channel current flowing at this time (data Is shown). The reason why the drain voltage is set to a low voltage is to prevent parasitic weak writing.

Further, the voltage applied to the control gate electrode 71 is changed, the voltage of the drain 74 is changed, the voltage of the drain 74 is used as a pulse signal, and the pulse width is changed. If the threshold voltage is adjusted and the threshold voltage is changed in the state of 2 n at intervals of several hundred mV, multi-valued data can be stored in the memory cell 70.

When reading multi-valued data, for example, a voltage of 0 V is applied to the source 73 and a voltage of 1 V is applied to the drain 74.
And detecting the voltage of the control gate electrode 71 when the channel current flows.

To erase data from the memory cell 70, for example, the control gate electrode 71 is grounded, and the source 73 is connected to 12V.
, A high electric field is generated between the floating gate electrode 72 and the source 73, and electrons accumulated in the floating gate electrode 72 are drawn out to the source 73 side by utilizing a tunnel phenomenon through a thin gate oxide film. This is done by:
This writing lowers the threshold voltage of the control gate electrode 71.

Such data erasure is performed in units of blocks (for example, 16 Kbytes or 64 Kbytes) including a plurality of memory cells 70.
K bytes). Further, since all the memory cells in the block are collectively erased, the voltage of the control gate electrode 71 of each memory cell after erasing is changed according to the threshold voltage of the control gate electrode 71 of each memory cell before erasing. If the threshold voltage becomes negative due to excessive erasure, a fatal defect occurs (correct data cannot be read at the time of reading).

In the memory cell 70, since writing is performed on the drain 74 side and erasing is performed on the source 73 side, it is desirable to individually optimize the profile of the drain junction and the profile of the source junction. The source 73 has an asymmetric structure. At the drain junction, an electric field concentration type profile is applied to increase the writing efficiency, and at the source junction, an electric field relaxation type profile is applied to enable application of a high voltage.

When erasing data, a high voltage is applied to the source 73. Therefore, it is necessary to increase the withstand voltage of the source junction, and it is difficult to miniaturize the source electrode. Source 7
There is a problem that hot holes are generated in the vicinity of 3 and some of them are trapped in the tunnel insulating film, thereby lowering the reliability of the cell.

Therefore, as an erasing method, for example, a negative voltage of −10 V is applied to the control gate electrode 71 so that the source 7
There is a method in which a voltage of 5 V is applied to 3 and data is erased by a tunnel current. In this method, since the voltage applied to the source 73 is low, the withstand voltage of the source junction can be reduced, and the gate length of the memory cell can be shortened. Furthermore, the size of the block to be erased is reduced, and erasing in sector units becomes possible.

In the erasing method in which a high voltage is applied to the source 73, an inter-band tunnel current flows and the current value becomes several mA in the entire memory array. Therefore, a high voltage is formed by a booster circuit in the storage device. And it is necessary to supply a high voltage from the outside. On the other hand, in the erasing method using a negative voltage, the voltage of the source 73 can be supplied by the power supply voltage, so that the unification of the power supply can be relatively easily realized.

Further, in the writing method using hot electrons, 1 mA per memory cell is used at the time of writing.
About current flows. For this reason, there is a writing method in which writing is performed using an FN tunnel current to reduce the amount of current per memory cell.

On the other hand, with the miniaturization of the semiconductor process and the spread of battery-operated portable devices, it is desired to reduce the operating voltage. The operating voltage is 5V, 3V, 2.7V. In addition, the operating voltage gradually decreases.

In a flash memory operating at a power supply voltage of 3 V or 2.7 V, the power supply voltage is applied to the control gate electrode as it is, or a voltage obtained by increasing the power supply voltage in order to increase the operation speed and expand the operation margin. 5V
Is applied to the control gate electrode.

Further, in a nonvolatile semiconductor memory device, many operation states such as writing, block erasing, batch erasing of the entire memory array, and reading of a state register are compared with a RAM which can perform writing and reading in a short time. Therefore, these operation states must be selectively executed. Therefore, the control signal (/ C
E, / WE) are also increasing, and with further diversification of operating states, even if existing control signals are combined, the types of control signals are insufficient, and new control signals need to be added, and storage The usability of the device has deteriorated.

Therefore, as disclosed in, for example, US Pat. No. 5,053,990, the types of control signals are not increased, and various operations are selectively performed by giving commands to the storage device instead of the control signals. The command method is now mainstream. In this command method, a command is input to a command recognition machine called a command state machine (CSM), and a write state machine (WSM) is input.
SM) performs an operation corresponding to the command.

For example, in the case of a block erase command as shown in FIG. 8, data 20H (H indicates a hexadecimal number) is input in the first cycle in which the control signals / CE and / WE both become "L". Subsequently, in the second cycle in which the control signals / CE and / WE both become "L", the data DOH and the address of the block to be erased are input. In the case of an erase suspend command, the data BOH is input in the first cycle in which both the control signals / CE and / WE are at "L".
In the first cycle when both CE and / WE are set to "L", data DOH
Enter Further, in the case of a write command, the data is transmitted in the first cycle in which the control signals / CE and / WE both become "L".
Input 40H (H indicates hexadecimal number) and continue to input control signal
Input the data to be written and the address of the memory cell in the second cycle in which both / CE and / WE become "L".

Such a command type storage device is disclosed in US Pat. No. 5,249,158, as well as one in which the size of each block to be erased is equalized as disclosed in US Pat. In some cases, the size of each block to be erased is made uneven as shown in FIG.

Alternatively, a memory device that performs both writing and erasing by using the FN tunnel current, or a memory
There is also a storage device called NAND type in which 16 or 16 units are connected in series. The NAND type has a lower read speed than the NOR type, but can have a smaller memory cell.

As described above, in addition to storing binary values (one bit) in one memory cell, four values (two bits), eight values (three bits), and sixteen values (four bits) can be used. ) Is attempted.

Further, in a nonvolatile semiconductor memory device, although a read operation is not changed to about 100 nanoseconds as compared with a general SRAM, DRAM or the like which performs writing and reading in about 100 nanoseconds, the write operation is performed in about 100 nanoseconds. This is as slow as 20 microseconds, and the erasing operation is even slower as several hundred milliseconds. Therefore, once the erase operation starts,
It is necessary to wait until the erasing operation is completed or to issue a command for temporarily suspending the erasing operation, and to perform the reading operation after the erasing operation is interrupted for several hundred microseconds by this command.

By the way, in a nonvolatile semiconductor memory device,
Some packages have a built-in two-chip storage device in one package. In this type of nonvolatile semiconductor memory device, two control signals / C are used to select one of the two chips.
When E is input and the write and erase operations of one chip are performed in response to the control signal / CE, the read operation, write and erase operation of the other chip are performed.

Further, JP-A-6-180999, JP-A-7-25
The nonvolatile semiconductor memory devices described in Japanese Patent No. 4292 and Japanese Patent Application Laid-Open No. 9-198880 include a one-chip storage device in one package, and the one-chip storage device has a first address space and a second address space. In some cases, the read operation of the second address space is performed while the write / read operation of the first address space is performed. Such an operation 1
Called chip dual work.

[0029]

However, in the above-mentioned conventional nonvolatile semiconductor memory device in which a two-chip storage device is incorporated in one package, two input pins for inputting two control signals / CE are required. And a decoder circuit for selecting one of the two control signals / CE is externally required. Similarly, when three or more storage devices are incorporated in one package, the same number of control signals / CE and input pins as the number of chips are required, and a decoder circuit for selecting one of the control signals / CE is required. Need externally. The external decoder circuit is disadvantageous for high-speed operation because the load and the delay time of the external decoder circuit are large as compared with the case where the decoder circuit is built in the nonvolatile semiconductor memory device. In addition, the number of input pins for inputting a control signal / CE is increased as compared with a normal nonvolatile semiconductor memory device in which a single chip storage device is incorporated in one package and only one control signal / CE is input. Therefore, the pin arrangement is not compatible with the normal nonvolatile semiconductor memory device.

For example, as shown in FIG.
In a 16-megabit dual-work nonvolatile semiconductor memory device having two built-in megabit flash memories, the address pins a0 to a18 for inputting the addresses A0 to A18 are the same as those of the 8-megabit flash memory. And the control signal / CE (instead of / CE, / B
There are two pins / ce for inputting E), which is different from 8-megabit flash memory.

As shown in FIG. 10, control signal / CE is transmitted to an internal circuit via input buffer 81. The input buffer 81 is reset by a reset signal R.

On the other hand, in a nonvolatile semiconductor memory device in which the conventional one-chip memory device is divided into a first address space and a second address space, the memory array area is determined by the layout in the chip, so that the memory capacity is arbitrary. It is difficult to divide the memory device into two, and it is difficult to realize a circuit configuration for simultaneously writing and erasing a two-chip storage device. Further, since the structure is completely different from that of a general-purpose chip, a period and personnel for developing a one-chip dual work are required.

In view of the above, the present invention has been made in view of the above-mentioned conventional problems, and has a dual-working structure which has compatibility in pin arrangement with a normal nonvolatile semiconductor memory device and does not require an external decoder circuit. It is an object of the present invention to provide a nonvolatile semiconductor memory device.

[0034]

As described above, the nonvolatile semiconductor memory device according to the present invention comprises: first address buffer means for inputting an address signal designating an address space corresponding to a storage capacity; Second address buffer means for designating the address space of the second address buffer, and control means for disabling the second address buffer means.

According to the present invention, if the address space specified by the first address buffer means is the first address space, the second address space can be specified by the second address buffer means. Therefore, a second address space can be added. When the second address space is not used, the control means sets the second address buffer means to disable. Thus, for example, the first address space of the one-chip storage device can be used alone, or the first and second address spaces of the two-chip storage device can be used. When a one-chip storage device is used, it is only necessary to disable the second address buffer means, so that compatibility with a normal storage device can be maintained.

In the nonvolatile semiconductor memory device according to the present invention, the first address buffer means for inputting an address signal designating an address space corresponding to the storage capacity, and the second address designating an address space larger than the storage capacity are provided. A buffer unit; and a selection unit for selecting a memory area based on an address space designated by the second address buffer unit and a control signal from the outside.

According to the present invention, the memory area can be selected based on the address space designated by the second address buffer means and an external control signal. For example, the address designated by the first address buffer means can be selected. An address area corresponding to the space can be selected and used, or an address area corresponding to the second address space specified by the second address buffer means can be selected and used.

Further, the nonvolatile semiconductor memory device of the present invention comprises a plurality of rewritable nonvolatile semiconductor memory devices and an address signal for designating an address space corresponding to the storage capacity of one nonvolatile semiconductor memory device. , A second address buffer for specifying an address space larger than the storage capacity, and the nonvolatile semiconductor memory devices based on the address space specified by the second address buffer. And selecting means for selecting any of the above.

Further, the nonvolatile semiconductor memory device of the present invention comprises a plurality of nonvolatile semiconductor memory devices capable of rewriting data and having mutually different storage capacities, and a memory capacity of one nonvolatile semiconductor memory device. First address buffer means for inputting an address signal for specifying an address space, and second address buffer means for specifying an address space larger than the storage capacity.
Address buffer means; and selecting means for selecting one of the nonvolatile semiconductor memory devices based on an address space designated by the second address buffer means and an external control signal.

According to the present invention, one of the nonvolatile semiconductor memory devices can be selected on the basis of the address space designated by the second address buffer means and an external control signal. Selecting and using a nonvolatile semiconductor memory device corresponding to the address space specified by the buffer means, or selecting and using a nonvolatile semiconductor memory device corresponding to the second address space specified by the second address buffer means; Can be. Therefore, it is possible to realize both the function of the normal nonvolatile semiconductor memory device and the function of the dual-work nonvolatile semiconductor memory device, and to shorten the development period as compared with realizing both functions individually. Development costs can be reduced.

In one embodiment, the plurality of data rewritable nonvolatile semiconductor memory devices are each a chip, and each chip is housed in one package.
The plurality of data rewritable nonvolatile semiconductor memory devices have independent address spaces that do not overlap with each other.

In this case, a control signal for identifying the address space of each nonvolatile semiconductor memory device is not required, and a decoding circuit for decoding the control signal is not required. For this reason, the package of the normal memory can be shared with the package of the above embodiment, and the burden on the user side is small. Furthermore, since the configuration of each chip is common, the productivity is excellent, the management is easy, and the cost can be reduced.

[0043]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram partially showing an embodiment of the nonvolatile semiconductor memory device of the present invention. The nonvolatile semiconductor memory device of the present embodiment is an 8-megabit flash memory (one-chip memory device),
As with the megabit memory, one pin / ce and each address pin a0-a18 are provided, as well as the address pin a1.
9. Each input buffer 12, 13, an address signal A19 processing logic circuit 14, a control circuit 15, an internal control signal / CE generation circuit 16, and the like are further added.

When receiving the reset signal R 1, the input buffer 12 applies an output corresponding to the reset signal R 1 to the internal control signal / CE generation circuit 16. In response to this, the internal control signal / CE generation circuit 16 outputs an internal control signal to the internal circuit to completely reset the one chip (low power operation state or chip non-selection state).

The input buffer 13 and the address signal A19 processing logic circuit 14 control signals CAM1 and CAM1 from the control circuit 15,
In response to CAM2, it is switched to enable or disable.

The nonvolatile semiconductor memory device of this embodiment is
When a normal flash memory is configured using a chip, the input buffer 13 and the address signal A19 processing logic circuit 14 are set to a disabled state. The internal control signal / CE generating circuit 16 inputs only the control signal / CE from the outside from the pin / ce via the input buffer 12, and makes the one chip operable in response to only the control signal / CE. Set.

The nonvolatile semiconductor memory device of the present embodiment
When a dual-working flash memory is configured using a chip, the input buffer 13 and the address signal A19 are used.
The processing logic circuit 14 is set to the enable state. The internal control signal / CE generation circuit 16 outputs “H” and “L” of the address signal A19 from the pin a19 via the input buffer 13.
To select one of the two chips.

FIG. 2 is a logic circuit diagram showing one example of the input buffer 12. The input buffer 12 receives the reset signal R1. When the reset signal R1 is “H”,
The input buffer 12 is enabled, and transmits the control signal / CE from the pin / ce to the internal control signal / CE generation circuit 16. When the reset signal R1 is "L", the input buffer 12 is disabled (in a non-selected state), and outputs a signal of "H" to the internal control signal / CE generation circuit 16. Therefore, the internal control signal / CE generation circuit 16
When an “H” signal is input from the input buffer 12, the 1
The chip is set to the reset state, and the "L" control signal / CE
Is input, the one chip is set in an operable state.

FIG. 3 shows an address signal A19 processing logic circuit 1.
4 is a logic circuit diagram showing an example of an internal control signal / CE generation circuit 16; FIG. The address signal A19 processing logic circuit 14 is X
The internal control signal / CE generation circuit 16 includes an OR circuit 21 and a NOR circuit 22. The NOR circuit 22 receives the control signal CAM1 from the control circuit 15. When the control signal CAM1 is "H", the address signal A1
Since the output of the NOR circuit 22 becomes "L" irrespective of "H" and "L" of the line 9, the OR circuit 23 is enabled, and from the pin / ce to the internal circuit via the internal control signal / CE generation circuit 16 And the control signal / CE are transmitted. That is, when the control signal CAM1 is "H", the address signal A19 processing logic circuit 14 is disabled, and the control signal / CE is transmitted to the internal circuit via the internal control signal / CE generation circuit 16. At this time, since the pin a19 of the address signal A19 does not perform its function, the operation and non-operation of the internal circuit are set only by the control signal / CE from the pin / ce, and the same control as that of a normal flash memory is performed. .

When the control signal CAM1 is "L",
The output of the XOR circuit 21 is applied to the OR circuit 23 via the NOR circuit 22. The XOR circuit 21 includes the control circuit 15
Control signal CAM2 from the input buffer 13 and the input buffer 13 from the pin a19.
, An address signal A19 is input. Control circuit 15
When the control signal CAM2 is set to "H", the address signal A19 becomes "L" and the XOR circuit 2
1 becomes "H", the output of the NOR circuit 22 becomes "L", the OR circuit 23 is enabled,
The control signal / CE is transmitted from / ce to the internal circuit via the internal control signal / CE generation circuit 16. When the control signal CAM2 is set to "L" by the control circuit 15, when the address signal A19 becomes "H", the XOR circuit 2
1 becomes "H", the output of the NOR circuit 22 becomes "L", the OR circuit 23 is enabled,
The control signal / CE is transmitted from / ce to the internal circuit via the internal control signal / CE generation circuit 16. That is, the control signal CAM
When 1 is "L", the control signal CAM2 becomes "H" and the address signal A19 becomes "L" or the control signal CAM2 becomes "L".
When 2 goes "L" and the address signal A19 goes "H", the operation and non-operation of the internal circuit can be set by the control signal / CE. Therefore, if "H" and "L" of the control signal CAM2 are made to correspond to two address spaces, by setting the address signal A19 to either "H" or "L", any one of the address spaces can be set. Can be selected, and the selected address space can be set to an operation state and a non-operation state in response to the control signal / CE. In addition, since the addition detection circuit (ATD) for detecting the address signal A19 is not required, the circuit scale hardly increases due to the addition of the pin a19 of the address signal A19.

FIG. 4 is a circuit diagram showing an example of the control circuit 15. The control circuit 15 includes a pair of P-type transistors 35, a pair of N-type transistors 36, a pair of nonvolatile memory cells 37, a CAM program circuit 38, and a knot circuit 39. The CAM program circuit 38 sets one of the threshold voltages of each of the nonvolatile memory cells 37 to be high and sets the other to be low.
2) is set to “H” or “L”. Such a circuit configuration is provided for each of the control signals CAM1 and CAM2. Also,
In the circuit configuration, each nonvolatile memory cell 37 can be replaced with a fuse.

FIG. 5 shows the pin arrangement of the package 41 when the nonvolatile semiconductor memory device of this embodiment is used as a normal 8 Mbit (512 K × 16 bits) flash memory (one-chip storage device). I have. When used as a normal memory, the memory array is not divided into two address spaces, so that the pin a19 of the address signal A19 is not required. Therefore, the pin a19 of the address signal A19 is not provided on the package 41. And package 4
1, the control signal CAM1 of “H” is sent from the control circuit 15 shown in FIG.
In addition to the OR circuit 22, the function of the pin a19 of the address signal A19 is disabled, and the pin a19 is connected to a predetermined potential ("H" or "L") by wire bonding. The pin arrangement of this package 41 is completely the same as that of a conventional flash memory and has compatibility.

FIG. 6 shows a package 42 of a dual-work 16-megabit flash memory in which the nonvolatile semiconductor memory device of the present embodiment is sealed in two chips. The package 42 of FIG. 5 having one pin / ce and each address pin a0 to a18
1 in that an address pin a19 is further provided. In the package 42, the control signal CAM1 of "L" is supplied from the control circuit 15 shown in FIG.
The pin a19 of the address signal A19 is used in addition to the NOR circuit 22 of the processing logic circuit 14. By making the "H" and "L" of the control signal CAM2 correspond to the address spaces of the two chips, and setting the address signal A19 to either "H" or "L", any one of the address spaces of the respective chips can be used. And sets the address space of the selected chip to the active state and the inactive state in response to the control signal / CE.

Next, two flash memories having different memory capacities are sealed in one package. First, for example, in a 2-megabit (128K × 16) flash memory to which the present invention is applied, existing address signals A0
Address pins in addition to the address pins a0 to a16
The address pin a17 of A17 is newly added. In a 4-megabit (256K × 16) flash memory to which the present invention is applied, existing address signals A0 to A17 are used.
In addition to the address pins a0 to a17, an address pin a18 for the address signal A18 is newly added. Further, in the 8-megabit (512K × 16) flash memory according to the above embodiment, an address pin a19 of the address signal A19 is newly added to the existing address pins a0 to a18 of the existing address signals A0 to A18. . In the 16-megabit (1024K × 16) flash memory to which the present invention is applied, in addition to the existing address pins a0 to a19 of the existing address signals A0 to A19, an address pin a20 of the address signal A20 is newly added. Add.

Here, for example, a 4-megabit flash memory to which the present invention is applied and a 16-megabit flash memory to which the present invention is applied are combined. In this case, a new address signal in a 4 megabit chip
The address pin a20 of A18 and the address pin a20 of the new address signal A20 in the 16-megabit chip are used in common as the address pin a20. The control signal CAM2 shown in FIG.
"H" and "L" correspond to the address spaces of the two chips, and the address signal A20 is set to either "H" or "L" to select one of the address spaces of the respective chips. , In response to the control signal / CE, the address space of the selected chip is set to an operation state and a non-operation state.

In the nonvolatile semiconductor memory device having such a configuration, the program area is allocated to a 4-megabit chip, the data area where rewriting is frequently performed is allocated to a 16-megabit chip, and the data area is set wider. be able to.

When a 2 @ N power chip is incorporated in one package, an address space larger than the actual address storage capacity may be set, and N addresses and address buffer circuits may be added. For example, when two chips are incorporated in one package, one address is added because N = 1, and when three chips are incorporated in one package, N = 1 is not sufficient. Therefore, N = 2, two addresses are added, and when four chips are further incorporated in one package, N = 2, and two addresses are added.

In the present invention, the memory cell shown in FIG. 7 may be used, or a memory cell using a ferroelectric thin film as a gate oxide film may be used. When a memory cell in which a ferroelectric thin film is used for a gate oxide film is used, polarization inversion is used, so that an extremely thin tunnel oxide film can be omitted and higher integration can be achieved. Further, a volatile semiconductor memory device may be combined with the nonvolatile semiconductor memory device of the present invention to selectively operate one of the two memories.

[0060]

As described above, according to the present invention, the first
The first address space can be designated by the address buffer means, and the second address space can be designated by the second address buffer means. When the second address space is not used, the control means sets the second address buffer means to disable. Thus, for example, the first address space of the one-chip storage device can be used alone, or the first and second address spaces of the two-chip storage device can be selectively used. When a one-chip storage device is used, it is only necessary to disable the second address buffer means, so that compatibility with a normal storage device can be maintained.

Further, according to the present invention, an address area corresponding to the address space designated by the first address buffer means is selected and used, or the address area corresponding to the second address space designated by the second address buffer means is used. An address area can be selected and used.

Further, according to the present invention, the nonvolatile semiconductor memory device corresponding to the address space designated by the first address buffer means is selected and used, or the second address space designated by the second address buffer means is used. Can be selected and used. Therefore, it is possible to realize both the function of the normal nonvolatile semiconductor memory device and the function of the dual-work nonvolatile semiconductor memory device, and to shorten the development period as compared with realizing both functions individually. Development costs can be reduced.

Further, there is no need for a control signal for identifying the address space of each nonvolatile semiconductor memory device, and no decoding circuit for decoding the control signal is required. For this reason, the package of the normal memory can be shared with the package of the above embodiment, and the burden on the user side is small. Furthermore, since the configuration of each chip is common, the productivity is excellent, the management is easy, and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram partially showing an embodiment of a nonvolatile semiconductor memory device of the present invention.

FIG. 2 is a logic circuit diagram showing one example of an input buffer in the nonvolatile semiconductor memory device of FIG. 1;

3 is a logic circuit diagram showing an example of an address signal A19 processing logic circuit and an internal control signal / CE generation circuit in the nonvolatile semiconductor memory device of FIG. 1;

FIG. 4 is a circuit diagram illustrating an example of a control circuit in the nonvolatile semiconductor memory device of FIG. 1;

FIG. 5 is a plan view showing a pin arrangement of a package when the nonvolatile semiconductor memory device of the present embodiment is used as a normal 8-megabit flash memory.

FIG. 6 is a plan view showing a package of a dual-work 16-megabit flash memory in which the nonvolatile semiconductor memory device of the present embodiment is sealed in two chips.

FIG. 7 is a circuit diagram showing a memory cell of the flash memory.

FIG. 8 is a table showing commands of a conventional flash memory.

FIG. 9 is a plan view showing a package of a conventional dual-work 16-megabit flash memory.

FIG. 10 is a block diagram showing an input buffer in a conventional flash memory.

[Explanation of symbols]

 12, 13 input buffer 14 address signal A19 processing logic circuit 15 control circuit 16 internal control signal / CE generation circuit

Claims (6)

[Claims] A first address buffer for inputting an address signal for specifying an address space corresponding to a storage capacity; a second address buffer for specifying an address space equal to or larger than the storage capacity; and the second address buffer And a control unit for disabling the nonvolatile semiconductor memory device. 2. A first address buffer means for inputting an address signal designating an address space corresponding to a storage capacity; a second address buffer means designating an address space equal to or greater than the storage capacity; and the second address buffer means And a selecting means for selecting a memory area based on an address space designated by the command and an external control signal. 3. A plurality of nonvolatile semiconductor memory devices capable of rewriting data, first address buffer means for inputting an address signal designating an address space corresponding to a storage capacity of one nonvolatile semiconductor memory device, Second address buffer means for designating an address space equal to or larger than the storage capacity; and selecting means for selecting one of the nonvolatile semiconductor memory devices based on the address space designated by the second address buffer means. Non-volatile semiconductor storage device provided. 4. A plurality of non-volatile semiconductor memory devices having different storage capacities capable of rewriting data and inputting an address signal designating an address space corresponding to the storage capacity of one non-volatile semiconductor storage device. A first address buffer unit, a second address buffer unit that specifies an address space equal to or larger than the storage capacity, and the nonvolatile memory based on an address space specified by the second address buffer unit and an external control signal. A non-volatile semiconductor storage device comprising: a selection unit for selecting any one of the semiconductor storage devices. 5. The nonvolatile semiconductor memory device according to claim 3, wherein the plurality of data rewritable nonvolatile semiconductor memory devices are respective chips, and each of the chips is housed in one package. . 6. The nonvolatile semiconductor memory according to claim 3, wherein said plurality of data rewritable nonvolatile semiconductor memory devices have independent address spaces which do not overlap each other. apparatus.