JP2000207896A - Repair circuit for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make repairable at the stages of water and package by providing plural anti-fuses short-circuiting by a programming signal from the out side, an anti-fuse program section generating a signal relating to a state of the anti- fuse, and a second fuse section switching in accordance with an output signal of the anti-fuse program section. SOLUTION: A column repair control section 30 outputs a control signal for performing column repair. An anti-fuse program section 40 comprises plural, for example, 22 anti-fuses, and generates a signal R<1:22> relating to the state of anti-fuses. The anti-fuses are programmed in accordance with a programming signal supplied from the outside, that is, high voltage HV and a decoding signal SDA. A repair signal generating section 50 receives other input signal and the signal R<1:22> from the anti-fuse program section 40, and generates a repair signal spb.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a repair circuit for a semiconductor device, and more particularly to a repair circuit for performing a laser repair at a wafer stage and then repairing an error generated in a burn-in test of a packaged semiconductor device. The present invention relates to a repair circuit of a semiconductor device in which an area occupied by the repair circuit is reduced and repair can be performed in both a wafer stage and a package stage.

[0002]

2. Description of the Related Art A semiconductor device has a great influence on reliability due to each process element of a manufacturing process. Therefore, at each stage of a manufacturing process, a desired shape and a doped shape of a semiconductor device are required through various experiments and inspections. It is adjusted so as to form a state that has been performed. However, even if a slight error occurs in the manufacturing process, the operation of the semiconductor device will be greatly affected.Therefore, the semiconductor device manufactured using test equipment (for example, a probe station, a tester), etc. Check that the equipment is manufactured as designed.

As described above, if there is at least one defect in the inspection stage, the device cannot function as a DRAM and is therefore treated as a defective product. However, D
Although there is a high possibility that a defect will occur in only a small number of cells due to an increase in the degree of integration of the RAM, discarding this as a defective product is an inefficient processing method that lowers the non-defective product rate. . Therefore, in this case,
A method of increasing the non-defective rate by using a redundancy memory cell provided therein and replacing a defective cell is adopted.

A repair circuit of a memory device is provided for each sub-array block, a spare row and a column are provided in advance, and a memory cell which has become defective due to a defect is removed.
Alternatively, a method of replacing a memory cell with a redundancy memory cell in a column unit is mainly used. When the wafer processor is completed, an inspection is performed. If a defective cell is found at this time, programming for switching an address line corresponding to the defective cell to an address line of the redundancy memory cell is performed in an internal circuit of the memory device. by this,
When a memory is accessed and an address corresponding to a defective cell is input, an address line of the redundancy cell is selected. Examples of the programming method include an electric fuse method in which a fuse is melted by an overcurrent, a method in which a fuse is burned out with a laser beam, a method in which a junction is short-circuited with a laser beam, and a method in which an EPROM memory cell is programmed. Among these methods, the method of cutting the fuse with a laser is simple and reliable, the layout is easy, and widely used, and a polysilicon wiring or a metal wiring is used as a fuse material.

FIG. 1 is a circuit diagram showing a general redundancy column repair control unit. The redundancy column repair control unit shown in FIG.
b0, gaxb <0: 1>, gy01_or) and output signals (axd_np, xpcg_np, ypc)
g_np). These output signals (axd_n
p, xpcg_np, ypcg_np) are used as shown in FIG. 2 or as input signals of the pair circuit.

[0006] The input signal (rasatv15_b0) is R
This signal is enabled when an AS (Row Address Strobe) is activated, and has a low potential when the first bank of the memory banks is driven.

A low-potential input signal (rasatv15_b
0) are inverters (I244 to I247, I250 to I2).
51) and the NAND gate (I248), and is directly input to the NAND gate (I252). Therefore, the NAND gate (I252) applies a high-potential pulse signal to the NMOS transistor of the transfer gate (T240),
(I253) supplies a low-potential pulse signal to the PMOS transistor in the transfer gate (T240). Therefore, when the input signal (rasatv15_b0) is at a low potential, the transfer gate is turned on.

At this time, an input signal which is a row address
In (gaxb <0: 1>), one signal is enabled by a high-potential pulse, and is input to the NAND gate (I222) via the NOR gate (I256), the inverter (I241), and the transfer gate (T240). . Therefore, the NAND gate (I222) generates a low potential output signal (axd_np) and enables the output signal (axd_np). The pulse signal that has passed through the transfer gate (T240) passes through the inverter (I220) and
(I220, I209, I229, I221, I22
8, I234) and applied to the NAND gate (I214). Therefore, the NAND gate (I214) generates a low potential output signal (xpcg_np). That is, at the moment when the input signal (gaxb <0: 1>) is disabled from the high potential to the low potential, the state changes from the high potential state to the low potential state, and the output signal (xpcg_np) is disabled.
At this time, the pulse width of the output signal (xpcg_np) is determined by the inverters (I209, I229, I221, I228,
I234).

On the other hand, when an external or internal address is input as a column address, the input signal (gy01_or) is enabled by a high potential pulse and the input signal (gy0_or) is input.
1_or) goes through the inverter (I48) and the inverters (I48, I30, I262, I263, I26).
4, I265) and to the NAND gate (I38). Therefore, when the input signal (gy01_or) is disabled from the high potential to the low potential, the output signal
(ypcg_np) is an inverter (I30, I262, I
263, I264, and I265), they have a low potential and are enabled.

FIG. 2 is a circuit diagram showing a repair circuit of a conventional laser-based semiconductor device. As shown in FIG. 2, the fuse sections 10a, 10b, and 10c and the address input sections 20a and 20b are connected in series, and the normal state depends on whether or not the polyfuses of the fuse sections 10a, 10b, and 10c are cut. Mode reset (Normal Mo
deReset) signal (nmr) and a repair signal (spb).

The fuse sections 10a, 10b and 10c are composed of a plurality of polyfuses, and are provided with an address input section 20a.
Is the decoded signal (ax9A <0: 3>, axB)
And a plurality of NMOS transistors each connected to the polyview of the fuse section 10a. The address input unit 20b outputs the decoded signal (gy
01 <0: 3>, gy23 <0: 3>, gy456 <
0: 7>), the fuse portions 10b, 10
It is composed of a plurality of NMOS transistors respectively connected to the poly fuse c.

A repair circuit is an output signal of the circuit shown in FIG.
(xpcg_np), and a refresh signal (ref_nor).
b) driven by the PMOS transistors (P1
19) and an NMOS transistor (N114). P
The MOS transistor (P119) and the common node (xf_c
om), a PMOS transistor (P117) is provided. A transfer gate is provided between the common node (xf_com) and the output node of the normal mode reset signal (nmr).
(T205), (T206) and inverters (I207, I1)
94, I202) and a transfer gate (T205).
Are driven by the output signal (axd_np) of the circuit of FIG.

The repair circuit comprises a PMOS transistor (P129) and an NMOS transistor (N126) driven by a normal mode reset signal (nmr).
And a PMOS transistor (P125) driven by the output signal (ypcg_np) of the circuit of FIG. P
The MOS transistor (P129) is connected to the common node (yf_c).
om) PMOS transistor driven by the potential
(P142), the NMOS transistor (N140) and the potential of the common node (yf_com) are
Inverters (I136, I146, I141, I132, I13) applied to the gate of the S transistor (P133)
5) is provided.

According to the level of the repair signal (spb) output from the repair circuit thus configured, a redundancy column corresponding to an address input through the address input units 20a and 20b is selected.

That is, in the precharge state, FIG.
Since the output signal (xpcg_np) of the circuit is high potential and the current state is not the refresh mode,
The refresh signal (ref_norb) has a low potential,
Row address for selecting redundancy block
The decoded signal (ax9, axA, axB)
9A <0: 3>, axB <0: 1>) have a low potential.
Therefore, the common node (xf_com) is in a precharge state at a high potential. Then, the output signal (ax
d_np) is in a high potential state, and the normal mode reset signal (nmr) is in a high potential state.

Further, the output signal (ypcg__) of the circuit of FIG.
np) is a high potential, normal mode reset signal (nmr)
Is a high potential, decoding signal (gy01 <0: 3>,
gy23 <0: 3>, gy456 <0: 7>) are at a low potential, so that the common node (yf_com) is in a low potential state. At this time, when the column address (gy01_or) is enabled to a high potential, the repair signal (spb) is output to the inverters (I136, I146, I141, I132, I132).
During the delay time according to 135), it has a high potential and is disabled. Decoding signal (gy01
<0: 3>, gy23 <0: 3>, gy456 <0: 7
> Is a decoding signal of the column address (gy0 to gy7), and the column address (gy01_or) and the NMO
The S transistor N66 is used to reduce the load on the common node yf_com.

The operation in the normal operation in the precharged state as described above is as follows. The row address (ax9, axA, axB) can be used to select, for example, a 1M memory block from a 8M (mega byte) memory block. At this time, the decoding signal (ax9A <0: 3>) is used. 1)
Signal and one of the decoding signals (axB <0: 1>) are enabled to a high potential. Then, the common node (xf_co
m) is discharged to a low potential. Further, since the output signal (axd_np) of the circuit of FIG. 1 is at a low potential, the transfer gate (T205) is turned on. Therefore, the normal mode reset signal (nmr) maintains the high potential state.

The normal mode reset signal (nmr) has a high potential, one of the decoding signals (gy01 <0: 3>), one of the decoding signals (gy23 <0: 3>), and the decoding signal (gy23 <0: 3>). gy456 <0: 7>) and the column address signal (gy01_or) each have a high potential, and the common node (yf_com) has a low potential. Therefore, the repair signal (spb) is disabled to a high potential as in the precharge state described above.
Therefore, the repair operation is not performed, and the normal cell is accessed.

On the other hand, at the time of repair, among the fuses included in the fuse sections 10a, 10b, and 10c in FIG. 2, the fuse at the address corresponding to the block and column of the defective cell is cut by laser. For example, ax9A <0>, a
xB <0>, gy01 <0>, gy23 <0>, and g
Assuming that the fuse corresponding to y456 <0> has been blown, the row address (ax9, axA, axB) is 8M.
Is used to select a 1M block from among the memory blocks. Then, the column address (gy0 to gy6)
Causes one of the 128 memory columns to be selected.

At this time, the output signal of the circuit shown in FIG.
(xpcg_np) is a high potential, refresh signal (ref
_Norb) is a low potential and the decoding signal (ax
9A <0: 3>) and one signal of the decoding signal (axB <0: 1>) are each enabled to a high potential. However, since the fuse corresponding to the memory block of the defective cell has been cut by the laser, the common node (xf_com) is precharged continuously in the high potential state. The output signal (axd_np) of the circuit shown in FIG.
(T205) is turned on. Therefore, the normal mode reset signal (nmr) is disabled from the high potential to the low potential, and at this time, the output signal (ypcg) of the circuit of FIG.
— Np) becomes a high potential.

The decoding signal (gy01 <
0: 3>, gy23 <0: 3>, and gy456 <0:
7>), each is enabled to a high potential, but since the fuse corresponding to the column of the defective cell has already been blown, the common node (yf_com) is not discharged and maintains the high potential state. Therefore, the repair signal
(spb) becomes low potential, and the redundancy column is enabled.

As described above, repair is performed by the laser method, and after testing the success of the repair and the possibility of the functional operation of the redundancy cell, the non-defective product that passes this test is put into a package and completed as a semiconductor device. .

In the semiconductor device completed as a package in this way, in order to detect early defects at an early stage, all semiconductor devices are subjected to burn-in in which voltage and ambient temperature are stressed under more severe conditions than actual use conditions. Perform a test.

As described above, the defect occurrence rate in the burn-in test of the packaged semiconductor device is 5 to 1
It is about 5%. However, since the packaging is performed, repair by the laser method becomes impossible, and there is a problem that the semiconductor device is discarded.

In order to solve such a problem, a fuse cut by a laser is not used, and the upper electrode and the lower electrode are programmed according to a voltage difference applied between the upper electrode and the lower electrode during programming. The insulation film between the electrodes is easily broken down by an electrical method at a breakdown voltage or higher,
By using an antifuse that changes like a resistor, a method of easily repairing even at the package stage is used.

However, when the repair circuit is composed of only the anti-fuse, a programming circuit for destroying the insulating film of the anti-fuse is required, which causes a problem that the chip area increases.

[0027]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a repair circuit for a semiconductor device which can repair defective cells at the wafer stage and the package stage of a semiconductor element and can increase the yield rate. It is in.

Another object of the present invention is to reduce the area of the repair circuit by combining the repair circuit of the laser type with the anti-fuse method which can be repaired by an electrical method even at the package stage. An object of the present invention is to provide a repair circuit for a semiconductor device.

[0029]

According to another aspect of the present invention, there is provided a column repair control unit, comprising a first fuse unit and an address input unit connected to the column repair control unit, the first fuse unit being a laser type. In a repair circuit of a semiconductor device including a repair signal generator for generating a signal for enabling a redundancy column, a plurality of antifuses short-circuited by an external programming signal are provided, and a signal relating to the state of the antifuse is generated. Further includes an anti-fuse program section for causing
The repair circuit of a semiconductor device, wherein the repair signal generator further includes a second fuse unit that is switched according to an output signal of the anti-fuse program unit.

[0030]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 3 is a block diagram showing a configuration of a repair circuit of a semiconductor device according to the present invention, and shows only a portion of all the repair circuits for repairing at a package stage after a burn-in test.

That is, the repair circuit of the semiconductor device according to the present invention comprises a column repair control section (30), an anti-fuse program section (40), and a repair signal generation section (50). Here, the column address control unit (30)
A control signal (xpcg_np,
axd_np, ypcg_ng) is output in the same manner as the circuit of FIG.

The anti-fuse program unit 40 includes a plurality of, for example, 22 anti-fuses, and generates a signal (R <1:22>) relating to the state of the anti-fuse. The antifuse is programmed according to a programming signal supplied from outside, that is, a high voltage (HV) and a decoding signal (SDA).

The repair signal generating section (50) includes the input signal described with reference to FIG.
Further receives the input of the signal (R <1:22>) from the controller and generates a repair signal (spb).

FIG. 4 is a detailed circuit diagram of the repair circuit of the semiconductor device shown in FIG.
Only shown in the figure. The repair signal generating section (50) is composed of a plurality of NMOS transistors, and is configured to perform anti-fuse programming according to an anti-fuse programming state.
It further includes fuse units 51a and 51b that are switched depending on whether the potential value of the signal (R <1:22>) output from (40) is a high potential or a low potential.

Therefore, in the package stage after the burn-in test, the anti-fuse is programmed, so that the N included in the fuse portions 51a and 51b is
The MOS transistor is turned on / off, and the corresponding address input through the address input units 20a and 20b is repaired.

At this time, the NMOS transistor uses a substrate bias voltage as a ground voltage. In this embodiment, the fuse portions 51a, 51b
Is composed of NMOS transistors, but PM
It can also be constituted by an OS transistor.

Hereinafter, the operation of the repair circuit using the antifuse will be described in detail with reference to FIGS.
First, when in the precharge state, when the antifuse is programmed, the signal (R <1:22>) is latched to a low potential, otherwise it is latched to a high potential and uses a polyfuse. The same state as at the time is maintained.

The signal (xpcg_np) is at a high potential, the signal (ref_norb) is at a low potential since it is not in the refresh mode, and the decoding signal (ax9A
<0: 3>, axB <0: 1>) are low potentials,
The common node (xf_com) is in a precharged state at a high potential. Then, the signal (axd_np) is in the high potential state, and the normal mode reset signal (nmr) is in the high potential state.

The signal (ypcg_np) has a high potential, the signal (nmr) has a high potential, and the decoding signal (gy01 <
0: 3>, gy23 <0: 3>, gy456 <0: 7
>) Has a low potential, so that the common node (yf_com) has a low potential. The signal (gy01_or) is enabled by a high-potential pulse when an internal or external column address enters. At this time, the repair signal (spb)
Is disabled to a high potential.

As described above, the operation during the normal operation in the precharged state is as follows. Decoding signals (ax9A <0: 3>, ax
B <0: 1>) becomes a high potential, the common node (xf_co
m) is discharged to a low potential. Further, the signal (a
xd_np) becomes low potential and turns on the transfer gate (T205). At this time, the normal mode reset signal (nmr) maintains the high potential state.

The signal (nmr) has a high potential, one of the decoding signals (gy01 <0: 3>), one of the decoding signals (gy23 <0: 3>), and the decoding signal (gy456 <0). : 7>) and the signal (gy01)
_Or) become high potential, and the common node (yf_co
m) is discharged to a low potential. At this time, the repair signal (spb) is disabled to a high potential.

Accordingly, the repair operation is not performed, and the normal cell is accessed. But,
At the time of repair, the antifuse of the corresponding address is programmed. For example, the decoding signal
(ax9A <0>, axb <0>, gy01 <0>, g
Assuming that the antifuse corresponding to y23 <0>, gy456 <0>) is programmed, the row address (ax9, axA, axB) is one of the 8M blocks.
Used to select M blocks. Then, one of the 128 memory columns is selected as the column address (gy0 to gy7).

The signal (xpcg_np) has a high potential and the signal (r
ef_norb) is a low potential and the decoding signal
(ax9A <0: 3>, axB <0: 1>) are each enabled to a high potential. However, at this time, since the antifuse, for example, the antifuse corresponding to the signal (R <1>, R <5>) is programmed,
The signals (R <1>, R <5>) become low potential, and turn off the corresponding NMOS transistor of the fuse unit 51a. Therefore, the common node (xf_com) is precharged continuously to the high potential state. Then, the signal (rasat15_
When (b0) is at a low potential and the signal (gaxb <0: 1>) is enabled to a high potential, the signal (axd_np) goes to a low potential and enables the transfer gate (T205). At this time, the normal mode reset (nmr) is disabled because the potential is changed from the high potential to the low potential.

Further, the signal (ypcg_np) goes to a high potential state, the signal (nmr) goes to a low potential state, and the decoding signals (gy01 <0: 3>, gy23 <0: 3>, and gy456 <0: 7). >), Each one is enabled to a high potential. However, since the antifuse is programmed, for example, the signals (R <7>,
When R <11> and R <15>) become low potential, the corresponding NMOS transistor of the fuse portion 51b is turned off. Therefore, the common node (yf_com) is not discharged and maintains a high potential state. Therefore, at this time, the repair signal (spb) becomes low potential, and the redundancy column is enabled.

Although the embodiments of the present invention have been described above, those skilled in the art will be able to make various modifications without departing from the scope of the present invention.

[0046]

As described above, according to the present invention, a semiconductor device repaired by a laser method is subjected to an electrical failure of about 5 to 15% in a package stage at a package stage in a burn-in test or the like. By mixing with the anti-fuse method so that repair can be performed by the method, not only the area of the chip can be reduced, but also the repair can be performed at the package stage, and the yield rate can be further increased.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a general column repair control unit.

FIG. 2 is a circuit configuration diagram showing a repair circuit of a conventional semiconductor device using a laser method.

FIG. 3 is a block diagram illustrating a configuration of a repair circuit of the semiconductor device according to the present invention.

4 is a detailed circuit diagram of a repair circuit of the semiconductor device shown in FIG.

FIG. 5 is a timing chart showing an operation of the circuit shown in FIG. 4;

[Explanation of symbols]

 10a, 10b, 10c, 51a, 51b: fuse unit 20a, 20b: address input unit 30: column repair control unit 40: anti-fuse program unit 50: repair signal generation unit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kim Pil-Jung South Korea 13-1 Hyundai Electronics Indus Trees Company Limited (72) Inventor We Jae Gyong South Korea Within Company Limited (72) Inventor Yu Dok-hyun Gungido Echoonsi Bvarueub South Korea 136-1 Hyundai Electronics Indus Trees Company Limited Miri San 136-1 Hyundai Electronics Industries Trees Company within the Limited (72) inventor Cho Hoyopu South Korea Gyungido Ichonshi Bubarueubu Amiri San 136-1 Hyundai Electronics Industries Trees Company Limited in

Claims (2)

[Claims] 1. A repair signal generator connected to the column repair controller and including a first fuse unit and an address input unit using a laser method, and configured to generate a signal for enabling a redundancy column. A repair circuit of the semiconductor device, comprising: a plurality of anti-fuses that are short-circuited by an external programming signal; and an anti-fuse program unit that generates a signal related to a state of the anti-fuse. A repair circuit for a semiconductor device, further comprising a second fuse unit switched according to an output signal of the anti-fuse program unit. 2. The repair circuit according to claim 1, wherein the second fuse unit includes a plurality of Ns connected in series with NMOS transistors included in the address input unit.
A repair circuit for a semiconductor device, comprising a MOS transistor and using a substrate bias voltage as a ground voltage.