JP2000183064A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a barrier film in crystallinity and a Cu film in (111) orientation by a method wherein a Ti film oriented in a (002) direction is provided as a part of a Cu buried wiring under a barrier film which is amorphous or contains fine crystals. SOLUTION: A groove wiring composed of a barrier metal 2 and a first Cu film 3 is formed in a first insulating film 11, a first silicon nitride film 4, a second insulating film 5, a second silicon nitride film 6, and a third insulating film 7 are successively deposited thereon, and then a contact hole 8 and a wiring groove 9 are provided. A Ti film 14 oriented in a (002) direction is deposited on the contact hole 8 and the wiring groove 9 through an ionization sputtering method, and a titanium nitride film 10 is deposited as a barrier film on the Ti film 14. Furthermore, a Cu seed layer 11 is deposited on the titanium nitride film 10, then a Cu plating film 12 is deposited, and a second Cu film 13 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a copper wiring and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a silicon LSI of the 0.18 μm generation or later, a delay due to a CR component of a wiring cannot be ignored for a high-speed transistor.
3μohm ・ cm) and lower resistance (specific resistance 1.7μohm ・ cm)
Studies have been made to use Cu) as the wiring material.

Further, the density of current flowing in wirings has been increasing with each generation with the miniaturization of elements, and the phenomenon of electromigration, in which the wiring material is pushed by electrons and moved when current is applied and the wirings are disconnected, has been developed. It is necessary to increase its resistance. Because Cu has a higher melting point than Al,
It is expected that deformation, that is, migration of atoms is unlikely to occur, and that electromigration resistance is also expected to be high.

However, there is a report that electromigration resistance is deteriorated in a fine wiring having a width of about 0.3 μm even in a Cu wiring [Y. Igarashi et al, VLSI Symp.,
p.76, 1996], and it is necessary to improve the electromigration resistance even in Cu wiring. To improve the electromigration resistance of Cu wiring, use Cu
It is known that the (111) orientation of the film may be increased (C. Ryu et al., Proc. IRPS., P. 201, 1997). The reason is as follows. First, Cu is an fcc metal, and the fcc metal is most stable on the densest surface (111). Second, the fact that the (111) orientation is high is because the deviation of the orientation of adjacent crystal grains is small and the number of crystal defects is small, so that diffusion of Cu atoms at the grain boundaries due to electromigration is suppressed.

In the case of Cu wiring, it is necessary to prevent Cu from diffusing into the insulating film due to heat treatment at about 400 ° C. during the wiring process, thereby preventing leakage between wirings from increasing. It is necessary to provide between the Cu film and the insulating film. As a barrier film, a titanium nitride, tantalum nitride, or tungsten nitride film containing amorphous or microcrystals having a strong barrier property against Cu diffusion is considered most promising.

Hereinafter, a Cu wiring technique using a titanium nitride film will be described with reference to FIG. First, as shown in FIG. 7A, a trench wiring composed of a barrier metal 2 and a first Cu film 3 is formed in a first insulating film 1 on a semiconductor device, and a first silicon nitride film 4 In the semiconductor device covered with the second insulating film 5, the second silicon nitride film 6, and the third insulating film 7, a contact hole 8 and a wiring groove 9 are formed. Here, the barrier metal 2 and the silicon nitride film 4 play a role (barrier property) of preventing the first Cu from diffusing into the insulating film due to the heat treatment at about 400 ° C. during the wiring process. The barrier metal 2 may be, for example, a titanium nitride film.

Next, as shown in FIG. 7B, a MOCVD-TiN (titanium nitride) film 10 is formed as a barrier film by MOCVD.
Is deposited. Next, a Cu film is deposited by a sputtering method, a Cu seed layer 11 film serving as a conductive layer is deposited, and then a Cu film is deposited by an electrolytic plating method to form a Cu plating film 12, as shown in FIG.
The contact hole 8 and the wiring groove 9 are buried. In a subsequent process involving a temperature rise, Cu crystal growth occurs, and the Cu plating film 12 and the Cu seed layer 11 become one film, and the second Cu film 1
3 is formed. Next, as shown in FIG. 7D, the MOCVD-TiN film 10 and the second Cu film 13 outside the wiring groove are removed by a CMP method or the like to form a wiring. Thereafter, a silicon nitride film and an insulating film are deposited, and the steps after FIG. 7A are repeated to form a multilayer wiring.

Here, the MOCVD-TiN film has a second C
It is also expected to improve the reliability of the upper wiring composed of the u film.

[0009]

However, MOCVD-
Although the TiN film has sufficient barrier properties at a heat treatment of about 400 ° C, the MO
It is known that a Cu film on a CVD-TiN film has low (111) orientation. Therefore, the electromigration resistance of the Cu wiring is low, and in order to improve the electromigration resistance, it has been proposed to use a tantalum film or a tantalum nitride film as a barrier film. Since mass production technology by the CVD method has not been established, these films are mainly formed by a sputtering method, and are known to have a tetragonal or amorphous crystal structure, respectively. In particular, it is known that the orientation on the tantalum film is oriented to (002) to improve the (111) orientation of Cu.

In a tantalum nitride film, amorphous tantalum nitride is formed at a nitrogen composition ratio of 33% or less, and the Cu film has good wettability on the tantalum nitride film.
It is known that the (111) orientation of Cu is high. FIG. 12 shows the results of our experiment.

[0011] Cu // MOCVD-Ti deposited on silicon nitride film
Cu (111) and (20) by X-ray diffraction in N, Cu // Ta, Cu // TaN structure
0) The peak intensity ratios were 2.4, 49, and 44, respectively, indicating that the (111) orientation of Cu on tantalum or tantalum nitride was improved. Thus, MOCVD-TiN
The problem with Cu wiring using barrier metal is that the (111) orientation is low and the electromigration resistance of the wiring is low.

However, since the MOCVD-TiN film is formed by the CVD method, there is an advantage that coverage is good and almost 100% film thickness can be formed on the side wall. On the other hand, Ta and TaN films are formed by sputtering, so coverage is poor, the thickness of the side wall is thinner than the contact bottom, the barrier property is deteriorated, and Cu is easily diffused into the insulating film on the side wall. There is a problem.

The present invention improves the (111) orientation of a Cu film on an amorphous barrier metal, such as MOCVD-TiN, which has excellent barrier properties, thereby improving the electromigration resistance of a copper wiring. It is intended to provide a manufacturing method.

[0014]

Means for Solving the Problems The present inventor has proposed under Cu
The presence of a (002) oriented Ti film (11
1) It was found that the orientation was high. In FIG. 12, after depositing 10 nm of Ti on a silicon nitride film by a sputtering method, exposing the surface to air, and then depositing Cu by a 50 nm sputtering method, a Cu // Ti laminated structure of Cu (111) / (200) X-ray The diffraction intensity ratio is 339, whereas the Cu // Ta structure formed by the same method has only 49. The barrier property of the Ti film itself against the Cu film is 350 °
Therefore, it is necessary to combine Cu with another barrier metal film.

[0015] Actually, Cu is deposited on the amorphous MOCVD-TiN film.
In the Cu // MOCVD-TiN structure, Cu (111) / (200) X
Although the X-ray diffraction intensity ratio is 2.4, the Cu // MOCVD-TiN / Ti structure having Ti with (002) orientation
It can be seen that the (111) orientation of Cu is higher than that of Cu.

The reason is considered as follows. First
The high orientation of Cu (111) on Ti is as shown in FIG.
The (002) -oriented Ti film has an in-plane atomic spacing of 2.95Å and an in-plane atomic spacing of 2.55Å in the Cu (111) plane, each of 7 times (2.95 × 7 = 20.
65), it is thought that this is because the lattice matching is eight times (2.55 × 8 = 20.40). When the (002) oriented Ti is below, the MOCVD-TiN film also has a T
It is considered that microcrystallization for forming the iN (111) plane proceeds. Then, the (111) -oriented TiN film has an in-plane atomic spacing of 3.
00 Å and 2.55 原子 in-plane atomic spacing in the Cu (111) plane, 6
It is thought that this is because lattice matching is performed by a factor of (3.00 × 5 = 18.00) and a factor of 7 (2.55 × 7 = 17.85), and the (111) orientation of the upper Cu film is improved.

In fact, the results of the X-ray diffraction measurement shown in FIGS. 8 and 14 show that the base of only Ti shown in FIG. 8B has a lattice constant of 2.3865 ° which is close to the lattice constant of the (002) plane of 2.34 °. Although there is a broad peak, in the MOCVD-TiN / Ti underlayer of FIG. 8C, the peak position is shifted to 2.4571 °, which is close to the lattice constant of 2.45 ° of the TiN (111) plane. It is evident that microcrystallization has progressed. However, since the peak height is as low as about 600 counts and the peak is broad, it is considered that the crystallinity of MOCVD-TiN is still strongly amorphous. This result is TE
Also confirmed by M. FIG. 10 shows an experimental result that the orientation of Cu (111) is improved when the Ti film thickness is increased in the Cu // MOCVD-TiN / Ti structure. It is understood that a thickness of about 5 nm is sufficient for Ti.

For the above reasons, the first semiconductor device and the method of manufacturing the same according to claims 1 and 7 of the present invention provide a method for manufacturing a semiconductor device, comprising: By providing a (002) oriented Ti film on the substrate, the crystallinity of the barrier film can be enhanced, and the (111) orientation of the upper Cu film can be enhanced.

FIG. 12 shows that the Cu (111) orientation is better on Ti than on the MOCVD-TiN / Ti structure.

Therefore, the second semiconductor device according to the second and ninth aspects of the present invention is characterized in that the barrier film between the Cu film and the barrier film containing amorphous or microcrystal as a part of the Cu embedded wiring. By providing the above (002) oriented Ti film, the (111) orientation of Cu can be increased without changing the crystallinity of the barrier film. Since the barrier film is said to have higher barrier properties as it is amorphous, this structure has the advantage that the (111) orientation of Cu can be increased without impairing the barrier properties.

Further, the present inventor has proposed that the insulating film is exposed to Ar plasma before depositing the (002) -oriented Ti film so that Cu film can be formed.
It has been found that the (111) orientation can be further enhanced. As shown in FIG. 11, by performing an Ar plasma treatment with an oxide film etching amount of about 5 nm, the (111) / (200) X-ray diffraction intensity ratio of Cu is improved from 257 to 405. Ar for this reason
It is said that the plasma treatment makes the surface of the silicon oxide film or the silicon nitride film silicon-rich. As a result, it is considered that the (002) crystallinity of the Ti film is improved.

For the above reasons, according to a third method of manufacturing a semiconductor device according to the present invention, the surface of the interlayer insulating film is exposed to Ar plasma before the step of forming a (002) oriented Ti film. By increasing the (002) orientation of Ti,
The (111) orientation of the upper Cu film can be improved.

Further, the fourth semiconductor device and the method of manufacturing the same according to the third and tenth aspects of the present invention provide a semiconductor device comprising:
02) By growing the oriented Ti film thick at the bottom of the wiring groove and thin on the side of the wiring and not necessarily (002) oriented, the Cu film grows so that the <111> axis is perpendicular to the side of the groove wiring Is suppressed and the growth is such that the <111> axis is oriented perpendicular to the bottom of the wiring, whereby the Cu (111) orientation in the trench wiring can be improved.

According to a sixth aspect of the present invention, there is provided a semiconductor device and a method of manufacturing the same, wherein MOCVD is used as a barrier film containing amorphous or microcrystal for Cu wiring which is effective in the present invention.
It indicates that there is a titanium nitride film deposited by a method or a tantalum nitride film or a tungsten nitride film deposited by a sputtering or CVD method.

The fifth semiconductor device and the method of manufacturing the same according to the fourth and eleventh embodiments use a method of forming a wiring pattern by etching, and the reason why the Cu (111) orientation is improved is as follows. This is the same as that described in the first semiconductor device and the manufacturing method thereof described in the items 1 and 7.

The sixth semiconductor device and the method of manufacturing the same according to the fifth and thirteenth aspects are only when a method of forming a wiring pattern by etching is used. The reason why the Cu (111) orientation is improved is as follows. This is the same as that described in the second and ninth aspects of the present invention.

The method of manufacturing a seventh semiconductor device according to the twelfth aspect of the present invention is only when a method of forming a wiring pattern by etching is used. The reason why the Cu (111) orientation is improved is as follows. This is the same as that described in the third method of manufacturing a semiconductor device.

By exposing the surface of the interlayer insulating film to Ar plasma before the step of forming a (002) oriented Ti film,
By increasing the (002) orientation, the (11)
1) The orientation can be improved.

As described above, in the present invention, a Cu wiring having high electromigration resistance can be formed by improving the (111) orientation of the Cu film.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIGS. 1 (a) to 1 (d)
The semiconductor device according to the first embodiment of the present invention and a method for manufacturing the same will be described with reference to FIGS.

First, as shown in FIG. 1A, a trench wiring comprising a barrier metal 2 and a first Cu film 3 is formed in a first insulating film 1 on a semiconductor device, and a first silicon nitride film is formed. 4, second
Insulating film 5, second silicon nitride film 6, third insulating film 7
In the semiconductor device covered with, a contact hole 8 having a depth of about 500 nm and a wiring groove 9 having a depth of about 300 nm are formed. Here, the barrier metal 2 and the silicon nitride film 4 play a role (barrier property) of preventing the first Cu from diffusing into the insulating film due to the heat treatment at about 400 ° C. during the wiring process. The barrier metal 2 may be, for example, a titanium nitride film.

Next, as shown in FIG. 1B, a (002) oriented Ti film 14 is deposited to a thickness of 10 nm by ionization sputtering or the like.
Next, an MOCVD-TiN (titanium nitride) film 10 is deposited to a thickness of 10 nm as a barrier film by MOCVD. After exposing the surface of TiN to air, a Cu film is deposited by sputtering, and a Cu seed layer 11 film serving as a conductive layer is deposited to a thickness of 100 nm. Then, as shown in FIG. Deposit Cu plating film 12
500 nm is deposited, and the contact hole 8 and the wiring groove 9 are buried. In a subsequent step involving a rise in temperature, crystal growth of Cu occurs, the Cu plating film 12 and the Cu seed layer 11 become one film, and the second Cu film 13 is formed.

Next, as shown in FIG. 1D, the Ti film 14, the MOCVD-TiN film 10, and the second Cu film 1 outside the wiring groove are formed by a CMP method or the like.
3 is removed to form a wiring. Thereafter, a silicon nitride film and an insulating film are deposited, and the steps after FIG. 1A are repeated to form a multilayer wiring.

In this embodiment, since the (002) -oriented Ti is below, the MOCVD-TiN film also has a microcrystal in which the in-plane atomic spacing forms a TiN (111) plane close to the Ti (002) plane. Is thought to progress. Then, the (111) -oriented TiN film has an in-plane atomic spacing.
Lattice matching of 3.00Å and 2.55Å in-plane atomic spacing in the Cu (111) plane was 6 times (3.00 × 5 = 18.00) and 7 times (2.55 × 7 = 17.85), respectively, and the upper layer Cu film (111) It is considered that the orientation is improved. FIG. 13 shows the results of measuring the (111) orientation of Cu in the wiring portion.

In the Cu // MOCVD-TiN structure, the value was 4.5 (Cu (111) /
(200) X-ray peak intensity ratio is 13 in Cu // MOCVD-TiN / Ti structure.
2, which is said to have high electromigration resistance despite the exposure of air between Cu and barrier metal deposition, and the Cu (111) ) / (200) X-ray peak intensity ratio 136 could be shown to be almost the same value.

Therefore, if this structure is used, the electromigration characteristics of Cu wiring using MOCVD-TiN having good side wall coverage and high barrier properties have a tantalum barrier.
It can be improved to the same level as Cu wiring.

(Second Embodiment) FIGS. 2A to 2D are explanatory views of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

As shown in FIG. 2A, a trench wiring composed of a barrier metal 2 and a first Cu film 3 is formed in a first insulating film 1 on a semiconductor device, and a first silicon nitride film 4 is formed. In the semiconductor device covered with the second insulating film 5, the second silicon nitride film 6, and the third insulating film 7, a contact hole 8 having a depth of about 500 nm and a wiring groove 9 having a depth of about 300 nm are formed. It is formed. Then, the semiconductor device is exposed to Ar plasma having a pressure of about 0.4 mTorr. Treatment time is carried out substantial amounts of SiO ₂ to 35nm etching. At this time, a bias voltage may be applied to the wafer side.

Next, as shown in FIG. 2B, a Ti film 14 having a (002) orientation and having a thickness of 10 nm is deposited by ionization sputtering or the like.
Next, an MOCVD-TiN (titanium nitride) film 10 is deposited to a thickness of 10 nm as a barrier film by MOCVD. After exposing the surface of TiN to air, a Cu film is deposited by a sputtering method, and a Cu seed layer 11 film serving as a conductive layer is deposited to a thickness of 100 nm. Then, as shown in FIG. Deposit Cu plating film 12
500 nm is deposited, and the contact hole 6 and the wiring groove 7 are buried. In a subsequent step involving a rise in temperature, crystal growth of Cu occurs, the Cu plating film 12 and the Cu seed layer 11 become one film, and the second Cu film 13 is formed.

Next, as shown in FIG. 2D, the Ti film 14, the MOCVD-TiN film 10, and the second Cu film 1 outside the wiring groove are formed by a CMP method or the like.
3 is removed to form a wiring. Thereafter, a silicon nitride film and an insulating film are deposited, and the steps after FIG. 2A are repeated to form a multilayer wiring.

In the present embodiment, Ti sputtering is performed by Ar sputtering.
It is thought that the (111) orientation of the upper Cu film is improved through the MOCVD-TiN film because the (002) orientation of the above is further improved.
FIG. 13 shows the results of measuring the (111) orientation of Cu in the wiring portion. Cu (111) / (200) which was 132 in Cu // MOCVD-TiN / Ti structure
X-ray peak intensity ratio decreased slightly to 110 in the Cu // MOCVD-TiN / Ti / Ar sputtered structure, but when the rocking curve of the Cu (111) peak was measured, the half-width increased from 3.84 to 1.89 ° As a result, it was found that the Cu (111) orientation was further improved. Even in Cu / Ta structure wiring continuously deposited in vacuum, which is said to have high electromigration resistance, C
The rocking curve of the u (111) peak was 2.42 °. Therefore, by using this structure, the electromigration characteristics of the Cu wiring using MOCVD-TiN having good sidewall coverage and high barrier properties can be improved more than the Cu wiring having a tantalum barrier. The contact resistance was measured for the presence or absence of the Ti film 14. MOCVD with 0.3 m square contact
In the MOCVD-TiN / Ti structure, the average value is 1.30?
It was found that the presence of the Ti film 14 of 0.83? Was more advantageous in terms of contact resistance.

(Third Embodiment) FIGS. 3A to 3D are diagrams illustrating a method for manufacturing a semiconductor device according to a third embodiment of the present invention. Since the contents of FIG. 3A are the same as those of the process of FIG.

Next, as shown in FIG. 3B, a Ti film 14 of (002) orientation is deposited to a thickness of 10 nm by ionization sputtering or the like.
Next, an MOCVD-TiN (titanium nitride) film 10 is deposited to a thickness of 10 nm as a barrier film by MOCVD. Further, the Ti film 15 with (002) orientation by ionization sputtering or the like is
accumulate. After exposing the surface of TiN to air, a Cu film is deposited by a sputtering method, and a Cu seed layer 11 film serving as a conductive layer is formed.
After the deposition of 50 nm, a Cu film is deposited by electrolytic plating as shown in FIG. 3C, a Cu plating film 12 is deposited to a thickness of 500 nm, and the contact holes 6 and the wiring grooves 7 are buried. In a subsequent step involving a rise in temperature, crystal growth of Cu occurs, the Cu plating film 12 and the Cu seed layer 11 become one film, and the second Cu film 13 is formed.

Next, as shown in FIG. 3D, the Ti film 14, the MOCVD-TiN film 10, the Ti film 15, and the second Cu film 13 outside the wiring groove are removed by a CMP method or the like to form a wiring. . Thereafter, a silicon nitride film and an insulating film are deposited, and the steps after FIG. 3A are repeated to form a multilayer wiring.

In this embodiment, since Cu is deposited directly on Ti, the Cu (111) orientation is further improved. Structure without pattern of Cu (111) orientation to seed layer (Fig. 12)
Compared with Cu // MOCVD-TiN / Ti, Cu // Ti / M
It can be seen that the X-ray diffraction intensity ratio of the OCVD-TiN / Ti structure is improved from 257 to 351. This is due to the continuous deposition of Cu / T in vacuum, which is said to have high electromigration resistance.
This value is almost the same as the Cu (111) / (200) X-ray peak intensity ratio 366 of the a-structure. Therefore, if this structure is used, the electromigration characteristics of Cu wiring using MOCVD-TiN, which has good sidewall coverage and high barrier properties, has a tantalum barrier
It can be improved to the same level as Cu wiring.

In the present invention, the Ti film 14 may be omitted. In that case, there is no underlying Ti film, so MOCVD-TiN
The (111) orientation of Cu can be increased without changing the crystallinity of the film 10. Since the barrier film is said to have higher barrier properties as it is amorphous, the structure in which the Ti film 14 is omitted has an advantage that the (111) orientation of Cu can be increased without impairing the barrier properties.

(Fourth Embodiment) In a fourth semiconductor device and a method of manufacturing the same according to the present invention, the (002) -oriented Ti in the embedded wiring is formed in the embedded wiring forming step shown in FIGS.
The film is thick on the bottom of the wiring groove, thin on the side of the wiring and not necessarily
By preventing the (002) orientation, the growth of the Cu film such that the <111> axis is perpendicular to the trench wiring side surface is suppressed,
It promotes growth so that the <111> axis is oriented perpendicular to the bottom of the wiring.

Thus, the Cu (111) orientation in the trench wiring can be improved. Rather, in this embodiment,
If no Ti film is formed on the side wall, the Cu (111) orientation improves.

(Fifth Embodiment) A semiconductor device according to a fifth embodiment of the present invention and a method of manufacturing the same will be described with reference to FIGS.

First, as shown in FIG. 4A, a (002) -oriented Ti film 14 is deposited to a thickness of 10 nm on a first insulating film on a semiconductor device by ionization sputtering or the like. Next, an MOCVD-TiN film 10 is deposited as a barrier film to a thickness of 10 nm by MOCVD. T
After exposing the surface of iN to air, the Cu film 1 is then sputtered.
6 is deposited to a thickness of 300 nm.

Next, as shown in FIG. 4B, a wiring pattern is formed with a resist 17, and as shown in FIG. 4C, the Ti film 14, the MOCVD-TiN film 10, and the Cu film 16 are etched by dry etching. Then, wiring is formed. Finally, as shown in Fig. 4 (d),
The silicon nitride film 18 and the second insulating film 5 surround the wiring.

Also in this example, since the (002) oriented Ti is below, the (111) oriented microcrystals increase in the TiN film, and it is considered that the (111) orientation of the upper Cu film is improved. . Therefore, if this structure is used, the electromigration characteristics of the Cu wiring using MOCVD-TiN having good side wall coverage and high barrier properties can be improved to the same level as the Cu wiring having a tantalum barrier.

(Sixth Embodiment) A semiconductor device according to a sixth embodiment of the present invention and a method of manufacturing the same will be described with reference to FIGS.

First, as shown in FIG. 5A, an Ar plasma process is applied to the first insulating film on the semiconductor device.

Next, as shown in FIG. 5B, a Ti film 14 of (002) orientation is deposited to a thickness of 10 nm by ionization sputtering or the like. Next, the MOCVD-TiN film 10 is used as a barrier film by MOCVD.
Deposit nm. After exposing the surface of TiN to air, a Cu film 16 is next deposited to a thickness of 300 nm by sputtering. Further resist 1
7, a wiring pattern is formed, and as shown in FIG. 5C, the Ti film 14, the MOCVD-TiN film 10, and the Cu film 1 are formed by dry etching.
6 is etched to form wiring. Finally, as shown in FIG. 5D, the silicon nitride film 18 and the second insulating film 5 surround the wiring.

In the present embodiment, Ti sputtering is performed by Ar sputtering.
It is thought that the (111) orientation of the upper Cu film is improved through the MOCVD-TiN film because the (002) orientation of the above is further improved.
Therefore, by using this structure, it is possible to improve the electromigration characteristics of Cu wiring using MOCVD-TiN having good sidewall coverage and high barrier properties.

(Seventh Embodiment) A semiconductor device according to a seventh embodiment of the present invention and a method of manufacturing the same will be described with reference to FIGS. 6 (a) to 6 (d).

First, as shown in FIG. 6A, a (002) -oriented Ti film 14 is deposited to a thickness of 10 nm on a first insulating film on a semiconductor device by ionization sputtering or the like. Next, an MOCVD-TiN film 10 is deposited as a barrier film to a thickness of 10 nm by MOCVD.
Next, the (002) oriented Ti film 15 is sputtered at 10 nm. Ti
After exposing the surface of the film 15 to air, Cu
A film 16 is deposited to a thickness of 300 nm.

Next, as shown in FIG. 6B, a wiring pattern is formed with a resist 17, and as shown in FIG. 6C, the Ti film 14, the MOCVD-TiN film 10, the Ti film 15,
The film 16 is etched to form a wiring. Finally, Fig. 6 (d)
The silicon nitride film 18 and the second insulating film 5 surround the wiring.

In this embodiment, Cu is deposited directly on Ti, and therefore, the Cu (111) orientation is further improved for the same reason as in the third embodiment. Therefore, if this structure is used, the electromigration characteristics of the Cu wiring using MOCVD-TiN having good side wall coverage and high barrier properties can be improved to the same level as the Cu wiring having a tantalum barrier.

In the present invention, the Ti film 14 may be omitted. In that case, there is no underlying Ti film, so MOCVD-TiN
The (111) orientation of Cu can be increased without changing the crystallinity of the film 10. Since the barrier film is said to have higher barrier properties as it is amorphous, the structure in which the Ti film 14 is omitted has an advantage that the (111) orientation of Cu can be increased without impairing the barrier properties.

In the above embodiment, the first Cu film 3
Although pure Cu is used for the second Cu film 13 and the Cu film 16, another Cu alloy may be formed. Also, two films, a Cu seed layer 11 and a Cu plating film 12, are deposited to form a second Cu film 13,
Without depositing a Cu seed layer or depositing a Cu plating film, a second Cu film 13 is formed at a time by a CVD method, an electroless plating method, a CVD + high-temperature sputtering method, a sputtering + reflow method, an ion plating method, or the like. Is also good.

As the first, second, and third insulating films, a coating film, a SiO ₂ film, or a CVD film having a low dielectric constant containing C may be used. In addition, although the method of burying the contact hole and the wiring groove at the same time is used as the wiring structure, either one may be buried by this method. Also, MOCV as a barrier metal
Although the D-TiN film is used, another barrier metal such as a tungsten nitride film may be used as long as the metal has a high melting point containing amorphous or microcrystals and a compound thereof. For example, if a tantalum nitride film with higher (111) orientation of Cu than on MOCVD-TiN is used as a barrier metal,
There is a possibility that the (111) orientation can be improved.

[0064]

According to the first semiconductor device and the method of manufacturing the same according to the first and seventh aspects of the present invention, as the part of the Cu embedded wiring, the (002) ) By providing an oriented Ti film, the crystallinity of the barrier film can be enhanced, and the (111) orientation of the upper Cu film can be enhanced.

The second semiconductor device according to the second and ninth aspects of the present invention is characterized in that a portion of the Cu film between the barrier film containing amorphous or microcrystals is formed on the barrier film as a part of the Cu embedded wiring. By providing the (002) oriented Ti film, the (111) orientation of Cu can be increased without changing the crystallinity of the barrier film. Since the barrier film is more amorphous as it has a higher barrier property, in this structure, Cu (11
1) There is an advantage that the orientation can be improved.

According to the third method of manufacturing a semiconductor device of the present invention, the surface of the interlayer insulating film is exposed to Ar plasma before the step of forming a (002) oriented Ti film.
By increasing the (002) orientation of Ti, the (11)
1) The orientation can be improved.

According to the fourth semiconductor device and the method of manufacturing the same of the present invention, the (002) -oriented Ti film in the buried wiring is thick at the bottom of the wiring groove, thin at the wiring side and not necessarily ( 002) By not being oriented,
By suppressing the growth of the Cu film with the <111> axis oriented perpendicular to the trench wiring side, and by growing the <111> axis perpendicular to the wiring bottom, Cu (111) orientation in the trench wiring Can be improved.

The fifth semiconductor device and the method of manufacturing the same according to the fourth and eleventh aspects of the present invention employ a method in which a wiring pattern is formed by etching, and the Cu (111) orientation is improved. The reason is the same as that described in the first semiconductor device and the manufacturing method thereof.

The sixth semiconductor device and the method of manufacturing the same according to the fifth and thirteenth aspects are only when a method of forming a wiring pattern by etching is used. The reason why the Cu (111) orientation is improved is as follows. This is the same as that described in the second and ninth aspects of the present invention.

The method for manufacturing a seventh semiconductor device according to the twelfth aspect of the present invention is only when a method of forming a wiring pattern by etching is used. The reason why the Cu (111) orientation is improved is as follows. This is the same as that described in the third method of manufacturing a semiconductor device.

By exposing the surface of the interlayer insulating film to Ar plasma before the step of forming a (002) oriented Ti film,
By increasing the (002) orientation, the (11)
1) The orientation can be improved.

As described above, in the present invention, a Cu wiring having high electromigration resistance can be formed by improving the (111) orientation of the Cu film.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a method for manufacturing a semiconductor device according to a first embodiment;

FIG. 2 is a sectional view showing a method for manufacturing a semiconductor device according to a second embodiment;

FIG. 3 is a sectional view illustrating a method for manufacturing a semiconductor device according to a third embodiment;

FIG. 4 is a sectional view showing a method for manufacturing a semiconductor device according to a fifth embodiment;

FIG. 5 is a sectional view showing a method for manufacturing a semiconductor device according to a sixth embodiment;

FIG. 6 is a sectional view showing a method of manufacturing a semiconductor device according to a seventh embodiment.

FIG. 7 is a cross-sectional view showing a conventional method for manufacturing a copper wiring for a semiconductor device.

FIG. 8 is a view showing an XRD spectrum showing the orientation of a Cu film on a silicon nitride film.

FIG. 9 is a diagram showing the orientation plane and the in-plane atomic spacing of each metal film.

FIG. 10: Cu (111) / (200) in Cu / MOCVD-TiN / Ti structure
Diagram showing dependency of X-ray peak intensity ratio on Ti film thickness

FIG. 11: Cu (111) / (200) in Cu / MOCVD-TiN / Ti structure
Diagram showing dependence of X-ray peak intensity ratio on Ar sputter cleaning amount

FIG. 12 is a diagram showing a relationship between a laminated structure and copper orientation.

FIG. 13 is a diagram showing a relationship between a laminated structure and copper orientation.

FIG. 14 is an XRD showing the orientation of a Cu film on a silicon nitride film.
Diagram showing spectrum

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st insulating film 2 barrier metal 3 1st Cu film 4 1st silicon nitride film 5 2nd insulating film 6 2nd silicon nitride film 7 3rd insulating film 8 Contact hole 9 Wiring groove 10 MOCVD- TiN film 11 Cu seed layer 12 Cu plating film 13 Second Cu film 14 Ti film 15 Ti film 16 Cu film 17 Resist

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/768 H01L 21/90 A F-term (Reference) 4K029 BA08 BA17 BA58 BA60 BB02 BD01 CA05 DC37 4K030 AA11 BA17 BA18 BA20 BA38 BB04 BB05 HA02 LA15 4M104 BB04 BB14 BB30 BB32 BB33 BB37 CC01 DD07 DD15 DD17 DD36 DD37 DD43 DD47 DD52 DD78 DD86 EE12 EE17 FF07 FF18 FF22 GG13 HH01 HH15 5F033 HH11 HH18 JJ31H33 MM13 NN06 NN07 PP06 PP11 PP15 PP20 PP27 PP33 QQ00 QQ09 QQ14 QQ37 QQ48 QQ72 QQ84 RR06 SS11 SS21 TT01 XX05 XX09

Claims (14)

[Claims] 1. A semiconductor device having a buried interconnect, wherein the buried interconnect is a barrier film containing a (002) -oriented Ti film and an amorphous or microcrystal on the Ti film,
A semiconductor device having a (111) -oriented Cu film on the barrier film. 2. A semiconductor device having a buried wiring, wherein the buried wiring is a barrier film containing amorphous or microcrystal, and a (002) -oriented Ti film on the barrier film.
A semiconductor device comprising: a film; and a (111) -oriented Cu film on the Ti film. 3. The semiconductor device according to claim 1, wherein the (002) -oriented Ti film in the buried wiring is thick at the bottom of the wiring groove, thin on the side of the wiring, and not (002) -oriented. 4. A semiconductor device having a Cu wiring, wherein the Cu wiring is a (002) -oriented Ti film, a barrier film containing amorphous or microcrystals on the Ti film, and (Cu) on the barrier film. 111) A semiconductor device having an oriented Cu film. 5. A semiconductor device having a Cu wiring, wherein the Cu wiring is a barrier film containing amorphous or microcrystal, a (002) -oriented Ti film on the barrier film,
A semiconductor device having a (111) -oriented Cu film on an i film. 6. The barrier film containing amorphous or microcrystals is a titanium nitride film deposited by MOCVD, a tantalum nitride film or a tungsten nitride film deposited by sputtering or CVD. 6. The semiconductor device according to 2, 4, or 5. 7. A step of forming a wiring recess in an interlayer insulating film deposited on a semiconductor substrate; and forming a (002) oriented Ti film on the interlayer insulating film and the wiring recess. Ti
Forming a barrier film containing amorphous or microcrystals on the film, and forming a Cu film on the barrier film so that the wiring recesses are buried and (111) oriented. Manufacturing method of a semiconductor device. 8. The method of manufacturing a semiconductor device according to claim 7, further comprising a step of exposing the surface of the interlayer insulating film to Ar plasma before the step of forming the (002) oriented Ti film. 9. A step of forming a wiring recess in an interlayer insulating film deposited on a semiconductor substrate, and a step of forming a barrier film containing amorphous or microcrystal on the interlayer insulating film and the wiring recess. And (002) oriented T on the barrier film.
A method of manufacturing a semiconductor device, comprising: a step of forming an i-film; and a step of forming a Cu film on the Ti film so that the wiring recesses are buried and oriented (111). 10. The method according to claim 7, wherein, in the step of forming a (002) oriented Ti film, the Ti film is thick on the bottom of the wiring groove, thin on the side of the wiring and not (002) oriented. Method of Manufacturing Semiconductor Device 11. A step of forming a (002) oriented Ti film on an interlayer insulating film deposited on a semiconductor substrate, and a step of forming a barrier film containing amorphous or microcrystal on the Ti film. And forming a (111) -oriented Cu film on the barrier film. 12. The method according to claim 11, further comprising a step of exposing the surface of the interlayer insulating film to Ar plasma before the step of forming the (002) oriented Ti film. 13. A step of forming a barrier film containing amorphous or microcrystal on an interlayer insulating film deposited on a semiconductor substrate, and a step of forming a (002) oriented Ti film on the barrier film. And forming a (111) -oriented Cu film on the Ti film. 14. A barrier film containing amorphous or microcrystals is a titanium nitride film deposited by MOCVD, or a tantalum nitride film or tungsten nitride film deposited by sputtering or CVD. 14. The method for manufacturing a semiconductor device according to any one of claims to 13.