JP2000150531A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

[PROBLEMS] To provide a power semiconductor device capable of realizing a high breakdown voltage with a simple structure and a method of manufacturing the same. SOLUTION: A semiconductor device has a surface potential stabilization region 6 and an electric field relaxation region 7 around the main operation region. The second electrode contact region 4 is spaced apart from the first interface between the first electrode region 2 and the second electrode region 3 by a predetermined distance required for electric field relaxation, and the surface of the second electrode region 3 Is formed. The surface potential stabilizing region 6 extends from the second interface between the second electrode contact region 4 and the second electrode region 3 to the outer peripheral portion of the chip without any gap. The electric field relaxation region 7 is a semiconductor region 2 which is a part of the first electrode region 2.
E, a semiconductor region 3E which is a part of the second electrode region 3, and a semiconductor region 6E which is a part of the surface potential stabilizing region 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a novel structure for realizing a high breakdown voltage of a power semiconductor device (power device) and a method of manufacturing the power semiconductor device. About.

[0002]

2. Description of the Related Art FIG. 8 shows a conventional power semiconductor device as a power bipolar transistor (power BJ).
(T) shows a sectional structural view. In the power BJT shown in FIG. 8, a RESURF (Reduced SURface Field) is provided around the power BJT.
A region 8 is provided, and a channel stopper region 9 is further provided around the outer periphery of the RESURF region 8 to improve the withstand voltage.

The power BJT is of an npn type having each of an n-type collector region 2, a p-base region 3, and an n-type emitter region 5. The collector region 2 is a low impurity density n ⁻ type semiconductor region formed on the surface of the n ⁻ type semiconductor substrate 1S. The power BJT includes a semiconductor substrate 1S
The collector voltage V _C is supplied through the n ⁺ -type collector connection region (collector contact region) 1 having a high impurity density on the back surface side and the back surface electrode 10 provided on the back surface of the semiconductor substrate 1S. The base region 3 is formed of a p ^- type semiconductor region having a low impurity density on the surface of the collector region 2.
The base region 3, the surface formed base connection region of the base region 3 (base contact region) 4, the base voltage V _B is supplied through the respective base wiring 14. The base contact region 4 is formed of a p ⁺ type semiconductor region having a higher impurity density than the base region 3. The base wiring 14 is provided on the protective film 11 on the front surface side of the semiconductor substrate 1S, and is electrically connected to the base contact region 4 through a contact hole formed in the protective film 11. The base wiring 14 is formed of an aluminum film. An emitter voltage V _E is supplied to the emitter region 5 through the emitter wiring 12. The emitter region 5
It is formed on the surface of base contact region 4 and is formed of an n ⁺ type semiconductor region having a higher impurity density than collector region 2. The emitter wiring 12 is formed in the same conductive layer and the same conductive material as the base wiring 14, and is electrically connected to the emitter region 5 through the contact hole of the protective film 11.

The RESURF region 8 is electrically connected to the side surface of the base region 3 and is disposed so as to surround the base region.
The p-type semiconductor region has a lower impurity density than the contact region 4. When the pn junction between the collector region 2 and the base region 3 of the power BJT is reverse-biased, the RESURF region 8 expands a depletion layer extending from the pn junction interface to the outer periphery (horizontal direction). In particular, it has a function of reducing the electric field concentration at the pn junction in the peripheral portion of the power BJT and improving the junction breakdown voltage.

That is, a high voltage which acts as a reverse bias is applied between the pn junctions, and the collector region 2
A depletion layer extends in each of the base regions 3. Similarly, RE
A high voltage is also applied to each of the SURF region 8 and the collector region 2, and a depletion layer spreads to each of the RESURF region 8 and the collector region 2 from the pn junction interface between them. These two depletion layers are integrated, and the electric field applied between the collector region 2 and the base region 3 is dispersed. As a result, the power BJ
Electric field concentration in the periphery of T is reduced, and a high breakdown voltage can be realized.

[0006] The channel stopper region 9 is formed in the RESURF region 8.
The outer periphery is formed on the surface of collector region 2 (BJT operation is not performed in this region) separated from RESURF region 8, and is formed of an n-type semiconductor region having a higher impurity density than collector region 2. Have been. A fixed voltage is supplied to the channel stopper region 9 through the power supply wiring 16, and the channel stopper region 9 is
It has a function as a guard ring for stabilizing the potential of the surface.

[0007]

In the power semiconductor device provided with the power BJT, no consideration is given to the following points.

First, in order to realize a high breakdown voltage, the base region 3 is located between the power BJT and the channel stopper region 9.
And a RESURF region different from the base contact region 4 (p
Type semiconductor region) 8 is required. Therefore, there is a problem that the number of semiconductor regions formed on the semiconductor substrate 1S increases and the structure becomes complicated.

Second, RESURF for realizing high breakdown voltage.
The region 8 is formed by a different manufacturing process from each of the base region 3 and the base contact region 4 of the power BJT. Therefore, the number of steps for forming the RESURF region 8 increases,
There is a problem that the number of manufacturing steps of the entire power semiconductor device increases.

Third, since the RESURF region 8 and the power BJT base region 3 and base contact region 4 are formed in different manufacturing steps, alignment between masks in the photolithography step (mask alignment) ) Is required. Similarly, mask alignment is required between the RESURF region 8 and the channel stopper region 9.
For this reason, it is necessary to secure an alignment allowance dimension on the planar pattern, and there is a problem that miniaturization of the power semiconductor device is hindered.

Fourth, there has been a problem that the mask alignment work increases in the manufacturing process of the power semiconductor device, and the productivity of the power semiconductor device decreases.

The present invention has been made to solve the above problems. Accordingly, a first object of the present invention is to provide a power semiconductor device capable of achieving a high breakdown voltage with a simple structure.

A second object of the present invention is to provide a method for manufacturing a power semiconductor device which can reduce the number of manufacturing steps while achieving the first object.

A third object of the present invention is to provide a method of manufacturing a power semiconductor device capable of realizing miniaturization by eliminating unnecessary dimensions required for a mask alignment margin while achieving the second object. To provide.

A fourth object of the present invention is to reduce the number of steps requiring mask alignment while eliminating the complexity of manufacturing and improving the productivity while achieving the third object. An object of the present invention is to provide a method for manufacturing a power semiconductor device that can be used.

[0016]

In order to solve the above problems, the present invention provides a first conductive type first electrode region having an outer peripheral portion, and a second conductive type first electrode region disposed on the surface of the first conductive type. The second electrode region is separated from the first interface between the first electrode region and the second electrode region by a predetermined distance required for electric field relaxation, and is formed on the surface of the second electrode region. On the surface of the second conductive type second electrode contact region, the first electrode region and the second electrode region, the second electrode contact region and the second
A semiconductor device comprising at least a surface potential stabilizing region having a higher impurity density than the first electrode region and extending from the second interface with the electrode region to the outer periphery without any gap. This is the first feature. Here, the “peripheral portion” corresponds to an end face of a chip or a wafer.
The “first conductivity type” and the “second conductivity type” are opposite conductivity types. For example, if the first conductivity type is n-type, the second conductivity type is p-type, and if the first conductivity type is p-type, the second conductivity type is
It is n-type. The “predetermined distance required for electric field relaxation” means, for example, 200 to realize a withstand voltage of 1700 V.
It may be about μm.

In the semiconductor device according to the first aspect of the present invention, the second electrode region located between the first and second interfaces on the plane pattern can be an electric field relaxation region. That is, if the region where the main current of the semiconductor device flows is defined as the “main operation region”, the electric field relaxation region can be formed using the peripheral region of the main operation region. When a reverse bias is applied to the pn junction formed by the first electrode region and the second electrode region due to the presence of the electric field relaxation region, the depletion layer expands in the electric field relaxation region having a low impurity density, and the outer peripheral edge of the pn junction is reduced. The electric field strength can be reduced. As a result, a high breakdown voltage of the semiconductor device, particularly, the power semiconductor device can be realized.

Further, in the semiconductor device according to the first feature of the present invention, it is necessary to separately configure a dedicated semiconductor region used only for electric field relaxation, such as the RESURF region described in the related art. do not do. That is, an electric field relaxation region can be constructed using a part of the second electrode region necessary for the operation of the semiconductor device, and a high breakdown voltage can be realized with a simple structure. Further, in the power semiconductor device thus configured, since the surface potential stabilization region is formed around the outer periphery of the main operation region, it is possible to further increase the breakdown voltage of the main operation region.

In the first aspect of the present invention, it is preferable that a distance between the first and second interfaces, that is, a predetermined distance required for electric field relaxation is larger than a junction depth of the second electrode region. . When the reverse bias is applied to the pn junction formed by the first and second electrode regions by sufficiently increasing the predetermined distance required for the electric field relaxation, the depletion layer spreads more smoothly due to the electric field relaxation region, and a higher This is because it is possible to withstand pressure. More preferably, the configuration may be such that the impurity density of the electric field relaxation region gradually decreases as the distance from the second interface increases.

The above structure can be understood as a diode structure, for example, assuming that the first electrode region is a cathode region and the second electrode region is an anode region. Alternatively, it can be understood as a diode structure in which the first electrode region is a cathode region and the second electrode region is an anode region. However, the first feature of the present invention is not limited to this diode structure, but may include various semiconductor device structures based on this diode structure. For example, the semiconductor device further includes a third electrode region of the first conductivity type formed on at least a part of the surface of the second electrode contact region, and the junction depth of the third electrode region is larger than the junction depth of the surface potential stabilizing region. If it is made deeper, a bipolar transistor (BJT) can be formed. In this case, the first electrode region is the collector region, the second electrode region is the base region, and the third electrode region is the third region.
The electrode region becomes the emitter region. Alternatively, the first electrode region is an emitter region, the second electrode region is a base region, and the third electrode region is a collector region.

In the semiconductor device according to the first aspect of the present invention, a second electrode contact region is formed having a plurality of holes, and a first conductive type third electrode region is formed inside the plurality of holes. If the junction depth of the third electrode region is made larger than the junction depth of the surface potential stabilization region, an electrostatic induction transistor (SIT) can be formed. In this case, the first electrode region is a drain region, the second electrode contact region is a gate region, and the third electrode region is a source region. Alternatively, the first electrode region is a source region, the second electrode contact region is a gate region, and the third electrode region is a drain region.

Further, in the structure of the BJT, the first
If a fourth electrode region of the second conductivity type is further provided below the electrode region, a gate turn-off (GTO) thyristor can be formed. In this case, the first conductivity type is n-type,
If the second conductivity type is p-type, the first electrode region is an n base region, the second electrode region is a p base region, the third electrode region is a cathode region, and the fourth electrode region is an anode region. If the conductivity types are all reversed, the first electrode region becomes the p base region, the second electrode region becomes the n base region, the third electrode region becomes the anode region, and the fourth electrode region becomes the cathode region. Alternatively, in the SIT structure, the second electrode
If it is configured to further have a conductive type fourth electrode region,
An electrostatic induction thyristor (SI thyristor) can be configured.
In this case, if the first conductivity type is n-type and the second conductivity type is p-type, the first electrode region is a channel region, the second electrode contact region is a gate region, the third electrode region is a cathode region,
The electrode region becomes the anode region. If the conductivity types are all reversed, the first electrode region becomes the channel region, the second electrode contact region becomes the gate region, the third electrode region becomes the anode region, and the fourth electrode region becomes the cathode region.

A second feature of the present invention is a step of selectively forming a second conductive type second electrode region on a part of the surface of a first conductive type semiconductor substrate serving as a first electrode region; The surface of the second electrode region is separated from the first interface between the first electrode region and the second electrode region by a predetermined distance required for electric field relaxation,
Forming a second electrode contact region having a second conductivity type with a higher impurity density than the second electrode region, and substantially all of the surface of the semiconductor substrate, the surface of the second electrode region, and the surface of the second electrode contact region; And introducing an impurity having an impurity density higher than that of the semiconductor substrate and the second electrode region and lower than that of the second electrode contact region into the substantially exposed surface of the semiconductor substrate and the second electrode region. Forming a surface potential stabilizing region selectively on the surface of the semiconductor device. here,
The term “substantially exposed” means that an unintended thin film such as a natural oxide film or an intentionally formed thin film such as a so-called “dummy oxide film (buffer oxide film)” used during ion implantation is allowed. It is. In other words, even if there are some very thin films on the surface of the semiconductor substrate, if impurities such as ion implantation can be introduced through these thin films,
It should be noted that here, "substantially exposed" should be understood.

According to the second feature of the present invention, a part of the second electrode region necessary for the operation of the semiconductor device can be made to function as an electric field relaxation region. A step for separately forming a semiconductor region dedicated to relaxation is not required. For this reason, the number of manufacturing steps can be reduced. Further, by introducing impurities into the entire surface of the semiconductor substrate, the surface potential stabilizing region can be selectively formed in the second region and the third region in a self-aligned manner. That is, the surface potential stabilizing region formed on the surface of the second region does not need to consider the margin for alignment with the second electrode contact region. Therefore, the planar pattern structure of the power semiconductor device can be easily miniaturized, and the manufacturing complexity due to the alignment can be further reduced. As a result, the productivity of the power semiconductor device can be improved.

The above-described method for manufacturing a semiconductor device can be considered as a method for manufacturing a diode, for example, when the first electrode region is regarded as a cathode region and the second electrode region is regarded as an anode region. However, the second feature of the present invention can include a method of manufacturing various semiconductor devices based on the diode structure. That is, in the second aspect of the present invention, after the step of forming the second electrode contact region, the step of further forming a third electrode region of the first conductivity type on at least a part of the surface of the second electrode contact region. If you have
A bipolar transistor can be manufactured. In this case, the first
The electrode region is a collector region, the second electrode region is a base region,
The third electrode region becomes an emitter region. Alternatively, the first electrode region is an emitter region, the second electrode region is a base region, and the third electrode region is a collector region.

[0026]

Next, first to fourth embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic,
It should be noted that the relationship between the thickness and the plane dimension, the ratio of the thickness of each layer, and the like are different from actual ones. Therefore,
Specific thicknesses and dimensions should be determined in consideration of the following description. In addition, it goes without saying that parts having different dimensional relationships and ratios are included between the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
FIG. 3 is a cross-sectional structural view of a power bipolar transistor (power BJT) as a power semiconductor device according to the embodiment. As shown in FIG. 1, in a power BJT according to the first embodiment of the present invention, a surface potential stabilizing region (guard ring region or equipotential ring region) 6 is provided over the entire outer periphery of the main operation region. In addition, an electric field relaxation region 7 is further provided in a part of the outer periphery. The “main operation region” of the power semiconductor device is an active region where a main current flows near the center of the semiconductor chip. By using the electric field relaxation region 7 outside the main operation region, the junction breakdown voltage of the power BJT, particularly the junction breakdown voltage at the peripheral portion of the chip can be improved. The semiconductor region for improving the withstand voltage is formed using an electrode region necessary for the main operation of the power BJT, and furthermore, a surface potential stabilizing region 6 is formed.
It is built by adding

The power BJT has the same basic structure as the power BJT shown in FIG. 8, and has a first conductivity type first electrode region (n-type collector region) 2 having an outer peripheral portion (chip end surface). The second electrode region (p base region) 3 of the second conductivity type disposed on the surface of the first electrode region and the first interface between the first electrode region 2 and the second electrode region 3 reduce the electric field. The surface of the second conductive type second electrode contact region (base contact region) 4 and the surface of the second electrode contact region 4 formed on the surface of the second electrode region 3 while being spaced inward by a necessary predetermined distance L1. The first formed on at least a part of
N having a conductive third electrode region (n-type emitter region) 5
It is composed of pn type.

The collector region 2 is a low impurity density n ⁻ type semiconductor region utilizing a part of the surface of the n ⁻ type semiconductor substrate 1S. Actually, only the central portion (the portion overlapping the emitter region 5) functions as the collector region (active collector region) 2 of the main operation region. Since the collector region 2 is formed with a low impurity density, the base region 3
And the junction withstand voltage of the pn junction formed between them can be improved. When a predetermined operating voltage is applied between the emitter electrode 12 and the collector electrode 10, if the active collector region 2 is almost completely depleted, the collector region 2 functions as a drift region. The collector region 2 is connected to a collector contact region 1 which is an n ⁺ -type semiconductor region having a high impurity density. This collector contact region 1 is a region on the back surface side of the semiconductor substrate 1S. collector·
A back surface electrode (collector electrode) 10 is further connected to the contact region 1 by ohmic contact. Then, a collector voltage V _C is supplied to the back electrode (collector electrode) 10. Collector contact area 1
Are formed with a high impurity density, and the resistance value of the collector contact region 1 itself is set low. As a result, the ohmic contact resistance between the collector contact region 1 and the back electrode 10 can be set low.
For example, a titanium (Ti) film, nickel (N
i) A composite film obtained by sequentially laminating a film, a palladium (Pd) film, and a silver (Ag) film can be used practically.

The base region 3 is formed on the surface of the collector region 2 by a p ^- type semiconductor region having a low impurity density. Since the base region 3 has a low impurity density, the junction breakdown voltage between the base region 3 and the collector region 2 can be improved as described above. The base region 3, the base region base contact region 4 is formed so as to expose the surface of 3, the base voltage V _B is supplied through the respective base wiring 14. Base contact area 4 is base area 3
It is formed of a p ⁺ -type semiconductor region having a higher impurity density than that of the first embodiment, and the resistance value of the base contact region 4 itself is set low. Further, the resistance of the ohmic contact between the base contact region 4 and the base wiring 1B is set low by using a p ⁺ -type semiconductor region having a high impurity density.
The base wiring 14 is formed on the protective film 1 on the front side of the semiconductor substrate 1S.
1 and is connected to the base contact region 4 through ohmic contact through a contact hole (not shown) formed in the protective film 11. For example, Al—Si or Al—Cu—S
An aluminum alloy film such as i can be used practically.

Emitter region 5 is formed on the surface of base contact region 4 and is formed of an n ⁺ type semiconductor region having a higher impurity density than collector region 2. First of the present invention
In this embodiment, the emitter region 5 is formed in a lattice shape when viewed in plan, and the outer periphery of the emitter region 5 is surrounded by the base contact region 4 except for the surface. The emitter region 5 is formed as a plurality of island regions arranged in a matrix or in a staggered manner in the base contact region 4 when viewed in a plan view.
May be formed so as to be exposed in a lattice shape when viewed two-dimensionally. An emitter voltage V _E is supplied to the emitter region 5 through the emitter wiring 12. Emitter wiring 1
2 is formed in the same conductive layer and the same conductive material as the base wiring 14 and is connected to the emitter region 5 through ohmic contact with the contact hole of the protective film 11.

The surface potential stabilizing region 6 is formed in a peripheral region of the surface of the collector region 2 which is not substantially used as power BJT. This surface potential stabilization region 6
Is formed of an n-type semiconductor region having a higher impurity density than the collector region 2 and a lower impurity density than each of the collector / contact region 1 and the emitter region 5. Further, the surface potential stabilizing region 6 includes the emitter region 5
Formed at a depth shallower than the junction depth. A fixed voltage is supplied to the surface potential stabilizing region 6 through the surface potential stabilizing wiring 15, so that the potential of the surface of the collector region 2 can be stabilized. The surface potential stabilizing wiring 15 is formed of the same conductive layer and the same conductive material as each of the base wiring 14 and the emitter wiring 12 described above.

The power B according to the first embodiment of the present invention
What is important in JT is the electric field relaxation region 7 shown in FIG. The electric field relaxation region 7 is a low impurity density n ⁻ -type semiconductor region 2 formed sequentially from the lower layer to the upper layer in FIG.
E, it can be understood that the semiconductor device is constructed by joining the p ^- type semiconductor region 3E having a low impurity density and the n-type semiconductor region 6E having a medium impurity density. The low impurity density p ⁻ -type semiconductor region 3E of the electric field relaxation region 7 corresponds to the RESURF region 8 of the power semiconductor device shown in FIG.
The electric field in the peripheral portion of the power BJT can be reduced, and the junction breakdown voltage can be improved.

The semiconductor region 2E is formed as a part of the collector region 2 of the power BJT, and is formed so as to surround the outer periphery of the collector region (active collector region) 2 through which a main current flows. In other words, the semiconductor region 2E utilizes a portion (extending portion) of the active collector region 2 of the power BJT drawn out to the outer periphery.

The semiconductor region 3E is formed as a part of the base region 3 of the power BJT, and is formed so as to surround the outer periphery of the base region (active base region) 3 through which a main current flows. Similarly to the semiconductor region 2E, the semiconductor region 3
E utilizes a portion where the active base region 3 of the power BJT is actively drawn out to the outside. The width dimension L1 of the semiconductor region 3E, more specifically, the leading dimension from the interface between the base region 3 and the base contact region 4 (second interface) to the interface between the base region 3 and the collector region 2 (first interface). (Lateral diffusion distance of base region 3) L1
Is set to be longer than the lead-out dimension L3 of the base region 3 of the power BJT according to the related art (see FIG. 8). Generally, the base region 3 of the power BJT shown in FIG.
Is a dimension as small as a margin for mask alignment, for example, a value of about 5 μm. Of course, the drawing dimension (lateral diffusion distance of the base region 3) L2 from the emitter region 5 to the first interface of the semiconductor region 3E shown in FIG.
Is set longer than the lead-out dimension L4 of the base region 3 of the power BJT shown in FIG.

That is, the width dimension L1 of the semiconductor region 3E of the electric field relaxation region 7 according to the first embodiment of the present invention is set as long as possible in order to improve the junction breakdown voltage within a range that does not hinder the degree of integration. It is. Preferably, width L1 of semiconductor region 3E is set to be larger than junction depth D1 of semiconductor region 3E (FIG. 8).
Drawn out L3 of base region 3 of power BJT shown in FIG.
Is set smaller than the junction depth D2 of the base region 3). In the first embodiment of the present invention, the width L1 of the semiconductor region 3E is set to, for example, 150 μm.
When the junction depth D1 is set to 15 μm to 90 μm, the withstand voltage of the power BJT (base
The withstand voltage between the collectors can be made closer to the ideal withstand voltage (plane withstand voltage), and even if the thickness of the collector region 2 is set to 450 μm or less, almost the ideal withstand voltage can be obtained.

The semiconductor region 6E includes the surface potential stabilizing region 6
And is formed along the inner periphery of the surface potential stabilizing region 6. As in the case of each of the semiconductor regions 2E and 3E, the semiconductor region 6E is formed of a semiconductor region of the same layer (same) as the surface potential stabilization region 6, and the surface potential stabilization region 6 is actively formed around the inside. This is the one that uses the part drawn out. This semiconductor region 6E
The power BJT can be formed in a self-aligned manner for each of the base region 3, the base contact region 4, and the surface potential stabilizing region 6 without mask alignment.

In the power semiconductor device thus configured, when a high reverse bias voltage is applied between the collector region 2 and the emitter region 5 of the power BJT, the collector region 2 and the base region 3 The depletion layer spreads at each of the pn junction between the base region 3 and the emitter region 5. Similarly, in the electric field relaxation region 7 arranged around the periphery of the power BJT, the semiconductor region 2E
A high voltage is applied between the semiconductor region 6E and the semiconductor region 6E, and a depletion layer spreads at each of the pn junction between the semiconductor region 2E and the semiconductor region 3E and the pn junction between the semiconductor region 3E and the semiconductor region 6E. . The depletion layer of the power BJT and the depletion layer of the electric field relaxation region 7 are respectively coupled, and the pn of the power BJT is
Since the electric field applied to the junction can be dispersed in the electric field relaxation region 7, the electric field concentration around the power BJT can be reduced. As a result, the junction breakdown voltage of the power BJT can be significantly improved.

Further, the semiconductor region 3E of the electric field relaxation region 7
Is formed as a portion where the active base region 3 of the power BJT is drawn out in the lateral direction (portion diffused in the lateral direction). The semiconductor region 3E extends from the main operation region side toward the surface potential stabilizing region 6. It has a profile (concentration gradient) in which the impurity density gradually decreases. That is, in the electric field relaxation region 7, the spread of the depletion layer at the pn junction increases smoothly in the same direction, and the electric field intensity can be gradually reduced, so that the electric field concentration can be favorably alleviated. Thus, the junction breakdown voltage of the power BJT can be further improved.

Further, a surface potential stabilizing region 6 is provided around the periphery of the power BJT, and in particular, the potential of the semiconductor region 6E of the electric field relaxation region 7 can be stabilized. The power BJT according to the embodiment can stably improve the junction breakdown voltage.

Next, a method for manufacturing the above-described power semiconductor device will be described. 2 (A), 2 (B), 3 (C), and 3 (D) show a power semiconductor showing a method of manufacturing a power BJT according to the first embodiment of the present invention for each step. It is a process sectional view of an apparatus.

[0042] (1) First, the impurity density of 5 × 10 ¹² ~
N composed of a single crystal silicon substrate of about 5 × 10 ¹⁴ atoms / cm ^3
- Prepare a type semiconductor substrate 1S. Then, as shown in FIG. 2A, a first electrode contact region (collector contact region) 1 is formed on the rear surface side of the n ⁻ type semiconductor substrate 1S by introducing an n type impurity. The collector / contact region 1 is set to have an impurity density of, for example, about 10 ¹⁸ to 10 ²⁰ atoms / cm ³ . Not the first electrode contact region (collector contact region) 1 formed, n ^- -type remainder of the semiconductor substrate 1S, i.e., n ^- surface side of the mold the semiconductor substrate 1S is the first electrode region (collector region) 2 . FIG.
In (A), the surface of the semiconductor substrate 1S at the central portion (hereinafter, this area on the planar pattern is referred to as “first area TA”).
Is a portion used as an active collector region 2 through which a main current flows after completion. In addition, a region where the electric field relaxation region 7 is to be formed (hereinafter, this region on the plane pattern is referred to as “second region”).
Area 7A ". ) Is a pseudo collector region 2 through which a main current hardly flows, and is a portion called “semiconductor region 2E” in the above.

(2) Thereafter, a thermal oxide film (first thermal oxide film) having a thickness of about 350 nm to 1 μm is formed on the surface of the collector region 2. Then, a photoresist pattern is formed on the thermal oxide film by a known photolithography process. This photoresist pattern is a mask for forming the second electrode region (base region) 3 and the second electrode contact region (base contact region) 4. Using this photoresist pattern, the thermal oxide film is removed by etching using a predetermined oxide film etching solution such as an ammonium fluoride (NH ₄ F) solution.
An impurity introduction mask (first impurity introduction mask) 55 shown in FIG. The first impurity introduction mask 55 may be formed by removing the thermal oxide film by dry etching such as reactive ion etching (RIE). After the thermal oxide film is removed by etching, the pattern of the photoresist is removed. Using the first impurity introduction mask 55 having the first region TA as an opening, p-type impurity ions such as ¹¹ B ⁺ are implanted at an acceleration energy of 350 KeV to 100 KeV and a dose of 1 × 10 ^{13 to} 5 × 10 ¹⁴ ions / cm 2. Ion implantation is performed in about ² (first ion implantation step). Then 110
Heat treatment (first drive-in) is performed at a diffusion temperature of about 0 ° C. to 1200 ° C. for a predetermined time in a non-oxidizing atmosphere or a quasi-non-oxidizing atmosphere containing a small amount of oxygen. That is, by this first drive-in, no oxide film is formed on first region TA, or an extremely thin oxide film is formed. Then, using the same first impurity introduction mask 55, at an acceleration energy of 80 to 30 KeV.
P-type impurity ions such as ¹¹ B ⁺ or ⁴⁹ BF ₂ ⁺ are implanted at a dose of about 1 × 10 ^{15 to} 5 × 10 ¹⁶ ions / cm ² (second ion implantation step). Thereafter, from 900 ° C. to 115
Heat treatment (second drive-in) is performed at a diffusion temperature of about 0 ° C. for a predetermined time in a non-oxidizing atmosphere, a quasi-non-oxidizing atmosphere containing a small amount of oxygen, or an oxidizing atmosphere. As a result,
As shown in FIG. 2B, in the first region TA, the surface of the collector region 2 has an impurity density of 4 × 10 ¹³ to 8 × 10 ¹⁴ atoms /.
A second electrode region (base region) 3 composed of ap ⁻ type semiconductor region of about cm ³ is formed, and a first interface between the first electrode region and the second electrode region is formed on the surface of the base region 3. At a predetermined distance (distance corresponding to the second region 7A) L1 from the substrate, and an impurity density of 8 × 10 ^{18 to} 5 × 10 ²⁰ atoms / cm ^3.
A second electrode contact region (base contact region) 4 composed of a p ⁺ type semiconductor region is formed. This second
The electrode region (base region) 3 and the second electrode contact region (base contact region) 4 are formed by vapor-phase diffusion using a solid source such as boron nitride (BN) or a liquid source such as (BBr ₃ ). -Deposition may be performed. It is also possible to carry out the method by a combination of the ion implantation method and the gas phase diffusion method. As mentioned above,
In the present invention, the base region 3 from the second interface between the second electrode contact region 4 and the second electrode region 3 to the first interface is referred to as “p ⁻ type semiconductor region 3E”. And The p ⁻ type semiconductor region 3E is a region that functions as the electric field relaxation region 7. Due to the nature of thermal diffusion, the semiconductor region 3E is generally a portion drawn laterally from the base contact region 4 so as to have a width L1 0.7 to 0.8 times the junction depth D1. (A part diffused in the lateral direction). As a matter of course, the semiconductor region 3E is formed with an impurity density substantially equal to that of the active base region 3 serving as the first region TA on the planar pattern. In this manner, the second electrode region (base region) 3 and the second electrode contact region (base contact region) 4 can be formed using the same first impurity introduction mask 55.
The mask alignment step can be omitted.

(3) First area TA after second drive-in
If the thickness of the oxide film formed thereon is small, a thermal oxidation step is further added, and a thickness of 350 nm to 75 nm is formed on the first region TA.
A thermal oxide film of about 0 nm is formed. At this time, the oxide film including the oxide film (first thermal oxide film) formed as the impurity introduction mask 55 is once removed entirely, and the entire surface is formed to a thickness of 350 nm.
New thermal oxide film (second thermal oxide film) of about 750 nm
56 may be formed. Then, a photoresist pattern is formed on the second thermal oxide film 56 by a known photolithography process. This photoresist pattern is a mask for forming the third electrode region (emitter region) 5. Using this photoresist pattern, a thermal oxide film 5 is formed by dry etching such as RIE.
6 is removed by etching. If there is room in the plane pattern, the thermal oxide film may be removed by wet etching using an ammonium fluoride (NH ₄ F) solution or the like. Thus, an impurity introduction mask (second impurity introduction mask) is formed by the second thermal oxide film 56, and the acceleration energy is 35 KeV.
An n-type impurity ion such as ⁷⁵ As ^{+ is} implanted at a dose of about 3 × 10 ^{15 to} 5 × 10 ¹⁶ ions / cm ² at a temperature of about 80 KeV (third ion implantation step). Thereafter, 800 ° C to 950
Heat treatment (third drive-in) is performed at a diffusion temperature of about ° C for a predetermined time. As a result, for example, 3 × 10 ¹⁸ to 1 × 10 ²¹ atom
An emitter region 5 having an impurity density of about s / cm ³ is formed. By the steps so far, the main operation section of the power BJT is substantially completed. Note that the third electrode region (emitter region) 5 may be formed by a gas phase diffusion method using a solid source or a liquid source.

(4) The oxide film on the entire surface of the semiconductor substrate 1S, including the third thermal oxide film formed after the third drive-in, is removed by using a predetermined oxide film etching solution such as an NH ₄ F solution. I do. Then, n-type impurity ions such as ⁷⁵ As ⁺ are implanted into the entire surface of the semiconductor substrate 1S at an acceleration energy of 35 to 80 KeV at a dose of about 1 × 10 ¹³ to 1 × 10 ¹⁵ ions / cm ² (fourth ion implantation step). ). At this time 5
Ions may be implanted after a dummy oxide film of 0 nm to 150 nm is formed on the entire surface. Thereafter, heat treatment (fourth drive-in) is performed in an oxidizing atmosphere at a diffusion temperature of about 800 ° C. to 950 ° C. for a predetermined time. The diffusion depth of the n-type impurity in the fourth drive-in is selected to be smaller than the junction depth of the emitter region 5 in the third drive-in.
As a result, as shown in FIG. 3 (D), for example, 5 × 10 ¹³ ~
An n-type surface potential stabilizing region 6 having an impurity density of about 1 × 10 ¹⁵ atoms / cm ³ is formed. This surface potential stabilization region 6
As shown in FIG. 3 (D), it can be considered that the second region GA is composed of two portions, that is, a third region GA which is the outer periphery of the second region 7A and an n-type semiconductor region 6E. It can be easily understood that the formation of the surface potential stabilizing region 6 may be performed by a gas phase diffusion method using a solid source or a liquid source. Since the n-type impurity is introduced into the entire surface of the semiconductor substrate 1S at an intermediate impurity density, the amount of the n-type impurity dominant on the surface (n ⁻ -type semiconductor region) of the semiconductor substrate 1S is set to n-type, Similarly, in the semiconductor region 6E formed in the semiconductor region 3E (p ^- type semiconductor region), the introduction amount of the n-type impurity is dominant, and the conductivity type is inverted from p-type to n-type. Conversely, in the base contact region (p ⁺ type semiconductor region) 4
Since the original impurity density is higher than the introduced amount of the n-type impurity, the conductivity type is not inverted and is maintained at the p-type. Similarly, in the emitter region 5, the conductivity type does not change because the original impurity density is higher than the introduced amount of the n-type impurity.
Maintained as n-type. The diffusion depth of the surface potential stabilization region 6 due to the fourth drive-in is selected to be shallower than the junction depth of the emitter region 5 due to the third drive-in. The presence does not affect the electrical characteristics of the completed power BJT. That is, the n-type impurity is introduced into the entire region of the semiconductor substrate 1S, but is 5 × 10 ¹³ to 1 × 10 ¹⁵ atoms /
Since the impurity concentration is set to an intermediate density of about ³ cm ³ , the surface potential stabilizing region 6 is formed in the third region GA around the power BJT.
And at the same time, the semiconductor region 6E functioning as the electric field relaxation region 7 can be selectively formed in the second region 7A. In addition, the semiconductor region 6E of the surface potential stabilizing region 6 and the semiconductor region 6E of the electric field relaxing region 7 can be formed in alignment with each of the base region 3 and the base contact region 4 in a self-aligned manner without any alignment margin. .

(5) Next, a protective film 11 is formed on the entire surface of the semiconductor substrate 1S by a thermal oxidation method. Protective film 11
It is also possible to employ an oxide film (SiO ₂ film) formed by the CVD method. Then, a photoresist pattern is formed on the protective film 11 by a photolithography process. The pattern of this photoresist is
1 is a mask for opening a contact hole inside. Using this photoresist pattern, only a predetermined portion of the protective film 11 is selectively etched away by dry etching such as RIE or ECR ion etching to open a contact hole. Then, Al-Si,
Alternatively, an aluminum alloy film of Al—Cu—Si or the like is deposited to a thickness of 0.4 μm to 10 μm by using a sputtering method, an electron beam (EB) evaporation method, or the like. Then, a pattern of a photoresist is formed on the aluminum alloy film by a photolithography process, and is patterned by dry etching such as RIE. As a result, the emitter wiring 12, the base wiring 14, and the surface potential stabilizing wiring 15 are formed as shown in FIG. Further, these emitter wiring 12 and base wiring 1
A final protective film 13 such as an oxide film (SiO ₂ film), a PSG film, a BPSG film, or a silicon nitride film (Si ₃ N ₄ film) is formed on the surface 4 and the surface potential stabilizing wiring 15 by a CVD method. . Further, a titanium (Ti) film,
A collector electrode 10 is formed by sequentially laminating a nickel (Ni) film, a palladium (Pd) film, and a silver (Ag) film using a sputtering method or an EB vapor deposition method. Then, an opening is further formed in the final protective film 13 for bonding, the package is mounted on a predetermined package, and a predetermined assembly process such as a resin mold is performed. The semiconductor device is completed.

In order to make the width dimension L1 larger than the junction depth D1 of the semiconductor region 3E, a method of oblique ion implantation using a high acceleration energy of 1 MeV to 3 MeV in the first ion implantation step is adopted. it can. At this time, in the second ion implantation step, vertical ion implantation may be performed with low acceleration energy. Alternatively, even in the steps shown in FIGS. 4A and 4B, the width L1 can be made larger than the junction depth D1 of the semiconductor region 3E. That is, (a) First, after performing the first ion implantation process using the first impurity introduction mask 55, a predetermined first drive-in is performed. Then, as shown in FIG. 4A, after this first drive-in, a composite film 57 made of any one of polycrystalline silicon (polysilicon), an oxide film, a nitride film, etc., or a combination thereof is formed to a thickness of 0.8 μm. It is deposited over the entire surface with a thickness of about 2 μm (the thickness is selected depending on the reduction width of the area of the opening).

(B) Thereafter, as shown in FIG.
If directional etching such as RIE is performed on the composite film 57, the side wall portion 58 having a width of about 0.8 μm to 2 μm remains inside the first impurity introduction mask 55. Therefore, the area of the opening of the mask for the second ion implantation step can be made smaller than the area of the opening of the mask for the first ion implantation step in a self-aligned manner. This self-aligned side wall portion 58
Using the and the first impurity introduction mask 55 as a mask, a second ion implantation step is performed. Then, after the second ion implantation step, if a predetermined second drive-in is performed, the junction depth D
The width L1 can be made larger than 1.

Note that the junction depth D1 of the base region 3 is 10
If it is necessary to ensure that the width L1 of the electric field relaxation region 7 is sufficiently larger than the junction depth D1, the thickness of the side wall portion 58 shown in FIG. Must be extremely thick. Therefore, in such a case, by using separate impurity introduction masks,
It is easier to form the base region 3 and the base contact region 4. For example, when the width dimension L1 of the electric field relaxation region 7 is set to 100 μm and the junction depth D1 is set to 40 μm, the thickness of the side wall 58 is 100−40 × 0.8 = 6.
About 8 μm is required. In such a case, it is preferable to use different impurity introduction masks. Further, if the width dimension L1 is large, the margin for mask alignment is sufficiently secured. Therefore, there is no need to form the base region 3 and the base contact region 4 in a self-aligned manner, so that no inconvenience occurs.

Even if the base region 3 and the base contact region 4 are formed using different impurity introduction masks as described above, these regions are essential for the main operation of the semiconductor device. It does not mean that the number has increased. At least, it should be noted that the number of steps can be reduced as compared with a manufacturing method in which a dedicated semiconductor region for electric field relaxation, such as the RESURF region in the related art, is separately configured. is there.

Also, without forming the surface potential stabilizing region 6 in a self-aligned manner, a mask alignment step is adopted by forming a photoresist pattern on the third thermal oxide film formed after the third drive-in. It may be possible to do it. In this case, the process is performed as follows using a mask (photoresist pattern) to form the surface potential stabilizing region 6.

First, using the mask, dry etching or wet etching is used to form second and third thermal oxide films other than the first region TA (where the first thermal oxide film is other than the first region TA). If it remains in the portion, the first thermal oxide film is removed as well, of course).

Next, a third impurity introduction mask composed of a composite film of an oxide film and a photoresist is formed while leaving the photoresist pattern used for the etching as it is.

Then, n-type impurity ions may be implanted using the third impurity introduction mask.

However, the above method is not a preferable method because the steps become complicated and a pattern shift cannot be avoided.

That is, as described above, the semiconductor region 6E of the electric field relaxation region 7 is formed in self-alignment with each of the base contact region 4 and the surface potential stabilization region 6 of the power BJT. The advantageous effects of the present invention can be obtained. Thus, the first aspect of the present invention
According to the embodiment, miniaturization of a power semiconductor device can be realized. Since the manufacturing complexity caused by the mask alignment can be reduced, the productivity of the power semiconductor device can be improved.

(Second Embodiment) The present invention can be applied to a high breakdown voltage diode. That is, FIG. 5 shows a sectional structural view of a high breakdown voltage diode as a power semiconductor device according to the second embodiment of the present invention. This high breakdown voltage diode has a common part in the basic structure with the power BJT shown in FIG.

That is, as shown in FIG. 5, the high breakdown voltage diode according to the second embodiment of the invention has a first conductivity type first electrode region (cathode region) 22 having an outer peripheral portion (chip end surface). The second electrode disposed on the surface of the first electrode region
The conductive type second electrode region (anode region) 23 is separated from the first interface between the first electrode region 2 and the second electrode region 3 by a predetermined distance L1 required for electric field relaxation. It is configured to have at least a second electrode contact region (anode contact region) 24 of the second conductivity type formed on the surface of the two-electrode region 3. Further, a first electrode contact region (cathode contact region) 21 of the first conductivity type and having a higher impurity density than the first electrode region (cathode region) 22 is disposed below the first electrode region (cathode region) 22. Have been. An anode electrode 25 is connected to the second electrode contact region (anode contact region) 24, and a cathode electrode 26 is connected to the first electrode contact region (cathode contact region) 21.

As shown in FIG. 5, a surface potential stabilizing region 6 and an electric field relaxing region 7 are arranged in the main operating region of the high breakdown voltage diode and its outer periphery, as in the first embodiment. Has been established. The electric field relaxation region 7 is a low impurity density n ⁻ -type semiconductor region 2 formed sequentially from the lower layer to the upper layer.
E, it can be understood that the semiconductor device is constructed by joining the p ^- type semiconductor region 3E having a low impurity density and the n-type semiconductor region 6E having a medium impurity density. The low impurity density p ⁻ -type semiconductor region 3E of the electric field relaxation region 7 corresponds to a conventional RESURF region, and can reduce the electric field around the high breakdown voltage diode to improve the junction breakdown voltage.

The semiconductor region 2E is formed as a part of the cathode region 22 of the high voltage diode, and is formed so as to surround the outer periphery of the cathode region (active cathode region) 22 through which the main current flows. In other words, the semiconductor region 2E utilizes a portion (extended portion) of the active cathode region 22 of the high breakdown voltage diode drawn out to the outer periphery.

The semiconductor region 3E is formed as a part of the anode region 23 of the high breakdown voltage diode, and is formed so as to surround the outer periphery of the anode region (active anode region) 23 through which the main current flows. As in the case of the semiconductor region 2E, the semiconductor region 3E uses a portion in which the active anode region 23 of the high-breakdown-voltage diode is actively drawn to the outer periphery. The width dimension L1 of the semiconductor region 3E, specifically, the anode region 23 and the anode contact region 24
The dimension L1 (the lateral diffusion distance of the anode region 23) from the interface (second interface) with the anode region 23 and the interface (first interface) between the anode region 23 and the cathode region 22 is the same as that of the conventional high breakdown voltage diode. Pullout dimension L of area 23
It is set longer than 3.

That is, the width L1 of the semiconductor region 3E of the high breakdown voltage diode according to the second embodiment of the present invention is set as long as possible to improve the junction breakdown voltage. Preferably, the width L1 of the semiconductor region 3E is set.
May be set to a dimension larger than the junction depth D1 of the semiconductor region 3E.

The semiconductor region 6E includes the surface potential stabilizing region 6
And is formed along the inner periphery of the surface potential stabilizing region 6. The semiconductor region 6E utilizes a portion where the surface potential stabilizing region 6 is actively drawn to the inner periphery. The semiconductor region 6E includes the anode region 23 and the anode contact region 2 of the high breakdown voltage diode.
4 can be formed without mask alignment (self-aligned).

In the high breakdown voltage diode configured as described above, when a high reverse bias voltage is applied between the cathode region 22 and the anode region 23, the pn junction between the cathode region 22 and the anode region 23 is reduced. The depletion layer spreads in the part. Similarly, a high voltage is applied between the semiconductor region 2E and the semiconductor region 6E also in the electric field relaxation region 7 disposed around the periphery of the high breakdown voltage diode, and a pn junction between the semiconductor region 2E and the semiconductor region 3E is formed. The depletion layer spreads at each of the pn junctions between the semiconductor region 3E and the semiconductor region 6E. The depletion layer of the high-breakdown-voltage diode and the depletion layer of the electric-field relaxation region 7 are coupled to each other, and the electric field applied to the pn junction of the high-breakdown-voltage diode can be dispersed in the electric-field relaxation region 7. Electric field concentration can be reduced. As a result, the junction breakdown voltage of the high breakdown voltage diode can be significantly improved.

Further, the semiconductor region 3E of the electric field relaxation region 7
Is formed as a portion where the active anode region 23 of the high breakdown voltage diode is diffused in the lateral direction. In the semiconductor region 3E, the impurity density gradually decreases from the main operation region side toward the surface potential stabilizing region 6. It has a profile (concentration gradient). That is, in the electric field relaxation region 7,
The spread of the depletion layer at the pn junction increases smoothly in the same direction, and the electric field intensity can be gradually reduced, so that the electric field concentration can be eased satisfactorily. The withstand voltage can be improved.

Further, a surface potential stabilizing region 6 is provided around the periphery of the high breakdown voltage diode. In particular, the potential of the semiconductor region 6E of the electric field relaxation region 7 can be stabilized. The high breakdown voltage diode according to the embodiment can stably improve the junction breakdown voltage.

(Third Embodiment) FIG. 6 shows a third embodiment of the present invention.
FIG. 4 is a cross-sectional structural view of a power electrostatic induction transistor (power SIT) as a power semiconductor device according to the embodiment. The power SIT shown in FIG. 6 is similar in basic structure to the power BJT shown in FIG. That is, the power SIT according to the third embodiment of the present invention is:
A first conductive type first electrode region (n-type drain region) 32 having an outer peripheral portion (chip end surface); a second conductive type second electrode region 33 disposed on the surface of the first conductive type 32;
A plurality of adjacent to the surface of the second electrode region 32 are separated from the interface (first interface) between the electrode region 32 and the second electrode region 33 by a predetermined distance L1 required for electric field relaxation. A second conductive type second electrode contact region (p-type gate region) formed with holes and a first conductive type third electrode region (n-type source region) formed inside the plurality of holes. ) 3
5 is further provided. Further, on the surfaces of the first electrode region 32 and the second electrode region 33, the second
Surface potential stabilization with a higher impurity density than that of the first electrode region, which is arranged extending from the interface (second interface) between the electrode contact region 34 and the second electrode region 33 to the outer periphery of the chip without any gap. It has a region 6.

The drain region 32 is a low impurity density n ⁻ type semiconductor region utilizing a part of the surface of the n ⁻ type semiconductor substrate 1S. Actually, only the portion immediately below the n-type source region 35 functions as the drain region (active drain region) 32 of the main operation region. This drain region 32 has 8
Since it is formed with a low impurity density of about × 10 ^{11 to} 6 × 10 ¹⁵ atoms / cm ³ , the depletion layer can be effectively expanded from the pn junction formed between the gate electrode 34 and the p-type gate region 34. At the same time, the junction breakdown voltage between the drain region 32 and the p-type gate region 34 can be improved. The drain region 32 sandwiched between the two p-type gate regions 34 operates as a channel region. Then, in the channel region 34 immediately below the n-type source region 35, a potential barrier against electrons injected from the n-type source region 35 is formed by the gate voltage applied to the two p-type gate regions 34. The potential barrier is given as a saddle point of a two-dimensional potential defined by a source-drain potential and a gate-gate potential. Therefore, the height of this potential barrier is determined by the gate voltage V
It can be controlled by _G and the drain voltage V _D. A drain contact region 3 formed of a high impurity density n ⁺ type semiconductor region on the back surface side of the semiconductor substrate 1S is formed in the drain region 32.
1. Drain electrode 3 disposed on the back surface of semiconductor substrate 1S
8, a drain voltage V _D is supplied.
When a predetermined operating voltage is applied between the source electrode 37 and the drain electrode 38, the active drain region 32 is almost completely depleted, so that the drain region 32 from the potential barrier to the drain contact region 31 is a "drift region". Function as Also, the drain contact region 31
Are formed as high impurity density regions so that the ohmic contact resistance between the drain contact region 1 and the back surface electrode 10 can be set sufficiently low. For the back electrode 10, for example, a composite film composed of a Ti / Ni / Pd / Ag film can be practically used.

The second electrode region 33 is a p ⁻ type semiconductor region having a lower impurity density than the p type gate region 34. The second electrode region 33 is formed in part of the drain region 32 in contact with the outermost p-type gate region 34. The surface of the p-type gate region 34 is arranged so as to be exposed in a lattice shape when viewed in a plan view, and the gate electrode 36 makes ohmic contact via a contact hole formed in the protective film 11. The gate electrode 36 other than the contact portion is provided on the protective film 11 on the front surface side of the semiconductor substrate 1S. Gate electrode 3
For 6, an aluminum alloy film such as Al-Si or Al-Cu-Si can be practically used.

For the gate electrode 36, for example, an aluminum alloy film such as Al-Si or Al-Cu-Si can be practically used. Then, the gate voltage V _G is supplied through the gate electrode 36 in the p-type gate region 34.

Source region 35 is formed of an n ⁺ type semiconductor region having a higher impurity density than drain region 32. The n ⁺ -type source regions 35 are formed as a plurality of island regions arranged in a matrix or in a staggered manner in the p-type gate region 34 in plan view. That is, the n ⁺ -type source region 35 functions in an arrangement sandwiched between the p-type gate regions 34. The source voltage V _S is supplied to the source region 35 through the source electrode 37. The source electrode 37 may have the same conductive layer as the gate electrode 36 or may have a different layer. The source electrode 37 is connected to the source region 35 through ohmic contact through a contact hole formed in the protective film 11.

The surface potential stabilizing region 6 provided around the periphery of the power SIT is formed over the entire surface of the semiconductor substrate 1S, that is, in the peripheral region of the surface of the drain region 32 which is not substantially used as the power SIT. , The n-type semiconductor region having a higher impurity density than the drain region 32 and a lower impurity density than each of the drain / contact region 31 and the source region 35. Further, the surface potential stabilizing region 6 is formed at a depth smaller than the junction depth of the source region 35. A fixed voltage is supplied to the surface potential stabilizing region 6 through the surface potential stabilizing wiring 15, so that the potential on the surface of the drain region 32 can be stabilized. The surface potential stabilizing wiring 15 may be formed of the same conductive layer and the same conductive material as the gate electrode 36 and the source electrode 37, but may be formed of different layers.

The power S according to the third embodiment of the present invention
What is important in IT is the electric field relaxation region 7 shown in FIG. The electric field relaxation region 7 is a low impurity density n ⁻ -type semiconductor region 2 formed sequentially from the lower layer to the upper layer in FIG.
E, it can be understood that it is constructed from the p ^- type semiconductor region 3E having a low impurity density and the n-type semiconductor region 6E having a medium impurity density. The low impurity density p ⁻ type semiconductor region 3E of the electric field relaxation region 7 corresponds to the conventional RESURF region 8, and can reduce the electric field around the power SIT to improve the junction breakdown voltage.

The semiconductor region 2E is formed as a part of the drain region 32 of the power SIT, and is formed so as to surround the outer periphery of the drain region (active drain region) 32 through which the main current flows. The semiconductor region 3E has a power S
It is configured as a part of the second electrode region 33 of IT.

The width L1 of the semiconductor region 3E, that is, the second
Lead-out dimension (second electrode region 33) from the interface (second interface) between electrode region 33 and p-type gate region 34 to the interface (first interface) between second electrode region 33 and drain region 32
Of the conventional power SIT.
The length is set longer than the lead-out dimension of the electrode region 33. That is, the width dimension L1 of the semiconductor region 3E of the electric field relaxation region 7 according to the third embodiment of the present invention is set as long as possible in order to improve the junction breakdown voltage within a range that does not hinder the degree of integration. And preferably, the semiconductor region 3E
May be set to a size larger than the junction depth D1 of the semiconductor region 3E. The semiconductor region 6E is electrically connected to the surface potential stabilizing region 6, and is formed along the inner periphery of the surface potential stabilizing region 6. Like each of the semiconductor regions 2E and 3E, the semiconductor region 6E
It is formed of a semiconductor region of the same layer (same) as the surface potential stabilization region 6, and utilizes a portion where the surface potential stabilization region 6 is actively drawn to the inner periphery. The semiconductor region 6E can be formed in a self-aligned manner with respect to each of the second electrode region 33 of the power SIT, the p-type gate region 34, and the surface potential stabilizing region 6 without mask alignment.

In the power SIT thus configured, a high reverse bias voltage is applied between the source region 35 and the p-type gate region 35 and between the drain region 32 and the p-type gate region 35, respectively. Then, a depletion layer spreads at each of the pn junctions. Similarly, power SI
A high voltage is applied between the semiconductor region 2E and the semiconductor region 6E also in the electric field relaxation region 7 disposed around the periphery of T, and a pn junction between the semiconductor region 2E and the semiconductor region 3E, the semiconductor region 3E A depletion layer spreads at each of the pn junctions between semiconductor and semiconductor region 6E. The depletion layer of the power SIT and the depletion layer of the electric field relaxation region 7 are coupled to each other, and the electric field applied to the pn junction of the power SIT can be dispersed in the electric field relaxation region 7, so that the electric field concentration around the power SIT can be reduced. Can be eased. As a result, the junction breakdown voltage of the power SIT can be significantly improved.

Further, the semiconductor region 3E of the electric field relaxation region 7
Is formed as a portion of the active second electrode region 33 of the power SIT diffused in the lateral direction.
E is a profile (concentration gradient) in which the impurity density gradually decreases from the main operation region side toward the surface potential stabilization region 6.
Having. That is, in the electric field relaxation region 7, the spread of the depletion layer at the pn junction increases smoothly in the same direction, and the electric field intensity can be gradually reduced, so that the electric field concentration can be favorably alleviated. Thus, the junction breakdown voltage of the power SIT can be further improved.

Further, a surface potential stabilizing region 6 is provided around the periphery of the power SIT, and in particular, the potential of the semiconductor region 6E of the electric field relaxing region 7 can be stabilized. The power SIT according to the embodiment can stably improve the junction breakdown voltage.

(Fourth Embodiment) FIG. 7 shows a fourth embodiment of the present invention.
Gate as a power semiconductor device according to the embodiment of the present invention
FIG. 2 is a sectional structural view of a turn-off (GTO) thyristor. The GTO thyristor according to the fourth embodiment of the present invention has an outer peripheral portion (chip end surface) having a diameter of 3 inches to 6 inches.
First conductivity type first electrode region (n base region) 4 having
3, a second electrode region (p base region) 44 of the second conductivity type disposed on the surface of the first electrode region, and an interface (first interface) between the first electrode region 2 and the second electrode region 3 ), A predetermined distance L1 to the inside, a second conductivity type second electrode contact region (p base contact region) 45 and a second electrode contact region 4 formed on the surface of the second electrode region 3. The first conductive type third electrode region (cathode region) 46 formed on at least a part of the surface of the first conductive region and the second conductive type fourth electrode region (anode region) 42 below the first electrode region 43 It has an npnp type. Below the fourth electrode region (anode region) 42, a fourth electrode contact region (anode contact region) 41 is further arranged. Here, the predetermined distance L1 means a distance necessary for electric field relaxation. The GTO thyristor according to the fourth embodiment of the present invention further includes:
On the surfaces of the first electrode region 43 and the second electrode region 44, the surface is extended without any gap from the interface (second interface) between the second electrode contact region 45 and the second electrode region 44 to the outer peripheral portion of the chip. And a surface potential stabilizing region 6 having a higher impurity density than the first electrode region.

The n base region 43 is a low impurity density n ⁻ type semiconductor region utilizing a part of the surface of the n ⁻ type semiconductor substrate 1S. Actually, only the portion immediately below the cathode region 46 functions as the n base region region (active n base region region) 43 of the main operation region. This n base area 4
3 is formed with a low impurity density, it is possible to improve the junction breakdown voltage of the pn junction formed with the p base region 44. An anode electrode 49 is disposed on the back surface side of the semiconductor substrate 1S functioning as a fourth electrode contact region (anode contact region) 41, and the anode voltage _VA is supplied to the anode electrode 49. The anode contact region 41 is formed with a high impurity density, and the resistance value of the anode contact region 41 itself is set low. As a result, the ohmic contact resistance between anode contact region 41 and anode electrode 49 can be set low. For example, the anode electrode 49
A composite film composed of a Ti / Ni / Pd / Ag film, a molybdenum (Mo) plate, a tungsten (W) plate, and the like can be practically used.

The p base region 44 is formed on the surface of the n base region 43 as a p ⁻ type semiconductor region having a low impurity density. Since the p-base region 44 has a low impurity density, the junction breakdown voltage between the p-base region 44 and the n-base region 43 can be improved. In p base region 44, p base contact region 4 formed so as to be exposed on the surface of p base region 44 is formed.
5, the gate voltage V _G through each of the gate electrodes 47
Is supplied. The p base contact region 45 is formed of a p ⁺ type semiconductor region having a higher impurity density than the p base region 44, and the resistance value of the p base contact region 45 itself can be set low. Further, by using a p ⁺ -type semiconductor region having a high impurity density, the ohmic contact resistance between the p base contact region 45 and the gate electrode 47 can be set low.

The gate electrode 47 is provided on the protective film 11 on the front surface side of the semiconductor substrate 1S, and passes through a contact hole formed in the protective film 11 to form a p base contact region 45.
Is electrically connected to For the gate electrode 47, for example, an aluminum alloy film such as Al-Si or Al-Cu-Si can be practically used.

The cathode region 46 is formed on the surface of the p base contact region 45, and is formed of an n ⁺ type semiconductor region having a higher impurity density than the n base region 43. In the fourth embodiment of the present invention, the cathode region 46 is formed in a lattice shape when viewed in a plan view.
Is surrounded by the p base contact region 45 except for the surface. The cathode region 46 is formed as a plurality of island regions arranged in a matrix or in a staggered manner in the p base contact region 45 when viewed in plan, and the surface of the p base contact region 45 is formed as a lattice when viewed in plan. It may be formed so as to be exposed in a shape. A cathode voltage V _K is supplied to the cathode region 46 through a cathode electrode 48. The cathode electrode 48 is formed of the same conductive layer and the same conductive material as the gate electrode 47, and is electrically connected to the cathode region 46 through a contact hole of the protective film 11.

The surface potential stabilizing region 6 provided around the outer periphery of the GTO thyristor covers the entire surface of the semiconductor substrate 1S.
That is, it is formed in a peripheral region of the surface of n base region 43 which is not substantially used as a GTO thyristor, and is formed of an n-type semiconductor region having a higher impurity density than n base region 43 and a lower impurity density than cathode region 46. Have been. Further, the surface potential stabilizing region 6 is formed at a depth smaller than the junction depth of the cathode region 46. A fixed voltage is supplied to the surface potential stabilizing region 6 through the surface potential stabilizing wiring 15, so that the potential of the surface of the n base region 43 can be stabilized. Surface potential stabilization wiring 15
Are formed of the same conductive layer and the same conductive material as each of the gate electrode 47 and the cathode electrode 48 described above.

What is important in the GTO thyristor according to the fourth embodiment of the present invention is the electric field relaxation region 7 shown in FIG. The electric field relaxation region 7 is constructed from the low impurity density n ⁻ -type semiconductor region 2E, the low impurity density p ⁻ -type semiconductor region 3E, and the medium impurity density n-type semiconductor region 6E shown in FIG. Can be understood. The low impurity density p ⁻ type semiconductor region 3E of the electric field relaxation region 7 corresponds to the RESURF region 8 of the conventional power semiconductor device, and relaxes the electric field around the GTO thyristor to improve the junction breakdown voltage. be able to. The semiconductor region 2E is G
An n base region (active n base region) configured as a part of the n base region 43 of the TO thyristor and through which a main current flows.
2 is formed so as to surround the outer periphery. The semiconductor region 3E is configured as a part of the p base region 44 of the GTO thyristor, and is formed so as to surround the outer periphery of the base region (active base region) 3 through which a main current flows. The width L1 of the semiconductor region 3E is set longer than the lead-out dimension of the p base region 44 of the conventional GTO thyristor. That is, the width dimension L1 of the semiconductor region 3E of the electric field relaxation region 7 according to the fourth embodiment of the present invention is:
The length is set as long as possible in order to improve the junction breakdown voltage within a range that does not hinder the degree of integration. Preferably, width L1 of semiconductor region 3E is set to be larger than junction depth D1 of semiconductor region 3E.

The semiconductor region 6E includes the surface potential stabilizing region 6
And is formed along the inner periphery of the surface potential stabilizing region 6. This semiconductor region 6E has G
For each of the p base region 44, the p base contact region 45, and the surface potential stabilizing region 6 of the TO thyristor,
It can be formed in a self-aligned manner without mask alignment.

In the power semiconductor device thus configured, a high reverse bias is applied between the n base region 43 and the p base region 44 or between the n base region 43 and the cathode region 46 of the GTO thyristor. When a voltage is applied, a depletion layer expands at each of a pn junction between n base region 43 and p base region 44 and a pn junction between p base region 44 and cathode region 46. Similarly, GT
A high voltage is applied between the semiconductor region 2E and the semiconductor region 6E also in the electric field relaxation region 7 arranged around the O-thyristor, and the electric field between the semiconductor region 2E and the semiconductor region 3E is increased.
pn junction, pn between semiconductor region 3E and semiconductor region 6E
A depletion layer spreads at each of the junctions. The depletion layer of the GTO thyristor and the depletion layer of the electric field relaxation region 7 are coupled to each other, and the electric field applied to the pn junction of the GTO thyristor can be dispersed in the electric field relaxation region 7. Can be eased. As a result, the junction breakdown voltage of the GTO thyristor can be significantly improved.

Further, the semiconductor region 3E of the electric field relaxation region 7
Is formed as a portion where the active p base region 44 of the GTO thyristor is drawn out in the horizontal direction (portion diffused in the horizontal direction), and the semiconductor region 3E extends from the main operation region side to the surface potential stabilizing region 6. And a profile (concentration gradient) in which the impurity density gradually decreases. That is,
In the electric field relaxation region 7, the spread of the depletion layer at the pn junction increases smoothly in the same direction, and the electric field strength can be gradually reduced. Further, the junction breakdown voltage of the GTO thyristor can be improved.

Further, a surface potential stabilizing region 6 is provided around the periphery of the GTO thyristor, and in particular, the potential of the semiconductor region 6E of the electric field relaxation region 7 can be stabilized. The GTO thyristor according to the embodiment can stably improve the junction withstand voltage.

(Other Embodiments) As described above, the present invention has been described with reference to the first to fourth embodiments.
The discussion and drawings that form part of this disclosure should not be understood as limiting the invention. From this disclosure, various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art.

For example, in the first embodiment, the present invention can be applied to an inverted (collector top type) BJT in which the collector region and the emitter region of the power BJT are exchanged.

Further, in the third embodiment, the first
If the second conductive type fourth electrode region is further provided below the electrode region, an electrostatic induction thyristor (SI thyristor) can be configured.

In addition, the present invention can be applied to various power semiconductor devices such as a power MOSFET and an insulated gate bipolar transistor (IGBT) which require a high junction breakdown voltage.

As described above, the present invention naturally includes various embodiments and the like not described herein. Therefore, the technical scope of the present invention is defined only by the matters specifying the invention according to the claims that are appropriate from the above description.

[0095]

According to the present invention, first, it is possible to provide a power semiconductor device capable of realizing a high breakdown voltage with a simple structure.

The present invention secondly provides, in addition to the first effect,
A method for manufacturing a power semiconductor device that can reduce the number of manufacturing steps can be provided.

Thirdly, the present invention provides, in addition to the second effect,
It is possible to provide a method of manufacturing a power semiconductor device capable of realizing miniaturization by eliminating unnecessary dimensions required as a mask alignment margin.

The present invention fourthly provides, in addition to the third effect,
By reducing the number of mask alignment steps, it is possible to provide a method for manufacturing a power semiconductor device capable of eliminating complexity in manufacturing and improving productivity.

[Brief description of the drawings]

FIG. 1 is a sectional structural view of a power bipolar transistor (power BJT) according to a first embodiment of the present invention.

FIG. 2 is a power BJT according to the first embodiment of the present invention.
FIG. 4 is a process cross-sectional view showing the manufacturing method for each process (part 1).

FIG. 3 is a power BJT according to the first embodiment of the present invention.
It is a process sectional view showing the manufacturing method for each of the processes (No. 2).

FIG. 4 is a power BJT according to the first embodiment of the present invention.
It is a process sectional view explaining other manufacturing methods.

FIG. 5 is a sectional structural view of a high breakdown voltage diode according to a second embodiment of the present invention.

FIG. 6 is a sectional structural view of a power static induction transistor (power SIT) according to a third embodiment of the present invention.

FIG. 7 is a sectional structural view of a gate turn-off (GTO) thyristor according to a fourth embodiment of the present invention.

FIG. 8 is a sectional structural view of a power BJT according to the related art.

[Explanation of symbols]

1S Semiconductor substrate 1 Collector connection region (collector / contact region) 2 Collector region 2E, 3E, 6E Semiconductor region 3 Base region 4 Base connection region (base / contact region) 5 Emitter region 6 Surface potential stabilization region 7 Electric field relaxation region 10 Back electrode 11, 13 Protective film 12 Emitter wiring 14 Base wiring 15 Surface potential stabilizing wiring 21 First electrode contact area (cathode contact area) 22 First electrode area (cathode area) 23 Second electrode area (anode area) 24 2 electrode contact region (anode / contact region) 25, 49 anode electrode 26, 48 cathode electrode 31 first electrode contact region (drain contact region) 32 first electrode region (drain region) 33 second electrode region 34 second electrode contact Area (gate area 35 third electrode region (source region) 37 source electrode 38 drain electrode 41 fourth electrode contact region (anode contact region) 42 fourth electrode region (anode region) 43 first electrode region (n base region) 44 second electrode region (P base region) 45 Second electrode contact region (p base contact region) 46 Third electrode region (cathode region)

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 29/80 H01L 29/80 V 29/861 29/91 DF term (Reference) 5F003 AP06 BA92 BC01 BE90 BG03 BH08 BH10 BH18 BH99 5F005 AF02 AH02 BA01 BB01 5F102 FA01 FB01 GC08 GJ03 GL07 GL15 GS10 HC15

Claims (7)

[Claims] 1. A first electrode region of a first conductivity type having an outer peripheral portion, and a second electrode region of a second conductivity type disposed on a surface of the first electrode region.
An electrode region, separated from a first interface between the first electrode region and the second electrode region by a predetermined distance required for electric field relaxation, and formed on a surface of the second electrode region. A second conductivity type second electrode contact region; and, on the surfaces of the first electrode region and the second electrode region, from a second interface between the second electrode contact region and the second electrode region to the outer peripheral portion. A semiconductor device comprising at least a surface potential stabilizing region having a higher impurity density than the first electrode region and extending without gaps. 2. The semiconductor device according to claim 1, wherein a distance between the first and second interfaces is larger than a junction depth of the second electrode region. 3. The semiconductor device further comprises a third electrode region of the first conductivity type formed on at least a part of a surface of the second electrode contact region, and a junction depth of the third electrode region is stable at the surface potential. The semiconductor device according to claim 1, wherein the semiconductor device is deeper than a junction depth of the activation region. 4. The second electrode contact region is formed with a plurality of holes, and further includes the first conductivity type third electrode region inside the plurality of holes, wherein the third electrode region has a plurality of holes. 3. The semiconductor device according to claim 1, wherein a junction depth is larger than a junction depth of the surface potential stabilizing region. 5. The semiconductor device according to claim 3, further comprising a fourth electrode region of the second conductivity type below the first electrode region. 6. A method for manufacturing a semiconductor device, comprising at least the following steps. (A) a step of selectively forming a second conductive type second electrode region on a part of the surface of the first conductive type semiconductor substrate to be the first electrode region; A predetermined distance required for electric field relaxation from a first interface between the first electrode region and the second electrode region, and the second conductivity type with a higher impurity density than the second electrode region. (C) a step of substantially exposing the surface of the semiconductor substrate, the surface of the second electrode region, and the surface of the second electrode contact region. An impurity having an impurity density higher than that of the semiconductor substrate and the second electrode region and lower than that of the second electrode contact region is introduced into the exposed surface, and is selectively applied to the surfaces of the semiconductor substrate and the second electrode region. Form a surface potential stabilization region in A process 7. The method according to claim 1, further comprising, after the step of forming the second electrode contact region, a step of further forming the third electrode region of the first conductivity type on at least a part of the surface of the second electrode contact region. The method for manufacturing a semiconductor device according to claim 6.