JP2000112559A - Multiprocessor and its controlling method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent useless power consumption in an operation stop state by stopping a clock in each processor connected to a network at the time of detecting a continuous stop state for fixed time in the processor itself. SOLUTION: Load data inputted from a network to a processor 1-m are received through an interface unit 13 and a specified process is executed by an instruction execution control part 11. At the time, an instruction idle counter 12 monitors the instruction issuing state of the control part 11 and counts the instruction execution stop time of the processor 1-m. When continuous stop time of fixed frequency is detected on the counter 12 after the completion of the process, a VPU 16 judges the idle state of the processor 1-m and allows the unit 13 to set up a processor state flag 131. Therefore clock distribution control part 14 stops clocks to be distributed to the control part 11, a cache 15 and the VPU 16. Thus, power consumption can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor, and more particularly, to a multiprocessor realizing low power consumption.

[0002]

2. Description of the Related Art Conventionally, a multiprocessor has a plurality of processors and can perform a plurality of operations in parallel. Therefore, a multiprocessor has been widely used to improve a processing speed.

[0003]

However, in the conventional multiprocessor as described above, even when the load on the entire system is extremely small, the clocks in all the processors operate in the same manner as at the peak time.
There is a problem that useless power is consumed in a processor in an operation halt state (in which no instruction is executed).

[0004] In recent years, the scale of the system has been increased, and the number of processors has increased, which has tended to further increase power consumption.

On the other hand, socially, reduction of power consumption has been widely taken up as an environmental problem, and there is a demand for suppressing power consumption in spite of an increase in the scale of the apparatus.

Therefore, in a bus-connected multiprocessor system, there is a method of performing bus monitoring and power control. However, in order to realize a bus monitoring device, it is necessary to consider the configuration of devices connected to the bus. A complicated HW is required.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the conventional technology, and has as its object to provide a multiprocessor capable of reducing power consumption.

[0008]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention requires a plurality of processors for processing a process generated when a program is executed, and a plurality of processors for executing the processes. A memory unit for storing data, a network unit for respectively connecting the plurality of processors and the memory unit,
In a multiprocessor including the plurality of processors and a clock generator that supplies a clock synchronized with a system to the memory unit, each of the plurality of processors performs generation and control of an instruction for executing the process. An instruction execution control unit to be executed; an instruction idle counter for counting an execution instruction stop time in the instruction execution control unit; And a clock distribution control unit for controlling the supply to

The clock distribution control unit may supply a clock supplied from the clock generator to the instruction execution control unit when the execution instruction suspension time in the instruction execution control unit is equal to or longer than a predetermined time. Is stopped.

The clock distribution control unit starts supplying a clock supplied from the clock generator to the instruction execution control unit when a process start notification is issued to its own processor. .

Also, a plurality of processors for processing processes generated at the time of program execution, a memory unit for storing data required when the processes are executed by the plurality of processors, the plurality of processors and the memory And a clock unit that supplies a clock synchronized with a system to the plurality of processors and the memory unit. When the time exceeds a predetermined time, the operation of the own processor is stopped.

When the execution instruction suspension time is equal to or longer than a predetermined time, the supply of the clock supplied from the clock generator to the own processor is stopped.

Further, when a process activation notification is issued to the own processor, the supply of the clock supplied from the clock generator to the own processor is started.

(Operation) In the present invention configured as described above, in each of the plurality of processors constituting the multiprocessor system, the instruction execution state in its own device is monitored, and the processor is continuously stopped for a predetermined time. The clock in the processor is stopped when a condition is detected,
Useless power is not consumed in the processor in the idle state.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a multiprocessor according to the present invention.

In this embodiment, as shown in FIG. 1, a plurality of processors 1 for processing a process that occurs when a program is executed
-1 to 1-n, a memory unit 2 for storing data required when a process is executed by the processors 1-1 to 1-n, and processors 1-1 to 1-n and the memory unit 2. Network unit 3 for connecting
And a clock generator 4 for supplying a clock synchronized with the system to the processors 1-1 to 1-n and the memory unit 2. Since the form of the network unit 3 is not the essence of the present invention, any form such as a bus form or a crossbar form may be used.

FIG. 2 is a block diagram showing a configuration of the processor 1-m shown in FIG. The processor 1-1
1 to n have the same configuration.

As shown in FIG. 2, the processor 1-m according to the present embodiment includes an instruction execution control unit 11 for generating and controlling an instruction for executing a designated process allocated by an operating system (hereinafter referred to as an OS); An instruction idle counter 12 for counting the execution instruction suspension time in the execution control unit 11, between the processor 1-1-1-n via the network unit 3, and between the processor 1-m and the memory unit 2 Monitor a network interface unit 13 for inputting / outputting data, a processor status flag 131 indicating a clock operation status in the processor 1-m, and a processor status flag 131;
It has at least a clock distribution control unit 14 that controls a clock supplied to a subunit in its own processor 1-m, and further has a Cache 15 and a VPU 16.

The network interface unit 13 transmits and receives data to and from the other processors 1-1 to 1-n or the memory unit 2.

The processor state flag 131 refers to the processor halt state report sent from the instruction idle counter 12 and the process start notification received from the network unit 3 and distributes the clock operation state in the processor 1-m by clock distribution. Output to the control unit 14.

The instruction execution control unit 11 refers to the process start notification received via the network interface unit 13 and generates and executes an instruction for executing an arbitrary process designated by the OS.

The instruction idle counter 12 receives the instruction execution state transmitted from the instruction execution control unit 11,
The continuous instruction execution stop time is counted. If the instruction execution suspension state has continued for a certain period of time, it is determined that the processor 1-m is in the idle state, and the processor state flag 13
1 sends a processor hibernation report.

The clock distribution control unit 14 receives a clock synchronized with the entire system from the clock generator 4, refers to the processor status flag 131, and controls the clock distribution to each subunit in the processor 1-m. I do.

The operation of the multiprocessor configured as described above will be described below.

The clock generator 4 sends out a synchronized clock to each unit. The plurality of processors 1-1 to 1-n and the memory unit 2 receive the clock output from the clock generator 4, and operate in synchronization with the clock.

The OS manages a plurality of processes executed by the processors 1-1 to 1-n. When the execution of the program is started, the OS performs scheduling of a group of processes constituting the program, and allocates a process to the processor 1-m. Note that the process activation method for the processor is not the essence of the present invention.

In the present embodiment, a process starting method by inter-processor communication via a network will be described as an example of a process starting method.

When a process group is scheduled in the OS and a process is allocated to the processors 1-1 to 1-n, process activation communication data is transmitted to the processor 1-m via the network unit 3.

When the processor 1-m receives the process start communication data addressed to itself transmitted via the network unit 3, the processor 1-m refers to the process start communication data and starts the process processing. You.

After the completion of the process, the processor 1-m
When it is detected that there is no instruction executed in the own processor within a predetermined time, the processor 1-
Some clocks in m are stopped, and the state transits to the clock stopped state.

Thereafter, when the processor 1-m in the clock stopped state receives the process start communication data addressed to itself, the stopped clock path in the processor is reactivated, and the process assigned by the OS is activated. Be executed.

Next, the operation in the processor 1-m will be described in detail.

When the execution of the program is started, scheduling is performed on the generated process in the OS, and the generated process is assigned to the processor 1-m.

When the process allocation is completed, process start communication data is transmitted to the processor 1-m via the network unit 3.

The process start communication data transmitted to the processor 1-m is received by the network interface 13 in the processor 1-m.

When the process start communication data is received by the network interface 13, the received process start communication data is transmitted to the network interface 13.
To the instruction execution control unit 11 in the processor 1-m.

When the process start communication data transmitted from the network interface 13 is received by the instruction execution control unit 11, the instruction execution control unit 11 issues a data load request for the memory address specified by the process start communication data. Issued to memory unit 2.

The data load request issued by the instruction execution control unit 11 is transmitted to the network interface unit 1
3 and the data received at the memory unit 2 via the network unit 3, the data stored at the address designated by the data load request is extracted in the memory unit 2, and the processor 1-m is extracted via the network unit 3. Is output to

The load data output from the memory unit 2 is received by the instruction execution control unit 11 via the network unit 3 and the network interface unit 13, and the instruction execution control unit 11 refers to the received load data, The designated process assigned by the OS is executed at the instruction level.

Here, the instruction idle counter 12 monitors the instruction issue state in the instruction execution control unit 11, and counts the instruction execution stop time in the processor 1-m.

When the next process does not occur for a long time after the completion of the process, when the instruction idle counter 12 detects a predetermined fixed number of continuous instruction execution suspension times, the processor 1-m enters the idle state. It is determined that there is, and idle state notification data is output to the network interface unit 13.

When the idle state notification data output from the instruction idle counter 12 is received by the network interface unit 13, the network interface unit 13 causes the processor state flag 1
31 is set. In this embodiment, the processor status flag 131 indicates that the network interface 1
2, it is not always necessary to be provided in the network interface unit 13 at the position of the processor status flag 131.

The clock distribution control unit 14 receives the clock generated by the clock generator 4 and distributes and controls the clock to the subunits constituting each processor.

Network interface unit 13
Is set in the clock distribution control unit 14, the sub-units other than the network interface unit 13 (in the present embodiment, the instruction execution control unit 11, Cache 15
The clock is fixed in the HI state (or the LO state) with respect to the clock distribution path of the VPU 16). In the memory / register in the sub-unit where the clock is stopped, the state at the time when the clock is fixed is held.

Thereafter, when a new process occurs, O
At S, scheduling of the generated process is performed,
The process start communication data is transmitted to the processor 1-m.

The network interface unit 13 in the processor 1-m receives the process start communication data addressed to itself via the network unit 3.

When the processor 1-m is in the clock stopped state, the processor state flag 131 is reset in the network interface unit 13 when the process start communication data is received.

In the clock distribution control unit 14, the processor state flag 131 is monitored, and the held clock path is activated.

When the clock is activated, the process start communication data is transmitted to the network interface unit 13.
To the instruction execution control unit 11.

When the process start communication data transmitted from the network interface 13 is received by the instruction execution control unit 11, the instruction execution control unit 11 stores the memory indicated by the process start communication data in the memory unit 2. A load request for the data stored in the address is issued, and the instruction sequence of the designated process is executed in the same manner as the above-described operation.

[0052]

As described above, in the present invention,
In each of a plurality of processors constituting a multiprocessor system, an instruction execution state in the own apparatus is monitored, and when a continuous stop state for a certain period of time is detected, a clock in the processor is stopped. Useless power is not consumed in the dormant processor, and power consumption can be reduced.

In a synchronous circuit employing a CMOS circuit, which is widely used in recent technologies, power consumption can be reduced by stopping a clock supplied to the synchronous circuit and fixing circuit data.

In a multiprocessor system, by controlling the internal clock operation for each processor with a relatively simple circuit, delicate power consumption control can be performed even in a large-scale system.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of a multiprocessor according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of a processor illustrated in FIG. 1;

[Explanation of symbols]

 1-1 to 1-n processor 2 memory unit 3 network unit 4 clock generator 11 instruction execution control unit 12 instruction idle counter 13 network interface unit 14 clock distribution control unit 15 Cache 16 VPU

Claims (6)

[Claims] 1. A plurality of processors for processing a process generated during execution of a program, a memory unit for storing data required when the processes are executed by the plurality of processors, the plurality of processors and the memory A multi-processor including a network unit that connects the respective units, and a clock generator that supplies a clock synchronized with a system to the plurality of processors and the memory unit, wherein each of the plurality of processors includes: An instruction execution control unit for generating and controlling an instruction for executing a process; an instruction idle counter for counting an execution instruction stop time in the instruction execution control unit; and Supplied Multiprocessors and having a clock distribution control unit for controlling the supply to the instruction execution control unit of the lock. 2. The multiprocessor according to claim 1, wherein the clock distribution control unit is supplied from the clock generator when an execution instruction suspension time in the instruction execution control unit is equal to or longer than a predetermined time. A supply of the supplied clock to the instruction execution control unit is stopped. 3. The multiprocessor according to claim 2, wherein the clock distribution control unit, when a process start notification is issued to its own processor, the instruction execution control unit of a clock supplied from the clock generator. Characterized in that the supply to the multiprocessor is started. 4. A plurality of processors for processing a process generated during execution of a program, a memory unit for storing data required when the processes are executed by the plurality of processors, the plurality of processors and the memory A multi-processor control method comprising: a network unit for connecting each of the units; and a clock generator for supplying a clock synchronized with a system to the plurality of processors and the memory unit. A method for controlling a multiprocessor, comprising: stopping the operation of its own processor when a predetermined time has elapsed. 5. The multiprocessor control method according to claim 4, wherein the supply of the clock supplied from the clock generator to the own processor is stopped when the execution instruction suspension time is equal to or longer than a predetermined time. A method for controlling a multiprocessor, the method comprising: 6. The multiprocessor control method according to claim 5, wherein when a process activation notification is issued to the own processor, the supply of the clock supplied from the clock generator to the own processor is started. Characteristic multiprocessor control method.