JPS62293331A - Data processor - Google Patents

Abstract

PURPOSE:To decrease the number of arithmetic circuits for logic arithmetic elements and to reduce the power consumption with a data processor, by supplying the low frequency clock signals obtained by dividing the basic clock signal to the data processor in its waiting state. CONSTITUTION:A waiting state detecting circuit 3 sends the signal to a switch 4 to inform a waiting state after checking a waiting state display flag set by a CPU 5. The switch 4 performs a switching action to apply the output signal of a divider 2 to the CPU 5. The divider 2 supplies the output signal having a frequency obtained by dividing the frequency of the output signal received from an oscillator 1 down to 1/n to the CPU 5. The CPU 5 increases the cycle of the basic clock signal for timing control and reduces the instruction executing frequency per unit time. Thus the number of logic arithmetic circuits of many logic arithmetic elements working under the control of the CPU 5 are reduced. At the same time, the power consumption of those logic arithmetic elements is also reduced. Thus the power consumption of a data processor is reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention detects when a data processing device, particularly a data processing device, is in a standby state, and detects the basic clock signal supplied to the data processing device. Instead, by dividing the frequency of this clock signal and supplying the obtained output signal to the data processing device, processing can be performed at a slower instruction execution speed than when instructions related to data processing are being executed. The present invention relates to a data processing device that reduces power consumption.

[Conventional technology]

FIG. 3 is a schematic diagram of a conventional data processing device, and FIG. 3 is a processing operation sequence diagram of the data processing device. In the figure, (1) is an oscillator, (Y) is a central processing unit, (L) is a main storage device, (7) is a display operation device, (g) is a mass storage device, (9) is a printer device, ( /θ) is the system bus. First, the processing operation sequence of the data processing device will be explained. As shown in FIG. 3, the data processing device includes a central processing unit (hereinafter referred to as CPTJ) (hereinafter referred to as CPTJ), a main memory device (hereinafter referred to as MEM) (6), and a plurality of input/output devices (hereinafter referred to as MEM). ) and (f), and each device is connected to each other via a system bus (IQ). As shown in the figure, M4 is connected to CPU (
When t) starts the processing operation, it starts displaying a message on the display/operation device (ri) in order to obtain business instructions to be processed, and waits until the operator gives instructions. When a response from the operator is obtained, the CPU (j) resumes the processing operation, analyzes the contents of the command, and stores the desired processing program and data to be processed into the M decoy (L) in the mass storage device <1.
In order to retrieve data from
(t) restarts the processing operation and processes the target data according to the processing program prepared in -(6). Next, the data resulting from the processing is transferred to the mass storage device (ff) and stored therein, and a message requesting the next work instruction is displayed and activated. In this case as well, following the same procedure as spinning, the CPU (
In the evening, I will wait.

Next, the operation of the oscillator (1) will be explained. As shown in FIG. 3, the output signal of the oscillator (1) is supplied to the CPU (t) for instruction execution in the CPU (t).
(A) A clock signal is defined which is the basis of timing control such as read timing, write timing, and startup timing for input/output devices. The frequency of the clock signal output from the oscillator (1) is set so that the C'PU (j-) can maximize its processing ability, and is always supplied to the CPU (t) at a constant frequency.

[Problem that the invention seeks to solve]

Conventional data processing equipment is in a standby state even when there is nothing to process, such as waiting for an operator's response or data transfer completion, so even when no valid processing results are obtained, the same power consumption as in the data processing state is required. There was a problem with consuming.

This invention was made to solve the above-mentioned problems, and the processing capacity of the data processing device can be maximized during data processing, and the overall power consumption can be reduced by reducing power consumption during standby. The purpose is to obtain a reduced data processing device.

[Means for solving problems]

When the data processing device according to the present invention is in the standby state, the oscillator is activated by switching the switch using the output signal of the standby state detection circuit that detects whether the data processing device is in the data processing state or in the standby state. Instead of the output signal, a low frequency clock signal obtained by dividing the output signal of the oscillator using a frequency divider is supplied to the data processing device.

[Effect]

In this invention, when in the standby state, the data processing device is supplied with a low frequency clock signal obtained by dividing the basic clock signal, which is the output signal of the p oscillator, by a frequency divider. The number of arithmetic circuits of logic operation elements constituting a processing device is reduced, and the power consumption of the logic operation elements is reduced.

〔Example〕

Next, an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a schematic diagram of the data processing device according to the above embodiment, and FIG. 2 is a diagram showing a general relationship between the number of operations per unit time of a logic operation element and the power consumption of the logic operation element. Ru. In the figure, (1) is an oscillator, (c) is a frequency divider, (3) is a standby state detection circuit that detects whether it is in a data processing state or in a standby state, and (i) is an oscillator (1) or a frequency divider. A switch that selects and passes one of the output signals of the frequency generator (2), (evening) is the CPU, (6) is the MlliiM,
(ri) is a control device, (j) is a mass storage device, (te) is a printer device, and (lθ) is a system bus.

First of all, the oscillator (1) supplied to the CPU (t)
The switching of the output signal will be explained. As explained above, when the data processing device waits for an operator's command, the processing program,
Enters standby state when transferring data to be processed. The standby state detection circuit (3) checks the standby state display flag that is explicitly set when the processing program executed in CP'CT(k) enters the standby state, or executes an instruction to check the environment of the data processing device. Since the data processing device continues to be in the standby state, the standby state detection circuit (3) detects that the data processing device has entered the standby state, and sends a signal indicating that it is in the standby state to the switch (1). Select one of the two input signals and pass it as the output signalC
The output signal from the oscillator (1) is given to the PU (event), but when a signal indicating that it is in a standby state is sent, the output signal of the frequency divider (ko) is given to crtl (event). Switch (switch). Branch 1B (J) is the oscillator (
It receives the output signal of oscillator (1) as input and outputs a signal having a frequency exactly n times lower than the frequency of the output signal from oscillator (1). Here, n is an integer constant that can be arbitrarily determined. When the data processing device enters the standby state in this way, the frequency of the output signal from the oscillator (1) that is supplied to the cpUD is lowered, and the period of the clock signal that is the basis of timing control is lengthened. The number of times instructions are executed per hour is reduced.

Next, the process of reducing power consumption will be explained.

The CPU combines a large number of logical operation elements and operates them under the control of basic timing, and executes instructions sequentially to perform processing. As shown in FIG. 2, it is known that when the number of logical operations performed by a logic operation element (per unit of time) decreases, the power consumed by the logic operation element decreases monotonically. As mentioned above, when crty (ri) enters the standby state and the number of command executions at nest time ib decreases,
The number of logical operations is also reduced, and as described above, the power consumed by the logical operation elements is also reduced. In this way, the power consumption of the data processing device is reduced.

In the above embodiment, an example has been described in which the output signal of the oscillator is divided into frequency dividers to obtain a low frequency clock signal, but another oscillator that provides a low frequency clock signal may also be used. There are no restrictions on the type or number of input/output devices that make up the data processing device, and the processing programs to be executed.
There are no restrictions on the type or amount of data to be processed.

[Effects of the Invention] As explained above, according to the data processing device of the present invention, when the data processing device is in the standby state, the standby state detection circuit detects that the data processing device is in the standby state; Instead of giving the oscillator's basic clock signal to the CPTT using the output signal, the switch is configured to give the CPU a low-frequency clock signal obtained by dividing the oscillator's basic clock signal, so there is no waste in the standby state. It is possible to save the power that would otherwise be consumed by the data processing device, reduce heat dissipation into the installation environment of the data processing device, and reduce cooling noise of the data processing device.

[Brief explanation of the drawing]

Fig. 1 is a schematic diagram of a data processing device that is an embodiment of the present invention, Fig. 2 is a general relationship between the number of operations of a logic operation element and power consumption, and Fig. 3 is a diagram of conventional data. A schematic diagram of the processing device, and FIG. V is a data processing operation sequence diagram. In the figure: - (1)...Oscillator, (2)...Frequency divider, (3)...Standby state detection circuit, (Ri)...Switch, (Evening)...CPT
T, (6)...-1(7)...Display operation device, (t)...
・Mass storage device, (9)...Printer device, (10)
...It is a system bus. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (2)

[Claims] (1) A standby state detection circuit that detects whether a data processing device is in a data processing state or a standby state, an oscillator that supplies a clock signal to the data processing device, and a low frequency output signal of the oscillator. A frequency divider that divides the frequency, and a switch that selects and passes either one of the direct output signal from the oscillator and the divided output signal from the frequency divider, A signal indicating the standby state causes the switch to select a branched output signal from the frequency divider instead of the direct output signal from the oscillator, and when the data processing device is in the standby state, A data processing device characterized in that an instruction for examining an environment is processed at a slower instruction execution speed than when an instruction involved in data processing is executed. (2) The data processing device according to claim 1, wherein the frequency divider is replaced by a low frequency oscillator different from the oscillator.