JP2000101360A - Amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an amplifier which can be used for plural frequencies with a small circuit scale and a small number of part items. SOLUTION: An input matching circuit 10 is connected to the gate of an FET 100, and an output matching circuit 20 and a drain bias applying circuit 30 are connected to its drain. A node N1 of the circuit 10 is connected to capacitors C1 and C2 via a switch 1. By switching the switch SW1 by switching signals S1 and S2, the capacitors C1 and C2 to be connected with the node N1 are switched. The node N2 of the circuit 20 is connected to capacitors C3 and C4 via a switch SW2. By switching the switch SW2 by switching signals S3 and S4, the capacitors C3 and C4 to be connected with the node N2 are switched.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to an amplifier including a transistor.

[0002]

2. Description of the Related Art In recent mobile communication, PDC (Personal Communication) is used.
al Digital Celluar), CDMA (Code Division Mult)
iple Access), PHS (Personal Handy phone Syste)
m), GMS (Global Systems for Mobile Communicat)
ion)), and the frequency is different for each method. When the frequency is different, the parameters of the impedance matching circuit used in the amplifier of the portable device are also different.

There are the following two methods for using different methods in the same portable device. The first method is to prepare a plurality of amplifiers with impedance matching corresponding to the frequency of each system, and switch the plurality of amplifiers by a switch according to the frequency. The second method is to use 1
A plurality of impedance matching circuits are prepared for one transistor, and the plurality of impedance matching circuits are switched by a switch according to a frequency. In this way, one portable device can be used in a plurality of ways.

[0004]

However, in any of the above methods, it is necessary to provide a plurality of amplifiers or a plurality of impedance matching circuits corresponding to a plurality of systems. This increases the circuit scale and the number of components. As a result, miniaturization and low cost of the portable device are hindered.

An object of the present invention is to provide an amplifier that can be used for a plurality of frequencies with a small circuit scale and a small number of components.

[0006]

The amplifier according to the first invention comprises a transistor and an impedance matching circuit connected to the transistor. The impedance matching circuit comprises a plurality of circuit elements and a plurality of impedance matching circuits. And a switch for switching the connection of the circuit element.

In the amplifier according to the present invention, the impedance of the impedance matching circuit is switched by switching the connection of a plurality of circuit elements included in the impedance matching circuit with a switch. This makes it possible to switch the frequency at which the impedance of the transistor matches the impedance of the input or output side circuit.

In this case, since the transistor and the impedance matching circuit are commonly used for a plurality of frequencies, the circuit scale is small and the number of components is small. Therefore, the size and cost of the system using the amplifier can be reduced.

[0009] Each of the plurality of circuit elements may be a capacitor, an inductor, or a line. In this case, the impedance of the impedance matching circuit can be switched by switching the connection of the capacitance, the inductor, or the line by the switch.

An amplifier according to a second aspect of the present invention includes a transistor, and a bias application circuit for applying a predetermined bias to an electrode of the transistor.
It includes a plurality of circuit elements and a switch for switching connection of the plurality of circuit elements.

In the amplifier according to the present invention, the impedance of the bias applying circuit is switched by switching the connection of a plurality of circuit elements included in the bias applying circuit with a switch. This makes it possible to switch the frequency at which the impedance of the transistor matches the impedance of the input or output side circuit.

In this case, since a transistor and a bias applying circuit are commonly used for a plurality of frequencies,
The circuit scale is small and the number of parts is small. Therefore, the size and cost of the system using the amplifier can be reduced.

[0013]

FIG. 1 is a circuit diagram showing a configuration of an amplifier according to a first embodiment of the present invention.

The amplifier shown in FIG. 1 includes an FET (field effect transistor) 100, an input matching circuit 10, and an output matching circuit 20.
And a drain bias application circuit 30. The input matching circuit 10 is connected between the gate of the FET 100 and the input terminal I1. The source of the FET 100 is grounded via the inductor L2. The output matching circuit 20
The drain bias application circuit 30 is connected between the drain of the FET 100 and the output terminal O1, and is connected to the node N3.

The input matching circuit 10 includes capacitors C1, C2, C
5, C6, a resistor R1, lines ML1, ML2, an inductor L1, and a switch SW1. The switch SW1 is
It consists of two FETs 1 and 2.

In input matching circuit 10, node N
1 is grounded via the FET1 and the capacitor C1, and is grounded via the FET2 and the capacitor C2. FE
The switching signals S1 and S2 are respectively applied to the gates of T1 and T2.
Is given.

The output matching circuit 20 includes capacitors C3 and C4, an inductor L3, a line ML4, and a switch SW2. The switch SW2 includes two FETs 3 and 4.

In output matching circuit 20, node N
2 is grounded via the FET3 and the capacitor C3, and grounded via the FET4 and the capacitor C4. FE
The switching signals S3 and S4 are respectively applied to the gates of T3 and T4.
Is given.

The drain bias application circuit 30
Includes capacitors C7, C8 and line ML3. The drain bias application circuit 30 forms a part of the output matching circuit 20. The drain bias VB is applied to the node N4 of the drain bias application circuit 30.

The inductors L1, L2 and L3 are inductor components of the bonding wire.

In the input matching circuit 10, when the FET1 of the switch SW1 is turned on in response to the switching signal S1, the capacitance C1 is connected to the node N1. When the FET2 of the switch SW1 is turned on in response to the switching signal S2, the capacitance C2 is connected to the node N1. Capacity C1
Is set to be different from the capacitance value of the capacitor C2. Thus, the impedance of the input matching circuit 10 can be switched by switching the switch SW1.

In the output matching circuit 20, when the FET3 of the switch SW2 is turned on in response to the switching signal S3, the capacitance C3 is connected to the node N2. When the FET 4 of the switch SW2 is turned on in response to the switching signal S4, the capacitance C4 is connected to the node N2. Capacity C3
Is set to be different from the capacitance value of the capacitor C4. Thus, by switching the switch SW2, the impedance of the output matching circuit 20 can be switched.

For example, when the FET 1 of the switch SW1 is turned on, the impedance between the FET 100 and the input side circuit can be matched at 800 MHz, and when the FET 2 of the switch SW1 is turned on, the impedance is 1450 MHz.
Thus, the impedance between the FET 100 and the circuit on the input side can be matched.

Further, when the FET3 of the switch SW2 is turned on, the impedance between the FET100 and the output side circuit can be matched at 800 MHz, and when the FET4 of the switch SW2 is turned on, the FET100 and the output side at 1450 MHz can be matched. The impedance with the circuit can be matched.

In the amplifier of this embodiment, since the FET 100, the input matching circuit 10, and the output matching circuit 20 are commonly used for a plurality of frequencies, the circuit scale is small and the number of components is small. Therefore, it is possible to reduce the size and cost of a communication device such as a portable device that supports a plurality of frequencies.

FIG. 2 is a circuit diagram showing a configuration of an amplifier according to a second embodiment of the present invention. The amplifier of FIG. 2 differs from the amplifier of FIG. 1 in the following points.

In the input matching circuit 10, instead of the switch SW1 and the capacitors C1 and C2 in FIG.
3. Capacitors C11 and C12 and an inductor L11 are provided. The capacitance value of the capacitance C11 is set to be different from the capacitance value of the capacitance C12. The switch SW3 includes three FETs 11, 12, and 13.

The node N1 is connected to the FET 11 and the capacitor C1.
1 and grounded via the FET 12 and the capacitor C12, and the FET 13 and the inductor L11
Grounded. The switching signals S11, S12, S13 are respectively applied to the gates of the FETs 11, 12, and 13.
Is given.

Further, a capacitor C20 is connected in parallel with the capacitor C6 via the switch SW4. The switch SW4 is composed of the FET14. The switching signal S14 is given to the gate of the FET14.

In the output matching circuit 20, instead of the switch SW2 and the capacitors C3 and C4 in FIG.
5 and capacitors C13, C14, and C15. The capacitance value of the capacitance C13, the capacitance value of the capacitance C14, and the capacitance value of the capacitance C15 are set to be different. The switch SW5 includes three FETs 15, 16, and 17.

The node N2 is connected to the FET 15 and the capacitor C1.
3 and grounded via the FET 16 and the capacitor C14, and grounded via the FET 17 and the capacitor C15. Switching signals S15, S16, and S17 are provided to the gates of the FETs 15, 16, and 17, respectively.

In the input matching circuit 10, when the FET 11 of the switch SW3 is turned on in response to the switching signal S11, the capacitance C11 is connected to the node N1. Further, in response to the switching signal S12, the FET1 of the switch SW3
When 2 turns on, the capacitor C12 is connected to the node N1. Further, in response to the switching signal S13, the switch S
When the FET 13 of W3 is turned on, the inductor L11 is connected to the node N1.

When the FET 14 of the switch SW4 is turned on in response to the switching symbol S14, the capacitor C20 is connected in parallel with the capacitor C6. Thus, the impedance of the input matching circuit 10 can be switched.

In the output matching circuit 20, when the FET 15 of the switch SW5 is turned on in response to the switching signal S15, the capacitance C13 is connected to the node N2. Further, in response to the switching signal S16, the FET1 of the switch SW5
When 6 turns on, the capacitor C14 is connected to the node N2. Further, in response to the switching signal S17, the switch S
When the FET 17 of W5 is turned on, the capacitance C1 is connected to the node N2.
5 is connected. Thus, the impedance of the output matching circuit 20 can be switched.

For example, in the input matching circuit 10, when the FET 11 of the switch SW3 is turned on, 800 MHz
z can match the impedance between the FET 100 and the input-side circuit. When the FET 12 of the switch SW3 is turned on, the impedance between the FET 100 and the input-side circuit can be matched at 1450 MHz.
When the FET 13 of the switch SW3 is turned on, 190
The impedance between the FET 100 and the input side circuit can be matched at 0 MHz.

When the FET 14 of the switch SW4 is turned on, the impedance between the FET 100 and the input side circuit can be matched at another frequency.

In the output matching circuit 20, when the FET 15 of the switch SW5 is turned on, 800 MHz
Can match the impedance between the FET 100 and the output side circuit. When the FET 16 of the switch SW5 is turned on, the impedance between the FET 100 and the output side circuit can be matched at 1450 MHz. When turned on, 1900
The impedance between the FET 100 and the output side circuit can be matched at MHz.

In the amplifier of this embodiment, since the FET 100, the input matching circuit 10, and the output matching circuit 20 are commonly used for a plurality of frequencies, the circuit scale is small and the number of components is small. Therefore, the size and cost of a communication device such as a portable device that supports a plurality of frequencies can be reduced.

Here, a simulation of frequency characteristics in the amplifier of FIG. 1 was performed. In this simulation, the gate width of the FET 100 was 12 mm. Microstrip lines were used as the lines ML1, ML2, ML3, and ML4. FIG. 3 is a schematic sectional view of the microstrip line. As shown in FIG. 3, the microstrip line includes a dielectric substrate 101, a microstrip conductor 102, and a ground conductor 103. The thickness H of the dielectric substrate 101 is 635 μm, and the thickness t of the microstrip line 102 is 10 μm. Further, the width of the microstrip line is W and the length is L.

In the amplifier of FIG. 1, the capacitance value of the capacitance C1 is 0 pF, and the capacitance value of the capacitance C2 is 20 pF. Capacity C
3, the capacitance value is 23 pF, and the capacitance value of the capacitor C4 is 7.5 pF.
It is. The capacitance values of the capacitors C5, C6, C7, and C8 are 3 pF, 12 pF, 1000 pF, and 8 pF, respectively. The resistance value of the resistor R1 is 100Ω. Inductor L
The inductance of L1, L2, and L3 is 0.25, respectively.
nH, 0.02 nH and 0.2 nH.

The width W of the line ML1 is 300 μm, the length L is 8700 μm, the width W of the line ML2 is 300 μm,
The length L is 2200 μm. The width W of the line ML3 is 30
0 μm, the length L is 1250 μm, the width W of the line ML4 is 300 μm, and the length L is 2300 μm.

FIGS. 4 and 5 are diagrams showing simulation results of frequency characteristics in the amplifier of FIG. FIG.
Is the FET1 of the switch SW1 and the F of the switch SW2.
FIG. 5 shows a simulation result when the ET3 is turned on, and FIG.
The simulation result when the FET4 of W2 is turned on is shown.

S11 is an S parameter indicating an input reflection coefficient, S22 is an S parameter indicating an output reflection coefficient, and S21 is an S parameter indicating a gain.

As shown in FIG. 4, the FE of the switch SW1
When T1 and the FET3 of the switch SW2 are turned on, the gain is maximum at 0.8 GHz, and the input reflection coefficient and the output reflection coefficient are small. That is, it can be seen that the impedance is matched at 0.8 GHz.

Further, as shown in FIG.
When the FET2 of the switch SW2 and the FET4 of the switch SW2 are turned on, the gain becomes maximum at 1.45 GHz, and the input reflection coefficient and the output reflection coefficient become small.
That is, it can be seen that the impedance is matched at 1.45 GHz.

In the first and second embodiments,
Although the impedance is switched by switching the connection of the capacitance or the inductor included in the input matching circuit 10 or the output matching circuit 20, the impedance of the input matching circuit or the output matching circuit may be switched by switching the connection of the line.

The frequency at which the impedance is matched is not limited to the input matching circuit 10 and the output matching circuit 20, but may be switched by switching the connection of circuit elements included in the bias applying circuit.

For example, a plurality of capacitors, inductors or lines may be connected to the node N3 or the node N4 in the drain bias application circuit 30 shown in FIGS. 1 and 2 via a switch. In this case, by switching the impedance of the drain bias application circuit 30, the FET 1
The frequency at which the impedance of 00 and the output side circuit are joined can be switched.

The amplifier of the present invention can be applied to both MMIC (monolithic microwave integrated circuit) and module IC.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of an amplifier according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of an amplifier according to a second embodiment of the present invention.

FIG. 3 is a schematic sectional view of a microstrip line.

FIG. 4 is a diagram showing a simulation result of a frequency characteristic in the amplifier of FIG. 1;

FIG. 5 is a diagram showing a simulation result of a frequency characteristic in the amplifier of FIG. 1;

[Explanation of symbols]

1,2,3,4,11,12,13,14,15,1
6, 17, 100 FET 10 Input matching circuit 20 Output matching circuit 30 Drain bias applying circuit SW1, SW2, SW3, SW4, SW5 Switch C1 to C8, C11 to C15, C20 Capacitance L1, L2, L3, L11 Inductor ML1, ML2 , ML3, ML4 line

Continued on front page F-term (reference) 5J067 AA04 AA51 CA61 CA75 CA92 FA18 HA09 HA25 HA29 HA33 HA39 HA40 KA13 KA14 KA29 KA44 KA47 KA68 KS25 KS27 LS12 MA21 SA13 TA01 TA03 5J092 AA04 AA51 CA61 CA75 CA92 HA18 HA09 HA39 HA39 KA29 KA44 KA47 KA68 MA21 SA13 TA01 TA03 VL01 VL05 5J103 AA02 AA05 DA35 DA41 EA03 EA05

Claims (3)

[Claims] 1. A semiconductor device comprising: a transistor; and an impedance matching circuit connected to the transistor, wherein the impedance matching circuit includes a plurality of circuit elements and a switch for switching connection of the plurality of circuit elements. Amplifier. 2. The amplifier according to claim 1, wherein each of the plurality of circuit elements is a capacitor, an inductor, or a line. 3. A transistor, comprising: a transistor; and a bias application circuit for applying a predetermined bias to an electrode of the transistor, wherein the bias application circuit switches a plurality of circuit elements and a connection between the plurality of circuit elements. And an amplifier.