JPH11150464A - Semiconductor switch circuit, control method for the circuit and attenuator circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a switch circuit with satisfactory isolation, where a size of a chip is made small by reducing the number of control terminals and the operability and the productivity of semiconductor components are improved. SOLUTION: This semiconductor switch circuit consists of a first field effect transistor FET1 that uses a channel between a drain and a source placed between input and terminals 1, 2 for a signal channel and of a second FET2 that connects the signal channel to ground GND and aids the isolation of the channel. A control voltage is applied to the drain or the source of the FET1 and also to the gate of the FET2 for applying switching control to the first and second FETs 1, 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor switch circuit, a control method of the circuit, and an attenuator circuit. More particularly, the present invention relates to a semiconductor switch circuit suitable for use in a portable terminal such as a portable telephone, a control method of the circuit, and an attenuator. Circuit.

[0002]

2. Description of the Related Art Conventionally, a semiconductor switch circuit has, for example,
As shown in JP-A-8-213891 (FIG. 9), FET3 in which the drain (D) is connected to the signal input terminal 101 and the source (S) is connected to the drain (D) of the FET4.
And the drain (D) is connected to the source (S) of the FET 3, and the source (S) is connected to the FET 4 grounded via a capacitor 10 connected in series, and the gate of each FET is connected to the gate via a gate resistor 107, 109. , FET3 control terminal V
₃ and the control terminal V ₄ of FET ₄ are provided,
Each of the drain (D) and the source (S) is grounded via a resistor, and the potential is always set to 0, so that the positive control voltage E
By providing ₃ and E ₄ , an FET switch circuit is configured.

Further, Japanese Patent Application Laid-Open No. 9-98078 (FIG. 1)
0), the signal input terminal 101 is connected to the capacitor 104.
FET 5 connected to drain (D) through
5 is grounded via the capacitor 10 to the source (S) of FET5.
The drain (D) of the FET 6 is connected to the drain (D) of the FET 6, and the source (S) of the FET 6 is used as the output signal terminal 102.
0 or +5 V to the control terminals V ₅ and V ₆ via
To control the FET switch.

[0004] However, the above-mentioned conventional circuit has two control terminals, and different voltages must be applied to the control terminals, resulting in a disadvantage that the circuit configuration becomes complicated.

[0005]

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned conventional disadvantages and to provide a semiconductor switch circuit having good isolation and a control method of the circuit. Another object of the present invention is to provide a semiconductor switch circuit in which the number of control terminals is reduced so that the chip size is reduced and the operability and productivity of semiconductor elements are improved.

Another object of the present invention is to provide a novel attenuator circuit having a large variable range.

[0007]

SUMMARY OF THE INVENTION The present invention basically employs the following technical configuration to achieve the above object. That is, a first aspect of the semiconductor switch circuit according to the present invention includes a first field-effect transistor having a channel portion between a drain and a source of a field-effect transistor provided between an input / output terminal as a signal path; A first capacitor provided between the first input / output terminal and one of the drain and source terminals of the first field effect transistor; and a second capacitor connected between the second input / output terminal and the first field effect transistor. In a semiconductor switch circuit including a second capacitor provided between the other terminals and a second field-effect transistor for ensuring isolation by dropping a path of the signal to the ground, the second capacitor And two capacitors connected in series for controlling the switching of the first and second field-effect transistors. A control terminal, a first resistor connecting the gate of the first field-effect transistor to ground, and a second resistor provided between the other terminal of the first field-effect transistor and the control terminal. A power supply connected to one of the drain and source terminals of the second field-effect transistor; a connection point of the two series-connected capacitors; A connection line provided between one terminal, a third resistor provided between the gate of the second field-effect transistor and the control terminal, and the other terminal of the second field-effect transistor And a capacitor provided between the ground and a ground. As a second mode, a channel portion between a drain and a source of a field effect transistor provided between an input / output terminal is provided. A first field-effect transistor that makes a signal path, a first capacitor provided between the first input / output terminal and one of a drain terminal and a source terminal of the first field-effect transistor, A second capacitor provided between the second input / output terminal and the other terminal of the first field-effect transistor; and a second capacitor for ensuring isolation by dropping the signal path to ground. In a semiconductor switch circuit including a field-effect transistor, two series-connected capacitors constituting the second capacitor, the first and second capacitors are connected to each other.
A control terminal for switching control of the field-effect transistor, a power supply connected to the other terminal of the first field-effect transistor, and a control terminal provided between the gate of the first field-effect transistor and the control terminal. A first resistor, a connection line provided between a connection point of the two capacitors connected in series and one terminal of a drain or a source of the second field-effect transistor,
A second resistor provided between the ground of a gate of the second field-effect transistor and a third resistor provided between the other terminal of the second field-effect transistor and the control terminal; And a capacitor provided between the other terminal of the second field-effect transistor and the ground. As a third mode, in addition to the above-described configuration, two capacitors connected in series are provided. And an inductor connected in parallel.

According to a first aspect of the method for controlling a semiconductor switch circuit according to the present invention, a first electric field is provided in which a channel portion between a drain and a source of a field effect transistor provided between an input / output terminal is used as a signal path. In a method for controlling a semiconductor switch circuit comprising an effect transistor and a second field effect transistor for obtaining isolation by dropping a signal path to ground, a control voltage is applied to a drain or a source of the first field effect transistor. And applying the same control voltage to the gate of the second field-effect transistor to control the switching of the first and second field-effect transistors.
As a second mode, a first field-effect transistor having a channel portion between a drain and a source of a field-effect transistor provided between an input / output terminal as a signal path, and an isolation by dropping the signal path to ground. A method of controlling a semiconductor switch circuit comprising a second field effect transistor, wherein a control voltage is applied to a gate of the first field effect transistor, and the control voltage is applied to a source or a drain of the second field effect transistor. And the switching control of the first and second field-effect transistors by applying the same control voltage.

Further, a first aspect of the attenuator circuit according to the present invention is a first field effect transistor having a channel portion between a drain and a source of a field effect transistor provided between an input / output terminal as a signal path; A first capacitor provided between the first input / output terminal and one of a drain and a source of the first field effect transistor; and a second capacitor provided between the second input / output terminal and the first field effect transistor. A second and a third capacitor connected in series between the other terminals of the transistor, a second field-effect transistor enabling the signal path to drop to ground, the first and the second A control terminal for controlling the second field-effect transistor, a first resistor connecting the gate of the first field-effect transistor to ground, and the first electric field. A second resistor provided between the other terminal of the transistor and the control terminal; a power supply connected to one of a drain terminal and a source terminal of the second field effect transistor; A connection line provided between a connection point of two capacitors connected in series and the one terminal of the second field-effect transistor, and a connection line provided between a gate of the second field-effect transistor and the control terminal. And a fourth capacitor provided between the other terminal of the second field-effect transistor and the ground.
A first field-effect transistor having a channel portion between a drain and a source of a field-effect transistor provided between an input / output terminal and a signal path; a first field-effect transistor; A first transistor provided between one of the drain and source terminals of the effect transistor;
And the second and third capacitors connected in series between the second input / output terminal and the other terminal of the first field effect transistor, and the signal path is dropped to ground. A second field-effect transistor, a control terminal for controlling the first and second field-effect transistors, and a power supply connected to the other terminal of the first field-effect transistor. A first resistor provided between the gate of the first field effect transistor and the control terminal; a connection point between the two capacitors connected in series; and a drain or source of the second field effect transistor. A connection line provided between any one of the terminals, a second resistor provided between the gate of the second field-effect transistor and ground, and the second field-effect transistor. A third resistor provided between the other terminal of the transistor and the control terminal, and a capacitor provided between the other terminal of the second field-effect transistor and ground, As a third aspect, in addition to the above configuration, an inductor is connected in parallel to the two capacitors connected in series,
A fourth aspect is characterized in that the output of the attenuator circuit is led to an amplifier, and the amplification of the amplifier is simultaneously controlled by the control voltage.

[0010]

Next, embodiments of the present invention will be described in detail with reference to the drawings. Referring to FIG.
An input signal terminal 1 is connected via a signal input side capacitor 4 to a drain side of a depletion mode field effect transistor FET1 made of GaAs.
On the source side, a capacitor 5 and an FET through which the input signal passes
The control terminal 3 is connected via the source resistor 8 of the FET 1 to determine the potential of the source 1. An output signal terminal 2 is provided from the capacitor 5 via a signal output side capacitor 6 connected in series with the capacitor 5, and the source of the FET 2 having a drain connected to a connection point J between the capacitors 5 and 6 is grounded via a capacitor 10. Have been. FET2
Is connected to the control terminal 3 via the gate resistor 9 and has the same potential as the source and drain of the FET 1. The drain and source of the FET 2 are connected to a fixed voltage application terminal 11 via a resistor 12 for applying a fixed voltage, and the potential of the drain and source of the FET 2 is fixed. In the switch circuit having the above configuration,
The gate width of the FET 1 is increased to reduce the input loss, and the values of the series-connected capacitors 4, 5, and 6 are also increased so that the loss of the input signal is reduced.

Further, it is desirable that the resistances 8 and 12 for applying a potential are increased as much as possible, and the resistance values are increased so as to reduce a loss with respect to an input signal. The gate width of FET2 is F
When the ET2 is in the ON state, the leakage signal from the FET1 is securely grounded, and when the ET2 is OFF, the OFF state is reliably maintained with respect to the amplitude of the input signal. It is desirable that the capacitor 10 not only maintain the potential of the FET 2 but also have a sufficiently large value to sufficiently ground the leakage signal from the FET 1 when the FET 2 is in the ON state.

Next, the operation of the embodiment of the present invention will be described in detail with reference to FIGS. Now, assuming that the potential of the control terminal 3 is 0 _(V) , since (gate potential) = (drain potential) = (source potential) = 0 _(V) of FET1, FET1 is in the ON state (resistance R _ON). ). On the other hand, the drain potential and the source potential of the FET 2 are set to the potential of the fixed applied potential terminal 11 +
Because it is kept to _{V (V)} and of the same potential + _{V (V)} FET2 is O
The state becomes the FF state. Therefore, the signal input from the input signal terminal 1 is output through the path of the capacitor 4 → R _ON → capacitor 5 → capacitor 6 → output signal terminal 2.

Conversely, when the potential of the control terminal 3 is changed to + V, the gate potential of the FET 1 is always 0 _V , and the source potential is
Since the capacitor 4.5 keeps + V _(V) ,
Since the FET1 is in the OFF state, the (drain potential) of the FET2 = (source potential) = (gate potential) = + V _(V) , and the FET2 is in the ON state, the input signal is
First, it is cut off by FET1, and even if a signal leaks, FE
Table 1 summarizes the above-mentioned states in which T2 (resistance R ' _ON ) is grounded via the capacitor 10 and is not output to the output signal terminal 2.

Further, the voltage of the control terminal 3 is changed from 0 → + V
_By gradually changing the _voltage to _(V) , the present switch circuit can also operate as an attenuator circuit. An example of this characteristic is shown in FIG. The insertion loss in the ON state of FET1 is -A [dB], and the insertion loss in the OFF state is -C.
[DB], when the voltage of the control terminal 3 changes from 0 to + V _(V) , the ON resistance changes due to the change of the voltage of the control terminal. Therefore, the attenuator amount is changed to -A to -C [dB]. Can be changed.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A specific example of a semiconductor switch circuit, a control method of the circuit, and an attenuator circuit according to the present invention will be described below in detail with reference to the drawings. 1 and 2 are circuit diagrams showing specific examples of a semiconductor switch circuit according to the present invention. As shown in FIG. 1, a channel portion between a drain and a source of a field effect transistor provided between input / output terminals 1 and 2 is shown in FIG. A first field-effect transistor FET1 which makes a signal path, a first input / output terminal 1 and a first field-effect transistor provided between one of the drain and source terminals of the first field-effect transistor FET1. A capacitor 4;
Isolation is ensured by dropping the signal path to the ground GND and the second capacitors 5 and 6 provided between the second input / output terminal 2 and the other terminal of the first field effect transistor FET1. A second field-effect transistor FET2 for switching the first and second field-effect transistors, and two series-connected capacitors 5, 6 constituting the second capacitor. A control terminal 3 for controlling the first field-effect transistor FET1
Resistor 7 that connects the gate of the gate to ground GND
A second resistor 8 provided between the other terminal of the first field-effect transistor FET1 and the control terminal 3; and a drain or a source of the second field-effect transistor FET2. A power supply P connected to one terminal and the two capacitors 5 and 6 connected in series;
And the second field-effect transistor FET2
A connection line W provided between the one terminal and a third resistor 9 provided between a gate of the second field-effect transistor FET2 and the control terminal 3;
1 shows a semiconductor switch circuit including the other terminal of the field effect transistor FET2 and the capacitor 10 provided between the ground GND.

The first embodiment of the present invention will be described in more detail.
Then, the embodiment of the present invention provides a GaAs having a thickness of 140 μm.
Field-effect transistor in depletion mode on s substrate
Star (FET) and MIM (Metal-Insulat)
er-Metal) structure, thickness 2.3 μm
Formed by gold-plated wiring
By using a sheet resistance of 1 kΩ
Formed. Gate width 1m for series FET1
m, a 400 μm FET is used for the parallel
All capacitors are 5pF, all resistors are 5kΩ, FET
Threshold voltage V _thIs -1.5v. Fixed voltage application
+3.0 V for terminal 11 and 0 for control terminal 3_(V)And +
3.0_(V)Shall be applied.

Next, the operation of the first specific example will be described with reference to FIG.
This will be described in detail with reference to FIG. Now, assuming that 0 _(V) is applied to the control terminal 3, the potential of the drain and source of the FET 1 is 0 _(V) of the same potential at the control terminal 3, so that the gate of the FET 1 is always grounded. From that
It is assumed that the ON resistance R _{ON of the} FET 1 is approximately 2.5Ω, and the signal input from the signal input terminal 1 is
And FET1. On the other hand, FET2 has a gate potential of 0 V and a source and drain potential of a fixed voltage application terminal 11.
3V, which is the same potential as the threshold voltage (−1.5
v) Since the potential (−3.0 v) or more is equivalent to the application of the gate potential of the FET 2, the drain and the source of the FET 2 are open. Therefore, F
The signal passing through ET1, capacitors 4 and 5 is FE
The signal is output to the signal output terminal 2 via the capacitor 6 without passing through T2. At this time, if the frequency is 1 GHz, for example, a loss of about 2.5 [dB] occurs in the input signal.

Conversely, +3.0 is applied to the control terminal 3._(V)Is applied
The gate potential of the FET 1 becomes 0 _(V), Sauce, dresse
In is +3.0 of the same potential as the control terminal 3._(V)Because
FET1 is equivalently -3.0 at the gate._(V)Is applied
And the threshold voltage is -1.5 V or more.
FET1 is open. Therefore, the signal input terminal 1
Even if a signal is input, the signal cannot pass.

The leakage signal that has passed through the FET 1 passes through the capacitor 5, the FET 2, and the capacitor 10 to the ground G.
Guided to ND. For this reason, isolation between the terminals 1 and 2 can be reliably obtained. Next, a second specific example of the present invention will be described with reference to FIG. FIG. 3 shows input / output terminals 1,
A first field-effect transistor FET1 which uses a channel portion between a drain and a source of the field-effect transistor provided between the first and second transistors as a signal path; a first input / output terminal 2 and a drain of the first field-effect transistor FET1; Or a first capacitor 16 provided between any one terminal of the source and a second capacitor provided between the second input / output terminal 1 and the other terminal of the first field effect transistor FET1. In a semiconductor switch circuit comprising: 14, 15 and a second field-effect transistor FET2 for ensuring isolation by dropping the signal path to the ground, two serially-connected two-ports constituting the second capacitor are provided. And capacitors for controlling switching of the first and second field-effect transistors. A terminal 3, a power source P, which is connected to the other terminal of said first field effect transistor FET1,
A first resistor 19 provided between the gate of the first field-effect transistor FET1 and the control terminal 3,
A connection line W provided between a connection point J between the two series-connected capacitors 14 and 15 and one of a drain terminal and a source terminal of the second field-effect transistor FET2; Transistor FET2
A second resistor 17 provided between the gate of the second transistor and the ground GND, a third resistor 18 provided between the other terminal of the second field-effect transistor FET2 and the control terminal 3, The second field effect transistor FET2
2 shows a semiconductor switch circuit composed of the other terminal of the first embodiment and a capacitor 10 provided between the ground GND.

Also, there is shown a semiconductor switch circuit in which an inductor 13 is connected in parallel to the two capacitors 14 and 15 connected in series. Next, the second specific example of the present invention will be further described with reference to FIG. 3. The circuit of FIG. 3 connects the inductor 13 having the inductance L in parallel with the capacitors 14 and 15, and
15 total capacitors C and resonance common wave number

[0021]

(Equation 1)

In the OFF state shown in FIG. 3 (b), the signal input from the input / output terminal 1 includes a capacitor (capacitance C ₁ ) 14 and an inductor 13 ( L) and the capacitor 15 (capacitance C ₂ ) via two paths, that is, a path forming a series resonance circuit.
, And is grounded via the ON resistance R ′ _ON of the FET 2 and the capacitor 10. Where the resonance frequency of the series resonance circuit

[0023]

(Equation 2)

When set to a desired frequency,
Is more impedance than the impedance of the capacitor 14.
With the inductor 13 forming the low-power series resonance circuit.
When the input signal passes through the capacitor 15, the grounding property is improved.
Up. In the ON state, input from the input signal terminal 1
The signal thus obtained is connected to the inductor 13 forming the parallel resonance circuit.
Resonant frequency f of total capacitor C affects desired frequency
By setting to a frequency that does not affect
Is a signal input from the input / output terminal 1
3 and input / output terminals via FET 1 and capacitor 16
2 reduces the loss of the input signal.
It is. For example, C ₁= 1pF, C_Two= 10 pF, L =
Assuming 2.5 nH, the resonance frequency of the parallel resonance circuit at the time of ON
number

[0025]

(Equation 3)

The series resonance circuit frequency at OFF

[0027]

(Equation 4)

If the frequency of the input signal is 1 GHz, the impedance of the inductor 13 is Z ¹ = ωL = 15.7Ω when ON, as compared with the passing impedance Z = 1 / ωC = 175Ω when there is no inductor. 1 /
It is reduced to 10 or less. For example, if Z = 15.7Ω is to be realized by a capacitor, C = 10 pF is required. In this case, C ₁ = C ₂ = 20 pF, and C ₁ = ₁ pF, C ₂ = 10 pF, and L = 2.5nH
A large area is required as compared with. Further, the passing loss of the switch circuit at this time is as shown in FIG. 1 (0.5 [dB] for each of the capacitors 14, 15, and 16;
Assuming 2.5 [dB] as 1.0 [dB], FIG.
Is assumed that the loss of the inductor 13 is 0.1 [dB],
(Because only the loss of the capacitor 16 and FET1)
The loss is 1.6 [dB], and there is an effect of approximately 1 [dB].

Next, a third embodiment of the present invention will be described with reference to FIGS. Instead of setting two applied voltages to the control terminal 3 of the switch circuit shown in FIG. 1, the switch circuit is used as a gain control circuit by applying a continuously changing voltage. The input side of the amplifier 14 is connected to the input / output terminal 2 of the switch circuit shown in FIG. 1 to constitute a gain control amplifier. Since the insertion loss (loss) in the ON state of the switch circuit shown in FIG. 1 is -A [dB], if the gain of the amplifier is B [dB], the gain of the gain control amplifier shown in FIG. −A [dB], and the voltage of the control terminal 3 is changed from 0 → +
FIG. 7B shows an example of the characteristics when the _voltage is changed to V _[V] . -C + B in the figure is the gain when the gain is minimized, and the gain change amount of the gain control circuit is ΔG ₀ =
AC.

Next, a fourth embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. Like the switch circuit shown in FIG. 1, the switch circuit shown in FIG. 3A is naturally used as a gain control circuit. In particular, since the switch circuit of FIG. 3 has a smaller insertion loss than the switch circuit of FIG. 1, if the gain control amplifier is configured with two switch circuits as shown in FIG. ΔG ₁ = D−C (D <
In the case of A), ΔG ₂ = 2 (D−C) in two stages.
Generally, since C >>A> D, ΔG ₂ >> ΔG ₁ > ΔG
_It becomes ₀ , and the gain control amount is almost doubled. FIG. 8A shows an example of this characteristic.

Next, a fifth embodiment of the present invention will be described with reference to FIG. In this example, a large gain control amount is obtained as in FIG. 5 by removing the output-side capacitor of the gain control circuit of FIG. 4 and simultaneously changing the gate bias of the first-stage FET of the amplifier 14. Compared to FIG. 5, the gain control circuit has one stage and the output side capacitor 6 is removed, so that the semiconductor integrated circuit has an advantage that a large gain control amount can be obtained with a small area. Referring to FIG. 6 in detail, when the FET 7 of the amplifier is of the enhancement type, the source of the FET 7 is connected to the source resistor 27 of the FET 7 and is supplied with the potential V _b (> 0). When the control voltage terminal 21 is 0 _(V) , the control terminal 2
The divided potential V _a is now a 1-dividing resistors 28, V
_a = 0 _[V] .

Therefore, FET1 has a potential of 0 _{(V) at} its gate,
Since V _{b [V]} is applied to the source and the drain, OF
Since Fb is _{Vb [V] at} the gate and 0 _[V] at the source and drain, the FET2 is turned ON and the gain control amount is minimized. At the same time, the first stage FET7 of the amplifier
Has a gain of 0 _[V] and a source potential of _{Vb [V]} , so that the FET 7 has no gain. As the control terminal voltage approaches + V _(V) from 0 v, FET1 is ON, FET2 is turned OFF, the gate bias of the first-stage FET7 amplifier becomes shallower (V _a becomes higher V _b) at the same time gain maximum -A + B [DB] is obtained. An example of this characteristic is shown in FIG.

In the figure, E denotes the gain (loss) of the amplifier when the gate potential of the first stage FET 7 of the amplifier is -Vb _[V] . When the gain change amount is 0 → + V, −A + B → −C
Since −E, ΔG ₃ = −A + B−C−E [dB] is obtained. Further, in this specific example, even if the threshold voltage V _{th of the} FET changes, the source potential V _b of the first-stage FET 7 of the amplifier changes with V _th , so that the variation of the gain change amount of the gain control circuit is reduced. There is an advantage that can be suppressed. This is briefly summarized in Table 2.

Further, when the values of A to E are specifically shown at 1 GHz, A = 2.5 [dB], B = 15 [dB],
= -20 [dB], D = 1.6 [dB], E = -30
[DB], the gain change amounts are ΔG ₀ = 1, respectively.
7.5 [dB], ΔG ₁ = 18.4 [dB], ΔG ₂ =
36.8 [dB], ΔG ₃ = 37.5 [dB],
The fifth specific example is a circuit that is small in size, has a large gain change amount, and can also compensate for _Vth . Further, in the FET, even in the depletion mode, the bias setting of the circuit of FIG. 6 (setting of gate potential, source potential, drain potential)
Needless to say, it works only by changing.

[0035]

As described above, according to the present invention, a semiconductor switch circuit having good isolation is provided.
An attenuator circuit with a large variable range was obtained. Further, in the present invention, by reducing the number of control terminals, the chip size can be reduced, and the operability and productivity of the semiconductor element can be improved.

In particular, in the high frequency operation in the microwave region, by changing the pin allocation of the package from the control pins to the ground pins, the number of the ground pins is increased and the operation can be stably performed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a semiconductor switch according to a first specific example of the present invention.

FIG. 2 is an operation explanatory diagram of FIG. 1;

FIG. 3A is a circuit diagram of a second specific example, FIG.
(C) is an operation explanatory diagram of the second specific example.

FIG. 4 is a circuit diagram of a third specific example of the present invention.

FIG. 5 is a circuit diagram of a fourth specific example of the present invention.

FIG. 6 is a circuit diagram of a fifth specific example of the present invention.

FIG. 7 is an operation explanatory diagram of a third specific example.

FIG. 8A is an operation explanatory diagram of a fourth specific example, and FIG.
FIG. 9 is an operation explanatory diagram of the fifth specific example.

FIG. 9 is a circuit diagram of a conventional technique.

FIG. 10 is a circuit diagram of a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input signal terminal 2 Output signal terminal 3 Control terminal 4, 5, 6, 10 Capacitor 7, 8, 9, 12 Resistance 11 Fixed voltage application terminal 13 Inductor 14 Amplifier FET1, 2 Field effect transistor GND Ground P Power supply

Claims (9)

[Claims] A first field-effect transistor having a channel portion between a drain and a source of a field-effect transistor provided between an input / output terminal and a signal path; a first field-effect transistor and the first electric field; A first capacitor provided between one of the drain and source terminals of the effect transistor; and a second capacitor provided between the second input / output terminal and the other terminal of the first field effect transistor. In a semiconductor switch circuit including a capacitor and a second field-effect transistor for ensuring isolation by dropping a path of the signal to ground, two capacitors connected in series constituting the second capacitor are provided. A control terminal for controlling switching of the first and second field effect transistors; and a first field effect transistor. A first resistor for connecting a gate of a star to the ground, a second resistor provided between the other terminal of the first field-effect transistor and the control terminal, and a second electric field. A power supply connected to one of the drain and source terminals of the effect transistor; and a connection line provided between a connection point between the two capacitors connected in series and the one terminal of the second field effect transistor. And a third resistor provided between the gate of the second field-effect transistor and the control terminal; and a capacitor provided between the other terminal of the second field-effect transistor and ground. A semiconductor switch circuit comprising: 2. A first field effect transistor having a channel portion between a drain and a source of a field effect transistor provided between an input / output terminal and a signal path, a first input / output terminal and the first electric field. A first capacitor provided between one of the drain and source terminals of the effect transistor; and a second capacitor provided between the second input / output terminal and the other terminal of the first field effect transistor. In a semiconductor switch circuit including a capacitor and a second field-effect transistor for ensuring isolation by dropping a path of the signal to ground, two capacitors connected in series constituting the second capacitor are provided. A control terminal for controlling switching of the first and second field effect transistors; and a first field effect transistor. A power supply connected to the other terminal of the star, a first resistor provided between the gate of the first field-effect transistor and the control terminal, and a connection point of the two capacitors connected in series A connection line provided between one of a drain terminal and a source terminal of the second field-effect transistor; a second resistor provided between a gate and ground of the second field-effect transistor; A third resistor provided between the other terminal of the second field effect transistor and the control terminal; and a capacitor provided between the other terminal of the second field effect transistor and ground. A semiconductor switch circuit comprising: 3. The semiconductor switch circuit according to claim 1, wherein an inductor is connected in parallel to said two capacitors connected in series. 4. A first field-effect transistor having a channel portion between a drain and a source of a field-effect transistor provided between an input / output terminal as a signal path and an isolation obtained by dropping the signal path to ground. A method of controlling a semiconductor switch circuit comprising a second field-effect transistor, wherein a control voltage is applied to a drain or a source of the first field-effect transistor, and the same control as the control voltage is applied to a gate of the second field-effect transistor A method for controlling a semiconductor switch circuit, comprising applying a voltage to control switching of a first and a second field effect transistor. 5. A first field-effect transistor having a channel portion between a drain and a source of a field-effect transistor provided between an input / output terminal and a signal path, and isolation obtained by dropping the signal path to ground. A method for controlling a semiconductor switch circuit comprising a second field-effect transistor, wherein a control voltage is applied to a gate of the first field-effect transistor, and a source or a drain of the second field-effect transistor has the same voltage as the control voltage. Controlling the switching of the first and second field-effect transistors by applying the control voltage of (i). 6. A first field effect transistor having a channel portion between a drain and a source of a field effect transistor provided between an input / output terminal and a signal path, a first input / output terminal and the first electric field. A first capacitor provided between one of a drain terminal and a source terminal of the effect transistor; and a series connection provided between the second input / output terminal and the other terminal of the first field effect transistor. Second and third capacitors, a second field-effect transistor capable of dropping the signal path to ground, and a control terminal for controlling the first and second field-effect transistors. A first resistor connecting a gate of the first field-effect transistor to the ground, the other terminal of the first field-effect transistor, and the control terminal A power supply connected to one of a drain terminal and a source terminal of the second field-effect transistor; and a connection point between the two series-connected capacitors. A connection line provided between the one terminal of the second field-effect transistor, a third resistor provided between a gate of the second field-effect transistor and the control terminal, An attenuator circuit comprising: a fourth capacitor provided between the other terminal of the second field-effect transistor and the ground. 7. A first field effect transistor having a channel portion between a drain and a source of a field effect transistor provided between an input / output terminal and a signal path, a first input / output terminal and the first electric field. A first capacitor provided between one of a drain terminal and a source terminal of the effect transistor; and a series connection provided between the second input / output terminal and the other terminal of the first field effect transistor. Second and third capacitors, a second field-effect transistor capable of dropping the signal path to ground, and a control terminal for controlling the first and second field-effect transistors. A power supply connected to the other terminal of the first field-effect transistor, and a power supply connected between a gate of the first field-effect transistor and the control terminal. A resistor, a connection line provided between a connection point of the two capacitors connected in series and one of a drain terminal and a source terminal of the second field effect transistor, and the second field effect. A second resistor provided between the gate of the transistor and the ground; a third resistor provided between the other terminal of the second field-effect transistor and the control terminal; An attenuator circuit comprising a capacitor provided between the other terminal of the field effect transistor and ground. 8. The attenuator circuit according to claim 6, wherein an inductor is connected in parallel to the two capacitors connected in series. 9. The attenuator circuit according to claim 8, wherein an output of said attenuator circuit is led to an amplifier, and an amplification degree of said amplifier is controlled simultaneously by said control voltage.