JP2000100818A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a wiring parasitic capacity, when a copper buried wiring is formed by CMP with a low-permittivity film as an inter-wiring insulating film, and a nitride film as a CMP stopper. SOLUTION: A wiring structure with nitride films 4 and 16 as a CMP stopper is so constituted that there is no nitride film between wirings 8 (20) in the same layer. In a manufacturing step, a wiring groove is formed by depositing a low/permittivity film (amorphous carbon) 3 and a nitride film 4. Copper is deposited, and CMP is conducted out with the nitride film 4 as a stopper. The CMP is continued after flattening, so that the upper face of the wiring 8 is made lower than the lower face of the nitride film 4. A low/permittivity film 9, an oxide film 10, and a nitride film 11 are deposited. A through-hole is drilled to form a W plug 14. Then, a low/permittivity film 15 and a nitride film 16 are deposited to form (step a) a wiring groove. Copper is deposited (step b), and CMP is so carried out that the upper face of the wiring 20 is made (step c) lower than the lower face of the nitride film 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a trench-filled wiring called a damascene wiring and a method of manufacturing the same.

[0002]

2. Description of the Related Art In order to improve the performance of LSIs, the miniaturization of devices has been steadily advanced. However, as the wiring width becomes narrower, the wiring resistance increases. It is no longer negligible. In order to reduce the wiring resistance, it has been studied to use Cu having lower resistance than the conventional alloy mainly containing Al as the wiring metal. Since Cu is a material that is difficult to dry-etch, in order to form a Cu wiring, a wiring groove is formed after forming an inter-wiring insulating film, and a chemical mechanical polishing (CMP) is performed after forming a Cu film. A method of removing excess wiring metal on the interlayer film by a method and embedding Cu in the groove is used.

In addition, since the distance between wirings is reduced and the interlayer film is made thinner for miniaturization and higher density of devices, parasitic capacitance of wirings increases, which also causes wiring delay. As a method for dealing with this, a technique for forming an inter-wiring insulating film (or an interlayer film) using a low dielectric constant material having a lower dielectric constant than a conventionally used oxide film material has been developed. . In this case, it is necessary to form a silicon nitride film serving as a stopper on the low dielectric film when the wiring material is buried in the wiring groove by the CMP, so that a two-layer film of the low dielectric film and the silicon nitride film or It is common practice to use a three-layer film of a low dielectric constant film, a silicon oxide film, and a silicon nitride film as an interwiring insulating film.

Meanwhile, recently, a fluorine-added amorphous carbon film has been developed as an inorganic low dielectric constant film and has attracted attention. Next, a conventional wiring forming method using a fluorine-added amorphous carbon film as an interwiring insulating film will be described with reference to FIGS. First, FIG.
As shown in FIG. 1A, a first silicon nitride film 2 is formed on a silicon substrate 1 on which a semiconductor element is formed and a flat interlayer insulating film and a contact plug (not shown) are formed. A first inter-wiring insulating film 3 made of amorphous carbon is formed, and a second silicon nitride film 4 is further formed. Next, as shown in FIG. 18B, a first resist film 5 having an opening in a wiring groove shape is formed by photolithography. Next, as shown in FIG. 18C, the second silicon nitride film 4 and the first inter-wiring insulating film 3 are etched to form the first wiring trench 6, and the resist film is removed. The etching conditions are selected so that the etching stops at the first silicon nitride film 2.

Next, as shown in FIG. 19A, a first metal film 7 made of copper is formed by electrolytic plating. Next, as shown in FIG. 19B, a surplus metal film is removed by a CMP method and a metal is buried in the groove to form a first metal wiring 8. At this time, the second silicon nitride film functions as a CMP stopper, and the first inter-wiring insulating film 3 is not removed. Next, as shown in FIG. 19C, a second inter-wiring insulating film 9 and a third silicon nitride film 11 made of fluorine-added amorphous carbon are formed.

Next, as shown in FIG. 20A, a second resist film 12 having an opening in a through-hole pattern is formed by photolithography. Next, FIG.
0 (b), the third silicon nitride film 11 and the second inter-wiring insulating film 9 are formed using the second resist film 12 as a mask.
Is etched to open a through hole 13, and then the resist film is removed. Next, as shown in FIG. 20C, the inside of the through-hole 13 is filled with tungsten to form a through-hole plug 14. This is realized by depositing tungsten on the entire surface and applying an etch-back method or a CMP method.

Next, as shown in FIG. 21A, a third wiring insulating film 1 made of fluorine-added amorphous carbon is formed.
The fifth and fourth silicon nitride films 16 are formed. Next, as shown in FIG. 21B, after the above-described wiring groove forming step, a second metal film 19 made of copper is formed by an electrolytic plating method. Thereafter, as shown in FIG.
The second metal wiring 20 buried in the wiring groove is formed by performing CMP using the silicon nitride film 16 as a stopper.

[0008]

In the prior art described above, the second and fourth silicon nitride films 4 are used as stopper films at the time of CMP for embedding the first and second metal wirings 8 and 20 in the insulating film. , 16 are used. Therefore, a silicon nitride film having a high relative dielectric constant exists between the metal wirings 8 and 20 in addition to the first and third wiring insulating films which are low dielectric constant insulating films. As a result, not only the inter-wiring insulating film made of a low dielectric constant material but also a stopper material having a high dielectric constant contributes to the inter-wiring capacitance of the metal wiring. Accordingly, as the wiring becomes finer, not only the wiring width but also the wiring interval and the wiring film thickness are becoming smaller, and the ratio of the stopper film to the insulating film amount between the wirings is becoming very large. For this reason, there arises a problem that the inter-wiring capacitance is not sufficiently reduced even if a low dielectric constant film is used as the inter-wiring insulating film.

This will be described in more detail with reference to FIG. FIG. 22 shows a simulation result of the dependence of the wiring capacitance on the thickness of the stopper film under the condition that the thickness of the wiring and the thickness of the laminated interlayer film (inter-layer insulating film and CMP stopper film) are constant at 5000 °. It is shown. The wiring width was 0.2 μm and the wiring interval was 0.2 μm. The material of the stopper film was a silicon oxide film or a silicon nitride film, and the material of the inter-wiring insulating film was a silicon oxide film or a low dielectric constant material. The relative permittivity of each material was 4.2 for the silicon oxide film, 6.0 for the silicon nitride film, and 2.5 for the low dielectric constant material. In addition, a structure in which there is no stopper film and all layers are silicon oxide films was also evaluated.

According to this, when a silicon nitride film having a high relative dielectric constant is used for the stopper film, the wiring capacitance is increased by up to 40% as compared with the case of using a silicon oxide film (shown by a circle in FIG. 22). ● compare). Further, as the thickness of the stopper film increases, the wiring capacitance increases. In particular, looking at the laminated structure of silicon nitride film / low dielectric constant material / silicon nitride film,
When the thickness of the stopper film is 1500 ° or more, the wiring capacity becomes larger than when all the layers are silicon oxide films (compare the dotted line with ● in FIG. 22), meaning that a low dielectric constant material is applied to the inter-wiring insulating film. Is lost. Therefore, an object of the present invention is to solve the above-mentioned problems of the conventional example. The main object of the present invention is to form a trench buried wiring using a low dielectric constant film as an inter-wiring insulating film, and to provide a CMP stopper film. An object is to enable the wiring capacitance to be sufficiently reduced regardless of the existence.

[0011]

According to the present invention, there is provided, in accordance with the present invention, a semiconductor device having a trench-filled wiring in which an inter-wiring insulating film includes a low dielectric constant film. The space between the wiring layers is filled with a wiring filling insulating film made of a material having a lower relative dielectric constant than the high relative dielectric constant film serving as a CMP stopper, and the upper surface of the wiring filling insulating film serves as a CMP stopper. A semiconductor device characterized by being covered with a high dielectric constant film, or
In a semiconductor device having a trench-filled wiring in which an inter-wiring insulating film includes a low-dielectric-constant film, at least one wiring has a thickness smaller than the thickness of the wiring and a high relative dielectric constant serving as a CMP stopper. The upper end portion is embedded in the inter-filling insulating film made of a material having a lower relative dielectric constant than the dielectric film in such a manner that the upper end protrudes from the inter-filling insulating film, and A semiconductor device is provided in which the protruding portion is covered with a low dielectric constant film on the side surface and the upper surface except for a through hole portion.

In order to achieve the above object, according to the present invention, (1) a step of forming an inter-wiring insulating layer including a low relative dielectric constant film and a high relative dielectric constant film serving as a CMP stopper;
(2) selectively removing the inter-wiring insulating layer by etching to form a wiring groove penetrating the inter-wiring insulating layer;
(3) forming a wiring material film completely filling the wiring groove on the inter-wiring insulating layer; and (4) performing CMP using the high relative dielectric constant film as a CMP stopper to form a wiring material film on the inter-wiring insulating layer. Removing the wiring material film and embedding the wiring material film in the wiring groove, and (5) polishing the wiring material film in the wiring groove by successively performing CMP to reduce the surface height to the high relative dielectric constant film. Forming a wiring layer below the lower surface of the semiconductor device, or removing the high relative dielectric constant film used as the CMP stopper in the step (4). .

[0013]

FIG. 23 to FIG. 25 are simulation results of capacitance characteristics for explaining the operation of the present invention. FIG.
In the case where a silicon oxide film is used as a first inter-wiring insulating film and a silicon nitride film is used as a stopper film above and below the wiring, the thickness of the metal wiring is set to 5000 °, the thickness of the silicon nitride film is set to 1000 °, and 4 shows a simulation result of wiring capacitance when the thickness of the silicon oxide film of FIG. The relative permittivity of the silicon oxide film is 4.2, and the relative permittivity of the silicon nitride film is 6.
0 was set. When the thickness of the silicon oxide film is 4000 °, it is a conventional structure in which both a silicon oxide film and a silicon nitride film as a stopper film exist between wirings. When the thickness of the silicon oxide film is 5000 °, the structure of the present invention has only the silicon oxide film between the wirings. As the thickness of the silicon oxide film increases, the wiring capacity decreases, and it can be seen that the wiring capacity can be reduced by about 5% in the structure of the present invention.

FIG. 24 shows a case where a fluorine-added amorphous carbon film is used as the first inter-wiring insulating film, and a silicon nitride film is used as a stopper film above and below the wiring. 10 thick
The wiring capacitance simulation results when the thickness of the fluorine-added amorphous carbon film between the wirings is changed from 4000 ° to 5000 ° are set to 00 °. The relative dielectric constant of the fluorine-added amorphous carbon film was 2.5. As in FIG. 23, the fluorine-added amorphous carbon film
It can be seen that the case of 00 ° is the structure of the present invention, and has an effect of reducing the wiring capacitance by 10% as compared with the conventional structure in which the fluorine-added amorphous carbon film and the silicon nitride film exist between the wirings.

Further, as shown in FIG. 25, a fluorine-added amorphous carbon film is used as a first inter-wiring insulating film.
Even when a silicon oxide film is used as the stopper film above and below the wiring, the wiring capacity can be reduced by about 5% of the structure in which the fluorine-added amorphous carbon film and the silicon oxide film exist between the wirings. Therefore, by preventing the presence of a high relative dielectric constant film such as a silicon nitride film between the wirings, it is possible to reduce the wiring capacitance by utilizing the feature of using the low relative dielectric constant film as the insulating film between the wirings. Will be possible.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the accompanying drawings. [First Embodiment] FIG. 5C is a sectional view of a semiconductor device according to a first embodiment of the present invention. Since this structure becomes apparent by knowing the manufacturing process, the manufacturing method will be described below with reference to FIGS. First, as shown in FIG. 1A, a first silicon nitride film 2 is formed on a silicon substrate 1 on which a semiconductor element is formed and a flat interlayer insulating film and a contact plug (not shown) are formed at a thickness of 1000 to 2000. A first inter-wiring insulating film 3 made of fluorine-doped amorphous carbon is formed by a CVD method, and a second silicon nitride film 4 is formed by a CVD method to a thickness of 1,000 to 2,000. To form a film.

Next, as shown in FIG. 1B, a first resist film 5 having a wiring groove-shaped opening is formed by photolithography. The wiring width (wiring groove width) is not particularly limited, but the wiring interval is set to 0.2 μm or less. Next, as shown in FIG. 1C, the first silicon nitride film 4 and the first inter-wiring insulating film 3 are etched using the first resist film 5 as a mask to form a first wiring groove 6, and the first wiring groove 6 is formed. Resist film 5
Is removed. At this time, the etching conditions are selected so that the etching stops at the first silicon nitride film 2.

Next, as shown in FIG. 2A, a first metal film 7 made of copper is formed by electrolytic plating. Next, as shown in FIG. 2 (b), an excess metal film is removed by a CMP method and metal is buried in the trench, and the first metal wiring 8 is formed.
To form The CMP conditions are a pressure of 2.0 psi and a back pressure of 1.5 psi. After the surplus metal film is removed from the second silicon nitride film 4, the metal film is excessively polished by continuing the CMP so that the wiring thickness is equal to or less than the thickness of the first inter-wiring insulating film 3. And At this time, in the area other than the groove, the second
The silicon nitride film 4 functions as a CMP stopper, and the first inter-wiring insulating film 3 is not removed. Next, FIG.
As shown in (1), a second inter-wiring insulating film 9 made of fluorine-added amorphous carbon is formed by a CVD method.

Next, as shown in FIG. 3A, an interlayer silicon oxide film 10 is formed to compensate for a step between the surface of the second silicon nitride film 4 and the surface of the first metal wiring 8. CM
After planarization by the P method, a third silicon nitride film 11 is further formed. Next, as shown in FIG. 3B, a second resist film 12 having an opening having a desired through-hole shape is formed by photolithography. The shape of the through-hole is 0.2 μm square. Then, the second resist film 1
The third silicon nitride film 11 is selectively etched using 2 as a mask. Next, as shown in FIG. 3C, after the resist film is removed, the interlayer silicon oxide film 10 and the second inter-wiring insulating film 9 are selectively etched using the third silicon nitride film 11 as a mask. A through hole 13 is opened.

Next, as shown in FIG. 4A, a through-hole plug 14 is formed by filling the through-hole 13 with tungsten. This is achieved by depositing tungsten on the entire surface and removing the tungsten on the third silicon nitride film by applying an etch-back method or a CMP method. Next, as shown in FIG. 4B, a third inter-wiring insulating film 15 and a fourth silicon nitride film 16 made of fluorine-added amorphous carbon are formed. Next, FIG.
As shown in (c), a third resist film 17 having an opening in a wiring groove shape is formed by photolithography.

Next, as shown in FIG. 5A, using the third resist film 17 as a mask, the fourth silicon nitride film 16 and the third inter-wiring insulating film 15 are etched to form a second wiring groove 18. Then, the resist film is removed. Next, FIG.
As shown in (b), a second metal film 19 made of copper is formed by an electrolytic plating method. Next, as shown in FIG. 5C, a second layer on the fourth silicon nitride film 16 is formed by a CMP method.
The metal film 19 is polished and removed to form a second metal wiring 20 in the wiring groove.
To form When forming the second metal wiring 20,
As in the case of forming the first metal wiring 8, the metal film 1 is excessively formed.
9, the surface height of which is the fourth silicon nitride film 1
6 below. Hereinafter, a through-hole plug and a buried metal wiring are further formed in an upper layer as necessary.

In the method according to the present embodiment, the step of excessively polishing by CMP for embedding the wiring groove with metal is employed. Therefore, the metal film recedes in the wiring groove portion, so that the silicon nitride film having a large relative dielectric constant is used. However, there is an advantage that a structure that does not exist between metal wirings can be realized without increasing the number of steps.

[Second Embodiment] FIG. 8C is a sectional view of a semiconductor device according to a second embodiment of the present invention. Since this structure becomes apparent by knowing the manufacturing process, the manufacturing method will be described below with reference to FIGS. First, as shown in FIG. 6A, a first silicon nitride film 2 is formed on a silicon substrate 1 on which a semiconductor element is formed and a flat interlayer insulating film and a contact plug (not shown) are formed from 1000 ° to 20 °.
A first inter-layer insulating film 3 made of fluorine-added amorphous carbon is formed, and a first silicon oxide film 21 is formed to a thickness of 300 to 500 °. The silicon nitride film 4 is changed from 1000Å to 20
A film is formed to a thickness of 00 °. Next, as shown in FIG. 6B, a first resist film 5 having an opening in a wiring groove shape is formed by photolithography, and the second silicon nitride film 4 is patterned using the first resist film 5 as a mask. The wiring width (wiring groove width) is not limited, but the wiring interval is set to 0.2 μm or less. Next, as shown in FIG. 6C, the resist film is peeled off, and then the first silicon oxide film 21 and the first inter-wiring insulating film 3 are etched using the second silicon nitride film 4 as a mask. The first wiring groove 6 is formed. The etching conditions are selected so that the etching stops at the first silicon nitride film 2.

Next, as shown in FIG. 7A, a first metal film 7 made of copper is formed by an electrolytic plating method. Next, as shown in FIG. 7B, the metal film on the second silicon nitride film 4 is removed by the CMP method, and the wiring film thickness is further reduced by the first inter-wiring insulating film 3 and the first silicon oxide film 21. The CMP is continued until the total film thickness becomes equal to or less than the total film thickness of the first metal wiring 8 formed in the wiring groove. At this time, in a region other than the groove, the second silicon nitride film 4 functions as a CMP stopper, and the underlying first silicon oxide film 21 is not etched. Next, as shown in FIG. 7C, a second inter-wiring insulating film 9 made of fluorine-added amorphous carbon is formed by a CVD method.

Next, as shown in FIG. 8A, an interlayer silicon oxide film 10 is formed, planarized by a CMP method, and a third silicon nitride film 11 is formed. Next, FIG.
As shown in FIG. 2B, after forming a through hole penetrating the third silicon nitride film 11, the interlayer silicon oxide film 10, and the second inter-wiring insulating film, tungsten deposition and CMP are performed.
To form a through-hole plug 14. afterwards,
Using the same method as the method of forming the first inter-wiring insulating film 3, the first silicon oxide film 21, the second silicon nitride film 4, and the first metal wiring 8, the third inter-wiring insulating film 15, When the silicon film 22, the fourth silicon nitride film 16, and the second metal wiring 20 are formed, the semiconductor device of the present embodiment shown in FIG. 8C can be obtained.

[Third Embodiment] FIG. 14B is a sectional view of a semiconductor device according to a third embodiment of the present invention. This structure will be clarified by describing the manufacturing process. Hereinafter, FIGS.
The manufacturing method will be described with reference to FIG. First, FIG.
As shown in FIG. 1, a first silicon nitride film 2 is formed on a silicon substrate 1 on which necessary semiconductor elements and wirings are formed by 1000 .ANG.
A first inter-layer insulating film 3 made of fluorine-added amorphous carbon, a first silicon oxide film 21 is formed to a thickness of 300 to 500 mm, and a second nitride film is formed. Silicon film 4 from 1000Å to 2
A film is formed to a thickness of 2,000 mm. Next, as shown in FIG. 9B, a first resist film 5 having an opening in a wiring groove shape is formed by photolithography. Subsequently, the second silicon nitride film 4 is patterned using the first resist film 5 as a mask. Next, as shown in FIG. 9C, the resist film is peeled and removed.

Next, as shown in FIG. 10A, the first silicon oxide film 21 is formed using the second silicon nitride film 4 as a mask.
Then, the first inter-wiring insulating film 3 is selectively etched to form the first wiring trench 6. At this time, the etching conditions are selected so that the etching stops at the first silicon nitride film 2. Next, as shown in FIG.
The metal film 7 is formed by an electrolytic plating method. Next, FIG.
As shown in FIG. 1C, the first metal wiring 8 is formed by removing an excess metal film by a CMP method and filling the groove with metal. At this time, in the region other than the groove, the second silicon nitride film 4 functions as a CMP stopper, and the first silicon oxide film 21
The first inter-wiring insulating film 3 is not removed.

Next, as shown in FIG. 11A, etching conditions are selected so that the silicon oxide film is not etched, and the second silicon nitride film 4 is removed. Next, FIG.
As shown in (b), a second inter-wiring insulating film 9 made of fluorine-added amorphous carbon is formed. Next, FIG.
As shown in (c), the interlayer silicon oxide film 10 is formed to compensate for a step between the surface of the first silicon oxide film 21 and the surface of the first metal wiring 8 due to the absence of the second silicon nitride film 4. The film is planarized by a CMP method, and a third silicon nitride film 11 is further formed.

Next, as shown in FIG. 12A, a second resist film 12 having an opening in the shape of a through hole to be formed is formed by photolithography. The shape of the through-hole is 0.2 μm square. After that, the third silicon nitride film 11 is etched using the second resist film as a mask. Next, as shown in FIG. 12B, after removing and removing the resist film, the third silicon nitride film 11 is used as a mask to etch the interlayer silicon oxide film 10 and the second inter-wiring insulating film 9 to form the through holes 13. Open. Next, as shown in FIG. 12C, the inside of the through-hole 13 is filled with tungsten to form a through-hole plug 14.

Next, as shown in FIG. 13A, a third wiring insulating film 1 made of fluorine-added amorphous carbon is formed.
5, the second silicon oxide film 22 and the fourth silicon nitride film 16 are sequentially formed by the CVD method. Next, as shown in FIG. 13B, a third resist film 17 having an opening in a wiring groove shape is formed by photolithography. Thereafter, using the third resist film 17 as a mask, the fourth resist
The silicon nitride film 16 is etched. Next, FIG.
As shown in (c), after the third resist film 17 is peeled off, the second silicon oxide film 22 and the second inter-wiring insulating film 15 are etched using the fourth silicon nitride film 16 as a mask to form a second wiring trench. 18 are formed.

Next, as shown in FIG. 14A, a second metal film 19 made of copper is formed by an electrolytic plating method. Then, in the same manner as when the first metal wiring 8 was formed, C
When the second metal film 19 is polished by the MP method to form the second metal wiring 20 and the fourth silicon nitride film 16 is removed by etching, the semiconductor device of this embodiment shown in FIG. 14B is obtained. .

In this embodiment, the silicon oxide film remains between the wirings, but its thickness is 300 to 500.degree., Which is larger than that of the prior art where the silicon nitride film is thick. The capacity can be reduced. The method according to the present embodiment employs a step of removing the silicon nitride film serving as a stopper film when the metal film is subjected to CMP using the silicon oxide film as an etching stopper. Therefore, although the number of steps increases, there is an advantage that the thickness of the metal wiring and the amount of insulator between the wirings can be easily controlled.

[Fourth Embodiment] FIG. 17C is a sectional view of a semiconductor device according to a fourth embodiment of the present invention. The structure of this embodiment will be clarified by describing its manufacturing process. Hereinafter, FIG.
The manufacturing method will be described with reference to FIGS.
First, as shown in FIG. 15A, a first silicon nitride film 2 is formed on a silicon substrate 1 on which a semiconductor element is formed and a flat interlayer insulating film and a contact plug (not shown) are formed at a thickness of 1000 to 2000. A first interlayer insulating film 3 made of fluorine-added amorphous carbon is formed, and a second silicon nitride film 4 is formed
A film is formed to a thickness of 2,000 to 2,000. Next, FIG.
As shown in FIG. 5B, a first resist film 5 having a wiring groove-shaped opening is formed by photolithography. Next, as shown in FIG. 15C, the second silicon nitride film 4 and the first inter-wiring insulating film 3 are etched to
After forming the wiring groove 6, the resist film is removed. The etching conditions are selected so that the etching stops at the first silicon nitride film 2.

Next, as shown in FIG. 16A, a first metal film 7 made of copper is formed by an electrolytic plating method. Next, as shown in FIG. 16B, a surplus metal film is removed by a CMP method and a metal is buried in the groove to form a first metal wiring 8. At this time, in the region other than the groove, the second silicon nitride film 4 functions as a CMP stopper, and the first inter-wiring insulating film 3 is not etched. Next, as shown in FIG. 16C, the second silicon nitride film 4 is dry-etched.
Is removed. At this time, the first
Even if the film thickness of the inter-wiring insulating film 3 is slightly reduced, there is no problem because it is compensated in the next step of forming the insulating film.

Next, as shown in FIG. 17A, a second inter-wiring insulating film 9 made of fluorine-added amorphous carbon is formed.
Is formed. Next, as shown in FIG. 17B, in order to compensate for a step between the surface of the first inter-wiring insulating film 3 and the surface of the first metal wiring 8, an interlayer silicon oxide film 10 is formed and a CM is formed.
After planarization by the P method, a third silicon nitride film 11 is further formed. Next, after forming a through hole penetrating the third silicon nitride film 11, the interlayer silicon oxide film 10, and the second inter-wiring insulating film 9 and forming a through-hole plug 14, the first inter-wiring insulating film 3 and the first metal If the third inter-wiring insulating film 15 and the second metal wiring 20 are formed using the same method as the method for forming the wiring 8, the semiconductor device of the present embodiment shown in FIG. 17C can be obtained. it can.

In the semiconductor device according to this embodiment, since only a low dielectric constant film exists between the wirings, the wiring capacitance is equal to or smaller than that of the other embodiments described above. In this embodiment,
When the silicon nitride film serving as the stopper film is etched when the metal film is subjected to the CMP, it is inevitable that the inter-wiring insulating film is also etched to some extent. However, compensation can be sufficiently obtained by forming an insulating film in a later step. This embodiment has an advantage that a CMP stopper film having a large relative dielectric constant can be prevented from being left between wirings without increasing the number of steps.

Although the preferred embodiments have been described above, the present invention is not limited to these embodiments, and can be appropriately changed without changing the gist. For example, in each of the above embodiments, the fluorine-added amorphous carbon was used for the inter-wiring insulating film.
Other inorganic materials such as F) and HSQ (hydrogen silsesquioxane) or organic materials such as polyimide and benzocyclobutene may be used. Further, the stopper film is not limited to the silicon nitride film of the embodiment, but may be a silicon oxide film or the like as long as the etching speed and the CMP polishing speed are different from those of the inter-wiring insulating film. The wiring material and the through-hole material are not limited to the copper and tungsten described in the embodiment, but may be an aluminum alloy or the like.

[0038]

As described above, according to the semiconductor device of the present invention, in a semiconductor device having a wiring having a damascene structure, a high dielectric constant material such as a silicon nitride film is not interposed between wirings in the same layer. Therefore, the wiring capacitance can be kept low even in a miniaturized and high-density semiconductor device. Therefore, according to the present invention, a high-performance semiconductor device with less wiring delay can be provided.

[Brief description of the drawings]

FIG. 1 is a part of a process order sectional view for explaining a manufacturing method according to a first embodiment of the present invention.

FIG. 2 is a part of a process order cross-sectional view in a step that follows the step of FIG. 1 for explaining the manufacturing method of the first embodiment of the present invention;

FIG. 3 is a part of a process order cross-sectional view in a step that follows the step of FIG. 2 for explaining the manufacturing method of the first embodiment of the present invention;

FIG. 4 is a part of a process order sectional view in a step that follows the step of FIG. 3 for explaining the manufacturing method of the first embodiment of the present invention.

FIG. 5 is a step-by-step sectional view in a step that follows the step of FIG. 4 for explaining the manufacturing method of the first embodiment of the present invention.

FIG. 6 is a part of a process order sectional view for explaining the manufacturing method according to the second embodiment of the present invention.

FIG. 7 is a part of a process order cross-sectional view in a step that follows the step of FIG. 6 for explaining the manufacturing method of the second embodiment of the present invention;

FIG. 8 is a step-by-step cross-sectional view in a step that follows the step of FIG. 7 for illustrating the manufacturing method of the second embodiment of the present invention.

FIG. 9 is a partial cross-sectional view in a process order for describing a manufacturing method according to a third embodiment of the present invention.

FIG. 10 is a part of a process order cross-sectional view in a step that follows the step of FIG. 9 for explaining the manufacturing method of the third embodiment of the present invention;

FIG. 11 is a part of a process order cross-sectional view in a step that follows the step of FIG. 10 for explaining the manufacturing method of the third embodiment of the present invention;

FIG. 12 is a part of a process order cross-sectional view in a step that follows the step of FIG. 11 for explaining the manufacturing method of the third embodiment of the present invention;

FIG. 13 is a part of a process order sectional view in a step that follows the step of FIG. 12 for explaining the manufacturing method of the third embodiment of the present invention;

FIG. 14 is a step-by-step sectional view in a step that follows the step of FIG. 13 for explaining the manufacturing method of the third embodiment of the present invention.

FIG. 15 is a part of a process order sectional view for explaining the manufacturing method according to the fourth embodiment of the present invention;

FIG. 16 is a part of a process order sectional view in a step that follows the step of FIG. 15 for explaining the manufacturing method of the fourth embodiment of the present invention;

FIG. 17 is a step-by-step sectional view in a step that follows the step of FIG. 16 for explaining the manufacturing method of the fourth embodiment of the present invention.

FIG. 18 is a part of a process order sectional view for explaining the manufacturing method of the conventional example.

FIG. 19 is a view for explaining a manufacturing method of a conventional example.
Part of a process order sectional view in a step following the step 8.

FIG. 20 is a view for explaining a conventional manufacturing method.
9 is a part of a step-by-step cross-sectional view in a step following the step 9;

FIG. 21 is a view for explaining a conventional manufacturing method.
Sectional sectional view in the step following the step 0.

FIG. 22 is a simulation result for explaining a problem of the conventional example.

FIG. 23 is a simulation result for explaining the operation of the present invention.

FIG. 24 is a simulation result for explaining the operation of the present invention.

FIG. 25 is a simulation result for explaining the operation of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 1st silicon nitride film 3 1st wiring insulating film 4 2nd silicon nitride film 5 1st resist film 6 1st wiring groove 7 1st metal film 8 1st metal wiring 9 2nd wiring insulating film 10 Interlayer silicon oxide film 11 Third silicon nitride film 12 Second resist film 13 Through hole 14 Through hole plug 15 Third interconnect insulating film 16 Fourth silicon nitride film 17 Third resist film 18 Second wiring groove 19 Second metal film Reference Signs List 20 second metal wiring 21 first silicon oxide film 22 second silicon oxide film

Continued on the front page F term (reference) 4M108 BA10 BB04 BC02 BC03 BC08 BC22 BC24 BD03 BE01 BE02 BE03 5F033 HH11 JJ19 KK11 MM01 PP27 QQ08 QQ09 QQ10 QQ23 QQ28 QQ31 QQ35 QQ37 QQ48 QQ49 RR01 RR04 RR06 XXRR

Claims (10)

[Claims] 1. A semiconductor device having trench-filled wiring in which an inter-wiring insulating film includes a low dielectric constant film,
At least one layer between the wirings is filled with a wiring filling insulating film made of a material having a lower relative dielectric constant than a high relative dielectric constant film serving as a CMP stopper, and the upper surface of the wiring filling insulating film is formed with a CMP stopper. Wherein the semiconductor device is covered with a high relative dielectric constant film. 2. A semiconductor device having a trench-buried wiring in which an inter-wiring insulating film includes a low dielectric constant film,
At least one layer of wiring has an upper end filled in an inter-wiring filling insulating film having a thickness smaller than the thickness of the wiring and made of a material having a lower relative permittivity than a high relative permittivity film serving as a CMP stopper. Embedded in a manner to protrude from the insulating film,
In addition, the semiconductor device is characterized in that a portion of the wiring protruding from the inter-wiring filling insulating film is covered with a low dielectric constant film on a side surface and an upper surface thereof except for a through hole portion. 3. The low-permittivity insulating film formed of only the low-permittivity insulating film, or a low-permittivity insulating film formed on the low-permittivity insulating film and a lower-permittivity insulating film formed thereon. 3. The semiconductor device according to claim 1, further comprising an intermediate dielectric constant insulating film having a high relative dielectric constant lower than that of the high relative dielectric constant insulating film. 4. The wiring according to claim 1, wherein the wiring is formed of copper or a material containing copper as a main component.
13. The semiconductor device according to claim 1. 5. A multi-layer trench-filled wiring is laminated with an interlayer insulating film interposed therebetween.
3. The semiconductor device according to claim 1, wherein the semiconductor devices are connected by through-hole plugs made of tungsten embedded in the interlayer insulating film. 6. The semiconductor device according to claim 1, wherein said low relative dielectric constant film is formed of fluorine-added amorphous carbon. 7. The semiconductor device according to claim 1, wherein said high relative dielectric constant film is formed of silicon nitride. 8. An inter-wiring insulating layer including a low-permittivity film and a high-permittivity film serving as a CMP stopper; and (2) selectively removing the inter-wiring insulating layer by etching. Forming a wiring groove penetrating the inter-wiring insulating layer, and (3) forming a wiring material film completely filling the wiring groove on the inter-wiring insulating layer; CMP using relative dielectric constant film as CMP stopper
Performing a step of removing the wiring material film on the inter-wiring insulating layer and embedding the wiring material film only in the wiring groove; and (5) polishing the wiring material film in the wiring groove by subsequently performing CMP. Forming a wiring layer whose surface height is equal to or lower than the lower surface of the high relative permittivity film. 9. An inter-wiring insulating layer including a low-permittivity film and a high-permittivity film serving as a CMP stopper; and (2) selectively removing the inter-wiring insulating layer by etching. Forming a wiring groove penetrating the inter-wiring insulating layer, and (3) forming a wiring material film completely filling the wiring groove on the inter-wiring insulating layer; CMP using relative dielectric constant film as CMP stopper
Forming the wiring embedded in the wiring groove by removing the wiring material film on the inter-wiring insulating layer; and (5) the high relative dielectric constant used as a CMP stopper in the previous step. Selectively removing the film by etching. 10. The relative dielectric constant between the low dielectric constant film and the high relative dielectric constant film serving as the CMP stopper, which is intermediate between the relative dielectric constants of the two insulating films, in the first step (1). 10. The method for manufacturing a semiconductor device according to claim 8, wherein an insulating film having the following is formed.