JP2000100054A - Secondary storage device - Google Patents
Secondary storage deviceInfo
- Publication number
- JP2000100054A JP2000100054A JP10267893A JP26789398A JP2000100054A JP 2000100054 A JP2000100054 A JP 2000100054A JP 10267893 A JP10267893 A JP 10267893A JP 26789398 A JP26789398 A JP 26789398A JP 2000100054 A JP2000100054 A JP 2000100054A
- Authority
- JP
- Japan
- Prior art keywords
- power
- storage device
- secondary storage
- cache memory
- hard disk
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、パーソナルコンピ
ュータ等に使用されるハードディスク等の二次記憶装置
の省電力に関するものである。The present invention relates to power saving of a secondary storage device such as a hard disk used in a personal computer or the like.
【０００２】[0002]
【従来の技術】従来、ハードディスク等の二次記憶装置
の省電力は、一定時間アクセスがない場合にディスクの
モーターをオフする手法が一般に行われている。またア
イドル状態の時には、サーボ系回路への電源をオフする
等の手法も用いられる場合がある。2. Description of the Related Art Conventionally, in order to save power of a secondary storage device such as a hard disk, a method of turning off a motor of a disk when access is not performed for a certain period of time is generally performed. In the idle state, a method of turning off the power to the servo circuit may be used.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、アクセ
ス速度の高速化のため大容量のキャッシュを搭載する事
が多くなり、二次記憶装置のディスクのモーターオフや
サーボ系回路への電源オフだけでは十分な省電力が得ら
れなくなっているのが現状である。本発明は二次記憶装
置のより一層の省電力を図ることを目的とする。However, in order to increase the access speed, a large-capacity cache is often mounted, and it is not sufficient to turn off the motor of the disk of the secondary storage device or the power supply to the servo circuit. At present, it is no longer possible to obtain significant power savings. An object of the present invention is to further reduce the power consumption of a secondary storage device.
【０００４】[0004]
【課題を解決するための手段】この課題を解決するため
に本発明は、省電力モードに入るタイムアウト時（ディ
スクのモーターオフ時）にはアクセススピードを向上さ
せるキャッシュは動作不要である事に着眼し、同時にキ
ャッシュも電源オフするように構成したものである。SUMMARY OF THE INVENTION In order to solve this problem, the present invention focuses on the fact that a cache for improving access speed is not required to operate when a timeout occurs when a power saving mode is entered (when a disk motor is turned off). At the same time, the cache is also powered off.
【０００５】これにより、正常使用状態の使い勝手の低
下をもたらさずに、省電力時の消費電流をさらに減少さ
せる効果が得られる。As a result, an effect of further reducing current consumption during power saving without lowering usability in a normal use state can be obtained.
【０００６】[0006]
【発明の実施の形態】本発明の請求項１に記載の発明
は、二次記憶装置であって、ホストインターフェース
と、記憶装置と、キャッシュ装置と、アクティビティー
を監視するタイマー処理装置と、電源供給装置とを持
ち、前記電源装置が前記タイマー処理装置からの指示に
より記憶装置の電源を切断するときに同時に前記キャッ
シュ装置の電源も切断する事により、消費電力の削減が
図れるという作用を有する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is a secondary storage device, comprising a host interface, a storage device, a cache device, a timer processing device for monitoring activity, and a power supply. This has the effect of reducing power consumption by simultaneously powering off the cache device when the power supply device powers off the storage device in response to an instruction from the timer processing device.
【０００７】以下、本発明の実施の形態について、図１
を用いて説明する。 （実施の形態１）図１は、本発明の一実施の形態に係る
二次記憶装置のハードウェア構成図である。Hereinafter, an embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. Embodiment 1 FIG. 1 is a hardware configuration diagram of a secondary storage device according to an embodiment of the present invention.
【０００８】図１において１−１はパーソナルコンピュ
ータ等とのホストインターフェース、１−２は電源装
置、１−３はハードディスク装置、１−４はキャッシュ
メモリー、１−５はキャッシュメモリーとホストインタ
ーフェース間のデータバス、１−６はキャッシュメモリ
ー１−４とハードディスク装置１−３間のデータバス、
１−７はタイマー装置である。In FIG. 1, 1-1 is a host interface with a personal computer, etc., 1-2 is a power supply, 1-3 is a hard disk drive, 1-4 is a cache memory, and 1-5 is a connection between the cache memory and the host interface. A data bus 1-6, a data bus between the cache memory 1-4 and the hard disk device 1-3,
1-7 is a timer device.
【０００９】以下その動作について説明する。二次記憶
装置が使用されているときには、ホストインターフェー
ス１−１とハードディスク装置１−３との間は、キャッ
シュメモリー１−４を介してデーターがやり取りされ
る。タイマー装置１−７はかかるアクティビティー（デ
ータのやりとりが行われているかどうか）を監視してい
る。The operation will be described below. When the secondary storage device is used, data is exchanged between the host interface 1-1 and the hard disk device 1-3 via the cache memory 1-4. The timer device 1-7 monitors such an activity (whether or not data is being exchanged).
【００１０】二次記憶装置が使用されなくなると、タイ
マー装置１−７が監視しているアクティビティーがゼロ
になる。タイマー装置１−７は、アクティビティーがゼ
ロになった後一定時間その状態が継続すれば、電源装置
１−２に省電力モードに移行するように指令を出す。電
源装置１−２は、ハードディスク装置１−３とキャッシ
ュメモリー１−４の電源を切断する。When the secondary storage device is not used, the activity monitored by the timer device 1-7 becomes zero. The timer device 1-7 issues a command to the power supply device 1-2 to shift to the power saving mode if the state continues for a predetermined time after the activity becomes zero. The power supply device 1-2 turns off the power of the hard disk device 1-3 and the cache memory 1-4.
【００１１】次にホストインターフェース１−１にデー
ター要求があった場合は、再び電源をオンして処理を進
める。Next, when a data request is made to the host interface 1-1, the power is turned on again and the processing proceeds.
【００１２】通常、キャッシュメモリー１−４はアクセ
スの高速化のために存在し、この機能を無効にするとア
クセス速度が低下するという欠点がある。本発明の場
合、次回アクセス時には、ハードディスク装置１−３の
電源オンシーケンスが必要となるときにのみキャッシュ
メモリー１−４の電源をオフする。ハードディスク装置
１−３に比べて相対的に短時間でキャッシュメモリー１
−４は電源オンで復帰するため、アクセス速度の低下は
無視できるほど小さい。また、一定時間二次記憶装置へ
のアクセスがない場合は、キャッシュメモリー内のデー
タはヒット率が低い場合が多いので実質的アクセス速度
の低下も無視できるほど小さいと考えられる。Normally, the cache memory 1-4 exists for speeding up access, and disabling this function has a disadvantage that the access speed is reduced. In the case of the present invention, at the next access, the power of the cache memory 1-4 is turned off only when a power-on sequence of the hard disk device 1-3 is required. The cache memory 1 is stored in a relatively short time as compared with the hard disk device 1-3.
Since -4 is restored when the power is turned on, the decrease in access speed is negligibly small. Further, when there is no access to the secondary storage device for a certain period of time, the data in the cache memory often has a low hit rate, so that the substantial decrease in the access speed is considered to be negligible.
【００１３】なお、以上の説明では、二次記憶装置をハ
ードディスク装置で構成した例で説明したが、他のフロ
ッピーディスクドライブや光ディスク等の脱着可能な二
次記憶装置についても同様に実施可能である。In the above description, an example has been described in which the secondary storage device is constituted by a hard disk device. However, the present invention can be similarly applied to another removable storage device such as a floppy disk drive or an optical disk. .
【００１４】[0014]
【発明の効果】以上のように本発明によれば、二次記憶
装置のより一層の省電力を図ることが可能となりその効
果は大きい。As described above, according to the present invention, it is possible to further reduce the power consumption of the secondary storage device, and the effect is great.
【図１】本発明の一実施の形態に係る二次記憶装置の構
成図FIG. 1 is a configuration diagram of a secondary storage device according to an embodiment of the present invention.
【符号の説明】 １−１ ホストインターフェース １−２ 電源装置 １−３ ハードディスク装置 １−４ キャッシュメモリー １−５ ホストインターフェースとキャッシュメモリー
の間のデータバス １−６ キャッシュメモリーとハードディスク装置の間
のデータバス １−７ タイマー装置[Description of Signs] 1-1 Host interface 1-2 Power supply 1-3 Hard disk drive 1-4 Cache memory 1-5 Data bus between host interface and cache memory 1-6 Data between cache memory and hard disk drive Bus 1-7 timer device
Claims (1)
前記ホストインターフェースと前記記憶装置との間にあ
るキャッシュ装置と、前記ホストインターフェースまた
は前記記憶装置のアクティビティーを監視するタイマー
処理装置と、前記記憶装置及び前記キャッシュ装置に電
源を供給し前記記憶装置の一部分または全部の電源供給
を切断する事が出来る電源供給装置とを有し、前記電源
供給装置は、前記タイマー処理装置からの指示により前
記記憶装置の一部または全部の電源を切断するときに同
時に前記キャッシュ装置の電源も切断する事を特徴とし
た二次記憶装置。1. A host interface, a storage device,
A cache device between the host interface and the storage device, a timer processing device for monitoring the activity of the host interface or the storage device, and a part of the storage device for supplying power to the storage device and the cache device Or a power supply device capable of cutting off the entire power supply, wherein the power supply device simultaneously turns off the power of a part or all of the storage device according to an instruction from the timer processing device. A secondary storage device characterized in that the power of the cache device is also cut off.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10267893A JP2000100054A (en) | 1998-09-22 | 1998-09-22 | Secondary storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10267893A JP2000100054A (en) | 1998-09-22 | 1998-09-22 | Secondary storage device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000100054A true JP2000100054A (en) | 2000-04-07 |
Family
ID=17451095
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10267893A Pending JP2000100054A (en) | 1998-09-22 | 1998-09-22 | Secondary storage device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000100054A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7076612B2 (en) * | 2000-04-12 | 2006-07-11 | Koninklijke Philips Electronics N.V. | Cache interface circuit for automatic control of cache bypass modes and associated power savings |
| JP2007094995A (en) * | 2005-09-30 | 2007-04-12 | Fujitsu Ltd | Disk storage device and cache control method for disk storage device |
| US7353406B2 (en) | 2003-11-26 | 2008-04-01 | Hitachi, Ltd. | Disk array optimizing the drive operation time |
| JP2009163310A (en) * | 2007-12-28 | 2009-07-23 | Nec Corp | Disk array device, physical disk restoration method, and physical disk restoration program |
| US8009378B2 (en) | 2009-01-30 | 2011-08-30 | Kabushiki Kaisha Toshiba | Storage device and information processing apparatus |
| US9824716B2 (en) | 2015-03-27 | 2017-11-21 | Fujitsu Limited | Storage control apparatus, storage apparatus, and computer-readable recording medium having stored therein storage control program |
-
1998
- 1998-09-22 JP JP10267893A patent/JP2000100054A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7076612B2 (en) * | 2000-04-12 | 2006-07-11 | Koninklijke Philips Electronics N.V. | Cache interface circuit for automatic control of cache bypass modes and associated power savings |
| US7353406B2 (en) | 2003-11-26 | 2008-04-01 | Hitachi, Ltd. | Disk array optimizing the drive operation time |
| US7657768B2 (en) | 2003-11-26 | 2010-02-02 | Hitachi, Ltd. | Disk array optimizing the drive operation time |
| JP2007094995A (en) * | 2005-09-30 | 2007-04-12 | Fujitsu Ltd | Disk storage device and cache control method for disk storage device |
| JP2009163310A (en) * | 2007-12-28 | 2009-07-23 | Nec Corp | Disk array device, physical disk restoration method, and physical disk restoration program |
| US8009378B2 (en) | 2009-01-30 | 2011-08-30 | Kabushiki Kaisha Toshiba | Storage device and information processing apparatus |
| US9824716B2 (en) | 2015-03-27 | 2017-11-21 | Fujitsu Limited | Storage control apparatus, storage apparatus, and computer-readable recording medium having stored therein storage control program |
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