JP2000089728A - Drive control device and electro-optical device - Google Patents

Abstract

(57) [Summary] Even if the characteristics of a TFT or the like constituting a drive circuit change, drive control that can maintain a good operation state as an electro-optical device by driving these in an initial good state. Provided is an apparatus and an electro-optical apparatus including the same. SOLUTION: In a drive control device for controlling a data line drive circuit 101 for driving a pixel in a liquid crystal device S,
The comparison circuit 9 compares the initial driving state, which is the driving state at the first time point, with the driving state at the second time point thereafter, and outputs a control signal Sc indicating the difference, and based on the output control signal Sc, And a timing generator 2 that controls the data line driving circuit 101 to drive the liquid crystal so as to return to the initial driving state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention belongs to the technical field of a drive control device in an electro-optical device typified by an active matrix type liquid crystal device, and more particularly, to maintain a good driving state of each electro-optical device. The present invention belongs to the technical field of a drive control device for performing drive control.

[0002]

2. Description of the Related Art The prior art of an electro-optical device will be described by taking an active matrix type liquid crystal device as an example. In the liquid crystal device, a pixel for applying a voltage to a liquid crystal layer is applied to each pixel portion arranged in a matrix. A switching element (specifically, for example, a two-terminal non-linear element such as a thin film transistor (TFT) or a diode) for applying a later-described image signal to the electrode and the pixel electrode to drive a corresponding liquid crystal layer ).

In each pixel portion, a plurality of scanning lines for applying a scanning signal for controlling on / off of the switching element to each switching element are arranged. A plurality of data lines are arranged so as to intersect in the pixel portion.

[0006] Each scanning line is connected to a scanning line driving circuit, and the scanning signal to be supplied to each scanning line at a predetermined timing is generated in the scanning line driving circuit.

On the other hand, each data line is connected to a data line driving circuit, and the data line driving circuit
The serially transmitted image signal is sampled sequentially,
The sampled image signal is supplied to each data line.

[0006] The image signals sequentially sampled and supplied to the data lines are supplied to the pixel electrodes in the respective pixel units via the switching elements during the period in which the switching elements of the respective pixel units are turned on by the scanning signal. And
A drive voltage according to an image signal is applied to a liquid crystal layer interposed between each pixel electrode and the counter electrode, whereby the liquid crystal molecule arrangement of the liquid crystal layer changes and an image corresponding to the image signal is displayed. Becomes

In the above-mentioned conventional liquid crystal device, in order to improve the resolution, a serial image signal supplied from the outside is converted into a plurality of parallel image signals (hereinafter referred to as phase expansion), and a data line driving circuit is provided. The supply has been done. The outline of this phase development technique will be described by taking as an example a case where an external image signal is developed into six phases.

When an image signal is sequentially supplied to the switching elements in each pixel portion, it is necessary to sample the image signal and apply the image signal to the switching element as described above. In some cases, the response speed of the TFT cannot follow the transmission frequency of the image signal transmitted serially.

Therefore, when the transmission frequency of the image signal is increased, the transmission frequency of the image signal can be followed even if the response speed of the sampling TFT is slow, as shown in FIG.
As shown in FIG. 8, the input image signal is developed into six parallel image signals (indicated by VID1 to VID6 in FIG. 8A) for each dot clock, and the data time per one pixel data is obtained. By extending the length and outputting a plurality of image signals in parallel, the sampling TF
A technique for increasing the sampling period by T has been developed, and this is a so-called phase development technique.

Each number in the image signal in FIG. 8A indicates an image signal to be supplied to a corresponding data line.

Then, the image signals VID1 to VID6 after the phase development are sampled and sequentially supplied to the respective data lines, so that the on-period of the switching of the sampling TFTs is, for example, as shown in FIG. In b), sampling signals for turning on each sampling TFT are indicated as S / H1 to S / H7, respectively.)
Even when the image signal is extended to the length of 4 dot clocks in the image signal, the image signal can be supplied to each data line following the transmission frequency of the input serial image signal.

That is, for example, in the case of the image signal VID1, as shown in FIG. 8C, each data (the first data, the seventh data, the thirteenth data) expanded to the length of six dot clocks. ,...) Are sequentially sampled by a sampling signal for four dot clocks, and sequentially supplied to the corresponding first data line, seventh data line, thirteenth data line. Similarly, with respect to the other image signals VID2 to VID6, each data is sampled in accordance with a sampling signal for 4 dot clocks, respectively.
The data is supplied to the data line in the corresponding order.

[0013]

However, according to the conventional liquid crystal device driving technique based on the phase expansion, the sampling timing changes from the initial state mainly due to the deterioration with time of the transistors constituting the data line driving circuit. As a result, there has been a problem that a so-called ghost may occur during image display. Also,
There is also a problem that the characteristics of the transistor change due to the influence of the use environment temperature of the liquid crystal device, the sampling timing changes from a normal initial state, and a ghost similarly occurs.

That is, the relationship between the image signal transmission timing and the sampling timing shown in FIG. 8 (c) is based on an ideal state in which the transistors constituting the data line driving circuit have no characteristic change due to aging or temperature change. Indicates the timing relationship when the timing is maintained. Actually, the timing relationship may be shifted due to a change in the characteristics of the transistors constituting the data line driving circuit. In that case, the ghost occurs. You do it.

More specifically, referring to FIG.
D1 and the timing at which the corresponding sampling TFT is turned on (in FIG. 9, reference characters S / H1, S / H7
Or, it is indicated by S / H13. ) Will be described as an example.

First, the sampling T shown in FIG.
While the timing of turning on the FT is normal,
If the timing at which the sampling TFT turns on is delayed by three dot clocks from the original timing as shown in FIG.
T is also turned on in the period of the seventh data indicated by the symbol T in FIG. 9A in addition to the period of the first data.

Therefore, the seventh data is applied to both the data line corresponding to the first sampling TFT and the original data line corresponding to the seventh sampling TFT. As a result, the screen DP Above, Figure 1
0 (a), the original character (FIG. 10)
In the case of (a), a ghost (shown by a dotted line in FIG. 10A) appears in the direction opposite to the scanning direction with respect to the character “A” shown by a solid line.

On the other hand, as shown in FIG. 9B, when the ON timing of the sampling TFT is advanced by three dot clocks from the original timing, for example, 1
The third sampling TFT is also turned on in the period of the seventh data indicated by the symbol T in FIG. 9B in addition to the period of the 13th data.

Accordingly, the seventh data is applied to both the data line corresponding to the original seventh sampling TFT and the data line corresponding to the thirteenth sampling TFT. As a result, the screen DP In the above, as shown in FIG. 10B, a ghost appears on the original character in the same direction as the scanning direction.

In the case shown in FIG. 10A or 10B, when the image signal is expanded into six phases, the ghost appears at a position separated from the original character by six pixels.

In addition to the above, as a cause of the appearance of the ghost, as shown in FIG. 9C, the voltage level of the sampling signal supplied to the gate electrode of the sampling TFT to be switched becomes low, and As a result, the sampling timing is delayed, which may result in a ghost. Further, when the voltage level of the sampling signal is low, the switching of the sampling TFT becomes insufficient, and the voltage level of the image signal sampled and supplied to the data line becomes a dull voltage waveform. In some cases, the image signal does not have a constant voltage, resulting in a ghost. Further, it is conceivable that the power supply voltage of the data line driving circuit becomes high, the sampling start timing of the sampling TFT is advanced, and as a result, a ghost occurs.

The above-mentioned problems are not limited to the TFT, and the electric field effect in which the switching element and the circuit element of the driving circuit are formed on the semiconductor substrate like a reflection type liquid crystal panel using the semiconductor substrate. Transistor (FE
The same is true for the case of T).

Therefore, the present invention has been made in view of the above-mentioned problems, and the problem is that even if the characteristics of a transistor or the like constituting a driving circuit change, the driving state before the present time may be changed. It is an object of the present invention to provide a drive control device capable of maintaining a good operation state as an electro-optical device by driving the device, and an electro-optical device including the same.

[0024]

In order to solve the above-mentioned problems, according to the present invention, there is provided a drive control apparatus for an electro-optical device having a pixel portion arranged in a matrix and a drive means for driving the pixel portion. A driving state of the electro-optical device at a first time point and a driving state of the electro-optical device at a second time point after the first time point are compared. Comparing means for outputting a difference signal indicating the difference between the driving states of the driving means, and the driving means based on the difference signal such that the driving state at the second time point returns to the driving state at the first time point. And a drive control means for controlling.

Therefore, a difference signal indicating the difference between the driving state at the first time point and the driving state at the second time point is output, and based on this, the driving state at the second time point is changed to the driving state at the first time point. Since the driving unit is controlled so as to return to the state, the electro-optical device can be driven while always maintaining the driving state at the first time point.

In order to solve the above-mentioned problem, in the present invention, the comparing means includes a storage means for storing information of the driving state at the first time, and the driving state at the second time. The difference signal is output by comparing the stored information of the driving state at the first point in time with the stored information.

Therefore, the driving state information at the first time point is stored in advance, and the driving state information at the second time point is compared with the driving state information to output a difference signal.
Since the drive state at the time point is restored to the stored drive state, the electro-optical device can be driven with a simple configuration while always maintaining the drive state at the first time point.

Further, in order to solve the above-mentioned problem, in the present invention, the driving means includes a plurality of stages of shift registers and a sampling signal which is output from the shift registers by narrowing a signal width of the output signals. A plurality of enable circuits for sequentially outputting, and a plurality of switches for receiving the sampling signal output from the enable circuit, sampling an image signal and supplying the sampled image signal to the pixel; The information of the driving state at the second time point is obtained based on the sampling signal output from any one.

Therefore, by obtaining the driving state at the second point in time based on the sampling signal output from one of the plurality of enable circuits set in advance, it is possible to extract the signal that most affects the phase shift of the sampling timing. Therefore, it is possible to appropriately recognize the driving state and return to the driving state at the first time point.

Further, in order to solve the above problems,
In the present invention, the comparing unit compares timing information of the sampling signal at the second time point with timing information of the sampling signal at the first time point, and determines a timing difference between the two sampling signals. And outputting the difference signal, and controlling the drive unit based on the difference signal so that a timing difference between the two sampling signals becomes substantially zero.

Thus, the difference information is output by comparing the timing information such as the phase of the sampling signal with the timing information such as the phase at the first time, so that the timing shift of the sampling signal is accurately recognized and the difference is output. By returning to the timing, it is possible to return to the driving state at the first time point.

In order to solve the above-mentioned problem, in the present invention, the drive control means controls the timing of an enable signal supplied to the enable circuit to control the timing of the sampling signal. Features.

Therefore, by controlling the timing such as the phase of the enable signal, the sampling signal is controlled so that the difference between the timing such as the phase at the second time and the timing such as the phase at the first time is substantially zero. Since it is generated, it is possible to reliably return to the timing at the first time point.

Further, in order to solve the above problem, in the present invention, the drive control means controls the timing of a shift clock signal supplied to the shift register in order to control the timing of the sampling signal. It is characterized by.

Therefore, by controlling the timing such as the phase of the shift clock signal of the shift register and controlling the timing such as the phase of the sampling signal output therefrom, the timing at the first time and the timing at the second time are controlled. Since the sampling signal is generated so that the difference from the timing described above is substantially zero, it is possible to reliably return to the drive timing at the first time point.

Further, in order to solve the above problems,
The present invention is characterized in that the comparing means obtains information on the driving state at the second time based on a voltage value of a signal extracted from the driving means.

Therefore, based on the information on the voltage difference between the first time point and the second time point, the driving means detects the difference in the driving state due to the voltage drop or the voltage rise, and appropriately returns to the driving state at the first time point. Can be.

Further, in order to solve the above problems,
In the present invention, the driving unit includes a plurality of stages of shift registers, and a plurality of switches that sample an image signal based on an output signal from the shift register and supply the image signals to the pixels. Voltage information of an output signal from a predetermined stage of the shift register at a first time;
Comparing the voltage information of the output signal from the predetermined stage of the shift register with the voltage information at the second time point, and outputting the difference signal indicating the difference between the two voltages;
The power supply voltage supplied to the driving means is controlled based on the difference signal so that the difference between the two voltages becomes substantially zero.

Accordingly, by controlling the power supply voltage of the shift register and controlling the operation speed of the shift register, the power supply is supplied to the driving means so that the difference between the power supply voltages at the first time and the second time is substantially zero. Since the supply is performed, the shift of the sampling timing of the image signal can be returned to the state at the first time point.

Further, in order to solve the above-mentioned problems, the present invention provides an electro-optical device including the drive control device according to any one of the above-mentioned inventions.

[0041]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a preferred embodiment of the present invention will be described with reference to FIGS.

In the embodiment described below, a plurality of pixels arranged in a matrix are each provided with a pixel portion provided with a switching element composed of a TFT, and a driving means for driving the pixel portion is provided. A description will be given using a liquid crystal device including a liquid crystal panel in which the driving circuit is integrally formed on the same substrate, and a drive control device for driving and controlling the liquid crystal panel.

Here, FIG. 1 is a block diagram showing a schematic configuration of the liquid crystal device of the embodiment, and FIG. 2 is a TFT array substrate (a TFT is formed for each pixel) of a pair of substrates constituting a liquid crystal panel. Wiring provided on the substrate)
FIG. 3 is a plan view showing a configuration of a peripheral circuit and the like. FIG. 3 is a circuit diagram showing a configuration of a data line driving circuit built in the liquid crystal panel and its peripheral portion. FIG. 4 is a timing chart showing an operation of the data line driving circuit. FIG. 5 is a circuit diagram showing a specific configuration of a clocked inverter in the data line driving circuit, FIG. 6 is a circuit diagram showing a configuration of a comparison circuit included in the liquid crystal device, and FIG. 7 is a comparison circuit. 6 is a timing chart showing the operation of FIG.

(I) Overall Configuration and Operation of Liquid Crystal Device First, the overall configuration of the liquid crystal device will be described with reference to FIG.

As shown in FIG. 1, the liquid crystal device S of the embodiment
Is an image signal Svi output from the external computer C.
d and a synchronizing signal Ssyc (a synchronizing signal Ssyc including a vertical synchronizing signal, a horizontal synchronizing signal, and the like for actually displaying an image corresponding to the image signal Svid).
Is displayed.

More specifically, a liquid crystal panel 200 including a pixel section, a timing generator 2 as drive control means, a signal processing section 3, a D / A converter 4, an amplifier 5, a serial / parallel conversion circuit (Hereinafter, referred to as an S / P conversion circuit or phase expansion circuit) 6, a power supply unit 7, a drive state storage circuit 8 as electrically writable storage means, and a comparison circuit 9 as comparison means. Have been.

Next, the general operation will be described.

The timing generator 2 is based on a synchronization signal Ssyc supplied from an external computer C.
A clock signal Sckl and an enable signal Senb, which serve as a reference for driving the liquid crystal panel 200, and a control signal Sd for setting a scanning start timing and a scanning direction of the liquid crystal panel 200 are generated and output to the liquid crystal panel 200.
Here, the control signal Sd includes a plurality of types of control signals and the like as described later.

At the same time, the timing generator 2 generates a clock signal Sckp for executing the signal processing in the signal processing unit 3 and generates the clock signal Sckp.
And a monitor clock signal S serving as a reference clock signal in a comparison process described later in the comparison circuit 9.
mk is generated and output to the comparison circuit 9.

On the other hand, the signal processing section 3 performs predetermined signal processing such as synchronization signal separation on the image signal Svid (including image information to be actually displayed) supplied from the external computer C, and performs signal processing. The generated image signal Sp is generated and D
/ A converter 4

As a result, the D / A converter 4 converts the image signal Sp from digital to analog, generates an analog image signal Sa, and outputs the analog image signal Sa to the amplifier 5.

Next, the amplifier 5 outputs the analog image signal Sa.
Is amplified by a predetermined amplification factor to generate an image signal Sap and output it to the S / P conversion circuit 6.

Then, the S / P conversion circuit 6 outputs the image signal S
ap is expanded into six parallel image signals, and each of the image signals V
ID1 to VID6 are generated and input to the liquid crystal panel 200.

Thus, the liquid crystal panel 200 uses the control signal Sd, the clock signal Sckl, and the enable signal Senb to control the image signals VID1 to VID as described later.
An image corresponding to D6 is displayed.

Here, the power supply unit 7 generates a power supply voltage used for the operation of each of the above-described components, and generates a power supply voltage Sd1,
Sd2, Sd3, Sd4, and Sd5 are respectively generated and supplied to the signal processing unit 3, the D / A converter 4, the amplifier 5, the S / P conversion circuit 6, and the liquid crystal panel 200.

Further, from the last stage of the enable circuit described later in the liquid crystal panel 200, the operation state of the data line drive circuit described later (more specifically, the shift state of the timing of sampling the image signal and outputting it to the data line) And a sampling signal Sm indicating the power supply voltage state of the data line driving circuit).

At this time, if the characteristics of each of the TFTs constituting the data line driving circuit change due to aging or temperature change in the sampling signal Sm, as shown in FIG. It will be faster and slower.

On the other hand, the drive state storage circuit 8 stores data relating to the pulse width, timing, and voltage value of the sampling signal Sm in the initial state (ie, the initial state when the liquid crystal device S is shipped from the factory). The pulse width and output timing of the initial state are output to the comparison circuit 9 as the initial state signal Sinp, and the voltage value of the initial state is output to the comparison circuit 9 as the initial state signal Sinv. Specifically, the drive state storage circuit 8 has a programmable frequency divider that can variably divide the reference clock signal supplied from the timing generator 2 according to the stored data, and periodically drives the frequency divider according to the stored data. To output a pulse Sinp. In the initial state,
If the data is set and stored so that the pulse S inp is output at the timing coincident with the output timing of the sampling signal Sm, the sampling signal S
m and the pulse S inp almost coincide with each other. The drive state setting circuit 8 also stores voltage value information supplied from the power supply unit 7 to the drive circuit of the liquid crystal panel 200, and outputs the information as Sinv.

Thus, the comparison circuit 9 periodically outputs the sampling signal S in accordance with the monitor clock signal Smk.
The pulse width or output timing of the sampling signal Sm is compared with the pulse width or output timing indicated by the initial state signal Sinp, and the pulse width or output timing indicated by the initial state signal Sinp is compared. From the control signal S indicating the degree of the timing shift.
c is generated and output to the timing generator 2. Then, the timing generator 2 responds to the control signal Sc in a time axis in a direction opposite to the time axis in which the timing is shifted due to a change in the characteristics of the TFT in the data line driving circuit. The pulse width or output timing of the enable signal Senb is controlled so as to shift the timing of the sampling signal Sm so that the timing shift indicated by the control signal Sc becomes substantially zero. Thereby, the timing shift caused by the change in the characteristics of the TFT is compensated, and the ghost (FIG. 1) is compensated.
0).

In parallel with the above operation, the comparison circuit 9
Periodically compares the voltage value of the sampling signal Sm output from the data line driving circuit with the voltage value indicated by the initial state signal Sinv according to the monitor clock signal Smk, and calculates the voltage value of the sampling signal Sm. Detects how much the voltage deviates from the voltage value indicated by the initial state signal Sinv, generates a control signal Sbc indicating the degree of the voltage deviation, and outputs it to the power supply unit 7.

The power supply section 7 generates a plurality of levels of power supply voltage using a resistor circuit, a booster circuit, etc., and generates a signal processing section 3, a D / A converter 4, an amplifier 5, an S / P conversion circuit 6
And a power supply circuit that supplies power supply voltages Sd1, Sd2, Sd3, Sd4, and Sd5 corresponding to the liquid crystal panel 200, respectively. The supplied power supply voltage may fluctuate.

Accordingly, the power supply unit 7 controls the voltage value of the power supply voltage Sd5 supplied to the data line drive circuit of the liquid crystal panel 200 so that the voltage deviation indicated by the control signal Sbc becomes substantially zero. In other words, the generation of the ghost (see FIG. 10) is suppressed by compensating for a change in the sampling operation of the data line driving circuit caused by the fluctuation of the power supply voltage.

(II) Configuration and Operation of Liquid Crystal Panel Next, the detailed configuration and operation of the liquid crystal panel 200 that generates the sampling signal Sm will be described with reference to FIG.

First, the overall structure of the liquid crystal panel 200 will be described with reference to FIG.

As shown in FIG. 2, the liquid crystal panel 200
For example, a TFT array substrate 1 made of a quartz substrate, hard glass, or the like is provided.

Then, on the TFT array substrate 1,
A plurality of pixel portions are provided in a matrix. The pixel array includes a plurality of data lines 35 (source electrode lines) arranged in the X direction, each extending in the Y direction, and a plurality of pixel lines arranged in the Y direction. Scanning line 31 (gate electrode line)
Is arranged.

At this time, each pixel section is provided corresponding to the intersection of each data line 35 and each scanning line 31, and the data line 35
And a TFT 30 connected to the scanning line 31, a pixel electrode 11 connected to the TFT 30, and a storage capacitor 12.

The TFT 30 is connected between the data line 35 and the pixel electrode 11, and applies an image signal supplied to the data line 35 to the pixel electrode 11 and the storage capacitor 12 during the conduction period.

At this time, the conduction state or non-conduction state of the TFT 30 is controlled in accordance with a scanning signal supplied via the scanning line 31 to which the gate electrode is connected.

Further, on the TFT array substrate 1, a capacitor line 31 ′ (electrode for a storage capacitor), which is a wiring for the storage capacitor 12 for maintaining the voltage applied to the pixel electrode 11 for a long time, is provided with respect to the scanning line 31. The storage capacitor 12 is formed between the pixel electrode 11 and the capacitor line 31 '.

Further, on the TFT array substrate 1, a sampling circuit 301 for sampling an image signal and supplying it to each of the plurality of data lines 35, and a data line driving circuit 1
01 and the scanning line driving circuit 104 are P-channel TFTs.
And an N-channel TFT as a circuit element.

The scanning line drive circuit 104 has a so-called bidirectional shift register, and includes a power supply voltage Sd5 supplied from the power supply unit 7, a timing generator 2
Shift clock and Y shift start pulse included in the clock signal Sckl supplied from the
Based on the above, a scanning signal having a predetermined pulse width and a predetermined timing is generated from the bidirectional shift register, and the scanning signal is applied to the scanning line 31 in a pulse-wise line-sequential manner.

At this time, the shift register starts shifting in response to the Y shift start pulse supplied every vertical scanning period, and performs a shift operation in synchronization with the Y shift clock supplied every horizontal scanning period. In accordance with the shift, a scanning signal is sequentially generated every horizontal scanning period.

As a result, in each pixel portion, the TFT 3 having the gate electrode connected to the scanning line 31 to which the scanning signal is applied.
0 is a conductive state and the scanning line 3 to which no scanning signal is applied.
The TFT 30 whose gate electrode is connected to 1 is turned off.

Here, the scanning line drive circuit 104 fixes the transfer direction of the bidirectional shift register in the forward or reverse direction in accordance with the transfer direction control signal included in the control signal Sd, so that the plurality of scan lines 31 On the other hand, it is configured to be able to sequentially supply the scanning signals in a top-to-bottom order or to sequentially supply the scanning signals in a bottom-to-top order.

On the other hand, the data line driving circuit 101 has a bidirectional shift register as described later, like the scanning line driving circuit 104. The bidirectional shift register shifts based on the power supply voltage Sd5 supplied from the power supply unit 7, the X shift clock and the X shift start pulse included in the clock signal Sckl supplied from the timing generator 2, the control signal Sd, and the like. Operate. The shift register starts shifting in response to an X start pulse supplied every horizontal scanning period, and performs a shift operation in synchronization with the X shift clock.

As a result, the data line driving circuit 101
The pulse width of a signal output in accordance with the shift operation of the shift register is controlled by an enable signal Senb from the timing generator 2 to generate a sampling signal having a predetermined pulse width and a predetermined timing, and output the sampling signal to the sampling circuit 301.

Next, the sampling circuit 301 is configured such that one sampling TFT 302 is connected to each data line 35. Therefore, the data line driving circuit 101 sequentially supplies the sampling signals to all the sampling TFTs 302 via the sampling signal lines 306 during the horizontal scanning period in which the scanning signals are applied.

Thus, the sampling TFT 302
Are switched by receiving a sampling signal at the gate electrode, sample the image signals VID1 to VID6 supplied to the image signal lines, and supply them to the respective data lines 35.

The image signal supplied to each data line 35 is transmitted to the pixel electrode 11 and the storage capacitor 12 connected to the scanning line 31 to which the scanning signal is supplied via the TFT 30 having the gate electrode connected thereto. Applied.

The data line driving circuit 101 fixes the transfer direction of the bidirectional shift register in the forward or reverse direction in accordance with the transfer direction control signal included in the control signal Sd, similarly to the scanning line drive circuit 104. It is configured to be able to sequentially supply image signals to the plurality of data lines 35 in the order from left to right or to sequentially supply image signals in the order from right to left.

As described above, the sampling circuit 301 includes a sampling TFT 302 constituting an analog switch for each data line 35. This T
Each of the image signals VID1 to VID is applied to the source electrode of the FT302.
ID6 is input, a sampling signal line 306 is connected to the gate electrode, and a data line 35 is connected to the drain electrode.

When the sampling signal S1 is input from the data line driving circuit 101 via the sampling signal line 306, each of the six image signals VID1 to VID6 is simultaneously sampled to form six data lines. To the adjacent data lines 35 at the same time. This is sequentially performed for each sampling signal Sn (n = 1, 2, 3,...), And sampling of each image signal is sequentially performed for each data line group within the horizontal scanning period.

That is, the data line driving circuit 101 and the sampling circuit 301 are configured to simultaneously supply the image signals VID1 to VID6 which are phase-expanded into six parallel signals and input to the data lines 35.

The sampling circuit 301 supplies the high-frequency image signals VID1 to VID6 to the respective data lines 35 stably at a predetermined timing in synchronization with the scanning signals. This is a sampling circuit.

The number of phase expansions of the image signal input to the sampling circuit 301 is determined according to the response speed of the sampling circuit 301. That is, the data line 35
When the number of signals is fixed, the number of phase expansions of the image signal can be reduced as the response speed increases. As a result, the burden on the signal processing unit 3 or the circuit configuration of the S / P conversion circuit 6 and the like is reduced by the sampling circuit 301.

In the above description, the sampling circuit 301 has six data lines 3 belonging to one data line group.
5, the image signals VID1 to VI which are expanded into six phases.
D6 is simultaneously sampled and supplied, and the application of such image signals VID1 to VID6 is sequentially performed for each data line group. However, the number of phase developments and the number of data lines applied simultaneously (that is, The number of data lines constituting the data line group is not limited to six.

That is, for example, if the response speed of the TFT of the sampling circuit 301 is high, the image signal serially transmitted to one image signal line is transmitted to each data line 3.
It may be configured to sample sequentially every five,
By increasing the number of phase expansions, image signals supplied in parallel, such as three-phase expansion, twelve-phase expansion, or twenty-four-phase expansion, are simultaneously supplied to three, twelve, or twenty-four data lines. Is also good.

The number of phase expansions is preferably a multiple of 3 in view of the fact that a color image signal is composed of signals related to three colors, in order to simplify control and the circuit.

(III) Configuration of Data Line Driving Circuit and Sampling Circuit Next, the specific configuration and operation of the data line driving circuit 101 and the sampling circuit 301 will be described with reference to FIGS.

First, the data line driving circuit 101 will be described.

As shown in FIG. 3, the data line driving circuit 10
Reference numeral 1 denotes a bidirectional shift register 111, a plurality of enable circuits 112a provided corresponding to outputs of odd-numbered stages of the bidirectional shift register 111, and outputs of even-numbered stages of the bidirectional shift register 111, respectively. And a plurality of enable circuits 112b respectively provided.

At this time, the bidirectional shift register 11
1 is an odd-numbered bidirectional shift register,
X is a transfer direction corresponding to the right direction (direction from left to right in FIG. 3) or the left direction (direction from right to left in FIG. 3).
Shift shift pulse SP to X shift clock signal CL
And its inverted clock signal CLINV.

The plurality of enable circuits 112 reduce the pulse width of the signal sequentially output from each stage of the bidirectional shift register 111, for example, the sampling TFT 302 and the second TFT connected to the first data line group adjacent to each other. This is a circuit that controls so that the sampling TFTs 302 connected to the data line group do not conduct simultaneously. By the operation of the enable circuit 112, the image signals VID1 to VID6 are sequentially supplied in data line group units at timings at which the data line groups do not overlap with each other.

A signal SP (L) (as a part of the clock signal Sckl) for starting the transfer of the transfer signal from left to right in FIG. 3 is supplied to the bidirectional shift register 111. 3 or a signal SP (R) (clock signal S) for starting a transfer of a transfer signal from the right to the left in FIG.
Supplied as part of ckl. ) Is input from the right side of FIG.

Next, the bidirectional shift register 111 will be described in detail.

As shown in FIG. 3, each stage of the bidirectional shift register 111 has a fixed transfer direction in accordance with a binary transfer direction control signal D supplied as a part of the control signal Sd and its inverted signal DINV. Each time the binary level of the shift clock signal CL and the inverted signal CLINV of the predetermined cycle changes, the transfer signal is fed back and transferred to the next stage and output, and the two clocked inverters 116 and 117 and the two inverters 114 And 115 respectively.

Here, the inverter 114 is constructed and connected such that the transfer is enabled when the transfer direction control signal D is at the high level, and the transfer direction is fixed in the right direction (L → R in FIG. 3). Also, the inverter 115 has an inverted signal DIN
The transfer is enabled when V is at the high level, and the configuration and connection are made such that the transfer direction is fixed in the left direction (R → L in FIG. 3).

When the transfer direction is fixed to the right (L → R) in FIG. 3, the clocked inverter 116 outputs the transfer signal transferred via the inverter 114 and the shift clock signal CL having the high level. When the transfer direction is fixed to the left (R → L) in FIG. 3, the transfer signal transferred via the inverter 115 is fed back when the shift clock signal CL is at a high level. Structured and connected.

Furthermore, the clocked inverter 117
When the transfer direction is fixed to the left (R → L) in FIG. 3, the transfer signal transferred via the inverter 115 is
The transfer is performed when the inverted signal CLINV is at a high level, and when the transfer direction is fixed to the right (L → R) in FIG.
The configuration and connection are made such that feedback occurs when the inverted signal CLINV is at a high level.

Next, the configuration and operation of the clocked inverter 116 will be described with reference to FIG. 5A and a circuit diagram of FIG. Will be described.

As shown in FIG. 5B, the clocked inverter 116 includes an N-channel TFT whose clock signal CL is input to the gate terminal, a P-channel TFT whose inverted signal CLINV is input to the gate electrode, P connected in parallel so that transfer signals are input to the gate electrodes, respectively.
Channel TFT and N-channel TFT, and power supply voltage Sd
Power supply VSS (ground potential power supply) and V
DD (high-level power supply) is connected as shown in FIG. Note that the other clocked inverters 117 have the same circuit configuration except that the clock signal CL and the inverted signal CLINV input to the clock input terminal are opposite to those in FIG. The inverters 114 and 115 also have a circuit configuration similar to that of FIG.
In the case of the inverter 115, the control signals DINV and D are inputted in place of the clocks CL and CLINV instead of the control signals D and DINV.

Next, enable circuits 112a and 112
b will be described.

As shown in FIG. 3, the enable circuit 112
a indicates the pulse width of the transfer signal output from the odd-numbered stage of the bidirectional shift register 111 by the first enable signal EN.
It is configured to limit the pulse width to B1 (a part of the enable signal Senb).

Here, as shown in FIG. 3, for example, as shown in FIG. 3, the enable circuit 112a includes a NAND circuit which receives a transfer signal and a first enable signal ENB1, and an inverter circuit which logically inverts its output and buffers it. FIG. 4 (a)
And (b), the pulse width of the transfer signal is limited to the pulse width of the first enable signal ENB1.

On the other hand, the enable circuit 112b limits the pulse width of the transfer signal output from the even-numbered stage of the bidirectional shift register 111 to the pulse width of the second enable signal ENB2 (a part of the enable signal Senb). It is configured as follows.

Here, as the enable circuit 112b, for example, as shown in FIG. 3, a NAND circuit having a transfer signal and a second enable signal ENB2 as inputs and an inverter circuit for logically inverting and buffering the output thereof are provided. FIG. 4 (a)
And (b), the pulse width of the transfer signal is limited to the pulse width of the enable signal ENB2.

Next, the operation of the data line driving circuit 101 will be described.
This will be described with reference to the timing chart of FIG.

In the timing charts shown in FIGS. 4A and 4B, when the X shift start pulse SP (L) or SP (R) is input at the beginning of the horizontal scanning period, X
The shift register performs a shift operation in accordance with the shift clock signals CL and CLINV, and the logical product of the output of the odd-numbered stage shift register and the enable signal ENB1 and the logical product of the output of the even-numbered stage shift register and the enable signal ENB2 are obtained. Thus, sampling signals S1, S2,... Are generated. The sampling signal is sequentially delayed by a half cycle of the clock signal CL, becomes a pulse narrower in width than the pulse width, and is supplied to the sampling circuit 301.

Further, any one of S1, S2, S3,..., Sn is output to the comparison circuit 9 as a sampling signal Sm. In FIG. 3, Sn is output to the comparison circuit 9 as the sampling signal Sm.

Next, the operation of the data line driving circuit 101 configured as described above will be described with reference to FIGS.

First, as shown in FIG. 3, when the transfer direction control signal D is fixed at a high level and the inverted signal DINV is fixed at a low level and is input to the bidirectional shift register 111, The clocked inverter 114 provided at each stage 111 and enabled to transfer under this condition and the clocked inverter 115 disabled to transfer under this condition allow the transfer direction to move rightward (L → R) in FIG. Fixed.

In this state, as shown in FIG. 4A, at the beginning of the horizontal scanning period, the X shift start pulse SP (L)
Is input, every time the binary level of the shift clock signal CL and the inverted signal CLINV changes, the clocked inverters 116 and 117 perform transfer and feedback, respectively, so that the transfer signal fed back is bidirectional. The data is transferred to the next stage (right stage) of the shift register 111 and output to the corresponding enable circuit 112a or 112b.

Since such feedback is applied at each stage,
The transfer signal is not dull and is sequentially transferred to the next stage. Then, the logical product of the output of the odd-numbered stage shift register and the enable signal ENB1 and the logical product of the output of the even-numbered stage shift register and the enable signal ENB2 are respectively obtained to generate sampling signals S1, S2,. .

Here, the sampling signals S1, S2,
.., Sn are sequentially delayed by a half cycle of the clock signal CL,
The pulse width is smaller than the pulse width, and each pulse is supplied to the sampling circuit 301.

Further, the data line driving circuit 101 outputs any one of the sampling signals S1, S2, S3,..., Sn to the comparison circuit 9 as a sampling signal Sm. In FIG. 3, the sampling signal Sm is S
n to the comparison circuit 9.

On the other hand, as shown in FIG.
Is fixed to the low level and the inverted signal DINV is fixed to the high level and input to the bidirectional shift register 111, the inverter 114 in each stage of the bidirectional shift register 111, which cannot transfer data under this condition. The transfer direction is fixed to the left (R → L) by the inverter 115 that can be transferred under this condition.

In this state, as shown in FIG. 4B, an X shift is performed at the beginning of the horizontal scanning period and the pulse SP (R) is shifted.
Is input, each time the binary level of the shift clock signal CL and the inverted signal CLINV changes, the clocked inverters 116 and 117 perform feedback and transfer, respectively, so that the transfer signal that has been fed back is both The data is transferred to the next stage (left stage) of the direction shift register 111 and output to the corresponding enable circuit 112a or 112b. Since such feedback is applied at each stage, the transfer signal is not dulled and is sequentially transferred to the next stage. The output of the odd-numbered shift register and the enable signal E
The logical product of NB1 and the logical product of the output of the even-numbered stage shift register and the enable signal ENB2 are respectively taken to generate sampling signals Sn, Sn-1,..., S1.

Here, the sampling signals Sn, Sn-1,.
, S1 are sequentially delayed by a half cycle of the clock signal CL,
The pulse width is smaller than the pulse width, and each pulse is supplied to the sampling circuit 301.

Further, the data line driving circuit 101 outputs one of the sampling signals Sn, Sn-1, Sn-2,..., S1 to the comparison circuit 9 as a sampling signal Sm. In FIG. 3, Sn is output to the comparison circuit 9 as the sampling signal Sm.
When the transfer direction of 11 is fixed in the left direction (R → L),
It is preferable to output S1.

It is assumed here that the bidirectional shift register 111
Is an even-numbered bidirectional shift register, the transfer direction is rightward (L → R) and the transfer direction is leftward (R → R).
In the case of L), the transfer signal output from the first stage (for example, the left end or the right end stage) of the bidirectional shift register 111 is a signal whose phase is shifted by a half cycle of the clock signal CL.

Therefore, by actually reversing the transfer direction,
In order for the liquid crystal panel 200 to display an image without any trouble, it is not enough to simply change the binary levels of the transfer control signal D and the inversion signal DINV, and it is necessary to invert the clock signal CL and the inversion signal CLINV. That is, in this case, the wiring of the clock signal CL and the inverted signal CLINV must be switched somewhere. Therefore, in the timing generator 2 and the like, a mechanism and control for switching the clock signal CL are required, which is very disadvantageous in terms of both the configuration and the control of the liquid crystal panel 200. In particular, such switching generally becomes more difficult as the driving frequency becomes higher.
In the case of the data line driving circuit 101 which is much higher than 04, it becomes very difficult.

However, the bidirectional shift register 11
When 1 is configured as an odd-numbered stage, FIG.
As shown in (b), the transfer direction is rightward in FIG.
3), the transfer signal output from the first stage (left end or right end stage) of the bidirectional shift register 111 is the same signal. That is,
In order to invert the transfer direction, it is only necessary to change the binary level of the transfer control signal D and the inverted signal DINV, and it is not necessary to invert the clock signal CL and the inverted signal CLINV. It is very advantageous.

Next, as described above, when the transfer signal is sequentially output from each stage of the bidirectional shift register 111 in the right or left direction in FIG. 3, the enable circuits 112a and 112b
Then, the following operation is performed.

That is, the pulse width of the transfer signal output from the odd-numbered stage of the bidirectional shift register 111 is changed by the enable circuit 112a to the pulse of the first enable signal ENB1 as shown in FIG. Limited by width. On the other hand, as shown in FIG. 4A or 4B, the pulse width of the transfer signal output from the even-numbered stage of the bidirectional shift register 111 is limited to the pulse width of the second enable signal ENB2 by the enable circuit 112b. Is done.

After that, if the transfer direction of the transfer signal whose pulse width is limited is the left direction (R → L) in FIG. 3, as shown in FIG.
, Sn (where n is an odd number) are sequentially output to the sampling circuit 301.

The transfer direction is rightward in FIG. 3 (L →
If R), as shown in FIG. 4B, the signals are sequentially output to the sampling circuit 301 as sampling signals Sn, Sn-1, Sn-2,..., S1.

Accordingly, the sampling signals S1, S2,
,..., Sn, an appropriate time interval is provided between image signals supplied to adjacent data line groups one after another. If an appropriate time interval is provided between the image signals as described above, these image signals are overlapped particularly in a high-frequency driving environment, and a ghost or a ghost caused by writing any preceding image signal components at all is considered. This is very advantageous because it is possible to prevent the occurrence of image unevenness.

Next, enable circuits 112a and 112
, Sn, or S generated by limiting the pulse width of the transfer signal by b.
.., S1 (where n is an odd number) are six sampling TFTs 302 constituting a sampling circuit 301 in a data line group consisting of six data lines corresponding to six image signals VID1 to VID6. Input to the gate electrode at the same time. As a result, the data line 35 becomes 6
The lines are simultaneously driven, and this operation is repeated, and the image signal V is output for each data line group including six data lines.
ID1 to VID6 are sequentially supplied.

Here, an image signal is supplied to one data line group based on the same one transfer signal.
The number of data lines 35 constituting the data line group is S / P
It is preferable to match the number of phase expansions of the image signals VID1 to VID6 input from the conversion circuit 6 to the data line driving circuit 101.

Therefore, the image signals VID1 to VID
In the case where the phase expansion is not performed in the format of No. 6, or when the writing capability of each TFT 302 of the sampling circuit 301 is high, or when a sufficient writing time is given to the sampling circuit 302, for example, the data line group is 1
It may be formed by two data lines.

(IV) Description of Scan Line Drive Circuit Next, the scan line drive circuit 104 will be described.

The scanning line driving circuit 104 has the odd-numbered stages of bidirectional shift registers 111 shown in FIG. 3, as in the case of the data line driving circuit 101. 3 with respect to the scanning line 31 in the downward direction in FIG. 3 (direction from top to bottom) or in FIG.
In the transfer direction corresponding to the middle-up direction (direction from bottom to top), transfer signals sequentially output from each stage of the bidirectional shift register 111 are directly used as scan signals, or in the same manner as in the case of the data line drive circuit 101. The scan signals are sequentially supplied through the enable circuits 112a and 112b shown in FIG.

In this case, the configuration of the bidirectional shift register 111 is the same, but the same transfer direction control signal D and inverted signal DINV as the data line drive circuit 101 may be used as the transfer direction control signal. A transfer direction control signal dedicated to the drive circuit 104 may be used.

At this time, if the same signal transfer method control D and inverted signal DINV as those of the data line driving circuit 101 are used, the switching of the transfer direction of the data line driving circuit 101 and the scanning line driving circuit 104 can be performed completely in conjunction. On the other hand, if the transfer direction control signal dedicated to the scanning line driving circuit 104 is used, the data line driving circuit 101 and the scanning line driving circuit 104
Can be independently switched.

The clock signal for the scanning line driving circuit 104 depends on the total number of the scanning lines 31 and the length of the vertical scanning period. However, unless special driving such as multi-sync driving is performed, ordinary fixed driving is performed. , Y shift start pulse SP
Are supplied at the beginning of the vertical scanning period, and a shift operation is performed according to a Y shift clock signal CL supplied every horizontal scanning period. These pulses and clocks are applied to the clock signal Sck
Included in l.

If the clock frequency in the scanning line driving circuit 104 is set low so that the scanning signals supplied to the adjacent scanning lines 31 can be prevented from substantially overlapping, the scanning line driving circuit 104 The enable circuits 112a and 112b controlled by the enable signal Senb from the timing generator 2 can be omitted.

Next, the operation of the scanning line driving circuit 104 thus configured will be described.

First, as a first case, transfer direction control signal signals D and DINV (or a dedicated transfer direction control signal)
Is fixed to one, the transfer direction in the bidirectional shift register 111 is downward (in the direction from top to bottom) in FIG. 2 or upward (in the direction from bottom to top) in FIG. Fixed. In this state, every time the level of the clock signal changes, the transfer signal is fed back and transferred to the next stage of the bidirectional shift register 111.

On the other hand, in the second case, when the levels of the transfer direction control signal D and the inverted signal DINV (or the dedicated transfer direction control signal) are fixed to the other, the transfer direction in the bidirectional shift register 111 is as described above. Is fixed in a direction opposite to the first case. In this state, every time the level of the clock signal changes, the transfer signal is fed back and transferred to the next stage of the bidirectional shift register 111.

With this configuration, in order to invert the transfer direction in the scanning line drive circuit 104, it is only necessary to change the binary level of the transfer direction control signal D and the inversion signal DINV (or a dedicated transfer direction control signal). There is no need to invert the clock signal.

As described above, the scanning signals are sequentially supplied to the odd-numbered scanning lines 31 by the scanning line drive circuit 104 based on the transfer signals sequentially output from the respective stages of the bidirectional shift register 111.

In this case, the number of the scanning lines 31 is an odd number.
Is provided, it is sufficient to supply the scanning signal to all the scanning lines 31 as it is. On the other hand, if the liquid crystal panel 200 is provided with an even number of scanning lines 31, for example, one of the upper or lower ends may be provided. Are configured so as not to use the scanning lines.

Further, regarding the scanning line driving circuit 104,
When the enable circuits 112a and 112b are used, the number of the scanning lines 31 may be odd or even.

(V) Configuration and Operation of Comparison Circuit Next, the detailed configuration and operation of the comparison circuit 9 will be described with reference to FIGS.

As shown in FIG. 6, the comparison circuit 9 includes a counter 9a, a holding circuit 9b, and a subtraction circuit 9c. The holding circuit 9b includes a plurality of storage circuits (latch circuits, flip-flop circuits, and the like) that latch and hold a plurality of bits of a signal input to the input terminal in accordance with the signal timing input to the clock terminal for each bit. .

First, the TF in the data line driving circuit 101
A control signal indicating how much the pulse width and timing of the sampling signal Sm indicating a timing shift due to the characteristic change at T deviate from the pulse width and timing of the initial state signal Sinp indicating the initial state of the sampling signal Sm. The generation operation of Sc will be described.

An initial state signal Sinp output from the driving state storage circuit 8 is periodically input to a reset terminal of the counter 9a, and the monitor clock signal Smk is input to a clock terminal of the counter 9a. Has been entered. The drive state storage circuit 8 receives a reference clock signal from the timing generator 2 and includes a program divider that divides the reference clock signal according to information (division ratio data) written and stored in advance. And
An initial state signal Sinp is periodically output according to the frequency division ratio. In the present invention, the sampling signal Sm output periodically at the first reference time (for example, the initial state)
The initial state signal Sinp is input at a timing at which the sampling signal should be output, since the frequency division ratio is set and stored so as to coincide with the timing.

With this configuration, the counter 9a changes the pulse included in the monitor clock signal Smk from when the initial state signal Sinp changes from “LOW” to “HIGH” and the counter 9a is reset until the counter 9a is reset next time. The number is counted, and the result is output to the input terminal of the holding circuit 9b as a count signal Scc composed of a signal of a plurality of bits.

On the other hand, the clock terminal of the holding circuit 9b has
The sampling signal Sm output from the data line driving circuit 101 is input.

With this configuration, when the sampling signal Sm changes from “LOW” to “HIGH”, the holding circuit 9b holds the count value made up of the multi-bit signal input as the count signal Scc and sends it to the control signal. It is output to the timing generator 2 as Sc.

Therefore, each T in the data line driving circuit 101
There is no timing shift in the FT due to the characteristic change,
When there is no pulse width shift or timing shift between the sampling signal Sm and the initial state signal Sinp (ie, when the sampling signal Sm and the initial state signal Sinp change from “LOW” to “HIGH” at the same timing) ), The holding circuit 9b outputs a control signal Sc whose content is “0” (ie, the deviation is “0”).

On the other hand, as shown in FIG. 7, each TFT in the data line drive circuit 101 has a delay due to a change in characteristics, and therefore, the timing when the sampling signal Sm changes from “LOW” to “HIGH”. However, when the initial state signal Sinp is later than the timing when the initial state signal Sinp changes from “LOW” to “HIGH”, the holding circuit 9b determines the number of pulses of the monitor clock signal Smk corresponding to the delay (FIG. 7).
In this case, a control signal Sc whose content is 4 pulses) is output.

Thus, the timing generator 2
As described above, the enable signal Sen is set so that the number of pulses indicating the shift included in the control signal Sc becomes zero.
The control for advancing the pulse timing of b is performed, thereby canceling the characteristic change of the TFT in the data line drive circuit 101, compensating for the operation delay caused by the characteristic change, and suppressing the occurrence of the ghost (see FIG. 10). I do. On the other hand, when the phase of the sampling signal Sm is advanced due to the temperature rise, the sampling signal Sm is earlier than the initial state signal Sinp, and the phase of the sampling signal Sm is advanced according to the corresponding count value Scc. Control signal S shown
c, delay control of the pulse timing of the enable signal Senb, cancels the change in the characteristics of the TFT in the data line driving circuit 101, and compensates for the operation fluctuation caused by the change in the characteristics, thereby obtaining the ghost (see FIG. 10). The occurrence of is suppressed.

Next, the TFT in the data line driving circuit 101
Of the control signal Sbc indicating how much the voltage value of the sampling signal Sm indicating the operation delay due to the characteristic change in the sample signal Sm deviates from the voltage value of the initial state signal Sinv indicating the initial state voltage value of the sampling signal Sm The operation will be described.

The sampling signal Sm is input to one input terminal of the subtraction circuit 9c.

On the other hand, to the other input terminal of the subtraction circuit 9c, the above-mentioned initial state signal Sinv indicating the voltage value of the sampling signal Sm in the initial state is input.

The subtraction circuit 9c outputs the initial state signal S
The voltage value of the sampling signal Sm is subtracted from the voltage value included in inv, and the control signal Sbc indicating the difference (ie, the difference between the voltage value of the sampling signal Sm and the voltage value indicated by the initial state signal Sinv) is obtained. Output. Specifically, the subtraction circuit 9c performs digital subtraction when:
An analog-to-digital converter for converting the signal voltage of the sampling signal Sm into a digital signal;
As inv, a digitized signal of the voltage value of the sampling signal based on the power supply from the power supply unit 7 in a normal state is input, and the difference between the two is subtracted. In the case of analog subtraction, the initial state signal Sinv is input as an analog voltage value, and a voltage difference from the sampling signal Sm is sensed,
The voltage difference is converted into a digital signal by an analog-digital converter. Thus, the control signal Sbc indicating the voltage difference is output. This control signal Sbc is also output as a digital signal composed of a plurality of bits, similarly to Sc.

As a result, the power supply section 7 supplies the control signal S
In particular, the supply voltage value of the power supply voltage Sd5 is changed so that the voltage difference represented by bc becomes substantially zero, thereby canceling the fluctuation of the power supply voltage supplied to the bidirectional shift register due to the characteristic change of the power supply unit 7. The ghost (see FIG. 10) is suppressed by compensating the operation delay of the data line driving circuit 101 caused by the fluctuation of the power supply voltage.

As described above, according to the operation of the liquid crystal device of the embodiment, the control signal indicating the difference between the current driving state of the bidirectional shift register 111 and the initial driving state for the driving pulse width and the voltage value. Output Sc and Sbc,
Based on this, the liquid crystal is driven by controlling the data line driving circuit 101 so that the current driving state returns to the initial driving state. Therefore, it is possible to always maintain the initial driving state and drive the liquid crystal satisfactorily. it can.

The control signals Sc and Sbc are output by storing the initial drive state in the drive state storage circuit 8 in advance and comparing the initial drive state with the current drive state by the comparison circuit 9. As a result, the current driving state is returned to the initial driving state, so that the liquid crystal can be driven with a simple configuration while always maintaining the initial driving state.

Further, since the current driving state is obtained based on the sampling signal Sm from the data line driving circuit 101, it is possible to accurately recognize the current driving state and return to the initial driving state.

Furthermore, since the control signal Sc is output by comparing the current phase of the sampling signal Sm with the phase indicated by the initial state signal Sinp, the sampling signal Sm is output.
By accurately recognizing the phase lag and returning the current phase to the initial phase, the current driving state can be returned to the initial driving state.

Further, by controlling the phase of the enable signal Senb by the timing generator 2, the difference between the current phase and the initial phase is made substantially zero, so that the current phase can be reliably returned to the initial phase. .

Furthermore, since the control signal Sbc is output by comparing the current voltage value of the sampling signal Sm with the voltage value indicated by the initial state signal Sinv, the voltage drop or voltage rise of the output signal of each enable circuit can be accurately determined. By recognizing and returning the current voltage value to the initial voltage value, it is possible to eliminate the influence of the operation delay based on the voltage drop or the like and to return the current driving state to the initial driving state.

Furthermore, the liquid crystal device S can be driven favorably while always maintaining the initial driving state.

In the above-described embodiment, the sampling signal Sn output from the data line driving circuit 101 is used as the sampling signal Sm for monitoring the operation delay in the data line driving circuit 101. For example, any of the sampling signals S1,..., Sn shown in FIG. 3 can serve the same role as the sampling signal Sm, and in this case, the same effect as in the above embodiment can be obtained. it can.

Furthermore, in the above-described embodiment, the comparison circuit 9 uses the monitor clock signal Smk to generate the control signal Sc. In addition, for example, the initial state signal Sinp is changed from “LOW” to “LOW”. A signal that changes from “LOW” to “HIGH” at the timing of changing to “HIGH” and a signal that changes from “HIGH” to “LOW” at the timing of changing the sampling signal Sm from “LOW” to “HIGH” is a control signal Sc. Can also be output as

In this case, the timing generator 2
In the data line driving circuit 10, the pulse width of the control signal Sc is detected and the pulse width and timing of the enable signal Senb are controlled so that the pulse width becomes substantially zero.
1 will be compensated for.

When the data line driving circuit 101 is not driven by the enable signal Senb, the end pulse signal of the bidirectional shift register 111 of FIG. 3 (indicated by Sep in FIG. 3) is used instead of the sampling signal Sm. ) Is input to the comparison circuit 9, and the phase or timing of the clock signal Sckl is controlled by the timing generator 2 based on the control signal Sc output from the comparison circuit 9. The ghost (FIG. 1) is canceled by canceling the change in the characteristics of the TFT of FIG.
0) can be suppressed.

Further, according to the present invention, the data line driving circuit 101
Can be applied not only for compensating the operation delay in the scanning line driving circuit 104 but also for compensating the operation delay in the scanning line driving circuit 104.

In the above embodiment, the case where the timing of the sampling signal Sm is delayed as compared with the timing indicated by the initial state signal Sinp is described. Even when the timing is advanced as compared with the timing indicated by the state signal Sinp, similarly, the shift is detected by the comparison circuit 9 and the timing of the enable signal Senb is advanced by the timing generator 2 by the amount of the shift, thereby reducing the shift. Can compensate.

Furthermore, by controlling the phases and voltage values of the image signals VID1 to VID6 in the signal processing unit 3 or the S / P conversion circuit 6 based on the control signal Sc or Sbc, the ghost due to the operation delay described above is obtained. Can be prevented. When the timing is controlled in the S / P conversion circuit 6 based on the control signal Sc, the image signal V output from the S / P conversion circuit 6 is controlled so as to follow the timing fluctuation of the sampling signal Sm.
The output timings of ID1 to VID6 are changed and controlled.
Specifically, when the sampling signal Sm is delayed,
The output timing of the image signal for one horizontal scan output in time series within the horizontal scan period is delayed by the timing delay. Thereby, the sampling timing and the transmission timing of the image signal are synchronized. When the timing of the sampling signal Sm is advanced, control may be performed so that the output timing from the S / P conversion circuit 6 is advanced.

Furthermore, the present invention is applicable not only to electro-optical devices such as a liquid crystal panel having a TFT formed on a substrate, but also to a method of replacing a substrate with a semiconductor substrate, replacing a TFT with a field-effect transistor, and connecting a transparent substrate such as glass to a semiconductor. The present invention can be similarly applied to an electro-optical device in which a pair of substrates sandwiching liquid crystal is constituted by substrates, and a switching element in a pixel portion, a switch of a sampling circuit, and a driving circuit are constituted by field-effect transistors formed in a semiconductor substrate. Further, for example, the present invention can be applied to a self-luminous active matrix display device using an electroluminescent element or the like.

[0175]

As described above, according to the present invention,
A difference signal indicating a difference between the driving state of the electro-optical element at the second time point and the driving state at the first time point earlier than that is output. Based on this, the driving state at the second time point is changed to the first time point. Since the driving unit is controlled to drive the electro-optical element so as to return to the driving state in the above, the electro-optical element can be driven while always maintaining the driving state at the first time point.

More specifically, for example, in a liquid crystal device including a matrix type liquid crystal element, the initial driving state of each liquid crystal element is always maintained when driving and controlling a data line driving circuit in which a characteristic change is likely to occur. Therefore, each liquid crystal element can be always driven and displayed satisfactorily.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a liquid crystal device according to an embodiment.

FIG. 2 shows a TF constituting a liquid crystal panel included in the liquid crystal device.
FIG. 2 is a plan view showing a configuration of various wirings, peripheral circuits, and the like provided on a T array substrate.

FIG. 3 is a circuit diagram showing a configuration of a data line driving circuit included in a liquid crystal panel and a peripheral portion thereof.

4A and 4B are timing charts showing the operation of the data line driving circuit, FIG. 4A is a timing chart showing a first case, and FIG. 4B is a timing chart showing a second case.

FIG. 5 is a circuit diagram showing a specific configuration of a clocked inverter.

FIG. 6 is a circuit diagram showing a configuration of a comparison circuit.

FIG. 7 is a timing chart showing the operation of the comparison circuit.

8A and 8B are timing charts showing a relationship between an image signal and another signal, FIG. 8A is a timing chart showing a relationship between an image signal and an image signal, and FIG. Is a timing chart showing the relationship between the image signal, the image signal, and the operation timing of the sampling circuit.

9A and 9B are diagrams showing a problem of the related art, wherein FIG. 9A is a timing chart showing a case where the sampling timing is delayed, FIG. 9B is a timing chart showing a case where the sampling timing is advanced, (C)
5 is a timing chart showing a case where the image signal pulse width is dull.

FIG. 10 is a diagram illustrating a state of occurrence of a ghost;
(A) is a diagram showing a first case, and (b) is a diagram showing a second case.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... TFT array substrate 2 ... Timing generator 3 ... Signal processing part 4 ... D / A converter 5 ... Amplifier 6 ... S / P conversion circuit 7 ... Power supply part 8 ... Drive state storage circuit 9 ... Comparison circuit 9a ... Counter 9b ... Hold Circuit 9c Subtraction circuit 11 Pixel electrode 31 Scan line (gate electrode) 30, 302 TFT 31 'Capacitance line 35 Data line (source electrode) 101 Data line drive circuit 104 Scan line drive circuit 111, 121 131, bidirectional shift register 112a, 112b enable circuit 114, 115, 116, 117 clocked inverter 200 liquid crystal panel 301 sampling circuit C computer S liquid crystal device DP screen Ssyc synchronization signal Svid, VID1 through VID6: Image signal Sckp, Sckl: Clock signal Smk: Monitor clock signal Senb ... Enable signal Sp ... Processed image signal Sa ... Analog image signal Sap ... Amplified image signal Sd1, Sd2, Sd3, Sd4, Sd5 ... Power supply voltage Sep ... End pulse signal Sbc, Sc ... Control signal Scc ... Count signal Sinp, Sinv ... Initial state signal Sd ... control signal Siv, DINV ... inverted signal D ... transfer direction control signal ENB1 ... first enable signal ENB2 ... second enable signal S1, S2, S3, ..., Sn, Sm ... sampling signal

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 2H093 NA16 NA43 NC09 NC13 NC16 NC22 NC23 NC25 NC27 NC28 NC34 NC44 ND15 ND34 ND58 5C006 AA01 AA15 AA16 AA22 AC21 AF25 AF42 AF46 AF51 AF61 AF67 AF71 AF82 BB16 BC03 BC13 BC16 BC20 BC22 BC23 BC23 BF07 BF11 BF14 BF16 BF23 BF25 BF26 BF27 BF28 BF32 BF43 BF46 BF49 FA16 FA18 FA22 FA33 5C080 AA10 BB05 CC03 DD05 DD20 DD29 EE29 EE30 FF11 JJ02 JJ03 JJ04

Claims (9)

[Claims] 1. A drive control device for an electro-optical device, comprising: a pixel portion arranged in a matrix; and a driving unit for driving the pixel portion, wherein: a driving state of the electro-optical device at a first time; 1
Comparing means for comparing the driving state of the electro-optical device at a second time point after the time point and outputting a difference signal indicating a difference between the driving state at the first time point and the driving state at the second time point; And a drive control means for controlling the drive means such that the drive state at the second time point returns to the drive state at the first time point based on the following. 2. The drive control device according to claim 1, wherein the comparison unit includes a storage unit that stores information on the drive state at the first time, and information on the drive state at the second time. A drive control device for outputting the difference signal by comparing the stored drive state information at a first time point with the stored drive state information. 3. The drive control device according to claim 1, wherein the drive unit sequentially shifts the sampling signal by reducing a signal width of a plurality of stages of shift registers and output signals sequentially output from the shift registers. A plurality of switches for outputting, and a plurality of switches for receiving the sampling signal output from the enable circuit, sampling an image signal and supplying the image signal to the pixel portion, A drive control device, wherein information on a drive state at the second time point is obtained based on the sampling signal output from any of them. 4. The drive control device according to claim 3, wherein the comparing unit compares timing information of the sampling signal at the second time with timing information of the sampling signal at the first time. And outputting the difference signal indicating the timing difference between the two sampling signals, and the drive control means controls the driving based on the difference signal such that the timing difference between the two sampling signals becomes substantially zero. A drive control device for controlling means. 5. The drive control device according to claim 4, wherein the drive control means controls a timing of an enable signal supplied to the enable circuit to control a timing of the sampling signal. Drive control device. 6. The drive control device according to claim 4, wherein the drive control means controls a timing of a shift clock signal supplied to the shift register in order to control a timing of the sampling signal. Drive control device. 7. The drive control device according to claim 1, wherein the comparison unit obtains information on the drive state at the second time based on a voltage value of a signal extracted from the drive unit. A drive control device characterized by the above-mentioned. 8. The drive control device according to claim 7, wherein the drive unit includes a plurality of shift registers, and a plurality of shift registers that sample an image signal based on an output signal from the shift register and supply the sampled image signal to the pixel unit. And a switch, wherein the comparing means comprises: voltage information of an output signal from a predetermined stage of the shift register at the first time; and voltage of an output signal from a predetermined stage of the shift register at the second time. Comparing the two signals with each other and outputting the difference signal indicating the difference between the two voltages. The drive control means controls the drive so that the difference between the two voltages becomes substantially zero based on the difference signal. A drive control device for controlling a power supply voltage supplied to the means. 9. An electro-optical device comprising the drive control device according to claim 1. Description: