JPH11282422A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device for reducing the degradation of liquid crystal without applying a DC power supply to the liquid crystal at the time of starting and ending an operation. SOLUTION: This device is provided with a signal electrode driving circuit 3 for receiving timing signals generated by a digital signal. processing circuit 2 based on an inputted clock and applying display signals to the drain electrode of a display part, a DC/DC converter 6 for outputting a counter electrode voltage to the common electrode of the display part and a signal electrode driving circuit analog power supply to the signal electrode driving circuit 3 based on an external voltage, a timing signal output circuit 16 for controlling the output of the digital signal processing circuit 2 corresponding to the CNT signals of a dot clock monitoring circuit 15 for monitoring and outputting the clock, and a power supply control circuit 17 for controlling the output of the DC/DC converter 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a liquid crystal display device including a thin film transistor (TFT).

[0002]

2. Description of the Related Art FIG. 5 is a diagram showing a configuration of a conventional liquid crystal display device. In FIG. 5, reference numeral 1 denotes an input dot clock DCLK, horizontal synchronization signal HS, vertical synchronization signal VS,
It has a signal electrode drive circuit and a digital signal processing circuit 2 for generating a timing signal for controlling the operation of the scan electrode drive circuit based on the data signals R, G, and B, and receives a single power supply VCC. The control circuit 3 is a signal electrode drive circuit whose operation is controlled by a timing signal generated by the control circuit 1, and the scanning electrode drive circuit 4 is controlled in operation by a timing signal generated by the control circuit 1. 5
Is a liquid crystal panel driven by output signals of the signal electrode driving circuit 3 and the scanning electrode driving circuit 4 to change the transmittance of liquid crystal to perform display. Reference numeral 6 denotes a scan electrode drive circuit power supply Vgh, Vgl for operating the scan electrode drive circuit 4 based on the input of the single power supply VCC, a signal electrode drive circuit analog power supply VDDA for operating the signal electrode drive circuit 3, and a liquid crystal panel 5. Is a DC / DC converter circuit for generating a common electrode voltage VCOM to be applied to the common electrode of FIG.

FIG. 6 is a diagram showing a detailed configuration of the liquid crystal panel shown in FIG. In the figure, reference numeral 7 denotes source bus lines X1, X2... Xn and gate bus lines Y1, Y2.
..TFTs arranged at intersections of Yn, 8 are TFs
The gate electrode of T7 is connected to the gate bus line Yi. Reference numeral 9 denotes a source electrode of the TFT 7, which is connected to the source bus line Xi. Reference numeral 10 denotes a drain electrode of the TFT 7, and each of the electrodes 8 to 10 and the source bus line X
i and the gate bus line Yi are formed on an array substrate (not shown). A common electrode 11 is formed on an opposing substrate (not shown) opposing the array substrate via the liquid crystal and opposing the drain electrode 10. The common electrode 11 constitutes a pixel electrode together with the drain electrode 10.

In such a conventional liquid crystal display device, the gate bus line Yi is connected to the output terminal of the scan electrode drive circuit 4, the source bus line Xi is connected to the output terminal of the signal electrode drive circuit 3, and the common electrode 11 is connected to the output terminal of the signal electrode drive circuit 3. A gate pulse (gate voltage) Vg, which is a scanning signal, is applied line-sequentially to the gate bus line Yi from the scan electrode driving circuit 4 while being connected to the DC / DC converter circuit 6, and only during the HI period when Vg becomes Vgh. The TFT 7 is turned on. From the signal electrode driving circuit 3, a display signal corresponding to each pixel is output to each source bus line Xi in synchronization with the gate pulse, and
The pixel capacitance is charged only during the ON period of FT7, and Vg becomes Vg
In the TFT off period of 1, the image is displayed by storing the charge charged in the pixel capacitance.

[0005]

In the conventional liquid crystal display device as described above, when a timing signal is not input to the scanning electrode driving circuit 4 and the signal electrode driving circuit 3, that is, the control circuit 1 supplies the dot clock DCLK and the horizontal signal. When the synchronizing signal HS and the vertical synchronizing signal VS are not input, the outputs of the scan electrode driving circuit 4 and the signal electrode driving circuit 3 become indefinite, and DC power is applied to the liquid crystal, thereby deteriorating the liquid crystal. Since such a situation generally occurs when the power switch of the liquid crystal display device is turned on and off, some countermeasure is required.

Conventionally, as a method for avoiding these problems, as disclosed in Japanese Patent Application Laid-Open No. Hei 5-100634, the dot clock is monitored during the power-on period by monitoring the dot clock. If not, a method of cutting off the high voltage of the liquid crystal driving system is used. However, in this method, since the output of the control circuit during the period when the power is turned on is undefined, an undefined signal is input to the timing signal input terminals of the scan electrode drive circuit and the signal electrode drive circuit. The output of the scan electrode drive circuit and the signal electrode drive circuit becomes uncertain under the influence of this signal, and DC power is applied to the liquid crystal.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to provide a liquid crystal display device in which no DC power is applied to the liquid crystal at the start and end of the operation, and the deterioration of the liquid crystal is reduced. It is an object.

[0008]

In the liquid crystal display device according to the present invention, a large number of pixels each having a first electrode and a second electrode disposed so as to face the first electrode are arranged in a matrix. The first voltage is applied to the first electrode and the second voltage is applied to the second electrode to change the transmittance of the liquid crystal sandwiched between the two substrates. Display section for performing display, a timing signal generating circuit for generating a timing signal based on an input clock signal, and a first drive for receiving a timing signal and supplying a first voltage to a first electrode of the display section Circuit, a second drive circuit that receives a timing signal and outputs a signal for controlling the first voltage, and outputs a second voltage to the second electrode of the display unit based on an external voltage, and outputs the first and second signals. Power supply to the second drive circuit Circuit, a monitoring circuit for monitoring a clock signal and outputting a monitoring signal, a timing output control circuit for controlling the output of the timing signal generating circuit in accordance with the monitoring signal of the monitoring circuit, and a power supply in response to the monitoring signal of the monitoring circuit It has a power supply control circuit for controlling the output of the circuit.

The power supply control circuit is provided on the input side of the power supply circuit. Also, the power control circuit
This is provided on the output side of the power supply circuit. Further, the monitoring circuit outputs a monitoring signal that causes the outputs of the timing output control circuit and the power supply control circuit to have a low potential when there is no clock input.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a block diagram showing a liquid crystal display device according to Embodiment 1 of the present invention. In the figure, 1 is an input dot clock DC
LK, a horizontal synchronizing signal HS, a vertical synchronizing signal VS, and data signals R, G, and B. A timing generating circuit that generates a timing signal for controlling the operation of a signal electrode driving circuit and a scanning electrode driving circuit, which will be described later. A control circuit having a certain digital signal processing circuit 2 and receiving a single power supply VCC;
Is a signal electrode drive circuit, which is a first drive circuit whose operation is controlled by a timing signal generated by the control circuit 1,
Is a scan electrode drive circuit which is a second drive circuit whose operation is controlled by a timing signal generated by the control circuit 1. Reference numeral 5 denotes a liquid crystal panel which is driven by output signals of the signal electrode driving circuit 3 and the scanning electrode driving circuit 4 and performs display by changing the transmittance of liquid crystal. Reference numeral 6 denotes scan electrode drive circuit power supplies Vgh and Vgl for operating the scan electrode drive circuit 4 and a signal electrode drive circuit analog power supply V for operating the signal electrode drive circuit 3 based on the input of the single power supply VCC.
It is a DC / DC converter circuit which is a power supply circuit for generating a counter electrode voltage VCOM which is a second voltage applied to a common electrode which is a second electrode in the liquid crystal panel 5.

Reference numeral 15 denotes a dot clock monitoring circuit that monitors the dot clock DCLK, and 16 denotes a timing signal output circuit that is a timing output control circuit that controls the output of the digital signal processing circuit 2 based on the output of the dot clock monitoring circuit 15. It is provided in the control circuit together with the monitoring circuit 15. Reference numeral 17 denotes a relay circuit for controlling a single power supply VCC input to the DC / DC converter circuit 6 by the output of the dot clock monitoring circuit 15 or VCC.
This is a power supply control circuit including a regulator and the like. Note that the detailed configuration of the liquid crystal panel is the same as that in FIG. 6, and a display signal of a first voltage is applied using the drain electrode 10 as a first electrode. FIG. 2 is a diagram showing timings of signals and power supplies in the liquid crystal display device according to the first embodiment of the present invention. 9 shows control contents during a period when the dot clock DCLK is not input when the operation of the liquid crystal display device starts and ends.

In the liquid crystal display device having such a configuration, a single power supply VCC input from outside the liquid crystal display device is used.
Is input to the power supply control circuit 17 and the control circuit 1. In the control circuit 1 of the first embodiment, a dot clock monitoring circuit 15 is newly provided. In the dot clock monitoring circuit 15, as shown in FIG. Then, a CNT signal is generated and output. By causing the CNT signal to act on the timing signal output circuit 16 of the control circuit 1, when the dot clock DCLK is not input, all outputs of the timing signal output circuit 16 become the GND level,
No signal is output to the scan electrode drive circuit 4 and the signal electrode drive circuit 3, and an output corresponding to the input digital signal is performed only during the period when the dot clock DCLK is input. Further, this CNT signal is input to the power supply control circuit 17 as a control signal for the power supply control circuit 17 so that the VCC level is supplied from the power supply control circuit 17 to the DC / DC converter circuit 6 only during the CNT signal HI period. I have. As a result, even when the dot clock DCLK is not input at the start and end of the operation and only VCC is input, the input of the DC / DC converter circuit 6 is at the GND level, and the output of the DC / DC converter circuit 6 is also GN.
It can be controlled to D level. Here, VCC 'is an output voltage of the power supply control circuit 17 whose output is controlled by the CNT signal,
Used as a power source for the DC / DC converter circuit. The operations of the signal electrode drive circuit 3 and the scan electrode drive circuit 4 are the same as those described in the related art.

Embodiment 2 FIG. FIG. 3 is a block diagram showing a configuration of a liquid crystal display device according to Embodiment 2 of the present invention. In the figure, 1 to 5, 15 and 16 are the same as those in FIG. Reference numeral 18 denotes a DC / DC converter circuit, which is configured so that the output of a power supply generation circuit 19 to which a single power supply VCC externally input is input is controlled by a CNT signal output from the dot clock monitoring circuit 15. FIG. 4 is a diagram showing timings of signals and power supplies in the liquid crystal display device according to the second embodiment of the present invention, and shows control contents during a period when the dot clock DCLK is not input at the start and end of the operation of the liquid crystal display device. I have.

In the liquid crystal display device according to the second embodiment,
The function of the control circuit 1 and the function of the dot clock monitoring circuit 15 of the control circuit 1 are the same as in the first embodiment. In the second embodiment, the CNT signal output from the dot clock monitoring circuit 15 is applied to the output stage of the DC / DC converter circuit 18 to start the operation as shown in FIG.
The dot clock DCLK at the end is not input,
Even during the period when only VCC is input, the output of the DC / DC converter circuit 18 can be controlled to the GND level.

[0015]

Since the present invention is configured as described above, it has the following effects. A large number of pixels each having a first electrode and a second electrode arranged so as to face the first electrode are arranged in a matrix, a first voltage is applied to the first electrode, and a second pixel is applied. A display unit that performs display by changing the transmittance of liquid crystal sandwiched between two substrates by applying a second voltage to the two electrodes, and a timing signal based on an input clock signal. A timing signal generating circuit that generates, a first driving circuit that receives the timing signal and supplies a first voltage to a first electrode of the display unit, and outputs a signal that receives the timing signal and controls a first voltage. A second drive circuit, a power supply circuit that outputs a second voltage to the second electrode of the display unit based on an external voltage and supplies power to the first and second drive circuits,
A monitoring circuit that monitors a clock signal and outputs a monitoring signal;
A timing output control circuit for controlling the output of the timing signal generation circuit in accordance with the monitoring signal of the monitoring circuit, and a power supply control circuit for controlling the output of the power supply circuit in accordance with the monitoring signal of the monitoring circuit; Is applied, the deterioration of the liquid crystal can be reduced. Also, since the power supply control circuit is provided on the input side of the power supply circuit,
The power supply circuit can be prevented from operating.

Further, since the power supply control circuit is provided on the output side of the power supply circuit, the output of the power supply circuit can be prevented. Further, since the monitoring circuit outputs a monitoring signal for setting the outputs of the timing output control circuit and the power supply control circuit to a low potential when there is no clock input, it is possible to reduce the deterioration of the liquid crystal due to the application of DC. Can be.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing timings of signals and a power supply in the liquid crystal display device according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 4 is a diagram showing timings of signals and power supplies in a liquid crystal display device according to a second embodiment of the present invention.

FIG. 5 is a diagram illustrating a configuration of a conventional liquid crystal display device.

FIG. 6 is a diagram showing a liquid crystal panel of a conventional liquid crystal display device.

[Explanation of symbols]

2 digital signal processing circuit, 3 signal electrode drive circuit,
4 scan electrode drive circuit, 5 liquid crystal panel, 6, 18
DC / DC converter circuit, 7 TFT, 8 gate electrode, 9 source electrode, 10 drain electrode, 1
1 common electrode, 15 dot clock monitoring circuit, 1
6 timing signal output circuit, 17 power supply control circuit,
19 Power supply generation circuit.

Claims (4)

[Claims] A plurality of pixels each having a first electrode and a second electrode arranged to face the first electrode are arranged in a matrix, and a first voltage is applied to the first electrode. A display unit that performs display by changing the transmittance of the liquid crystal sandwiched between the two substrates by applying the second voltage to the second electrode while applying the second voltage to the second electrode also receives the input clock signal. A timing signal generating circuit that generates a timing signal, a first driving circuit that receives the timing signal and supplies a first voltage to a first electrode of the display unit, and receives the timing signal and receives the first signal. A second drive circuit that outputs a signal for controlling a voltage, and outputs a second voltage to a second electrode of the display unit based on an external voltage and supplies power to the first and second drive circuits Power supply circuit, monitor the above clock signal A monitoring circuit that outputs a monitoring signal, a timing output control circuit that controls the output of the timing signal generation circuit according to the monitoring signal of the monitoring circuit, and controls an output of the power supply circuit according to the monitoring signal of the monitoring circuit. A liquid crystal display device comprising a power supply control circuit. 2. The liquid crystal display device according to claim 1, wherein the power supply control circuit is provided on an input side of the power supply circuit. 3. The liquid crystal display device according to claim 1, wherein the power supply control circuit is provided on an output side of the power supply circuit. 4. The monitoring circuit according to claim 1, wherein when there is no input of a clock, the monitoring circuit outputs a monitoring signal for setting the outputs of the timing signal output control circuit and the power supply control circuit to a low potential. 4. The liquid crystal display device according to claim 3.