JP2000078610A - Display image converter - Google Patents

Abstract

(57) [Problem] To provide a display image conversion device capable of rotating a display image by 90 degrees in an image input device including a luminance signal and a color difference signal, capable of reducing a memory. SOLUTION: A dot sequential processing circuit 1 using first and second color difference signals as a dot sequential signal, a first memory 2 for holding field image data of a luminance signal, and a dot sequential processing circuit 1
, A memory control circuit 4 for rotationally converting the data held in the memory, and a vertical correction process for the output signal of the second memory to obtain the first, A vertical processing circuit 5 for generating a second color difference signal;
Decoding processing for creating R, G, B signals to be given to the display panel based on the luminance signal after rotational conversion from the first memory 2 and the first and second color difference signals after rotational conversion of the vertical processing circuit 5 And a circuit 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display image conversion apparatus for rotating a display image by 90 degrees and displaying the image on a display such as a liquid crystal panel.

[0002]

2. Description of the Related Art Generally, the screen of a display such as a liquid crystal display is horizontally long.
Can be rotated 90 degrees to change the viewing direction to a portrait screen. However, simply rotating the display also rotates the display image and data (here, for example, characters and symbols such as place names attached to a map on the display) together with the display. Therefore, in order to use the display in a rotated state, the image itself needs to be rotated by 90 degrees in the opposite direction so that the upper, lower, left, and right sides of the image are normal (the original shape). Displaying an image rotated by 90 degrees in this manner is hereinafter referred to as “rotation conversion” of the image.

[0003] As a conventional example in which image and display data are rotationally converted by signal processing of a video signal, Japanese Patent Laid-Open Publication No.
In the device disclosed in Japanese Patent No. 6887, an image is rotated 90 degrees using a multiport memory. In another conventional example disclosed in Japanese Patent Application Laid-Open No. 9-6312, data is rotated by 90 degrees in character units, and the data is rearranged by a multiport memory. Japanese Patent Laid-Open Publication No. Hei 7-175444 discloses a method of rotating and converting an image and display data in a liquid crystal display device. The display image is rotated by 90 degrees by arranging it in the horizontal direction and the horizontal direction, and switching between them.

[0004] However, in the above-mentioned conventional example, there is no description about specific image rotation conversion for a color image.
Therefore, a conventional display image conversion device in the case where input signals are R, G, and B signals will be described with reference to the drawings. FIG. 23 is a block diagram showing a configuration of a conventional display image conversion device using R, G, and B signals as input signals. In FIG. 23, a first memory 81, a second memory 82, and a third memory 83 write input data for one field of R, G, and B, respectively, and convert horizontal and vertical pixel positions. This is a memory for reading out and displaying on a liquid crystal panel as an image display device. The memory control circuit 4 controls writing and reading of each of the memories 81, 82, and 83 independently, and controls each address so that a writing address and a reading address are orthogonal to each other. Memory 8
1, 82, and 83 to enable the horizontal and vertical pixel positions to be transformed to rotationally transform the image. FIG. 24 shows the input data to the first memory 81 before the rotation conversion of the R signal and the output data from the memory after the rotation conversion in the display image conversion apparatus in which the input signals are the R, G, and B signals. It is. Although not shown, the same applies to the G signal and the B signal. As described above, the configuration including the memories 81, 82, and 83 that can store the respective signals of R, G, and B enables the rotation conversion.

[0005]

However, in the ordinary display image conversion apparatus having the above-mentioned structure, R, G, B
Requires three memories for storing the respective image data. In signal processing of digital image data using such a memory, the data ratio between the luminance signal and the first and second color difference signals is reduced in order to reduce the memory size and the scale of the signal processing circuit associated therewith. Y: Cb: Cr = 4: 2: 2 method or 4: 1 with 2: 1
In general, a Y: Cb: Cr = 4: 1: 1 method is used. Here, Y indicates a luminance signal, Cb indicates a first color difference signal, and Cr indicates a second color difference signal. When performing the rotation conversion of the display image of the input image data having the luminance signal and the first and second color difference signals as described above, the memory size is changed to the conventional input image data method using the R, G, and B signals. In comparison, in the case of Y: Cr: Cb = 4: 2: 2, 2 /
3, 1/2 in the case of Y: Cr: Cb = 4: 1: 1 system
Obviously. However, conventionally, there is no document or device describing a specific configuration of a display image conversion apparatus in a rotation conversion method of a display image of input image data having such a luminance signal and a color difference signal.

An object of the present invention is to provide an image display apparatus of an input image data system having a luminance signal and a color difference signal capable of reducing the required memory.
It is an object of the present invention to provide a display image conversion device that converts the positions of pixels in the horizontal direction and the vertical direction to enable rotation conversion of a display image.

[0007]

According to the present invention, there is provided a display image conversion apparatus for displaying an image by input image data having a luminance signal and first and second color difference signals. A display image conversion device that converts the position of a pixel in a direction and outputs converted image data to a display panel, wherein a dot sequential processing circuit for converting the first and second color difference signals into a dot sequential signal; A first memory for holding field image data of the luminance signal, a second memory for holding dot-sequential color difference signal data output by the dot-sequencing circuit, and a field image held in the first memory A memory control circuit for generating an address for converting the data and the position of the dot-sequential color-difference signal data held in the second memory on the display screen and generating an address for reading the data; A vertical correction circuit for performing vertical correction processing on the converted dot-sequential color difference signal data to generate first and second color difference signals after position conversion, and a luminance after position conversion output from the first memory. A decoding processing circuit that generates R, G, and B signals to be applied to the display panel based on the signals and the first and second color difference signals after the position conversion output by the vertical processing circuit. I do.

According to the display image conversion apparatus having the above configuration, in an input image data type image display apparatus having a luminance signal and first and second color difference signals, a first memory for luminance signal data and first and second color difference signals are provided. The rotation-converted image can be displayed using only the second memory for the second color difference signal data. Therefore, an image display device with a reduced memory size can be provided.

A display image conversion apparatus according to another aspect of the present invention is an image display apparatus for displaying an image based on input image data having a luminance signal and first and second color difference signals. Convert the position of the pixel of
What is claimed is: 1. A display image conversion device for outputting converted image data to a display panel, comprising: a luminance horizontal interpolation processing circuit that performs horizontal interpolation processing of the luminance signal; and a color difference that performs horizontal interpolation processing on the second color difference signal. A horizontal interpolation processing circuit; a dot sequential processing circuit for converting the first color difference signal and the second color difference signal output by the horizontal interpolation processing circuit into a dot sequential signal; and the luminance horizontal interpolation processing circuit A first memory for holding the field image data of the luminance signal output by the second memory, a second memory for holding the dot sequential color difference signal data output by the dot sequential processing circuit, and the first memory A memory control circuit for generating an address for converting and reading a position on the display screen between the field image data and the dot-sequential color difference signal data held in the second memory, and a conversion output from the second memory A vertical processing circuit that performs vertical correction processing on the dot-sequential color difference signal data to generate first and second color difference signals after position conversion, a position-converted luminance signal output from the first memory, A decoding processing circuit that generates R, G, and B signals to be applied to the display panel based on the first and second color difference signals after the position conversion output by the vertical processing circuit.

[0010] In the display image conversion apparatus having this configuration,
In an input image data type image display device having a luminance signal and first and second color difference signals, only a first memory for luminance signal data and a second memory for first and second color difference signal data are provided. , The rotation-converted image can be displayed. Therefore, an image display device with a reduced memory size can be provided. Further, in a horizontal interpolation process before the rotation conversion by the memory control, a process for canceling a delay after the rotation conversion is performed, so that an increase in circuit scale is minimized, and the luminance signal and the first and second color difference signals are reduced. And the delay difference between the first color difference signal and the second color difference signal can be minimized.

In the display image conversion apparatus having the above-described configuration, the luminance horizontal interpolation circuit includes a horizontal delay circuit for delaying the input luminance signal in the horizontal direction, and an interpolation coefficient for an output of the horizontal delay circuit. A first multiplier for multiplying K, a second multiplier for multiplying the input luminance signal by an interpolation coefficient (1−K), and an addition for adding outputs of the first and second multipliers And a vertical line delay between a converted color difference signal output of the vertical processing circuit that has been delayed in the vertical direction and a converted luminance signal output of the first memory that has not been delayed in the vertical direction. It is preferable to adjust the horizontal delay time before conversion and the position of the virtual data in advance so that the times are the same.

The chrominance horizontal interpolation circuit includes a horizontal delay circuit for delaying the input second chrominance signal in the horizontal direction, and an internal circuit for the delayed second chrominance signal output from the horizontal delay circuit. A first multiplier that multiplies the interpolation coefficient K;
Interpolation coefficient (1-K) for the input second color difference signal
, And an adder that adds the outputs of the first and second multipliers. The second multiplier calculates the virtual value of the input second color difference signal with respect to the input first color difference signal. It is preferable to delay the data position by K data.

In the above-described display image conversion apparatus having the two configurations, the memory control circuit converts the positions of the pixels in the horizontal direction and the vertical direction.
It is preferable to control the addresses of the first and second memories so that the read addresses are orthogonal to the write addresses of the respective memories, and to control the addresses of the first and second memories in the same manner. . Further, the dot-sequentialization processing circuit may be arranged such that the number of horizontal data of the luminance signal is 2N and the number of horizontal data of the first and second color difference signals is N.
In the image display device for displaying an image based on the input image data, the first color difference signal and the second color difference signal are switched for each data at the rate of the number of horizontal data of the luminance signal, and the first color difference signal and the second And a second color difference signal.

The vertical processing circuit may further include a line memory for delaying the color-converted signal output from the second memory after the position conversion for one horizontal period, and a line memory after the position conversion output from the second memory. And a first and second switching circuit for switching the color difference signal output from the line memory and the color difference signal after position conversion delayed by one horizontal period every one horizontal period, and the first and second switching circuits are provided. The switching circuit is
The first color difference signal stored in the second memory is only an even line, and the second color difference signal is only an odd line.
And the second color difference signal are preferably output so as to be output to all the lines. Further, the vertical processing circuit includes a first line memory for delaying the position-converted color difference signal output from the second memory for one horizontal period, and a first line memory output from the first line memory.
A second line memory for further delaying the color difference signal delayed by the horizontal period by one horizontal period, a position-converted color difference signal output from the second memory, and 2 output from the second line memory A vertical interpolation circuit that performs vertical interpolation on the color difference signal after the position conversion delayed by the horizontal period, an output of the vertical interpolation circuit, and one horizontal signal output from the first line memory. A first and a second switching circuit for switching the position-converted color difference signal delayed by a period for each horizontal period, wherein the first and second switching circuits are configured such that the first color difference signal is only for even-numbered lines. The first and second color difference signals output from the memory, in which the second color difference signals are only odd-numbered lines, are output to all the lines so as to be vertical continuous line signals. Switch It is preferred.

Further, a display image conversion apparatus according to another aspect of the present invention is an image display apparatus for displaying an image based on input image data having a luminance signal and first and second color difference signals. A display image conversion apparatus for converting the position of a pixel and outputting converted image data to a display panel, comprising: a line sequential processing circuit for converting the first and second color difference signals into line sequential signals for each line. A color difference horizontal interpolation processing circuit that performs horizontal interpolation processing on the line sequential color difference signal output from the line sequential processing circuit; a first memory that holds field image data of the luminance signal; A second memory for holding line-sequential color difference signal data output by the insertion processing circuit, field image data held in the first memory, and line-sequential color difference signal data held in the second memory And a memory control circuit for generating an address for converting and reading, and performing a horizontal interpolation process on the converted color difference signal output from the second memory, and converting the converted first and second color difference signals. A post-conversion horizontal interpolation circuit to be created, a converted luminance signal output from the first memory, and the converted first and second color difference signals output from the post-conversion horizontal interpolation circuit; And a decode processing circuit for generating R, G, and B signals to be applied to the display panel.

According to the display image conversion apparatus having this configuration, in the input image data type image display apparatus having the luminance signal and the first and second color difference signals, the first memory for the luminance signal data and the color difference signal It is possible to display a rotation-converted image using only the second memory for data. Therefore, an image display device with a reduced memory size can be provided. Further, in the processing before the rotation conversion by the memory control, the line sequential processing and the color difference horizontal interpolation processing are performed,
A post-conversion horizontal interpolation processing circuit having a very simple configuration that does not use a line memory, and performs a vertical delay difference between a luminance signal and first and second color difference signals, and a difference between a first color difference signal and a second color difference signal. It is possible to eliminate the delay difference.

In this display image conversion apparatus,
The memory control circuit converts horizontal and vertical pixel positions in the first and second memories, so that a read address is orthogonal to a write address of the first and second memories. And the addresses of the first and second memories are preferably controlled in the same manner. Further, in the image display device for displaying an image based on input image data in which the number of vertical lines of the first and second color difference signals is N, the line sequential processing circuit may include a first color difference signal on even lines. It is preferable to switch every line so that the second color difference signal is output to each odd line.

Further, the color difference horizontal interpolation circuit includes a horizontal delay circuit for delaying the input second color difference signal in the horizontal direction, and an interpolation coefficient K for an output of the horizontal delay circuit.
, A second multiplier for multiplying the input second color difference signal by an interpolation coefficient (1−K), and an output of the first and second multipliers. It is preferable that the virtual position of the input second color difference signal is delayed by K data with respect to the input first color difference signal. Further, the post-conversion horizontal interpolation circuit includes a horizontal delay circuit for delaying the color-converted signal after position conversion output from the second memory in the horizontal direction, and an interpolation coefficient K for the output of the horizontal delay circuit. A first multiplier for multiplying (0 ≦ K ≦ 1), a second multiplier for multiplying the input second color difference signal by an interpolation coefficient (1-K),
An adder for adding the output of the first multiplier and the output of the second multiplier, and a switch for switching the output of the adder and the color difference signal output from the second memory for each data. The first and second switching circuits,
The switching circuit of the present invention converts the color difference signals output from the second memory, in which the first color difference signal is only even-numbered data and the second color difference signal is only odd-numbered data, into first and second data.
It is preferable to switch so that any of the color difference signals of (1) and (2) becomes data continuous in the horizontal direction.

Further, a display image conversion apparatus according to another aspect of the present invention is an image display apparatus for displaying an image using input image data having a luminance signal and first and second color difference signals. A display image conversion apparatus for converting the positions of the pixels of the image data and outputting the converted image data to a display panel, wherein a dot sequential processing circuit for converting the first and second color difference signals into a dot sequential signal; A memory for dividing the field image data of the luminance signal and the dot-sequential chrominance signal data output by the dot-sequencing circuit into upper bits and lower bits, and holding the field image data divided and held in the memory And a memory control circuit for generating an address for converting and reading each position of the dot-sequential color difference signal data on the display screen, and a post-conversion output from the memory. A vertical processing circuit that performs vertical correction processing on the color difference signal to generate first and second color difference signals after the position conversion, a luminance signal after the position conversion output from the memory, and an output signal from the vertical processing circuit. And a decode processing circuit for generating R, G, B signals to be given to the display panel based on the first and second color difference signals after the position conversion.

According to the display image conversion apparatus having the above configuration, in the input image data type image display apparatus having the luminance signal and the first and second color difference signals, the memory for displaying the rotated image is provided with the luminance signal. Only one memory having the same bit area as that of the memory can be realized. Therefore,
An image display device with a reduced memory size can be provided.

Further, in this display image conversion apparatus, the dot sequential processing circuit includes a horizontal signal number of 2 for the luminance signal.
In an image display apparatus for displaying an image based on input image data in which the number of horizontal data of N and the first and second color difference signals is N, the first color difference signal and the second color difference signal are represented by the number of horizontal data of the luminance signal. It is preferable to switch the data at a rate of 1 for each data to obtain a color difference signal having 2N horizontal data.

Further, a display image conversion apparatus according to another aspect of the present invention is an image display apparatus for displaying an image based on input image data having a luminance signal and first and second color difference signals. A display image conversion apparatus for converting the positions of the pixels of the image data and outputting the converted image data to a display panel, wherein the luminance signal and the first and second color difference signals are converted to a dot sequential signal. A processing circuit; a memory for holding the dot-sequential signal data output by the dot-sequencing processing circuit; and an address for converting and reading the position of the dot-sequential signal data held in the memory on the display screen. A memory control circuit, a dot-sequential demodulation circuit for separating the converted dot-sequential signal data output from the memory into a luminance signal and a color difference signal, and A vertical processing circuit that performs vertical correction processing on the converted color difference signal to generate first and second color difference signals after position conversion, a position-converted luminance signal output from the point-sequential demodulation processing circuit, A decoding processing circuit that generates R, G, and B signals to be applied to the display panel based on the first and second color difference signals after the position conversion output by the vertical processing circuit.

According to the display image conversion device having this configuration, in the input image data type image display device having the luminance signal and the first and second color difference signals, the memory for displaying the rotated image is provided. This can be realized with one memory having the same bit area as only the luminance signal. Therefore, an image display device with a reduced memory size can be provided.

Further, in this display image conversion apparatus, the dot sequential processing circuit includes a luminance signal whose horizontal data number is two.
In an image display apparatus for displaying an image based on input image data in which the number of horizontal data of N and the first and second color difference signals is N, the first color difference signal and the second color difference signal are represented by the number of horizontal data of the luminance signal Is switched every data at a rate of 3 to obtain third color difference signal data having a horizontal data number of 2N, and furthermore, the luminance signal data and the third color difference signal data
It is preferable that the image data is switched for each data at a rate of twice the number of horizontal data to obtain 4N horizontal data.

Further, in the display image converter having the above-described two configurations, the memory control circuit converts the positions of the pixels in the horizontal direction and the vertical direction, so that the read address is orthogonal to the write address. Preferably, the address of the memory is controlled. The vertical processing circuit may further include a line memory for delaying the converted color difference signal output from the memory by one horizontal period, a converted color difference signal output from the memory, and an output signal from the line memory. A first and a second switching circuit for switching the color difference signal delayed by one horizontal period every one horizontal period. It is preferable to switch the converted color difference signals output from the memory, in which the two color difference signals are only odd-numbered lines, such that both the first and second color difference signals are output to all the lines.

Further, the vertical processing circuit includes a first line memory for delaying the converted color difference signal output from the memory by one horizontal period, and a delayed conversion output from the first line memory. After one more color difference signal
A second line memory for delaying a horizontal period, and a converted color difference signal output from the memory and a converted color difference signal output from the second line memory and delayed by two horizontal periods in a vertical direction. Vertical interpolation processing circuit for performing the interpolation processing of the above, a converted color difference signal output from the vertical interpolation processing circuit, and 1 output from the first line memory.
A first and a second switching circuit for switching a color difference signal delayed by a horizontal period every horizontal period;
Switching circuit, the first color difference signal is only for even lines,
Of the converted color difference signal output from the memory in which the color difference signals of only the odd number lines are output so that both the first and second color difference signals become continuous line signals and are output to all the lines. Is preferred.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, input image data of an embodiment includes a luminance signal and first and second color difference signal data in which the number of image data in the horizontal direction is 1/2 each of the luminance signal. (Y: Cb: Cr = 4: 2: 2 system) will be described. Hereinafter, the first color difference signal is Cb and the second color difference signal is Cr.

Embodiment 1 Embodiment 1 of a display image conversion apparatus according to the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram illustrating the configuration of the display image conversion device according to the first embodiment. FIG. 2 is a timing chart (hereinafter, referred to as a horizontal data timing chart) of the rate of the number of horizontal data of the luminance signal, Cb, and Cr signals in the first embodiment. As shown in FIG. 1, a display image conversion apparatus for rotating an image by 90 degrees according to the first embodiment includes a first memory 2 for holding field image data of an input luminance signal, and an input Cb and Cr 2 A dot-sequential processing circuit 1 for converting the color difference signals of the system into dot-sequential signal data, a second memory 3 for holding the dot-sequential color-difference signal data, and first and second memories 2 and 3 respectively. A memory control circuit 4 for converting the positions of the field image data and the dot-sequential color difference signal data on the display screen and generating addresses for reading the converted data.
A vertical correction circuit 5 for performing vertical correction processing on the converted color difference signal output from the second memory 3 to generate Cb and Cr signals after position conversion, and a position conversion output from the first memory 2 It comprises a decoding circuit 6 for creating R, G, B signals to be given to the display panel based on the luminance signal after that and the Cb and Cr signals after position conversion output from the vertical correction circuit 5.

The dot-sequentialization processing circuit 1 receives two input color difference signals of Cb and Cr as shown in FIGS. 2B and 2C as shown in FIG. The luminance signal is switched for each data at the rate of the number of data in the horizontal direction, and a dot-sequential color difference signal having the same rate as the luminance signal shown in FIG. 2D is output. In the first memory 2 and the second memory 3, the field image data of the input luminance signal and the dot-sequential chrominance signal data output from the dot-sequential processing circuit 1 are written respectively, and the horizontal and vertical rotation conversions are performed. And read out. And the memory control circuit 4
Gives the same address to the first memory 2 and the second memory 3, controls writing and reading independently, and sets the reading address orthogonal to the writing address. The address of the first and second memories 2 and 3 is controlled.

FIG. 3A shows the input data of the luminance signal to the first memory 2 before the rotation conversion and the output data from the first memory 2 after the rotation conversion in the first embodiment. FIG. 3B shows input data of a dot-sequential color difference signal to the second memory 3 and output data from the second memory 3 after the rotation conversion. As is clear from FIG. 3, the luminance signal data is regular data in which the positions of the pixels on the display screen have been converted, whereas the Cb and Cr signal data are data that are switched and output for each line.

The vertical processing circuit 5 is for outputting both the Cb and Cr signals switched and output for each line to all the lines. As shown in FIG. 4, the vertical processing circuit 5
a line memory 11 for delaying the b and Cr signals by one horizontal period (hereinafter referred to as 1H), Cb and Cr signals output from the second memory 3, Cb delayed by 1H output from the line memory 11, It comprises a first switching circuit 12 and a second switching circuit 13 for switching a Cr signal every 1H.

FIG. 5 is a timing chart of the rate of the number of vertical data of the vertical processing circuit 5 (hereinafter, referred to as a vertical rate timing chart). As shown in FIG. 5E, the first switching circuit 12 outputs the Cb signal, so that the Cb signal output from the second memory 3 is output on the even-numbered lines, and 1H to 1H on the odd-numbered lines. The delayed Cb signals are switched and output. Here, as shown in FIG. 5D, the Cb signal output from the second memory 3 when the switching signal is H, and the line memory 1 when the switching signal is L
A switching signal for outputting a Cb signal delayed by 1H from 1 is provided. On the other hand, as shown in FIG. 5F, the second switching circuit 13 outputs the Cr signal by delaying the Cr signal by 1H from the line memory 11 on the even line and the second memory on the odd line in order to output the Cr signal. 3 are output by switching the respective Cr signals. By outputting the signal with the necessary delay as described above, the necessary image rotation can be obtained. In this way, the vertical processing circuit 5 outputs Cb, C
An r signal is output. The decoding circuit 6 converts the luminance signal after rotation conversion output from the first memory 2 and the Cb and Cr color difference signals output from the vertical processing circuit 5 into R, G,
The output is sent to a display panel such as a liquid crystal to display an image after rotation conversion. With the above configuration, the luminance signal whose memory size can be reduced, C
With respect to the input image data having the b and Cr signals, it is possible to display an image obtained by rotationally converting the input image data.

Embodiment 2 Embodiment 2 of the display image conversion device according to the present invention will be described with reference to the drawings.
FIG. 6 is a block diagram illustrating the configuration of the display image conversion device according to the second embodiment. FIG. 7 is a block diagram illustrating a configuration of a luminance horizontal interpolation processing circuit according to the second embodiment. As shown in FIG. 6, the display image conversion apparatus according to the second embodiment includes a luminance horizontal interpolation processing circuit 21 that performs interpolation processing on an input luminance signal and a Cr signal, a chrominance horizontal interpolation processing circuit 22, Is added to the display image conversion device of the first embodiment. Therefore, the same parts as those in the first embodiment will be described with the same reference numerals.

As shown in FIG. 7, the luminance horizontal interpolation processing circuit 21 delays the inputted luminance signal by one data (hereinafter 1T).
), A first multiplier 32 for multiplying the output of the horizontal delay circuit 31 by an interpolation coefficient K (0 ≦ K ≦ 1), and an interpolation coefficient for the input luminance signal. A second multiplier 33 for multiplying (1-K), and an adder 34 for adding outputs of the first and second multipliers
It is composed of FIG. 8 is a horizontal rate timing chart of the luminance horizontal interpolation processing circuit 21. In this example, by performing horizontal interpolation processing on the input luminance signal with the interpolation coefficient K = 0.5, the luminance signal virtually delayed by 1.5T as shown in FIG. It is possible to output.

The chrominance horizontal interpolation circuit 22 has the same configuration as the luminance horizontal interpolation circuit 21 and will be described with reference to FIG. The color difference horizontal interpolation circuit 22 delays one data of the Cr signal input by the horizontal delay circuit 31 (2T at the rate of the number of data of the luminance signal) as shown in FIG. 8D. C after horizontal interpolation delayed by 1T (a delay of 1/2 data with respect to the input Cr signal)
An r signal is output.

The dot sequential processing circuit 1 switches the two color difference signals of the input Cb signal and the Cr signal which is the output of the color difference horizontal interpolation processing circuit for each data at the rate of the number of data of the luminance signal. As shown in FIG. 8E, Cb and Cr signals having the same data number rate as the luminance signal are used. In the first memory 2 and the second memory 3, the luminance signal output from the luminance horizontal interpolation processing circuit 21 and the Cb and Cr signals output from the dot sequential processing circuit 1 are written, respectively. It is read out by performing vertical rotation conversion. The memory control circuit 4 gives the same address to the first memory 2 and the second memory 3, controls writing and reading independently, and sets the read address orthogonal to the write address. The address of the first and second memories 2 and 3 is controlled as described above.

FIG. 9 shows the input data to the first and second memories 2 and 3 before the rotation conversion of the luminance signal and the dot-sequential color difference signal and the first and second data after the rotation conversion in the second embodiment. The output data from the memory will be described. As shown in FIG. 9A, the luminance signal data is 1.
Although the position of the pixel on the display screen is converted into regular data with a delay of 5H, as shown in FIG. 9B, the dot-sequential color difference signal data is obtained by adding a Cb signal and a Cr signal to each line. Will be the data output to The vertical processing circuit 5
The dot-sequential color difference signal data output for each line is used to output both the Cb and Cr signals to all lines, and is the same as the configuration in the first embodiment. FIG. 10 is a vertical rate timing chart of the vertical processing circuit 5 according to the second embodiment. As in the first embodiment, the Cb or Cr signal output from the second memory 3 every 1H and the Cb or Cr signal output from the line memory 11
10 (e) and (f) of FIG.
The Cb and Cr signals shown in FIG. The decoding circuit 6 converts the rotation-converted luminance signal output from the first memory 2 and the rotation-converted luminance signal output from the vertical processing circuit 5.
The b and Cr signals are converted into R, G, and B signals, and the output is sent to a display panel such as a liquid crystal to display an image that has been rotationally converted.

In the second embodiment, the delay difference between the Cb signal and the Cr signal and the delay difference between the luminance signal and the Cb and Cr signals generated in the vertical direction after the rotation conversion in the first and second memories are calculated. The luminance horizontal interpolation processing circuit 21 and the color difference horizontal interpolation processing circuit 22 before the conversion can be corrected in advance. Therefore, without increasing the number of line memories or the like which would lead to an increase in the scale of the LSI, it is
As shown in (g) and (g), the virtual vertical positions of the luminance signal and the color difference signal can be matched. Further, as shown in FIGS. 10E and 10F, it is possible to minimize the difference in the vertical position between the Cb signal and the Cr signal, thereby suppressing the generation of a false color. In the second embodiment, the luminance horizontal interpolation processing circuit 21 sets the interpolation coefficient to K = 1, and outputs a luminance signal delayed by 1T from the luminance horizontal interpolation processing circuit 21. FIG. By using the vertical processing circuit 55 having the configuration shown in FIG.
5, the vertical position of the Cb and Cr signals output from No. 5 can be perfectly matched to eliminate the occurrence of false colors.

The vertical processing circuit 55 shown in FIG. 11 comprises a first line memory 35 for delaying the color difference signal output from the second memory 3 by 1H,
The 1H-delayed color difference signal output from
A second line memory 36 for delaying, a vertical interpolation processing circuit 37 for performing vertical interpolation on the output of the second memory 3 and the output of the second line memory 36, The color difference signal output from the processing circuit 37 and the color difference signal output from the first line
It comprises a first switching circuit 38 and a second switching circuit 39 for switching every H. FIG. 12 is a vertical rate timing chart of the vertical processing circuit 55. In this example, the vertical interpolation coefficient K is set to 0.5. In the vertical interpolation processing circuit 37, the color difference signal output from the second memory 3 shown in FIG. In order to add and average the 2H-delayed color difference signal output from the second line memory 36 shown in FIG. 12D, the color difference signal shown in FIG. 12E is output. The color difference signal output from the vertical interpolation circuit 37 and the color difference signal output from the first line memory 36 shown in FIG. The output of the signal is shown in FIG.
(G) and (f) show the Cb and Cr signals.

With the above configuration, according to the second embodiment, it is possible to display an image obtained by rotating and converting input image data having a luminance signal whose memory size can be reduced and Cb and Cr signals. . Further, in the process before the rotation conversion by the memory control, a process for canceling the delay after the rotation conversion is performed, thereby minimizing the increase in the circuit scale, the vertical delay difference between the luminance signal and the Cb and Cr signals, and the C delay.
It is possible to minimize or eliminate the difference in delay between the r signal and the Cb signal.

Third Embodiment A third embodiment of the display image conversion apparatus according to the present invention will be described with reference to the drawings. FIG. 13 is a block diagram illustrating a configuration of a display image conversion device according to the third embodiment of the present invention. 14 and 15 are vertical rate timing diagrams according to the third embodiment. As shown in FIG. 13, the display image conversion apparatus according to the third embodiment includes a line sequential processing circuit 41 that performs pre-rotational conversion processing of input Cb and Cr signals, and a color difference horizontal interpolation processing circuit 22. The configuration is the same as that of the display image conversion apparatus according to the first embodiment except that a post-conversion horizontal interpolation circuit 42 for performing post-rotation conversion processing is provided. The same parts as those in the first embodiment will be described with the same reference numerals.

Line Sequential Processing Circuit 41 in Third Embodiment
14 shows the input two-color difference signals of Cb and Cr in FIG.
(E), a line-sequential color difference signal in which Cb and Cr signals are arranged every 1H. The chrominance horizontal interpolation circuit 22 has the same configuration as that of the second embodiment. The chrominance horizontal interpolation circuit 22 performs an interpolation process on the line-sequential chrominance signal output from the line-sequential processing circuit 41 to delay the Cb and Cr signals by 0.5T. create. Further, the Cb and Cr signals subjected to the interpolation processing,
The line-sequential chrominance signal output from the line-sequential processing circuit 41 is switched for each data at the rate of the number of data of the luminance signal, and as shown in FIG. It is to be. The first memory 2 and the second memory 3 are memories in which the input luminance signal and the color difference signal output from the color difference horizontal interpolation processing circuit 22 are written, and read by performing horizontal and vertical rotation conversion. . The memory control circuit 4 controls the first memory 2
And the second memory 3 are given the same address, and independently control writing and reading, and
The addresses of the memories 2 and 3 are controlled so that the read address is orthogonal to the write address.

FIG. 16 shows the input data to the first and second memories 2 and 3 and the rotation of the luminance signal and the chrominance signal output from the chrominance horizontal interpolation circuit 22 before rotation conversion in the third embodiment. The converted first and second memories 2,
3 shows the output data. As shown in FIG. 16A, the luminance signal is regular data in which the positions of the pixels on the display screen are converted, but the color difference signal is a Cb signal and a Cr signal.
Signal is output for each data. The post-conversion horizontal interpolation processing circuit 42 converts the Cb signal and the Cr signal for each data output from the second memory 3 into Cb and Cr signals at the same rate as the luminance signal.
With a configuration in which interpolation processing is performed on the r signal and switching is performed, Cb and Cr signals at the same rate as the luminance signal shown in (c) and (d) of FIG. 17 are output. The decoding circuit 6 converts the luminance signal after rotation conversion output from the first memory 2 and the Cb and Cr signals output from the horizontal interpolation processing circuit 42 after conversion into R, G, and B signals. The output is sent to a liquid crystal panel or the like, and the rotation-converted image is displayed.

In the third embodiment, since the chrominance signal data of the vertical line is reduced to 1/2 in advance, the actual rate of the horizontal chrominance signal after the rotation conversion is reduced. However, the memory is of a very simple configuration without using a line memory. It is possible to display an image obtained by rotating and converting input image data having a luminance signal, a Cb and Cr signal whose size can be reduced, and further, a vertical delay difference between the luminance signal and the Cb and Cr signals, and a Cr signal. It is possible to eliminate the difference in delay between the signal and the Cb signal.

<< Embodiment 4 >> A display image conversion apparatus according to Embodiment 4 of the present invention will be described with reference to the drawings. FIG. 18 is a block diagram illustrating a configuration of a display image conversion device according to the fourth embodiment of the present invention. FIG. 19 is a horizontal rate timing chart according to the fourth embodiment. FIG. 20 is a diagram illustrating input data to the memory before rotation conversion and output data from the memory after rotation conversion according to the fourth embodiment.

As shown in FIG. 18, the display image conversion apparatus according to the fourth embodiment includes a dot sequential processing circuit 62 for converting an input luminance signal and Cb and Cr signals into a dot sequential signal, and a dot sequential processing circuit. A memory 63 for holding the dot-sequential signal data output from the memory 62, and a memory control circuit 65 for generating an address for converting and reading the position of the pixel on the display screen of the dot-sequential signal data held in the memory 63. This is different from the display image conversion device of the first embodiment.
The same parts as those in the first embodiment will be described with the same reference numerals.

The dot sequential processing circuit 62 of the fourth embodiment converts the input luminance signal and the two color difference signals of Cb and Cr into two times the data rate of the luminance signal as shown in FIG. Switching, as shown in FIG. 19D, a dot sequential signal in which the luminance signal at twice the rate of the luminance signal and the Cb and Cr signals are arranged in one line. In the memory 63, dot sequential signals of the luminance signal and the Cb and Cr signals output from the dot sequential processing circuit 62 are written, and the horizontal and vertical pixel positions on the display screen are converted and read. The memory control circuit 64 controls the writing and reading independently, and controls the memory 63 so that the reading address is orthogonal to the writing address.
Is controlled. Further, as shown in FIG. 20, when sequentially counting up the vertical addresses,
Reading is performed by switching between two necessary horizontal addresses.
Thus, an output from the memory 63 after the rotation conversion as shown in FIG. 20 is obtained.

The dot-sequential demodulation processing circuit 65 converts the rotation-converted dot-sequential signal output from the memory 63 into a luminance signal and Cb
21A and 21B, and a signal after being output from the memory 63 shown in FIGS. 21A and 21B is used as an input signal, and is divided into FIGS. 21C, 21D, and 21E. As shown in (2), switching is performed so as to obtain an output signal separated into a luminance signal and Cb and Cr signals. The vertical processing circuit 5 is for outputting the output of the dot-sequential demodulation processing circuit 65 in which each of the Cb signal and the Cr signal is output for each line to both the Cb and Cr signals on all the lines. The same processing as in 1 is performed. The decoding circuit 6 converts the luminance signal after rotation conversion output from the point-sequential demodulation processing circuit 65 and the Cb and Cr signals output from the vertical processing circuit 5 into R, G, and B signals.
The output is sent to a liquid crystal panel or the like to display an image obtained by rotation conversion.

With the above arrangement, the luminance signals, Cb and C
It is possible to realize a memory for displaying an image obtained by rotating and converting input image data having an r signal with a single memory having the same bit area as only a luminance signal.
When there is room in the bit area of the memory, the bit area of the luminance signal and the bit area of the dot-sequentialized Cb and Cr signals are set to a bit area obtained by adding them.
Rotation conversion is possible with one memory. For example, as shown in FIG. 22, a memory 66 that divides the field image data of the luminance signal and the dot sequential Cb and Cr signal data output from the dot sequential processing circuit 1 into upper bits and lower bits and uses them is used. This can be realized by a configuration in which the data held in the memory 66 is rotationally converted by the memory control circuit 67 at the position of the pixel on the display screen, divided into upper bits and lower bits, and read.

Further, in the above-described first to fourth embodiments, it is also possible to combine the technique of reducing the memory size by changing the horizontal and vertical access directions for each field while keeping the write and read address controls orthogonal. It is possible. In the first to fourth embodiments, Y: C
b: Cr = 4: 2: 2 system has been described, but Y: C
It goes without saying that the b: Cr = 4: 1: 1 method can be handled by controlling the memory. It is also possible to realize a display image conversion system by combining the contents of the first to fourth embodiments.

[0051]

As is apparent from the above detailed description of the embodiments, it is possible to display an image obtained by rotating and converting input image data having luminance signals, Cb and Cr signals whose memory size can be reduced. Becomes possible.

Further, in addition to the effect of the rotation conversion, in the processing before the rotation conversion by the memory, the processing for canceling the delay after the rotation conversion is performed, so that the increase in the circuit scale is minimized, and the luminance signal and Cb And the delay difference between the Cr signal and the Cr signal and the Cb signal can be minimized or eliminated.

In the rotation conversion, it is possible to eliminate a vertical delay difference between the luminance signal and the Cb and Cr signals and a delay difference between the Cr signal and the Cb signal with a very simple configuration that does not use a line memory. is there.

Further, the above-mentioned rotation conversion can be realized by one memory having the same bit area as that of only the luminance signal.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a display image conversion device according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram illustrating an operation of a dot sequential processing circuit according to the first embodiment of the present invention.

FIG. 3 is an explanatory diagram illustrating an operation of rotation conversion in a memory according to the first embodiment of the present invention.

FIG. 4 is a configuration diagram of a vertical processing circuit according to the first and second embodiments of the present invention.

FIG. 5 is a vertical rate timing chart illustrating an operation of the vertical processing circuit according to the first embodiment of the present invention.

FIG. 6 is a configuration diagram of a display image conversion device according to a second embodiment of the present invention.

FIG. 7 is a configuration diagram of a luminance horizontal interpolation processing circuit according to a second embodiment of the present invention.

FIG. 8 is a horizontal rate timing chart showing an operation before a memory input in Embodiment 2 of the present invention.

FIG. 9 is an explanatory diagram illustrating an operation of rotation conversion in a memory according to the second embodiment of the present invention.

FIG. 10 is a vertical rate timing chart illustrating an operation of the vertical processing circuit according to the second embodiment of the present invention.

FIG. 11 is a configuration diagram of a vertical processing circuit according to another embodiment in the first and second embodiments of the present invention.

FIG. 12 is a vertical rate timing chart illustrating an operation of a vertical processing circuit according to another embodiment of the second embodiment of the present invention.

FIG. 13 is a configuration diagram of a display image conversion device according to a third embodiment of the present invention.

FIG. 14 is a vertical rate timing chart illustrating an operation of the line sequential processing circuit according to the third embodiment of the present invention.

FIG. 15 is an explanatory diagram illustrating the operation of the color difference horizontal interpolation processing circuit according to the third embodiment of the present invention.

FIG. 16 is an explanatory diagram illustrating an operation of rotation conversion in a memory according to the third embodiment of the present invention.

FIG. 17 is an explanatory diagram illustrating an operation of a horizontal interpolation processing circuit after conversion in Embodiment 3 of the present invention.

FIG. 18 is a configuration diagram of a display image conversion device according to a fourth embodiment of the present invention.

FIG. 19 is a horizontal rate timing chart showing an operation of the dot sequential processing circuit in Embodiment 4 of the present invention.

FIG. 20 is an explanatory diagram illustrating an operation of rotation conversion in a memory according to the fourth embodiment of the present invention.

FIG. 21 is an explanatory diagram illustrating an operation of a dot-sequential demodulation processing circuit according to a fourth embodiment of the present invention.

FIG. 22 is a configuration diagram of a display image conversion device in another embodiment of Embodiment 4 of the present invention.

FIG. 23 is a configuration diagram of a conventional display conversion device.

FIG. 24 is an explanatory diagram showing an operation of rotation conversion in a memory in a conventional display conversion device.

[Explanation of symbols]

 1,62 point sequential processing circuit 2,3,63,66 memory 4,64,67 memory control circuit 5,55 vertical processing circuit 6 decoding circuit 11,35,36 line memory 12,13,38,39 switching circuit 21 Luminance horizontal interpolation processing circuit 22 color difference horizontal interpolation processing circuit 31 horizontal delay circuit 32,33 multiplier 34 adder 37 vertical interpolation processing circuit 41 line sequential processing circuit 42 converted horizontal interpolation processing circuit 65 point sequential demodulation processing circuit

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Sumihiro Domitsu 1006 Kazuma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. F term (reference) 5C006 AA01 AA14 AA22 AB01 AC02 AC28 AF06 AF13 AF42 AF44 AF46 AF85 BB12 BF01 BF05 BF07 BF26 BF28 FA44 5C057 AA06 BA05 DA05 EA01 EA02 EA07 EB15 GF07 GG01 GG06 GG07 GJ01 GJ03 GL00 GM07 5C080 AA10 BB05 CC03 DD22 EE23 FF09 GG08 JJ02 JJ04 JJ05

Claims (17)

[Claims] 1. An image display device for displaying an image based on input image data having a luminance signal and first and second color difference signals, wherein horizontal and vertical pixel positions are converted to display the converted image data. A display image conversion device for outputting to a panel, a dot sequential processing circuit for converting the first and second color difference signals into a dot sequential signal, and a first memory holding field image data of the luminance signal A second memory for holding dot-sequential color difference signal data output from the dot-sequencing circuit; a field image data held in the first memory; and a dot-sequential color difference signal held in the second memory. A memory control circuit for generating an address for converting a position on a display screen with data in a horizontal direction and a vertical direction and reading the data; and a position-converted point output from the second memory. A vertical processing circuit that performs vertical correction processing on the next color difference signal data and creates first and second color difference signals after position conversion; a position-converted luminance signal output from the first memory; From the first and second color difference signals after the position conversion output from the processing circuit, R, G,
A display image conversion apparatus, comprising: a decoding processing circuit that generates a B signal. 2. An image display device for displaying an image based on input image data having a luminance signal and first and second color difference signals, wherein the positions of pixels in the horizontal and vertical directions are converted to display the converted image data. A display image conversion device for outputting to a panel, comprising: a luminance horizontal interpolation processing circuit that performs horizontal interpolation processing of the luminance signal; and a chrominance horizontal interpolation processing circuit that performs horizontal interpolation processing on the second chrominance signal. A dot sequential processing circuit for converting the first color difference signal and the second color difference signal output by the color difference horizontal interpolation processing circuit into a dot sequential signal; and output by the luminance horizontal interpolation processing circuit. A first memory for holding field image data of a luminance signal, a second memory for holding dot-sequential color difference signal data output by the dot-sequencing processing circuit, and a field image data held in the first memory A memory control circuit for generating an address for converting the position on the display screen between the data and the dot-sequential color difference signal data held in the second memory in the horizontal direction and the vertical direction, and for reading out the data. A vertical processing circuit for performing a vertical correction process on the output dot-sequential color difference signal data after the position conversion and generating the first and second color difference signals after the position conversion; and a position conversion output from the first memory. R, G, and B given to the display panel from the post-luminance signal and the first and second color difference signals after the position conversion output by the vertical processing circuit.
A display image conversion device, comprising: a decoding processing circuit that generates a signal. 3. An image display device for displaying an image based on input image data having a luminance signal and first and second color difference signals, wherein horizontal and vertical pixel positions are converted to display the converted image data. A display image conversion device for outputting to a panel, a line sequential processing circuit for converting the first and second color difference signals into line sequential signals for respective lines, and a line output by the line sequential processing circuit A chrominance horizontal interpolation circuit for sequentially performing horizontal interpolation on the chrominance signal; a first memory for holding field image data of the luminance signal; and a line-sequential chrominance signal data output by the chrominance horizontal interpolation circuit. A second memory to be held, and positions of the field image data held in the first memory and the line-sequential color difference signal data held in the second memory on the display screen in the horizontal and vertical directions. A memory control circuit for generating an address for converting and reading the data, performing a horizontal interpolation process on the line-sequential color difference signal data after the position conversion output from the second memory, and performing the first and the second after the position conversion. A post-conversion horizontal interpolation processing circuit for generating a second color difference signal; a position-converted luminance signal output from the first memory; and a position-converted first signal output from the post-conversion horizontal interpolation processing circuit. And a decode processing circuit for generating R, G, B signals to be given to the display panel from the second color difference signal. 4. An image display device for displaying an image based on input image data having a luminance signal and first and second color difference signals, wherein horizontal and vertical pixel positions are converted to display the converted image data. A display image conversion device for outputting to a panel, a dot sequential processing circuit for converting the first and second color difference signals into a dot sequential signal, field image data of the luminance signal, and the dot sequential processing circuit A memory for dividing and storing the dot-sequential color difference signal data output into upper bits and lower bits, and positions of the field image data and the dot-sequential color difference signal data divided and held in the memory on the display screen. A memory control circuit for generating an address for converting and reading, and performing a vertical correction process on the dot-sequential color difference signal data after the position conversion output from the memory. And the post position conversion 1
And a vertical processing circuit for generating a second color difference signal; a position-converted luminance signal output from the memory; and a position-converted first and second color difference signals output from the vertical processing circuit. A display image conversion device, comprising: a decode processing circuit that creates R, G, and B signals to be applied to a display panel. 5. An image display device for displaying an image based on input image data having a luminance signal and first and second color difference signals, wherein the horizontal and vertical pixel positions are converted to display the converted image data. A display image conversion device for outputting to a panel, comprising: a dot sequential processing circuit for converting the luminance signal and the first and second color difference signals into a dot sequential signal; A memory for holding the dot-sequential signal data, a memory control circuit for generating an address for converting and reading the position of the pixel on the display screen of the dot-sequential signal data held in the memory, and an output from the memory A point-sequential demodulation processing circuit for separating the point-sequential signal data after the position conversion into a luminance signal and first and second color difference signals; A vertical processing circuit that performs vertical correction processing on the next color difference signal data and creates first and second color difference signals after position conversion; a position-converted luminance signal output by the point-sequential demodulation processing circuit; From the first and second color difference signals after the position conversion output from the processing circuit, R,
A display image conversion device, comprising: a decode processing circuit that creates G and B signals. 6. The memory control circuit converts horizontal and vertical pixel positions so that a read address is orthogonal to a write address of each of the first memory and the second memory. And controlling the addresses of the first memory and the second memory and controlling the same addresses of the first memory and the second memory.
The display image conversion device according to any one of Items 2 and 3. 7. The memory control circuit controls an address of the memory such that a read address is orthogonal to a write address of the memory in order to convert a position of a pixel in a horizontal direction and a vertical direction. The display image conversion device according to any one of claims 4 and 5, wherein: 8. An image display apparatus, wherein the dot sequential processing circuit displays an image based on input image data in which the number of horizontal data of the luminance signal is 2N and the number of horizontal data of each of the first and second color difference signals is N. , The first color difference signal and the second
5. The color difference signal of any one of claims 1, 2 and 4, wherein the color difference signal is switched for each data at a rate of the number of horizontal data of the luminance signal, and the number of horizontal data is 2N. Display image conversion device. 9. The image display device according to claim 1, wherein the line sequential processing circuit displays an image based on input image data in which the number of vertical lines of the first and second color difference signals is N.
The first color difference signal is applied to the even lines, and the second color difference signal is applied to the odd lines.
4. The display image conversion apparatus according to claim 3, wherein switching is performed for each line so that the color difference signals are output. 10. An image display apparatus, wherein the dot sequential processing circuit displays an image based on input image data in which the number of horizontal data of the luminance signal is 2N and the number of horizontal data of each of the first and second color difference signals is N. , The first color difference signal and the second
Is switched every data at the rate of the number of horizontal data of the luminance signal to obtain third color difference data having a horizontal data number of 2N. Further, the luminance signal and the third color difference data are twice as large as the luminance signal. The display image conversion apparatus according to claim 5, wherein switching is performed for each data at a rate of the number of horizontal data to obtain image data having a number of horizontal data of 4N. 11. A line memory for delaying, by one horizontal period, a position-converted color difference signal output from the second memory, the vertical processing circuit including: a line memory after the position conversion output from the second memory; And a first and a second switching circuit that switches the color difference signal output from the line memory and the color difference signal after the position conversion delayed by one horizontal period every one horizontal period. The second switching circuit converts the color difference signals held in the second memory, in which the first color difference signal is only even-numbered lines, and the second color difference signal is only odd-numbered lines, between the first and second color difference signals. 3. The display conversion device according to claim 1, wherein the switching is performed such that any one of the lines is output to all the lines. 12. A first line memory for delaying the position-converted color difference signal output from the second memory for one horizontal period, the vertical processing circuit including: a first line memory; and a first line memory output from the first line memory. A second line memory for further delaying the converted color difference signal delayed by one horizontal period by one horizontal period, a position-converted color difference signal output from the second memory, and the second line memory A vertical interpolation processing circuit that performs vertical interpolation processing on the position-converted color difference signal delayed by two horizontal periods, and a position-converted color difference signal output by the vertical interpolation processing circuit. A first and a second switching circuit for switching a position-converted color difference signal output from the first line memory and delayed by one horizontal period every horizontal period; Switching circuit The position-converted color difference signal output from the second memory, in which the first color difference signal is only even-numbered lines and the second color difference signal is only odd-numbered lines, is either one of the first and second color difference signals. 3. The display conversion device according to claim 1, wherein the switching is performed such that the output signal is a line signal that is continuous in the vertical direction and is output to all the lines. 4. 13. A line memory for delaying the position-converted color difference signal output from the memory by one horizontal period, the vertical processing circuit, the position-converted color difference signal output from the memory, A first and a second switching circuit for switching a position-converted color difference signal output from the line memory delayed by one horizontal period every one horizontal period, wherein the first and second switching circuits One color difference signal is an even line only, and the second color difference signal is an odd line only. The position-converted color difference signals output from the memory are all the first and second color difference signals. The display conversion device according to any one of claims 4 and 5, wherein switching is performed so as to be output to the display conversion device. 14. A first line memory for delaying the position-converted color difference signal output from the memory by one horizontal period, and one horizontal line output from the first line memory. A second line memory for further delaying the position-converted color difference signal delayed by a period by one horizontal period; a position-converted color difference signal output from the memory; and a second line memory output from the second line memory A vertical interpolation processing circuit that performs vertical interpolation on the position-converted color difference signal delayed by two horizontal periods; a position-converted color difference signal processed by the vertical interpolation processing circuit; The first and second switching circuits are configured to switch a position-converted color difference signal output from one line memory and delayed by one horizontal period for each horizontal period, and wherein the first and second switching circuits include: First Color difference signal only the even lines, the color difference signal after conversion second color difference signal is output from the memory is only odd lines, said first
6. The display conversion device according to claim 4, wherein switching is performed such that both the color difference signal and the second color difference signal become continuous line signals and are output to all lines. . 15. A horizontal delay circuit for horizontally delaying the input luminance signal, the luminance horizontal interpolation processing circuit comprising: a horizontal delay circuit for horizontally delaying the input luminance signal; and an interpolation coefficient K (0 ≦ K ≦
1) a first multiplier for multiplying the input luminance signal by an interpolation coefficient (1-K); and an output of the first and second multipliers. A vertical-delay-processed color-difference signal output of the vertical processing circuit that has been delayed in the vertical direction, and a position-converted luminance signal output from the first memory that has not been vertically delayed. 3. The display conversion apparatus according to claim 2, wherein the horizontal delay time of the color difference signal before the position conversion and the position of the virtual data are adjusted in advance so that the vertical line delay times of the color conversion signals become the same. 16. The color difference horizontal interpolation circuit includes: a horizontal delay circuit for delaying the input second color difference signal in a horizontal direction; and an internal circuit for the delayed second color difference signal output from the horizontal delay circuit. A first multiplier for multiplying an interpolation coefficient K (0 ≦ K ≦ 1), and an interpolation coefficient (1-K) for the input second color difference signal
, And an adder for adding the output of the first multiplier and the output of the second multiplier. 4. The display conversion device according to claim 2, wherein the virtual position of the color difference signal is delayed by K data. 17. A horizontal delay circuit for horizontally delaying a color difference signal after position conversion output from the second memory, the horizontal interpolation processing circuit after conversion, and an internal circuit for an output of the horizontal delay circuit. Insertion coefficient K (0 ≦ K ≦
1) a first multiplier for multiplying the second color difference signal by an interpolation coefficient (1-K)
A second multiplier for multiplying an output of the first multiplier and an output of the second multiplier, and a color difference output from the adder and the second memory. And first and second switching circuits for switching a signal for each data, wherein the first and second switching circuits are configured such that only the first color difference signal is an even-numbered data and the second color difference signal is an odd number. 4. The color difference signal output from the second memory, which is only the first data, is switched such that both the first and second color difference signals are continuous data in the horizontal direction. The display conversion device according to claim 1.