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ITTO910929A1 - Procedimento per la fabbricazione di circuiti integrati in tecnologia mos. - Google Patents

Procedimento per la fabbricazione di circuiti integrati in tecnologia mos.

Info

Publication number
ITTO910929A1
ITTO910929A1 IT000929A ITTO910929A ITTO910929A1 IT TO910929 A1 ITTO910929 A1 IT TO910929A1 IT 000929 A IT000929 A IT 000929A IT TO910929 A ITTO910929 A IT TO910929A IT TO910929 A1 ITTO910929 A1 IT TO910929A1
Authority
IT
Italy
Prior art keywords
procedure
manufacture
integrated circuits
mos technology
mos
Prior art date
Application number
IT000929A
Other languages
English (en)
Inventor
Manlio Sergio Cereda
Giancarlo Ginami
Enrico Laurin
Andrea Ravaglia
Original Assignee
Sgs Thomson Microelectronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics
Priority to ITTO910929A priority Critical patent/IT1250233B/it
Publication of ITTO910929A0 publication Critical patent/ITTO910929A0/it
Priority to EP92118785A priority patent/EP0545082B1/en
Priority to DE69231484T priority patent/DE69231484T2/de
Priority to JP4320695A priority patent/JPH05251555A/ja
Publication of ITTO910929A1 publication Critical patent/ITTO910929A1/it
Application granted granted Critical
Publication of IT1250233B publication Critical patent/IT1250233B/it
Priority to US08/475,555 priority patent/US5696399A/en
Priority to US08/524,080 priority patent/US5663080A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H01L21/76218—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers introducing both types of electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers, e.g. for isolation of complementary doped regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Local Oxidation Of Silicon (AREA)
ITTO910929A 1991-11-29 1991-11-29 Procedimento per la fabbricazione di circuiti integrati in tecnologia mos. IT1250233B (it)

Priority Applications (6)

Application Number Priority Date Filing Date Title
ITTO910929A IT1250233B (it) 1991-11-29 1991-11-29 Procedimento per la fabbricazione di circuiti integrati in tecnologia mos.
EP92118785A EP0545082B1 (en) 1991-11-29 1992-11-02 Process for manufacturing MOS-type integrated circuits comprising LOCOS isolation regions
DE69231484T DE69231484T2 (de) 1991-11-29 1992-11-02 Verfahren zur Herstellung von Isolationszonen des LOCOS-Typs für integrierte Schaltungen vom MOS-Typ
JP4320695A JPH05251555A (ja) 1991-11-29 1992-11-30 Ｍｏｓ型集積回路の製造方法
US08/475,555 US5696399A (en) 1991-11-29 1995-06-07 Process for manufacturing MOS-type integrated circuits
US08/524,080 US5663080A (en) 1991-11-29 1995-09-06 Process for manufacturing MOS-type integrated circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ITTO910929A IT1250233B (it) 1991-11-29 1991-11-29 Procedimento per la fabbricazione di circuiti integrati in tecnologia mos.

Publications (3)

Publication Number Publication Date
ITTO910929A0 ITTO910929A0 (it) 1991-11-29
ITTO910929A1 true ITTO910929A1 (it) 1993-05-29
IT1250233B IT1250233B (it) 1995-04-03

Family

ID=11409750

Family Applications (1)

Application Number Title Priority Date Filing Date
ITTO910929A IT1250233B (it) 1991-11-29 1991-11-29 Procedimento per la fabbricazione di circuiti integrati in tecnologia mos.

Country Status (5)

Country Link
US (2) US5696399A (it)
EP (1) EP0545082B1 (it)
JP (1) JPH05251555A (it)
DE (1) DE69231484T2 (it)
IT (1) IT1250233B (it)

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US6380016B2 (en) * 1998-06-23 2002-04-30 Ross Alan Kohler Method for forming programmable CMOS ROM devices
US6362049B1 (en) * 1998-12-04 2002-03-26 Advanced Micro Devices, Inc. High yield performance semiconductor process flow for NAND flash memory products
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US7238563B2 (en) * 2003-03-10 2007-07-03 Kabushiki Kaisha Toshiba Semiconductor device having isolation region and method of manufacturing the same
JP4540320B2 (ja) * 2003-09-19 2010-09-08 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
US20060108641A1 (en) * 2004-11-19 2006-05-25 Taiwan Semiconductor Manufacturing Company, Ltd. Device having a laterally graded well structure and a method for its manufacture

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Also Published As

Publication number Publication date
EP0545082A3 (en) 1994-10-12
JPH05251555A (ja) 1993-09-28
US5663080A (en) 1997-09-02
US5696399A (en) 1997-12-09
EP0545082A2 (en) 1993-06-09
IT1250233B (it) 1995-04-03
ITTO910929A0 (it) 1991-11-29
EP0545082B1 (en) 2000-09-27
DE69231484T2 (de) 2001-02-08
DE69231484D1 (de) 2000-11-02

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19971129