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ITMI20051578A1 - Circuito decodificatore di riga per memorie non volatili programmabili e cancellabili elettricamente - Google Patents

Circuito decodificatore di riga per memorie non volatili programmabili e cancellabili elettricamente

Info

Publication number
ITMI20051578A1
ITMI20051578A1 IT001578A ITMI20051578A ITMI20051578A1 IT MI20051578 A1 ITMI20051578 A1 IT MI20051578A1 IT 001578 A IT001578 A IT 001578A IT MI20051578 A ITMI20051578 A IT MI20051578A IT MI20051578 A1 ITMI20051578 A1 IT MI20051578A1
Authority
IT
Italy
Prior art keywords
clearable
electrically
row decoder
decoder circuit
volatile memories
Prior art date
Application number
IT001578A
Other languages
English (en)
Inventor
Paolo Rolandi
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT001578A priority Critical patent/ITMI20051578A1/it
Priority to US11/504,539 priority patent/US7447103B2/en
Publication of ITMI20051578A1 publication Critical patent/ITMI20051578A1/it
Priority to US12/244,717 priority patent/US7649773B2/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
IT001578A 2005-08-12 2005-08-12 Circuito decodificatore di riga per memorie non volatili programmabili e cancellabili elettricamente ITMI20051578A1 (it)

Priority Applications (3)

Application Number Priority Date Filing Date Title
IT001578A ITMI20051578A1 (it) 2005-08-12 2005-08-12 Circuito decodificatore di riga per memorie non volatili programmabili e cancellabili elettricamente
US11/504,539 US7447103B2 (en) 2005-08-12 2006-08-14 Row decoder circuit for electrically programmable and erasable non volatile memories
US12/244,717 US7649773B2 (en) 2005-08-12 2008-10-02 Row selector circuit for electrically programmable and erasable non volatile memories

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT001578A ITMI20051578A1 (it) 2005-08-12 2005-08-12 Circuito decodificatore di riga per memorie non volatili programmabili e cancellabili elettricamente

Publications (1)

Publication Number Publication Date
ITMI20051578A1 true ITMI20051578A1 (it) 2007-02-13

Family

ID=37767199

Family Applications (1)

Application Number Title Priority Date Filing Date
IT001578A ITMI20051578A1 (it) 2005-08-12 2005-08-12 Circuito decodificatore di riga per memorie non volatili programmabili e cancellabili elettricamente

Country Status (2)

Country Link
US (2) US7447103B2 (it)
IT (1) ITMI20051578A1 (it)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7515475B1 (en) * 2007-07-02 2009-04-07 Sun Microsystems, Inc. Mechanism for compensating for gate leakage in a memory
GB0813014D0 (en) 2008-07-16 2008-08-20 Groveley Detection Ltd Detector and methods of detecting
TWI393141B (zh) * 2008-09-03 2013-04-11 Elan Microelectronics Corp A column decoder that can be used to speed up the read speed in a number of programmable flash memories
CN106664145A (zh) * 2014-07-31 2017-05-10 西门子公司 用于在通信网络中传输时间同步消息的方法、网络部件和通信网络

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0638318B2 (ja) * 1985-02-15 1994-05-18 株式会社リコー Ｅｐｒｏｍの書込み方法
FR2591789B1 (fr) * 1985-12-17 1988-02-19 Labo Electronique Physique Circuit decodeur pour memoire ram statique
EP1168365A3 (en) * 1991-12-09 2004-09-29 Fujitsu Limited Negative-voltage bias circuit
US6363020B1 (en) * 1999-12-06 2002-03-26 Virage Logic Corp. Architecture with multi-instance redundancy implementation
US6545923B2 (en) * 2001-05-04 2003-04-08 Samsung Electronics Co., Ltd. Negatively biased word line scheme for a semiconductor memory device
US6809986B2 (en) * 2002-08-29 2004-10-26 Micron Technology, Inc. System and method for negative word line driver circuit
KR100699852B1 (ko) * 2005-07-14 2007-03-27 삼성전자주식회사 Ｈｐｍｏｓ를 이용한 불휘발성 메모리 장치의 워드라인디코더

Also Published As

Publication number Publication date
US7447103B2 (en) 2008-11-04
US7649773B2 (en) 2010-01-19
US20090027965A1 (en) 2009-01-29
US20070041263A1 (en) 2007-02-22

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