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IT955985B - Sistema per l elaborazione dei dati perfezionato - Google Patents

Sistema per l elaborazione dei dati perfezionato

Info

Publication number
IT955985B
IT955985B IT25031/72A IT2503172A IT955985B IT 955985 B IT955985 B IT 955985B IT 25031/72 A IT25031/72 A IT 25031/72A IT 2503172 A IT2503172 A IT 2503172A IT 955985 B IT955985 B IT 955985B
Authority
IT
Italy
Prior art keywords
data processing
processing system
perfected
perfected data
processing
Prior art date
Application number
IT25031/72A
Other languages
English (en)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of IT955985B publication Critical patent/IT955985B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1063—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently virtually addressed

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
IT25031/72A 1971-06-29 1972-05-30 Sistema per l elaborazione dei dati perfezionato IT955985B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US15791871A 1971-06-29 1971-06-29

Publications (1)

Publication Number Publication Date
IT955985B true IT955985B (it) 1973-09-29

Family

ID=22565881

Family Applications (1)

Application Number Title Priority Date Filing Date
IT25031/72A IT955985B (it) 1971-06-29 1972-05-30 Sistema per l elaborazione dei dati perfezionato

Country Status (6)

Country Link
US (1) US3693165A (it)
JP (1) JPS5240936B1 (it)
DE (1) DE2230266C2 (it)
FR (1) FR2144290A5 (it)
GB (1) GB1366001A (it)
IT (1) IT955985B (it)

Families Citing this family (84)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3786427A (en) * 1971-06-29 1974-01-15 Ibm Dynamic address translation reversed
GB1354827A (en) * 1971-08-25 1974-06-05 Ibm Data processing systems
BE788028A (fr) * 1971-08-25 1973-02-26 Siemens Ag Memoire associative
US3902164A (en) * 1972-07-21 1975-08-26 Ibm Method and means for reducing the amount of address translation in a virtual memory data processing system
US3829840A (en) * 1972-07-24 1974-08-13 Ibm Virtual memory system
US3781808A (en) * 1972-10-17 1973-12-25 Ibm Virtual memory system
US3806888A (en) * 1972-12-04 1974-04-23 Ibm Hierarchial memory system
GB1447297A (en) * 1972-12-06 1976-08-25 Amdahl Corp Data processing system
US3839704A (en) * 1972-12-06 1974-10-01 Ibm Control for channel access to storage hierarchy system
US3848234A (en) * 1973-04-04 1974-11-12 Sperry Rand Corp Multi-processor system with multiple cache memories
US3825904A (en) * 1973-06-08 1974-07-23 Ibm Virtual memory system
US3898624A (en) * 1973-06-14 1975-08-05 Amdahl Corp Data processing system with variable prefetch and replacement algorithms
US3928857A (en) * 1973-08-30 1975-12-23 Ibm Instruction fetch apparatus with combined look-ahead and look-behind capability
US3866183A (en) * 1973-08-31 1975-02-11 Honeywell Inf Systems Communications control apparatus for the use with a cache store
US3840863A (en) * 1973-10-23 1974-10-08 Ibm Dynamic storage hierarchy system
FR130806A (it) * 1973-11-21
FR2258112A5 (it) * 1973-11-30 1975-08-08 Honeywell Bull Soc Ind
FR2253425A5 (it) * 1973-11-30 1975-06-27 Honeywell Bull Soc Ind
FR122199A (it) * 1973-12-17
NL7317545A (nl) * 1973-12-21 1975-06-24 Philips Nv Geheugensysteem met hoofd- en buffergeheugen.
US3896419A (en) * 1974-01-17 1975-07-22 Honeywell Inf Systems Cache memory store in a processor of a data processing system
US3949369A (en) * 1974-01-23 1976-04-06 Data General Corporation Memory access technique
US3949368A (en) * 1974-01-23 1976-04-06 Data General Corporation Automatic data priority technique
US3909798A (en) * 1974-01-25 1975-09-30 Raytheon Co Virtual addressing method and apparatus
US3938100A (en) * 1974-06-07 1976-02-10 Control Data Corporation Virtual addressing apparatus for addressing the memory of a computer utilizing associative addressing techniques
US3911403A (en) * 1974-09-03 1975-10-07 Gte Information Syst Inc Data storage and processing apparatus
JPS5144850A (it) * 1974-10-15 1976-04-16 Ricoh Kk
JPS5540950B2 (it) * 1974-11-30 1980-10-21
US4056845A (en) * 1975-04-25 1977-11-01 Data General Corporation Memory access technique
US4024508A (en) * 1975-06-19 1977-05-17 Honeywell Information Systems, Inc. Database instruction find serial
US4042912A (en) * 1975-06-19 1977-08-16 Honeywell Information Systems Inc. Database set condition test instruction
US4044334A (en) * 1975-06-19 1977-08-23 Honeywell Information Systems, Inc. Database instruction unload
US4025901A (en) * 1975-06-19 1977-05-24 Honeywell Information Systems, Inc. Database instruction find owner
US4212058A (en) * 1975-09-27 1980-07-08 National Research Development Corporation Computer store mechanism
FR2348544A1 (fr) * 1976-04-15 1977-11-10 Honeywell Bull Soc Ind Ensemble double de memoire associative
JPS52130532A (en) * 1976-04-27 1977-11-01 Fujitsu Ltd Address conversion system
US4048671A (en) * 1976-06-30 1977-09-13 Ibm Corporation Address match for data processing system with virtual addressing
JPS533029A (en) * 1976-06-30 1978-01-12 Toshiba Corp Electronic computer
US4084226A (en) * 1976-09-24 1978-04-11 Sperry Rand Corporation Virtual address translator
US4128875A (en) * 1976-12-16 1978-12-05 Sperry Rand Corporation Optional virtual memory system
US4126893A (en) * 1977-02-17 1978-11-21 Xerox Corporation Interrupt request controller for data processing system
US4126894A (en) * 1977-02-17 1978-11-21 Xerox Corporation Memory overlay linking system
US4080652A (en) * 1977-02-17 1978-03-21 Xerox Corporation Data processing system
US4080651A (en) * 1977-02-17 1978-03-21 Xerox Corporation Memory control processor
JPS5454536A (en) * 1977-10-08 1979-04-28 Fujitsu Ltd Data processor
US4285040A (en) * 1977-11-04 1981-08-18 Sperry Corporation Dual mode virtual-to-real address translation mechanism
US4156906A (en) * 1977-11-22 1979-05-29 Honeywell Information Systems Inc. Buffer store including control apparatus which facilitates the concurrent processing of a plurality of commands
US4376297A (en) * 1978-04-10 1983-03-08 Signetics Corporation Virtual memory addressing device
US4170039A (en) * 1978-07-17 1979-10-02 International Business Machines Corporation Virtual address translation speed up technique
US4277826A (en) * 1978-10-23 1981-07-07 Collins Robert W Synchronizing mechanism for page replacement control
CA1123964A (en) * 1978-10-26 1982-05-18 Anthony J. Capozzi Integrated multilevel storage hierarchy for a data processing system
US4217640A (en) * 1978-12-11 1980-08-12 Honeywell Information Systems Inc. Cache unit with transit block buffer apparatus
US4264953A (en) * 1979-03-30 1981-04-28 Honeywell Inc. Virtual cache
US4400774A (en) * 1981-02-02 1983-08-23 Bell Telephone Laboratories, Incorporated Cache addressing arrangement in a computer system
JPS60500187A (ja) * 1982-12-30 1985-02-07 インタ−ナシヨナル・ビジネス・マシ−ンズ・コ−ポレ−シヨン データ処理システム
US4551799A (en) * 1983-02-28 1985-11-05 Honeywell Information Systems Inc. Verification of real page numbers of stack stored prefetched instructions from instruction cache
JPS59157887A (ja) * 1983-02-28 1984-09-07 Hitachi Ltd 情報処理装置
US4747070A (en) * 1984-01-09 1988-05-24 Wang Laboratories, Inc. Reconfigurable memory system
US4669043A (en) * 1984-02-17 1987-05-26 Signetics Corporation Memory access controller
US4991081A (en) * 1984-10-31 1991-02-05 Texas Instruments Incorporated Cache memory addressable by both physical and virtual addresses
JPH0652511B2 (ja) * 1984-12-14 1994-07-06 株式会社日立製作所 情報処理装置のアドレス変換方式
US4884197A (en) * 1985-02-22 1989-11-28 Intergraph Corporation Method and apparatus for addressing a cache memory
US4899275A (en) * 1985-02-22 1990-02-06 Intergraph Corporation Cache-MMU system
US5255384A (en) * 1985-02-22 1993-10-19 Intergraph Corporation Memory address translation system having modifiable and non-modifiable translation mechanisms
US4860192A (en) * 1985-02-22 1989-08-22 Intergraph Corporation Quadword boundary cache system
US4868738A (en) * 1985-08-15 1989-09-19 Lanier Business Products, Inc. Operating system independent virtual memory computer system
US5091846A (en) * 1986-10-03 1992-02-25 Intergraph Corporation Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency
WO1988007721A1 (en) * 1987-04-02 1988-10-06 Unisys Corporation Associative address translator for computer memory systems
GB8728494D0 (en) * 1987-12-05 1988-01-13 Int Computers Ltd Multi-cache data storage system
IT1219238B (it) * 1988-04-26 1990-05-03 Olivetti & Co Spa Dispositivo di traslazione dell'indirizzo per un memoria operativa di computer
JPH0291747A (ja) * 1988-09-29 1990-03-30 Hitachi Ltd 情報処理装置
US5150471A (en) * 1989-04-20 1992-09-22 Ncr Corporation Method and apparatus for offset register address accessing
JP3038781B2 (ja) * 1989-04-21 2000-05-08 日本電気株式会社 メモリアクセス制御回路
US4969122A (en) * 1989-08-21 1990-11-06 Sun Microsystems, Inc. Apparatus for page tagging in a computer system
JPH04233642A (ja) * 1990-07-27 1992-08-21 Dell Usa Corp キャッシュアクセスと並列的にメモリアクセスを行なうプロセッサ及びそれに用いられる方法
US5553270A (en) * 1993-09-01 1996-09-03 Digital Equipment Corporation Apparatus for providing improved memory access in page mode access systems with pipelined cache access and main memory address replay
US6161167A (en) * 1997-06-27 2000-12-12 Advanced Micro Devices, Inc. Fully associate cache employing LRU groups for cache replacement and mechanism for selecting an LRU group
US6848024B1 (en) * 2000-08-07 2005-01-25 Broadcom Corporation Programmably disabling one or more cache entries
US6748492B1 (en) 2000-08-07 2004-06-08 Broadcom Corporation Deterministic setting of replacement policy in a cache through way selection
US6732234B1 (en) 2000-08-07 2004-05-04 Broadcom Corporation Direct access mode for a cache
US6748495B2 (en) 2001-05-15 2004-06-08 Broadcom Corporation Random generator
US7266587B2 (en) * 2002-05-15 2007-09-04 Broadcom Corporation System having interfaces, switch, and memory bridge for CC-NUMA operation
JP2005267148A (ja) * 2004-03-18 2005-09-29 Konica Minolta Business Technologies Inc メモリ制御装置
US11886877B1 (en) * 2021-09-24 2024-01-30 Apple Inc. Memory select register to simplify operand mapping in subroutines

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3401376A (en) * 1965-11-26 1968-09-10 Burroughs Corp Central processor
US3470540A (en) * 1967-04-24 1969-09-30 Rca Corp Multiprocessing computer system with special instruction sequencing
US3569938A (en) * 1967-12-20 1971-03-09 Ibm Storage manager
GB1266579A (it) * 1969-08-26 1972-03-15

Also Published As

Publication number Publication date
JPS5240936B1 (it) 1977-10-15
DE2230266C2 (de) 1983-10-27
DE2230266A1 (de) 1973-01-11
GB1366001A (en) 1974-09-04
US3693165A (en) 1972-09-19
FR2144290A5 (it) 1973-02-09

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