GB1447297A - Data processing system - Google Patents

Abstract

1447297 Data processing AMDAHL CORP and FUJITSU Ltd 19 Nov 1973 [6 Dec 1972] 53521/73 Heading G4A A multichannel data processing unit comprises a main store, instruction unit, execution unit, input/output control and logic circuitry for converting virtual addresses contained in instruction words into real addresses using for each channel an associated stored address conversion parameter. The input/output control comprises a channel unit which can transfer data between storage control and a channel memory (448, Fig. 2, not shown) in the channel unit under the control of a logic unit (430<SP>1</SP>) and transfer information between the channel memory and the input/output devices under the control of a logic unit (432<SP>1</SP>). As described the logic units are part of a shift register in a channel memory, the memory also comprising a local channel store 406 (Fig. 3) including a channel buffer store and a subchannel state store and a sub-channel buffer store 408. Registers 404 are operative to store data or write data into the storage unit at an address held in a store unit address register (464, Fig. 4, not shown). Data to be fed to the input/ output devices by interface logic 407 is held in a register (468) and data for the devices entered into a further register (438). Assuming initially that all the channels being controlled are idle when the first input/output command is fetched by the instruction unit, the effective address is fed via bus 426 to the channel unit. State logic 428 recognizes the instruction as a start input/output instruction and waits for the channel information which is circulating through the shift register to arrive in location SCS1 when operation and control logic 429 allows the contents of stage SCS1 to be entered into a staging register (721, Fig. 6, not shown) and stage SCS2 is latched in the operation pending condition. Logic 429 becomes dedicated to the address channel (other sections of the shift register may be dedicated to other channels) and fetches a channel address word into the channel buffer store in the local store 406. Procedure logic locates the address of the first channel command word. If the first command is a transfer of data to main store, logic 432 causes data to be transferred from input/output controller 411 via interface 407 to the local channel store 406. Logic 430 controls the transfer to main store when sufficient data has been received. Operations may be effected with either real or virtual addresses, controlled by command words TL or TVL. When a command TVL is issued (designated by code XX010000 in bits 0-7) bits 8-31 designate the next logical address. The second part of the command word represent a sub-channel translation word STW in which the first 8 bits specify the segment table length in units of 64 bytes, the next 16 bits specify the starting address of the segment table, 2 bits specify the page size and 2 bits specify the segment size. Translation is effected within the storage unit 4 (Fig. 7). The first part of the first channel command word results in the channel number on bus 426 (Fig. 3) being used to address local channel store 406 to cause data on bus 419 to be stored in the channel buffer store. The sub-channel translation word STW is latched into register 326 (Fig. 7). The logical address in the command word is fed on bus 353 to translation adder 327 for addition to the segment field of the word STW. The result on bus 397 is fed to buffer address register 363 to access buffer store 355 to read out the real starting address to register 390, this being then fed to the translation adder together with the page field to derive a further address for buffer 355 which results in a real address being fed to the register 390 for concatenation with the low order bits of the channel command word. The real address is then stored in the channel buffer store of the local channel store 406. Checks are made after each operation to ensure that the fields of the segment and page are not longer than the size of the page table and the segment table. When a TL command is issued designated by code XX100000 in bits 0-7, bits 8-31 specify the real address of the next command. An indirect data addressing facility enables mapping between 24 bit virtual addresses.