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IT1312471B1 - Metodo di verifica in scrittura del valore di soglia nelle memorie non volatili - Google Patents

Metodo di verifica in scrittura del valore di soglia nelle memorie non volatili

Info

Publication number
IT1312471B1
IT1312471B1 IT1999MI001017A ITMI991017A IT1312471B1 IT 1312471 B1 IT1312471 B1 IT 1312471B1 IT 1999MI001017 A IT1999MI001017 A IT 1999MI001017A IT MI991017 A ITMI991017 A IT MI991017A IT 1312471 B1 IT1312471 B1 IT 1312471B1
Authority
IT
Italy
Prior art keywords
verification
writing
threshold value
volatile memories
memories
Prior art date
Application number
IT1999MI001017A
Other languages
English (en)
Inventor
Marco Pasotti
Giovanni Guaitini
Pier Luigi Rolandi
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT1999MI001017A priority Critical patent/IT1312471B1/it
Priority to US09/569,232 priority patent/US6292398B1/en
Publication of ITMI991017A1 publication Critical patent/ITMI991017A1/it
Application granted granted Critical
Publication of IT1312471B1 publication Critical patent/IT1312471B1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G11C2211/5621—Multilevel programming verification

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
IT1999MI001017A 1999-05-11 1999-05-11 Metodo di verifica in scrittura del valore di soglia nelle memorie non volatili IT1312471B1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT1999MI001017A IT1312471B1 (it) 1999-05-11 1999-05-11 Metodo di verifica in scrittura del valore di soglia nelle memorie non volatili
US09/569,232 US6292398B1 (en) 1999-05-11 2000-05-11 Method for the in-writing verification of the threshold value in non-volatile memories

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT1999MI001017A IT1312471B1 (it) 1999-05-11 1999-05-11 Metodo di verifica in scrittura del valore di soglia nelle memorie non volatili

Publications (2)

Publication Number Publication Date
ITMI991017A1 ITMI991017A1 (it) 2000-11-11
IT1312471B1 true IT1312471B1 (it) 2002-04-17

Family

ID=11382931

Family Applications (1)

Application Number Title Priority Date Filing Date
IT1999MI001017A IT1312471B1 (it) 1999-05-11 1999-05-11 Metodo di verifica in scrittura del valore di soglia nelle memorie non volatili

Country Status (2)

Country Link
US (1) US6292398B1 (it)
IT (1) IT1312471B1 (it)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1308857B1 (it) * 1999-10-29 2002-01-11 St Microelectronics Srl Metodo e circuito di lettura per una memoria non volatile.
US6507523B2 (en) * 2000-12-20 2003-01-14 Micron Technology, Inc. Non-volatile memory with power standby
ITMI20011231A1 (it) * 2001-06-12 2002-12-12 St Microelectronics Srl Circuiteria di rilevamento per la lettura e la verifica del contenutodi celle di memoria non volatili programmabili e cancellabili elettric
US6535428B2 (en) * 2001-06-14 2003-03-18 Stmicroelectronics S.R.L. Sensing circuit for memory cells
DE60325453D1 (de) * 2003-02-28 2009-02-05 St Microelectronics Srl System zur Spannungssteuerung für multibit Programmierung eines kompakten nichtflüchtigen Speichers mit reduzierter Integrationsfläche
US6912150B2 (en) * 2003-05-13 2005-06-28 Lionel Portman Reference current generator, and method of programming, adjusting and/or operating same
DE10327284B4 (de) * 2003-06-17 2005-11-03 Infineon Technologies Ag Prüflesevorrichtung für Speicher
ITMI20052350A1 (it) * 2005-12-09 2007-06-10 St Microelectronics Srl Metodo di programmazione di celle di memoria in particolare di tipo flash e relativa architettura di programmazione
US7518934B2 (en) * 2007-03-23 2009-04-14 Intel Corporation Phase change memory with program/verify function
US8023345B2 (en) * 2009-02-24 2011-09-20 International Business Machines Corporation Iteratively writing contents to memory locations using a statistical model
US8166368B2 (en) * 2009-02-24 2012-04-24 International Business Machines Corporation Writing a special symbol to a memory to indicate the absence of a data signal
US8386739B2 (en) * 2009-09-28 2013-02-26 International Business Machines Corporation Writing to memory using shared address buses
US8230276B2 (en) * 2009-09-28 2012-07-24 International Business Machines Corporation Writing to memory using adaptive write techniques
US8463985B2 (en) 2010-03-31 2013-06-11 International Business Machines Corporation Constrained coding to reduce floating gate coupling in non-volatile memories
CN106558345A (zh) * 2015-09-25 2017-04-05 北京兆易创新科技股份有限公司 一种基于电流比较的位扫描方法和系统
CN113284537B (zh) 2020-01-31 2025-01-07 台湾积体电路制造股份有限公司 用于rram单元的混合式自跟踪参考电路
US11495294B2 (en) * 2020-01-31 2022-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid self-tracking reference circuit for RRAM cells

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69524558T2 (de) * 1995-01-27 2002-07-18 Stmicroelectronics S.R.L., Agrate Brianza Schnittweises Annäherungsverfahren zum Abtasten von nichtflüchtigen Mehrfachniveauspeicherzellen und dementsprechende Abtastschaltung
EP0805454A1 (en) * 1996-04-30 1997-11-05 STMicroelectronics S.r.l. Sensing circuit for reading and verifying the content of a memory cell
US5930167A (en) * 1997-07-30 1999-07-27 Sandisk Corporation Multi-state non-volatile flash memory capable of being its own two state write cache

Also Published As

Publication number Publication date
ITMI991017A1 (it) 2000-11-11
US6292398B1 (en) 2001-09-18

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