IE79095B1 - A digital filter production process - Google Patents

Abstract

The invention relates to a digital filter production process to produce cost effective solutions for design requirements. A digital filter design received at step 1 is used to produce a finite precision unit in step 5. Least significant bits of coefficients selected in step 8 are removed in step 9 and the filter is tested in step 10. Leading sign bits associated with coefficients are stripped in step 22 and retested in step 24 to test conformity with the design specification in step 25. Coefficients of the filter are activated in step 33 and a function counter J is iteratively used to shave a desired number of bits before a semiconductor mask Z is produced for implementation in an integrated circuit.

Description

CAMPUS INNOVATION CENTRE, ROEBUCK CASTLE, BELFIELD, DUBLIN 4, IRELAND.

(C) Copyright 1998, Government of Ireland. Ε 960068 A digital filter production process Introduction The present invention relates to a digital filter production process.

A variety of filter production processes are known for producing filters for use in applications where it is necessary to filter sampled digital data. An example of a filter production process is shown in European Patent Application No. EP 0 240 645 A, which describes an automated production technique for bandpass crystal filters. Processes of this type allow for the large scale production of high filters, however they do not address the problems of optimal filter implementation. PCT Patent Application No. Wo 86/07227 discloses a routine for digital filter optimisation. While this aids production of the filter it does not address the issues of word length or component reutilisation critical when implementing the filter on an integrated circuit.

It is also known to use a number of software packages to provide a modelled digital filer implementation with a filter response dictated by a users design specification desired specification. Such models however, take no account of the physical implementation of the filter. This is particularly relevant when producing the digital filters in integrated circuits where the semiconductor area required is critical or where there are limitations relating to power or operating speed.

It is an object of the invention to provide a process for producing a digital filter which overcomes at least some of these problems.

Accordingly there is provided a digital filter production process for producing a finite word length digital filter comprising the steps of:receiving a digital filter design specification and generating an infinite word length filter implementation using an empirical design strategy having a model filter response; ♦ configuring a high end filter test unit in response to a plurality of filter design coefficients produced * by the empirical design strategy and loading a finite precision unit associated with the high end filter test unit; removing a least significant bit from at least one filter design coefficient of the finite test unit; and verifying the functionality of the finite test unit against the received digital filter design specification.

In this way, optimal filters specifications may be produced which require a minimum of semiconductor real estate. The overall cost of the filter is reduced in the same way because of the saving in semiconductor area required. This saving is achieved due to the reduction in word lengths throughout the filter by minimising the use of large components. Production costs are further reduced by tackling design problems early in the developmental cycle.

Preferably the step of removing a least significant bit comprises the iterative steps of:reading a control value from a counter register; isolating a desired filter design coefficient associated with the control value; removing the least significant bit of the isolated « filter design coefficient and generating a test signal by combining a preset test pattern and a preset noise signal; generating a filter response for the digital filter and validating the generated filter response against the model filter response; and storing the control value in response to a validated filter response.

Preferably the step of removing the least significant bit is performed simultaneously for a number of filter design coefficients associated with the control value.

In addition to reducing the area of semiconductor required for the filter this bit reduction ensures that the overall power requirements of filter produced are reduced.

Preferably the process further includes the steps of:isolating a filter design coefficient and analyzing response of each bit of the filter design coefficient in response to an applied test signal to identify leading sign component bits; and removing all lead zero bits associated with the isolated filter design coefficient.

Ideally the step of removing all lead zero bits associated with the isolated filter design coefficient further includes the steps of:generating a test signal by combining a preset test pattern and a preset noise signal, generating a filter response for the digital filter incorporating the filter design coefficient with leading sign bits removed and validating the generated filter response against the model filter response; and adding one least significant bit to the isolated filter design coefficient in response to a not valid condition.

Ideally each filter design coefficient is isolated and stripped of leading sign bits in turn.

Preferably the process includes the steps of:selecting an array of filter design coefficients * associated with the digital filter in response to a received function value; / removing a bit from at least one filter design coefficient of the array, generating a filter response for the digital filter incorporating the array of filter design coefficients using an applied test signal and validating the generated filter response against the model filter response; and storing the function value in response to a validated filter response.

This iterative process allows the re-use of components in the filter by considering the timing details of imposed or fixed components. Thus, the filter can use the shortest possible word lengths throughout while still meeting general timing requirements of the specification.

According to one aspect of the invention there is provided a semiconductor mask whenever produced by the process .

According to another aspect of the invention there is provided a digital filter whenever produced by the process .

Preferably the number of bits removed from the array is iteratively incremented. In this way the use of fast cells or components can be minimised, further reducing the semiconductor area required.

I For the purposes of this specification the term infinite word length is taken to mean both floating point word lengths or excessively large word lengths.

The invention will be more clearly understood from the following description thereof, given by way of example only with reference to the accompanying drawing in which:Fig. 1 is a diagrammatic view of a digital filter production process in accordance with the invention.

Referring to Fig. 1 there is illustrated a digital filter production process according to the invention.

Optimisation of digital systems is critical to producing cost effective solutions to design requirements. As there is a general demand for increased functionality and reduced size in a wide range of devices, designers and producers of the devices must continuously strive to make optimal use of the semiconductor area available. This is particularly relevant in the production of digital filters where large numbers of multipliers are used. Large multipliers required to meet design constraints are inherently slower and require more power than smaller multipliers and the current invention is directed to achieving the required functionality using a minimum of semiconductor real estate.

A digital filter specification is received from a designer at step 1. Digital filters of this type may be used in a wide variety of applications to remove noise components of samples digital data or to prevent transmission of particular sample frequencies.

A software package is used to generate an infinite word length filter implementation in step 2. It will be noted that any one of the number of computer design packages such as MATLAB (as produced by The MathWorks Inc, 24 Prime Park Way, Natick, MA), may be used and that specific details relating to the generation ‘of the infinite word length digital filter have been omitted in order not to unnecessarily obscure an understanding of the present invention. A high end filter test unit is then configured in step 3 using the coefficients generated by the model infinite word length filter produced in step 2.

A test signal is then generated in step 4 by combining a sample test pattern A with a chosen noise signal C. The sample test pattern A may be of any preferred type such * as the test card used to verify the correct operation of a television set and the applied noise signal B may be 4 of any type, for example, a gaussiam noise signal is preferred for video applications however laplacian, uniform or any other suitable noise signal may be used depending on the filter application.

The high end filter test unit configured in step 3 is then limited to produce a finite precision unit in step 5. This finite precision unit prevents the incorporation of infinite word lengths such as those produced in step 2. Precision of the word lengths in the finite precision unit are initially set sufficiently high to allow an exact representation of the digital filter produced in step 2.

The number of coefficients in the finite precision unit of step 5 is noted in step 6 and the number used to set a counter D by a set counter step 7. The set counter step 7 loads the counter D with a factorial of the number of coefficients identified in step 6. A particular coefficient of the finite precision unit of step 5 is selected in step 8 and the contents of the counter D is used to configure the remaining coefficients before the least significant bit of the selected coefficient of step 8 is removed in step 9.

The test signal C produced in step 4 is then used to determine the filter response of the filter with the coefficient settings dictated by the contents of the counter D in step 10. A derived filter response E is compared with a model filter response in step 11 to evaluate the power difference between the derived filter response and the model filter response F to determine the signal to noise ratio degradation of the filter.

The filter is then tested in step 12 to determine if the design specification of step 1 has been compromised and if not compromised, the contents of the counter D are stored as a counter correct entry G in step 13. The counter D is then checked in step 14 to see if a zero value has been reached. If a zero value has not been reached, then the counter B is decremented in step 15. If in step 12, the selected coefficient of step 8 having had the least significant bit removed in step 9, does not pass design specification in step 12 then the existing coefficients are perturbed and the new coefficients are tested for conformity to design requirements using minimum mean square error method. If the filter still does not meet specification then in step 13 the contents of the counter D are stored in G as a test fail and an immediate check is performed in step 14 to determine whether the contents of the counter D have reached zero.

The contents of the counter D decremented in step 15 determine whether the coefficient selected in step 8 should be held at current value for a further iteration of steps 9, 10, 11, 12, 13, 14 and 15 or should be released in step 18.

This is particularly advantageous in that it allows a full test pattern to be achieved in an automatic fashion. Each individual coefficient can be isolated and an array of results stored in G to indicate which is the optimal arrangement of coefficients having the least significant bit removed without reading the design specification.

When the contents of the counter D are determined to be zero in step 14, the optimal values associated with the counter correct G are used to isolate each coefficient in turn in step 20. The test signal C produced in step 4 is then used to monitor the operation of the coefficient isolated in step 20 and all leading sign bits associated with this coefficient are stripped in step 22. The test signal C is then reapplied in step 23 to determine the filter response E associated with the filter having all leading sign bits of the isolated coefficient of step 20 removed. The derived filter response E is then compared against the model filter response F in step 24 to test conformity with the design specification in step 25. If the filter is not in conformity with the design specification, one most significant bit is added to the coefficient isolated in step 20 and the test of steps 23, 24 and 25 reapplied until conformity with the design specification is once again achieved. In step 27, it is identified whether the coefficient isolated in step 20 was the last coefficient and if not, the next coefficient is selected in step 28 to be isolated in step 20. When the last coefficient has been identified in step 27, then the total number of bits associated with the filter is calculated in step 30. This maximum number of bits values is then used to set a function counter J in step 31. The function counter J is initially set with a value zero and incremented in the remaining steps of the process to determine the maximum number of bits which can be shaved from the filter implementation to reduce the surface area of semiconductor required on an integrated circuit. The function counter J is incremented in step 32 and the new value is loaded into the function counter J in step 32. The coefficients of the filter are activated in step 33 and the contents of the function counter J is used to remove the number of bits in the function counter J in step 34. The filter response of the filter having the number of bits contained in the function counter J removed in step 34 is then tested using the test signal C to produce a new derived filter response E in step 35. The functionality of the filter is tested in step 36 by comparing the derived filter response E against the model filter response F in step 36. If the design specification has not been found to be compromised in step 37, then a decision is made in step 39 as to whether further bit reduction is possible. If further bit reduction is possible, the function counter J is again incremented in step 32 and the signal re-tested using the coefficient selected in step 33 and tested in steps 34, 35, 36 and 37. If in step 37, the design specification is found to have been compromised, then a new array is selected in step 33 and this iteration continues until a desired number of bits contained in the function counter J have been successfully shaved. When it is determined in step 39 that the optimum number of bits have been removed, then a semiconductor mask Z is produced for - implementation in an integrated circuit.

' Thus, a greatly cost reduced digital filter is produced which conforms to design requirements. Cost reductions * 5 are achieved by optimum use of multiplier cells, adders, registers, and multiplexers. By using a variety of costing libraries, production cost estimates may be produced at any stage in the design process.

It will be appreciated that the process described for 10 the production of a digital filter above may equally be applied to the production of other types of digital systems. Similarly, it will be noted that the filter response tests described above may be altered to include any or all of frequency, step, ramp or any other suitable test response.

It will also be appreciated that the process may equally be applied to the production of FIR or HR filters.

It will be noted that throughout the process, results note the relative size of the multipliers required in order to balance the digital system produced. This is particularly relevant in that using an overly large multiplier to compensate for bits removed from particular coefficients does not result in semiconductor area savings and further increases the power budget of the final design.

It will also be noted that while exhaustive iterations for bit reduction are described the use of a pseudo random number generator is also envisaged to produce specific test patterns to reduce production times.

It will be appreciated that the techniques described •a above may also be used to reduce internal data paths.

It is envisaged that the order in which the various steps of the process may be altered with bit reduction on multiple coefficients being conducted before attempting bit reduction on coefficient groups.

The minimum mean square error techniques may be used at - any point in the process to determine conformity with the specification and will allow perturbation of individual or groups of coefficients to reduce the number of bits required to implement the design.

The invention is not limited to the embodiments hereinbefore described, which may be varied in both construction and detail.

Claims (10)

CLAIMS Μ

1. A digital filter production process for i producing a finite word length digital filter comprising the steps of:5 receiving a digital filter design specification and generating an infinite word length filter implementation using an empirical design strategy having a model filter response; 10 configuring a high end filter test unit in response to a plurality of filter design coefficients produced by the empirical design strategy and loading a finite precision unit associated with the high end 15 filter test unit; removing a least significant bit from at least one filter design coefficient of the finite test unit; and verifying the functionality of the finite 20 test unit against the received digital filter design specification.

2. A digital filter production process as claimed in claim 1 wherein the step of removing a least 25 significant bit comprises the iterative steps of: reading a control value from a counter register; isolating a desired filter design 30 coefficient associated with the control value; removing the least significant bit of the isolated filter design coefficient and generating a test signal by combining a preset test pattern and a preset noise signal; '' generating a filter response for the 4 digital filter and validating the generated filter response against the model filter response; and storing the control value in response to a validated filter response.

3. A digital filter production process as claimed in claim 2 wherein the step of removing the least significant bit is performed simultaneously for a number of filter design coefficients associated with the control value.

4. A digital filter production process as claimed in any of claims 1 to 3 further including the steps of:isolating a filter design coefficient and analyzing response of each bit of the filter design coefficient in response to an applied test signal to identify leading sign component bits; and removing all lead zero bits associated with the isolated filter design coefficient.

5. A digital filter production process as claimed in claim 4 wherein the step of removing all lead zero bits associated with the isolated filter design coefficient further includes the steps of: - » generating a test signal by combining a f preset test pattern and a preset noise signal, generating a filter response for the digital filter incorporating the filter design coefficient with leading sign bits removed and validating the generated filter response against the model filter response; and adding one most significant bit to the 5 isolated filter design coefficient in response to a not valid condition.

6. A digital filter production process as claimed in claim 4 or claim 5 wherein each filter design coefficient is isolated and stripped of leading 10 sign bits in turn.

7. A digital filter production process as claimed in any preceding claim further including the steps of:selecting an array of filter design 15 coefficients associated with the digital filter in response to a received function value; removing a bit from at least one filter design coefficient of the array, generating 20 a filter response for the digital filter incorporating the array of filter design coefficients using an applied test signal and validating the generated filter response against the model filter response; 25 and storing the function value in response to a validated filter response.

8. A digital filter production process as claimed in claim 7 wherein the number of bits removed 30 from the array is iteratively incremented.

9. A semiconductor mask whenever produced by the process as claimed in any preceding claim.

10. A digital filter whenever produced by the process as claimed in any preceding claim.