GB2466776A

GB2466776A - Bootstrapping to reduce the effect of bond pad parasitic capacitance in a MEMS microphone circuit

Info

Publication number: GB2466776A
Application number: GB0823665A
Authority: GB
Inventors: John Laurence Pennock; Colin Findlay Steele; Goran Stojanovic
Original assignee: Wolfson Microelectronics PLC
Current assignee: Cirrus Logic International UK Ltd
Priority date: 2008-12-30
Filing date: 2008-12-30
Publication date: 2010-07-07
Also published as: GB0823665D0

Abstract

The effect of a parasitic capacitance between a bond pad 126 and the IC substrate is reduced by applying a bootstrapping signal from amplifier 128 to a diffusion region 402 placed under the bond pad. The effective reduction in the parasitic capacitance reduces the attenuation of signals from a capacitive sensor such as a MEMS electret microphone, which may be located on a second IC 100. Bootstrapping may be applied to the parasitic capacitance of the corresponding bond pad on the second IC (122, figures 1 and 10) by use of a similar diffusion region.

Description

APPARATUS AND METHOD RELATING TO A CAPACITIVE TRANSDUCER AND

ASSOCIATED ELECTRONIC CIRCUITRY

Field of the invention

This invention relates to the field of capacitive transducers and associated electronic circuitry, and relates in particular, but not exclusively, to an apparatus and method for compensating for signal loss due to parasitic capacitance.

Background of the invention

Consumer electronics devices are continually getting smaller and, with advances in technology, are gaining ever increasing performance and functionality. This is clearly evident in the technology used in consumer electronic products such as, for example, mobile phones, laptop computers, MP3 players and personal digital assistants (PDAs).

Requirements of the mobile phone industry, for example, are driving components to become smaller with higher functionality and reduced cost. For example, some mobile phones now require multiple microphones for noise cancelling, or accelerometers to allow inertial navigation, while maintaining or reducing the small form factor and aiming at a similar total cost to previous generation phones.

This has encouraged the emergence of miniature transducers. For example, in respect to speech applications, initially electret microphones were used to capture speech, but more recently micro-electrical-mechanical (MEMS) transducers have been introduced.

MEMS transducers may be used in a variety of applications including, but not limited to, pressure sensing, ultrasonic scanning, acceleration monitoring and signal generation. Traditionally such MEMS transducers are capacitive transducers some of which comprise one or more membranes with electrodes for read-out/drive deposited on the membranes and/or a substrate. Relative movement of these electrodes modulates the capacitance between them, which then has to be detected by associated electronic circuitry such as sensitive electronic amplifiers.

Figure 1 illustrates a schematic diagram of a MEMS device 99 comprising a MEMS transducer 100 and an electronic circuit 102.

The MEMS transducer 100 is shown as being formed on a separate integrated circuit to the electronic circuit 102, the two being electrically connected using, for example, bond wires 112, 124. The MEMS transducer 100 comprises a MEMS capacitor CMEMS having first and second plates 118, 120 that are respectively connected to first and second bond pads 114, 122.

The electronic circuit 102 comprises a charge pump 104, a diode 106, a reservoir capacitor (CRes) 108, an amplifier 128, a bias circuit 131, third, fourth, and fifth bond pads 110, 126 and 130, and an optional digital-to-analogue converter (DAC) 132 with an associated sixth bond pad 134.

The following now describes the basic operation of the MEMS device.

The charge pump 104 receives a supply voltage VDD and a first reference voltage VREF1 and outputs an output voltage VDD* (that is greater than the supply voltage VDD). The output voltage VDD* charges up the reservoir capacitor 108, via the diode 106, to a first bias voltage Vb. The reservoir capacitor 108 supplies a relatively stable, i.e. clean, voltage Vb, via the bond pad 110, the bond wire 112 and the bond pad 114, so as to bias the first platel 18 of the MEMS capacitor CMEMS.

The MEMS capacitor CMEMS outputs, via the second bond pad 122, an analogue voltage signal in response to a sound pressure wave.

The amplifier 125 receives, via the bond pad 122, the bond wire 124 and the bond pad 126 the analogue voltage signal from the MEMS capacitor CMEMS, and amplifies the analogue voltage signal. The amplified analogue signal, which may be a current or a voltage depending upon the type of amplifier used, is then output, for further processing, via the fifth bond pad 130. Alternatively, the electronic circuitry 102 may comprise a DAC 132, in which case, the amplified analogue signal is output, via the sixth bond pad 134, as a digital signal. The digital signal may be output instead of, or in addition to, the amplified analogue signal. The amplifier also receives from the bias circuit 131, a second bias voltage VREF2 via a bias impedance (not illustrated). The second bias voltage VREF2 also biases the second plate 120 of the MEMS capacitor CMEMS.

As can be seen in Figure 1, a transducer (CMEMS) can be fabricated on a separate integrated circuit to its associated electronic circuitry. The separate integrated circuits (100, 102) can either be packaged separately, or mounted on a common substrate within the same package. When the transducer and associated electronic circuitry are formed on separate integrated circuits, interconnecting elements such as bond wires (for example bond wires 112, 124), or studs, bumps etc. are used to electrically interconnect the separate integrated circuits 100, 102. It should be noted that a transducer and its associated electronic circuitry can also be fabricated on the same integrated circuit, i.e. a fully integrated solution. The present invention is also applicable and/or adaptable to such fully integrated solutions.

In a circuit arrangement such as that disclosed in Figure 1, parasitic capacitances can have a degrading effect on the analogue voltage signal received from the MEMS transducer CMEMS. For example, a parasitic capacitance associated with the bond pad 122 can contribute to a loss in signal from the MEMS transducer. Likewise, a parasitic capacitance associated with the bond pad 126 can also contribute to a signal loss. As such, the parasitic capacitances attenuate the signals from the MEMS transducer and, as a result, the signals received by the electronic circuitry do not accurately reflect the true MEMS signal.

Summary of the invention

It is an aim of the present invention to provide an apparatus and method for mitigating or reducing the effect of parasitic capacitance.

According to a first aspect of the present invention, there is provided a circuit for compensating for the effect of a parasitic capacitance associated with a signal path in an integrated circuit, the parasitic capacitance having first and second plates, a first plate of the parasitic capacitance being coupled to the signal path. The circuit comprises a correcting circuit configured to couple a correction signal to the second plate of the parasitic capacitance, the correction signal being a replicated version of a signal on the signal path.

According to another aspect of the present invention, there is provided an integrated circuit comprising: a first bond pad coupled, in use, to receive a signal from an associated integrated circuit; a second bond pad coupled, in use, to provide a signal to the associated integrated circuit; a first parasitic capacitance associated with the first bond pad, the first parasitic capacitance having a first plate coupled to the first bond pad; a second parasitic capacitance associated with the second bond pad, the second parasitic capacitance having a first plate coupled to the second bond pad; and wherein the first plate of the first parasitic capacitance is coupled to the second plate of the second parasitic capacitance.

According to a further aspect of the present invention, there is provided a device comprising: a first integrated circuit comprising: a capacitive transducer connected to receive an input signal from a first bond pad and connected to pass an output signal to a second bond pad, the first and second bond pads having respective first and second parasitic capacitances; and a second integrated circuit (102) comprising: electronic circuitry connected to pass an output signal to a third bond pad and connected to receive an input signal from a fourth bond pad, the third and fourth bond pads having respective third and fourth parasitic capacitances; and a correction circuit configured to couple a replicated version of a signal received on the fourth bond pad to a second plate of the fourth parasitic capacitance, the fourth parasitic capacitance having a first plate coupled to the fourth bond pad.

According to another aspect of the present invention, there is provided a method for compensating for the effect of a parasitic capacitance associated with a signal path in an integrated circuit, the parasitic capacitance having first and second plates, the first plate being coupled to the signal path. The method comprises the steps of: coupling a correction signal to the second plate of the parasitic capacitance, the correction signal being a replicated version of a signal on the signal path.

According to another aspect of the present invention, there is provided a method of compensating for the effect of parasitic capacitance in an integrated circuit comprising: a first bond pad coupled, in use, to receive a signal from an associated integrated circuit; a second bond pad coupled, in use, to provide a signal to the associated integrated circuit; wherein a first parasitic capacitance is associated with the first bond pad, the first parasitic capacitance having a first plate coupled to the first bond pad; and wherein a second parasitic capacitance is associated with the second bond pad, the second parasitic capacitance having a first plate coupled to the second bond pad. The method comprises the step of coupling the first plate of the first parasitic capacitance to the second plate of the second parasitic capacitance.

According to another aspect of the present invention, there is provided a method for compensating for the effect of parasitic capacitance in a device comprising: a first integrated circuit comprising: a capacitive transducer connected to receive an input signal from a first bond pad and connected to pass an output signal to a second bond pad, the first and second bond pads having respective first and second parasitic capacitances; and a second integrated circuit comprising: electronic circuitry connected to pass an output signal to a third bond pad and connected to receive an input signal from a fourth bond pad, the third and fourth bond pads having respective third and fourth parasitic capacitances. The method comprises the steps of coupling a replicated version of a signal received on the fourth bond pad to a second plate of the fourth parasitic capacitance, the fourth parasitic capacitance having a first plate coupled to the fourth bond pad.

According to another aspect of the present invention, there is provided a method of forming an integrated circuit having a bond pad coupled to a signal path, the bond pad having an associated parasitic capacitance, the parasitic capacitance having a first plate connected to the bond pad. The method comprises the step of forming a well-region in the integrated circuit near the second plate of the parasitic capacitance, such that an electrical connection can be made to the second plate of the parasitic capacitance.

Brief description of the drawings

For a better understanding of the invention, and to show more clearly how it may be carried into effect, reference will now be made, by way of example only, to the accompanying drawings in which: Figure 1 is a schematic diagram of a MEMS transducer interfaced with electronic circuitry; Figure 2 is a schematic diagram illustrating the parasitic capacitance associated with a bond pad; Figure 3 is a schematic diagram illustrating the parasitic capacitances associated with some of the bond pads of Figure 1; Figures 4 a to 4d show the electrical equivalent diagrams of the parasitic capacitances shown in Figure 3; Figure 5 is a schematic diagram showing a conducting region provided under a bond pad according to a first aspect of the invention; Figure 6a shows a first embodiment of the invention for compensating for the effect of parasitic capacitance; Figure 6b shows the electrical equivalent of Figure 6a; Figure 7 shows a further embodiment of the invention for compensating for the effect of parasitic capacitance; Figure 8 shows an example of a buffer amplifier used in the embodiment of Figure 7; Figure 9 shows a further embodiment of the invention for compensating for the effect of parasitic capacitance; Figure 10 shows a further embodiment of the invention for compensating for the effect of parasitic capacitance; Figure 11 illustrates the equivalent circuit of Figure 10; Figure 1 2a illustrates a cross sectional view of two bond pads that can be used in the embodiment of Figures 10 and 11; Figure 12b illustrates the equivalent circuit of Figure 12a.

Figures 13a and 13b illustrate the effect of bootstrapping the bottom plates of the bond pad parasitic capacitances; and Figure 14 shows examples of bond pad configurations.

Detailed description

The description of the embodiments below will be made in relation to a MEMS device in the form of an analogue/digital microphone. However, it will be appreciated that some or all aspects of the present invention may also be applicable to any other type of high input impedance, or small output signal, transducers such as capacitive MEMS devices and/or capacitive transducers, including non-MEMS type capacitive transducers.

It is also noted that the description of the embodiments will be made in relation to the parasitic capacitance associated with a bond pad. However, it is noted that the invention is equally applicable to any form of parasitic capacitance, including, but not limited to, parasitic capacitances introduced by other nodes in an integrated circuit.

Figure 2 shows a bond pad, for example the bond pad 126 of Figure 1, in further detail.

As will be familiar to a person skilled in the art, generally a bond pad is an area of metal, for example (although not necessarily) square in shape, that is on the one hand electrically connected to a component or connection within an integrated circuit to which the bond pad is attached, and on the other hand enables electrical connection to an external integrated circuit, component or connection (for example via a bond wire 124, as illustrated, that is connected to an exposed surface of the bond pad, or a "flip-chip" arrangement, not illustrated, whereby a metal ball or stud is formed on the bond pad for electrical connection with a similar bond pad mounted on a separate integrated circuit).

A bond pad 126 is typically formed on an oxide or dielectric layer 200, which in turn is formed on a substrate 202, for example a silicon wafer. A passivation layer 206 may be formed on the oxide or dielectric layer 200 and etched away to expose the bond pad 126. The bond pad has an associated parasitic capacitance (illustrated by the capacitor CP). This parasitic capacitance CP exists between the bond pad and the substrate 202 such that it is present in the oxide or dielectric layer 200. A bond wire 124 (for example, gold, aluminium or copper) is shown connected to the bond pad 126 and is used for connecting the bond pad to another component, for example another bond pad (not shown) which, like all bond pads, will also have a respective parasitic capacitance.

Figure 3 illustrates how the parasitic capacitance shown in Figure 2 can affect the analogue voltage signal that is output from the MEMS transducer CMEMS of Figure 1.

For simplicity a number of features shown in Figure 1 have been removed or grouped together in Figure 3 for clarity. As can be seen, a parasitic capacitance CPB1 associated with the bond pad 122 causes a signal loss in the analogue voltage signal received from the MEMS transducer CMEMS. Likewise, a parasitic capacitance CPA1 associated with the bond pad 126 causes a further signal loss in the analogue voltage signal received from the MEMS transducer CMEMS. As such, the voltage signal received by the amplifier 128 from the MEMS transducer 100 is attenuated by the parasitic capacitances associated with the first and second bond pads 122, 126.

Figures 4a to 4d show the circuit equivalent of the parasitic capacitances illustrated in Figure 3. From Figure 4a it can be appreciated that the parasitic capacitances CPB1 and CPA1 of Figure 3 are effectively connected in parallel, such that they add to form a larger capacitance CP = CPB1 + CPA1, as shown in Figure 4b.

Referring to Figures 4c and 4d, the effect of the parasitic capacitances CPB1 and CPA1 on the MEMS signal AVMEMS can be represented as follows, whereby VslG relates to the signal that will be seen by the electronic circuitry after being attenuated by the parasitic capacitances: Al Z14-Z2-1-z3 Al LtV

AV

SIC z3 Z1 Z2 i+1-i AQ= ____ i

LR LMEIIS

AT MEldS AVdE.4s

AISZG--

71 +I-+ L RES L MEMS. r.J %.CRES CM EMS A MEMS capacitive microphone will typically have a capacitance CMEMS of about 1 pF.

Each of the first and second bond pads 122, 126 will typically have a parasitic capacitance CPB1, CPA1 of about 0.1 pF. The reservoir capacitor CRES will typically have a value of 5OpF. If a constant charge Q is applied to the MEMS capacitive microphone such that any movement of a membrane inresponse to sound pressure waves causes the voltage across the MEMS capacitive microphone to change by a small value VMEMS, the parasitic capacitances CPB1 and CPA1Of the bond pads 122, 126 will attenuate the voltage VMEMS such that a smaller signal iVsIG is seen by the electronic circuitry. Using the example values described above, the signal zVsIG seen by the electronic circuitry will be as follows: 0.8 AVMEMS In other words, the MEMS signal LVMEMS is attenuated by nearly 20% due to the parasitic capacitances CPB1 and CPA1, which is clearly undesirable.

According to a first aspect of the present invention, a correcting circuit is provided for mitigating or reducing the effect of parasitic capacitance, for example the parasitic capacitance introduced by a bond pad. According to a first embodiment, a circuit is provided for compensating for the parasitic capacitance introduced by the bond pad 126. In its broadest sense, this aspect of the invention comprises a circuit for compensating for the effect of a parasitic capacitance associated with a signal path in an integrated circuit, the parasitic capacitance having first and second plates, a first plate of the parasitic capacitance being coupled to the signal path. The circuit comprises a correcting circuit configured to couple a correction signal to the second plate of the parasitic capacitance, the correction signal being a replicated version of a signal on the signal path.

Figure 5 shows an example of how a conductive region, for example an n-well 402, can be formed under the bond pad 126 so that access to, the otherwise inaccessible, bottom plate of the parasitic capacitor CPA1 can be achieved. Further details of the n-well can be found in co-pending application P1218GBOO by the present applicant.

G B082 36 75.4 With reference to Figure 5, the n-well 402 (assuming a p-type substrate 202 is being used), is deposited under or near the bond pad 126 to allow access to the bottom plate 403 of the parasitic capacitance OPAl, and hence enable a correction signal to be connected via this parasitic capacitance CPA1 to the signal path. It will be appreciated that if the substrate were an n-type substrate, a p-well would be used.

The bond pad is formed on an oxide or dielectric layer 200, which is formed on a substrate 202, for example a silicon wafer. The previously deposited n-well 402 is formed within the (p-type) substrate 202 under the area where a bond pad is required, such that the upper surface of the n-well 402 and the upper surface of the substrate 202 form a planar surface on which the oxide or dielectric layer 200 is formed. In a CMOS process such an n-well layer 402 will already be present elsewhere on the integrated circuit, to aid the fabrication of PMOS transistors, so addition of the n-well under the site of a required bond pad only requires modification of the mask layout, and not any additional manufacturing steps. The invention is intended also to embrace any other method or process for forming a conductive region such as the n-well 402, as will be familiar to a person skilled in the art, for example using a base or emitter layer in a bipolar or BiCMOS process It is noted that although the embodiments of the invention will be described using an n-well to access the parasitic capacitance, it will be appreciated that other conducting layers or regions can be used for this purpose, including, but not limited to, conducting layers or regions that already exist on the integrated circuit in the vicinity of the parasitic capacitance, for example a metal shielding layer.

Fig. 6a illustrates how the conducting region, for example the n-well 402 described above, is used in conjunction with the amplifier 128 to provide a bootstrap connection for compensating for the effect of the parasitic capacitance in the bond pad 126. In the embodiment shown in Figure 6a the bootstrap connection is provided between the inverting input of the amplifier 128 and the parasitic capacitance CPA1 of the bond pad 126, via the n-well 402 provided near the parasitic capacitance CPA1 of the bond pad 126.

In the embodiment of Figure 6a the non-inverting amplifier 128 has, or substantially has, unity gain. A change in voltage EV seen on the non-inverting input of the amplifier 128 is mirrored on the inverting input. If the parasitic capacitance CPA1 is small then it is possible to provide the bootstrap connection, or correction signal, between the non-inverting input of the amplifier 128 and the n-well 402, i.e. when the parasitic capacitance CPA1 is small the non-inverting input of the amplifier 128 can drive the parasitic capacitance, such that it boosts the voltage on the signal path to compensate for any loss that would otherwise be introduced by the parasitic capacitance.

Alternatively, a correction signal can be coupled from the output of the amplifier (not illustrated). It is noted that the specific choice of correction signal connection can be made according to time constant and loop gain considerations.

Fig. 6b illustrates the ideal circuit equivalent of Figure 6a.

According to an alternative embodiment shown in Figure 7, a buffer amplifier 145 is provided in the path of the correction signal, i.e. bootstrap connection, for example when the non-inverting input of the amplifier 128 in unable to drive the parasitic capacitance CPA1 directly. According to one embodiment the buffer amplifier 145 has, or substantially has, unity gain for driving the bottom plate of the parasitic capacitor CPA1. The buffer amplifier 145 can be provided when the parasitic capacitance CPA1 is relatively large. Although not illustrated, it is noted that the buffer amplifier 145 may also be provided when the bootstrap connection is made between the output of the amplifier 128 and the n-well 402.

Fig. 8 illustrates a detailed example of how the buffer amplifier 145 of Figure 7 may be implemented. Node 147 of the buffer amplifier 145 is connected to the bond pad 126 via the n-well 402. The buffer amplifier 145 comprises a plurality of p-type transistors including a first p-type transistor P1, a second p-type transistor P2, and a third p-type transistor P3. The sources of the first and second p-type transistors P1, P2 are connected to a supply voltage, VDD, and have a common gate connection that is connected to the drain of the first transistor P1. The drain of the first transistor P1 is also connected to ground via a current source IS. The drain of the second p-type transistor P2 is connected to node 147, i.e. the node that is connected to the signal path via the n-well 402, the parasitic capacitance CPA1 and the bond pad 126.

The third p-type transistor P3 has its source connected to the node 147 and its drain connected to ground. The gate of the third p-type transistor P3 is connected to the non-inverting input of the LNA 128. The third p-type transistor acts as an unity gain amplifier, such that any change in voltage tV received from the amplifier 128 (for example its non-inverting input) is reflected by a change in voltage V at the node 147, which in turn is connected to the signal path.

It is noted that other configurations of buffer amplifier 145 may be used without departing from the scope of the present invention. It is also noted that, if the substrate associated with the amplifier 128 were an n-type substrate, a p-well would be used and the bootstrap amplifier 145 would comprise a plurality of n-type transistors.

Furthermore, it is noted that an n/p-type bipolar arrangement of transistors could also be used.

From the above it will be appreciated that the first aspect of the invention provides a correction signal, i.e. bootstrap connection that acts to compensate or mitigate for the effect of the parasitic capacitance of the bond pad 126.

According to another aspect of the present invention, a circuit is provided for compensating or mitigating for the degradation of the signal from the MEMS transducer due to the parasitic capacitance of the bond pad 122, i.e. on the integrated circuit 100 having the transducer.

Figure 9 illustrates the part of the problem when trying to mitigate for the parasitic capacitance associated with the bond pad 122. It will be appreciated that, even when a connection has been made to the bottom plate of CPB1, for example using an n-well region 901, there is still a need to provide a correction signal from the electronic circuit 102 to the bottom plate of CPB1.

Figure 10 illustrates the solution to the problem illustrated in Figure 9. As can be seen, a correction signal (i.e. a replicated version of the signal on the signal path), is coupled for example from the inverting input of the amplifier in the electronic circuit 102. As such, this bootstraps both the bottom plates of the bond pad parasitic capacitances CPA1 and CPB1. Although Figure 10 shows both the parasitic capacitances CPA1 and CPB1 having correction signals coupled thereto, it will be appreciated that the correction signal could be coupled to just the parasitic capacitance CPA1 as shown in Figure 6a, or just the parasitic capacitance CP81. It is noted that the circuit shown in Figure 10 does not provide any compensation for the parasitic capacitances CPA2 and CPB2 associated with bond pads 110 and 114, respectively, as they are not associated with the signal path downstream of the MEMS transducer (i.e. between bond pads 122 and 126). It is noted, however, that the invention could also be applied to the parasitic capacitances associated with these bond pads, if desired.

Figure 11 illustrates the equivalent circuit of Figure 10, and shows the connection of the parasitic capacitances CPA1, CPA2, CP81 and CP82 associated with bond pads 126, 110, 122 and 114, respectively.

Figure 12a illustrates a cross sectional view of two bond pads that can be used as shown in Figures 10 and 11. For example, the first plate (or top plate) of a parasitic capacitance CPAVB2 is connected to a bond pad 110/114, and also connected to the second plate (or bottom plate) of a corresponding parasitic capacitance CPA1/B1, the top plate of which is connected to a bond pad 126/122.

Figure 12b illustrates the equivalent circuit of Figure 12a.

Figures 1 3a and 1 3b illustrate the effect of bootstrapping the bottom plates of the bond pad parasitic capacitances. It can be appreciated that, by bootstrapping the various parasitic capacitances in this manner, the effect of the parasitic capacitances can be effectively eliminated, as represented in Figure 13b. Therefore, the signal from the MEMS transducer is not degraded by the various parasitic capacitances.

According to a further aspect of the invention, the parasitic capacitance CP associated with a bond pad may be further reduced by reducing the area of the bond pad. This may be achieved by altering the shape of the bond pad, as shown in Figure 14. For example, an octagonal, hexagonal or circular bond pad would have a reduced parasitic capacitance compared to a square bond pad.

As mentioned above, although the various embodiments describe a MEMS capacitive microphone, the invention is also applicable to any form of capacitive transducer, including non-MEMS devices, and including transducers other than microphones, for example accelerometers or ultrasonic transmitters/receivers.

It is noted that the embodiments described above may be used in a range of devices, including, but not limited to, analogue microphones, digital microphones, accelerometers or ultrasonic transducers. The invention may also be used in a number of applications, including, but not limited to, consumer applications, medical applications, industrial applications and automotive applications. For example, typical consumer applications include portable audio players, laptops, mobile phones, PDAs and personal computers. Typical medical applications include hearing aids. Typical industrial applications include active noise cancellation. Typical automotive applications include hands-free sets, acoustic crash sensors and active noise cancellation.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim, "a" or "an" does not exclude a plurality, and a single feature or other unit may fulfil the functions of several units recited in the claims. Any reference signs in the claims shall not be construed so as to limit their scope.

Claims

CLAIMS1. A circuit for compensating for the effect of a parasitic capacitance associated with a signal path in an integrated circuit, the parasitic capacitance having first and second plates, a first plate of the parasitic capacitance being coupled to the signal path, the circuit comprising: a correcting circuit configured to couple a correction signal to the second plate of the parasitic capacitance, the correction signal being a replicated version of a signal on the signal path.
2. A circuit as claimed in claim 1, further comprising: a region of n-type or p-type semiconductor material formed in the integrated circuit, wherein the correcting circuit is configured to couple the correction signal to the second plate of the parasitic capacitance using the region of n-type or p-type semiconductor material
3. A circuit as claimed in claim 2, wherein the region of n-type or p-type semiconductor material is provided in a substrate layer of the integrated circuit, adjacent the second plate of the parasitic capacitance.
4. A circuit as claimed in claim 3, wherein the region is doped with a polarity that is opposite to the polarity of the substrate layer.
5. A circuit as claimed in any one of the preceding claims, wherein an amplifier is provided in the signal path, the amplifier comprising: a non-inverting input terminal coupled to receive a signal on the signal path; an output terminal for providing an output signal; and an inverting input terminal coupled to receive a feedback signal from the output terminal; wherein the correction circuit is configured to couple the inverting input terminal of the amplifier with the second plate of the parasitic capacitance.
6. A circuit as claimed in any one of claims 1 to 4, wherein an amplifier is provided in the signal path, the amplifier comprising: a non-inverting input terminal coupled to receive a signal on the signal path; an output terminal for providing an output signal; and an inverting input terminal coupled to receive a feedback signal from the output terminal; wherein the correction circuit is configured to couple the output terminal of the amplifier with the second plate of the parasitic capacitance.
7. A circuit as claimed in claim 5 or 6, wherein the correction circuit further comprises a buffer amplifier connected in the path of the correction signal.
8. A circuit as claimed in claim 7, wherein the buffer amplifier comprises: a first transistor (P1) and a second transistor (P2), the first and second transistors (P1, P2) being configured in a common gate arrangement, and having their respective source terminals connected to a supply voltage; a current source connected between a drain terminal of the first transistor (P1) and ground, the drain of the first transistor (P1) also being connected to the common gate of the first and second transistors (P1, P2); a third transistor (P3) having a source terminal connected to a drain terminal of the second transistor (P2) and the second plate of the parasitic capacitance, the third transistor (P3) further having a drain terminal connected to ground, and a gate terminal coupled to receive the correction signal from the amplifier.
9. A circuit as claimed in any one of the preceding claims, wherein the first plate of the parasitic capacitance is coupled to a first bond pad connected to the signal path.
10. A circuit as claimed in claim 9, wherein a second bond pad is provided on the signal path of the integrated circuit, the second bond pad having a second parasitic capacitance associated therewith, the second parasitic capacitance having a first plate connected to the second bond pad, wherein the circuit further comprises: an electrical connection between the second plate of the first parasitic capacitance and a first plate of the second parasitic capacitance.
11. A circuit as claimed in claim 10, wherein the first bond pad forms part of a signal path arranged, in use, to receive a signal from a capacitive transducer, and wherein the second bond pad forms part of a signal path arranged, in use, to pass a signal to the capacitive transducer.
12. An integrated circuit (102) comprising a circuit as claimed in any one of claims 1 toll.
13. An integrated circuit (100) comprising: a first bond pad (114) coupled, in use, to receive a signal from an associated integrated circuit (102); a second bond pad (122) coupled, in use, to provide a signal to the associated integrated circuit (102); a first parasitic capacitance (CPB2) associated with the first bond pad (114), the first parasitic capacitance having a first plate coupled to the first bond pad; a second parasitic capacitance (CPB1) associated with the second bond pad (122), the second parasitic capacitance having a first plate coupled to the second bond pad; and wherein the first plate of the first parasitic capacitance (CPB2) is coupled to the second plate of the second parasitic capacitance (CPB1).
14. An integrated circuit as claimed in claim 13, further comprising: a region of n-type or p-type semiconductor material formed in the integrated circuit (100) near the second plate of the second parasitic capacitance (CPB1), for enabling an electrical connection to be made to the second plate of the second parasitic capacitance.
15. An integrated circuit as claimed in claim 14, wherein the region of n-type or p-type semiconductor material is provided in a substrate layer of the integrated circuit, adjacent the second plate of the parasitic capacitance.
16. An integrated circuit as claimed in claim 15, wherein the region is doped with a polarity that is opposite to the polarity of the substrate layer.
17. An integrated circuit as claimed in any one of claims 13 to 16, further comprising a capacitive transducer connected to receive an input signal from the first bond pad (114), and connected to pass an output signal to the second bond pad (122).
18. A device (99) comprising: a first integrated circuit (100) comprising: a capacitive transducer (CMEMS) connected to receive an input signal from a first bond pad (114) and connected to pass an output signal to a second bond pad (122), the first and second bond pads having respective first and second parasitic capacitances (CPB2 and CP61); and a second integrated circuit (102) comprising: electronic circuitry connected to pass an output signal to a third bond pad (110) and connected to receive an input signal from a fourth bond pad (126), the third and fourth bond pads having respective third and fourth parasitic capacitances (CPA2 and CPA1); and a correction circuit configured to couple a replicated version of a signal received on the fourth bond pad (126) to a second plate of the fourth parasitic capacitance (OPAl), the fourth parasitic capacitance having a first plate coupled to the fourth bond pad (126).
19. A device as claimed in claim 18, wherein the correction circuit further comprises: a connection between the second plate of the fourth parasitic capacitance (CPA1) and the third bond pad (110).
20. A device as claimed in claim 19, wherein the correction circuit further comprises: a connection between a second plate of the second parasitic capacitance (CP61) and the first bond pad (114), the second parasitic capacitance (0P51) having a first plate connected to the second bond pad (122).
21. A device as claimed in any one of claims 18 to 20, further comprising: a first bond connection (112) for connecting the first bond pad (114) and the third bond pad (110); and a second bond connection (124) for connecting the second bond pad (122) and the fourth bond pad (126).
22. A method for compensating for the effect of a parasitic capacitance associated with a signal path in an integrated circuit, the parasitic capacitance having first and second plates, the first plate being coupled to the signal path, the method comprising the steps of: coupling a correction signal to the second plate of the parasitic capacitance, the correction signal being a replicated version of a signal on the signal path.
23. A method as claimed in claim 22, further comprising the step of coupling the correction signal to the second plate of the parasitic capacitance using a region of the integrated circuit that is electrically isolated from the integrated circuit, but electrically connected to the second plate of the parasitic capacitance.
24. A method as claimed in claim 23, wherein the conducting region is a region of n-type or p-type semiconductor material formed in a layer of the integrated circuit.
25. A method as claimed in claim 24, wherein the conducting region is a well-region of n-type or p-type semiconductor material formed in a substrate layer of the integrated circuit.
26. A method as claimed in any one of claims 22 to 25, wherein an amplifier is provided on the signal path, the amplifier having: a non-inverting terminal for receiving a signal on the signal path; an output terminal for providing an output signal; and an inverting terminal connected to receive a feedback signal from the output terminal; and wherein the step of coupling the correction signal comprises the step of coupling the inverting terminal of the amplifier to the second plate of the parasitic capacitance.
27. A method as claimed in any one of claims 22 to 25, wherein an unity gain amplifier is provided on the signal path, the amplifier having: a non-inverting terminal for receiving a signal on the signal path; an output terminal for providing an output signal; and an inverting terminal connected to receive a feedback signal from the output terminal; and wherein the step of coupling the correction signal comprises the step of coupling the output terminal of the amplifier to the second plate of the parasitic capacitance.
28. A method as claimed in claim 25 or 26, wherein the step of coupling the correction signal further comprises the step of passing the correction signal through a buffer amplifier.
29. A method as claimed in any one of claims 22 to 28, wherein the first plate of the parasitic capacitance is coupled to a first bond pad connected to the signal path.
30. A method as claimed in claim 29, wherein a second bond pad is provided on the signal path of the integrated circuit, the second bond pad having a second parasitic capacitance associated therewith, the second parasitic capacitance having a first plate connected to the second bond pad, wherein the method further comprises the step of: connecting the second plate of the first parasitic capacitance and a first plate of the second parasitic capacitance.
31. A method as claimed in claim 30, wherein the first bond pad forms part of a signal path arranged, in use, to receive a signal from a capacitive transducer, and wherein the second bond pad forms part of a signal path arranged, in use, to pass a signal to the capacitive transducer.
32. A method of compensating for the effect of parasitic capacitance in an integrated circuit (100) comprising: a first bond pad (114) coupled, in use, to receive a signal from an associated integrated circuit (102); a second bond pad (122) coupled, in use, to provide a signal to the associated integrated circuit (102); wherein a first parasitic capacitance (CPB2) is associated with the first bond pad (114), the first parasitic capacitance having a first plate coupled to the first bond pad; and wherein a second parasitic capacitance (CPBI) is associated with the second bond pad (122), the second parasitic capacitance having a first plate coupled to the second bond pad; the method comprising the step of: coupling the first plate of the first parasitic capacitance (CPB2) to the second plate of the second parasitic capacitance (CPB1).
33. A method as claimed in claim 33, further comprising the steps of providing a region of n-type or p-type semiconductor material in the integrated circuit (100) near the second plate of the second parasitic capacitance (CPB1), for enabling an electrical connection to be made to the second plate of the second parasitic capacitance.
34. A method as claimed in claim 33, wherein the step of providing a region of n-type or p-type semiconductor material comprises the step of provided the region of n-type or p-type semiconductor material in a substrate layer of the integrated circuit, adjacent the second plate of the parasitic capacitance.
35. A method as claimed in claim 34, further comprising the step of doped the region with a polarity that is opposite to the polarity of the substrate layer.
36. A method as claimed in any one of claims 33 to 35, further comprising the step of connecting a capacitive transducer to receive an input signal from the first bond pad (114), and connecting the capacitive transducer to pass an output signal to the second bond pad (122).
37. A method for compensating for the effect of parasitic capacitance in a device (99) comprising: a first integrated circuit (100) comprising: a capacitive transducer (CMEMS) connected to receive an input signal from a first bond pad (114) and connected to pass an output signal to a second bond pad (122), the first and second bond pads having respective first and second parasitic capacitances (CPB2 and CPB1); and a second integrated circuit (102) comprising: electronic circuitry connected to pass an output signal to a third bond pad (110) and connected to receive an input signal from a fourth bond pad (126), the third and fourth bond pads having respective third and fourth parasitic capacitances (CPA2 and CPA1); the method comprising the steps of coupling a replicated version of a signal received on the fourth bond pad (126) to a second plate of the fourth parasitic capacitance (CPA1), the fourth parasitic capacitance having a first plate coupled to the fourth bond pad (126).
38. A method as claimed in claim 37, further comprising the step of connecting the second plate of the fourth parasitic capacitance (CPA1) to the third bond pad (110).
39. A method as claimed in claim 38, further comprising the step of connecting a second plate of the second parasitic capacitance (CPB1) to the first bond pad (114), the second parasitic capacitance (CPBI) having a first plate connected to the second bond pad (122).
40. A method as claimed in any one of claims 37 to 39, further comprising the steps of: connecting the first bond pad (114) and the third bond pad (110); and connecting the second bond pad (122) and the fourth bond pad (126).
41. A method of forming an integrated circuit having a bond pad coupled to a signal path, the bond pad having an associated parasitic capacitance, the parasitic capacitance having a first plate connected to the bond pad, the method comprising the step of: forming a well-region in the integrated circuit near the second plate of the parasitic capacitance, such that an electrical connection can be made to the second plate of the parasitic capacitance.
42. A method as claimed in claim 41, wherein the step of forming the well-region comprises the step of forming the well-region in a substrate layer of the integrated circuit.
43. A method as claimed in claim 42, further comprising the step of doping the well-region with a polarity that is opposite to the polarity of the substrate layer.
44. A MEMS device comprising a capacitive transducer and a circuit as claimed in anyoneofclaimsltoll.
45. An ultrasound imager, comprising a MEMS device as claimed in claim 44.
46. A sonar transmitter, comprising a MEMS device as claimed claim 44.
47. A sonar receiver, comprising a MEMS device as claimed in claim 44.
48. A mobile phone, comprising a MEMS device as claimed in claim 44.
49. A personal desktop assistant, comprising a MEMS device as claimed in claim 44.
50. An MP3 player, comprising a MEMS device as claimed in claim 44.
51. A laptop, comprising a MEMS device as claimed in claim 44.