CN111786638A

CN111786638A - Signal link parasitic optimization system

Info

Publication number: CN111786638A
Application number: CN202010577695.5A
Authority: CN
Inventors: 王永; 吴巍
Original assignee: Nanjing Yudu Communication Technology Co ltd
Current assignee: Nanjing Yudu Communication Technology Co ltd
Priority date: 2020-06-23
Filing date: 2020-06-23
Publication date: 2020-10-16

Abstract

The invention discloses a signal link parasitic optimization system, which comprises an integrated circuit and is characterized in that: the integrated circuit comprises an analog circuit and a radio frequency circuit, wherein the analog circuit and the radio frequency circuit both comprise a signal amplifier, the analog circuit and the radio frequency circuit are both provided with a direct current offset calibration circuit connected with the signal amplifier, the direct current offset calibration circuit is provided with a current source, in a circuit needing to be introduced with current calibration, an optimizer is connected between the current source and the circuit in series, and the optimizer comprises a mos switch and a resistor. Through the added series switch or transmission switch and resistor, the parasitic capacitance introduced by the current source due to large size is well shielded, the optimization workload of the circuit designer in the later simulation is greatly reduced, and the additional large parasitic capacitance added to the signal link working normally due to the introduction of direct current calibration current is also avoided, so that the frequency domain characteristic of the signal link is ensured.

Description

Signal link parasitic optimization system

Technical Field

The invention relates to the technical field of signal links, in particular to a signal link parasitic optimization system.

Background

In the design of an integrated circuit, an analog circuit and a radio frequency circuit are included, a signal amplifier is an unavoidable circuit architecture, in a radio frequency receiving link, direct current offset causes link function errors, so that a direct current offset calibration circuit is indispensable, but a direct current offset technology of current compensation introduces parasitic capacitance for reducing noise and influences signal bandwidth, in the design of a high-speed high-gain amplifier, the parasitic capacitance of a rear-end layout often greatly limits the bandwidth of the amplifier, the signal bandwidth and the gain are consideration factors which must be compromised, in the design of an analog radio frequency integrated circuit chip, a layout engineer designs a layout according to a circuit of a circuit engineer, the rear-end layout work is realized through one-to-one comparison of tools, but parasitic resistance and capacitance are inevitably introduced into the layout, so that the rear-end design work is not completely consistent with the simulation of a front-end circuit, an excellent circuit designer can consider performance influence caused by parasitic capacitance resistance in circuit design, so that design margin is reserved, however, the circuit design time is inevitably increased, on the other hand, inexperienced layout engineers can introduce the parasitic capacitance resistance beyond the estimation of the circuit designer into the design, and after the post-simulation confirmation, the layout must be modified, so that the design period is also increased.

Disclosure of Invention

The present invention is directed to a system for optimizing signal link parasitics, which solves the above-mentioned problems of the prior art.

In order to achieve the above purpose, the invention provides the following technical scheme: the utility model provides a parasitic optimization system of signal link, includes integrated circuit, integrated circuit includes analog circuit and radio frequency circuit, all include signal amplifier in analog circuit and the radio frequency circuit, just all be provided with the DC offset calibration circuit in analog circuit and the radio frequency circuit and be connected with signal amplifier, the DC offset calibration circuit is provided with the current source, in the circuit that needs to introduce the current calibration, series connection optimizer between current source and circuit, the optimizer includes mos switch and resistance, just one of them between mos switch and the resistance is only selected for use to the optimizer.

Preferably, the mos switch is a small-size mos switch.

Preferably, the resistor is a small-sized resistor.

Preferably, the current source of the direct current offset calibration circuit is provided by a large-size MOS tube.

Preferably, the signal amplifier is a folded cascode amplifier.

Preferably, the optimizer is located in the folded position of the folded cascode amplifier.

In the technical scheme, the invention provides the following technical effects and advantages:

the invention well shields the parasitic capacitance of the current source due to large size by adding the series switch or the transmission switch and the resistor, so that the time of an engineer for optimizing the layout is reduced in the layout design, the optimization workload of the circuit designer for post simulation is also greatly reduced, and meanwhile, the technology also avoids adding extra large parasitic capacitance to the normally working signal link due to the introduction of direct current calibration current, thereby ensuring the frequency domain characteristic of the signal link.

Drawings

In order to more clearly illustrate the embodiments of the present application or technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present invention, and other drawings can be obtained by those skilled in the art according to the drawings.

FIG. 1 is a block diagram of the overall structure of the present invention

FIG. 2 is a circuit diagram of DC offset calibration for a switch isolation parasitic capacitor according to the present invention.

FIG. 3 is a circuit diagram of an operational amplifier using switched isolation parasitic capacitors according to the present invention.

FIG. 4 is a diagram of a DC offset calibration circuit for an electrical isolation from parasitic capacitance in accordance with the present invention.

FIG. 5 is a circuit diagram of an operational amplifier using resistors to isolate parasitic capacitances according to the present invention.

Detailed Description

In order to make the technical solutions of the present invention better understood, those skilled in the art will now describe the present invention in further detail with reference to the accompanying drawings.

The invention provides a signal link parasitic optimization system as shown in fig. 1-5, which comprises an integrated circuit, wherein the integrated circuit comprises an analog circuit and a radio frequency circuit, the analog circuit and the radio frequency circuit both comprise signal amplifiers, the analog circuit and the radio frequency circuit are both provided with direct current offset calibration circuits connected with the signal amplifiers, the direct current offset calibration circuits are provided with current sources, in the circuit needing to introduce current calibration, optimizers are connected in series between the current sources and the circuit, the optimizers comprise mos switches and resistors, and the optimizers only select one of the mos switches and the resistors;

further, in the above technical solution, the mos switch is a small-sized mos switch;

further, in the above technical solution, the resistor is a small-sized resistor;

further, in the above technical solution, the current source of the dc offset calibration circuit is provided by a large-sized MOS transistor;

further, in the above technical solution, the signal amplifier is a folded cascode amplifier;

further, in the above technical solution, the optimizer is located at a folded position of the folded cascode amplifier;

the implementation mode is specifically as follows: referring to fig. 1 and fig. 2 (the differential circuit is simplified into a single-end circuit), a general application of the capacitance parasitic parameter optimization technology is described, fig. 1 and fig. 3, a current source Ip is provided by a large-sized MOS transistor, the parasitic capacitance is large, the effect of the current Ip can change the common mode point of an amplifying circuit, the circuit is typically applied as a direct current calibration circuit of a programmable amplifier or an active R3 filter, the direct current mismatch of the circuit is calibrated by providing the current Ip, so that the circuit can operate at a proper operating point, referring to fig. 2 and fig. 4, the simplified form of the folded cascode amplifier, the high gain and the high bandwidth are two performance indexes which are always pursued by the amplifier, there is often a compromise relationship between the two, the size of the high bandwidth device cannot be too large, and the high gain requires a large device size to increase the on-resistance, the Vx point in fig. 2 is generally the third pole of the two-stage folded operational amplifier, the existence of the layout parasitic capacitor enables the stability of the operational amplifier to be reduced, the bandwidth to be reduced, the difficulty of layout design is greatly increased, the post simulation verification time of a circuit designer is influenced by repeatedly adjusting the layout, the two capacitor series circuits in the figures 2 and 4 utilize the principle that capacitor series connection is equivalent to circuit parallel connection, the value of the two capacitor series circuits is determined by a small series capacitance value, and the influence of the parasitic parameter of the circuit in the layout design is weakened due to the fact that the two capacitor series circuits are just the factor.

While certain exemplary embodiments of the present invention have been described above by way of illustration only, it will be apparent to those of ordinary skill in the art that the described embodiments may be modified in various different ways without departing from the spirit and scope of the invention. Accordingly, the drawings and description are illustrative in nature and should not be construed as limiting the scope of the invention.

Claims

1. A signal link parasitic optimization system comprising an integrated circuit, characterized in that: the integrated circuit comprises an analog circuit and a radio frequency circuit, wherein the analog circuit and the radio frequency circuit both comprise a signal amplifier, the analog circuit and the radio frequency circuit are both provided with a direct current offset calibration circuit connected with the signal amplifier, the direct current offset calibration circuit is provided with a current source, in a circuit needing to be introduced with current calibration, an optimizer is connected between the current source and the circuit in series, the optimizer comprises a mos switch and a resistor, and the optimizer only selects one of the mos switch and the resistor.

2. The system of claim 1, wherein the signal link parasitic optimization system comprises: and the mos switch is a small-size mos switch.

3. The system of claim 1, wherein the signal link parasitic optimization system comprises: and the resistor is a small-size resistor.

4. The system of claim 1, wherein the signal link parasitic optimization system comprises: the current source of the direct current offset calibration circuit is provided by a large-size MOS tube.

5. The system of claim 1, wherein the signal link parasitic optimization system comprises: the signal amplifier is a folding cascode amplifier.

6. The system of claim 5, wherein the signal link parasitic optimization system comprises: the optimizer is located in the folded position of the folded cascode amplifier.