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GB2448276A - Distributive scoreboard scheduling in an out-of-order processor - Google Patents

Distributive scoreboard scheduling in an out-of-order processor

Info

Publication number
GB2448276A
GB2448276A GB0814234A GB0814234A GB2448276A GB 2448276 A GB2448276 A GB 2448276A GB 0814234 A GB0814234 A GB 0814234A GB 0814234 A GB0814234 A GB 0814234A GB 2448276 A GB2448276 A GB 2448276A
Authority
GB
United Kingdom
Prior art keywords
instruction
distributive
scoreboard
operand availability
availability bits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB0814234A
Other versions
GB0814234D0 (en
GB2448276B (en
Inventor
Xing Yu Jiang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MIPS Tech LLC
Original Assignee
MIPS Technologies Inc
MIPS Tech LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MIPS Technologies Inc, MIPS Tech LLC filed Critical MIPS Technologies Inc
Publication of GB0814234D0 publication Critical patent/GB0814234D0/en
Publication of GB2448276A publication Critical patent/GB2448276A/en
Application granted granted Critical
Publication of GB2448276B publication Critical patent/GB2448276B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

A processor core and a method for distributive Scoreboard scheduling in an out-of-order processor pipeline. In an embodiment, control logic appends operand availability bits to each instruction. The appended operand availability bits form a distributive Scoreboard for each instruction. The appended operand availability bits are propagated together with the instruction through multiple stages of the processor pipeline. An instruction dispatch buffer stores the instruction and the operand availability bits. A dispatch controller determines when an instruction is to be issued. The determination is based, at least in part, on the operand availability bits stored in the instruction dispatch buffer.
GB0814234A 2006-02-28 2007-02-12 Distributive scoreboard scheduling in an out-of-order processor Expired - Fee Related GB2448276B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/362,764 US7721071B2 (en) 2006-02-28 2006-02-28 System and method for propagating operand availability prediction bits with instructions through a pipeline in an out-of-order processor
PCT/US2007/003752 WO2007100487A2 (en) 2006-02-28 2007-02-12 Distributive scoreboard scheduling in an out-of-order processor

Publications (3)

Publication Number Publication Date
GB0814234D0 GB0814234D0 (en) 2008-09-10
GB2448276A true GB2448276A (en) 2008-10-08
GB2448276B GB2448276B (en) 2011-06-15

Family

ID=38265592

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0814234A Expired - Fee Related GB2448276B (en) 2006-02-28 2007-02-12 Distributive scoreboard scheduling in an out-of-order processor

Country Status (4)

Country Link
US (1) US7721071B2 (en)
CN (1) CN101395573B (en)
GB (1) GB2448276B (en)
WO (1) WO2007100487A2 (en)

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Publication number Publication date
CN101395573A (en) 2009-03-25
WO2007100487A3 (en) 2007-11-22
GB0814234D0 (en) 2008-09-10
WO2007100487A2 (en) 2007-09-07
US7721071B2 (en) 2010-05-18
CN101395573B (en) 2012-06-06
GB2448276B (en) 2011-06-15
US20070204135A1 (en) 2007-08-30

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