CN111506347B - Renaming method based on instruction read-after-write related hypothesis - Google Patents

Abstract

The invention discloses a renaming method based on related assumptions of instruction writing and reading, and relates to the technical field of computer microelectronic chips. The invention comprises two stages: stage 1: completing the reading of the RAT and judging the related attribute of the register; based on various instruction read-after-write related assumptions, obtaining a plurality of rename register maps of each source register, and simultaneously generating an onehot control signal for selecting a correct rename register in parallel; stage 2: the final renaming register of each source register is selected according to onehot control signals generated in the 1 st stage, and the mapping relation between the architecture register and the physical register of the RAT table is updated. Under the same condition, the invention can obtain higher main frequency; renaming is carried out by an assumed method, so that the implementation complexity of renaming is reduced, the bandwidth performance of renaming is improved, and a better method is provided for realizing a high-performance processor.

Description

Renaming method based on instruction read-after-write related hypothesis

Technical Field

The invention belongs to the technical field of computer microelectronic chips, and particularly relates to a renaming method based on related assumptions of instruction writing and reading.

Background

The development of microprocessors has made tremendous progress in the short decades. The performance of processors is continually improved from a hardware architecture, process and software-hardware combination. Hardware architecture experiences from single-shot scalar to multiple-shot superscalar; from the initial 3-stage pipeline to several tens of stage pipelines; from sequential execution instructions to out-of-order execution instructions; from no cache to a 3-level cache storage structure; from physical single core to physical Multi-Core (CMP), and logical single core to logical Multi-core (SMT), simultaneous Multi-Threading); even for clustered systems for super operations, instruction-level parallel and thread-level parallel execution of processors has evolved tremendously. Instruction level parallel bandwidth requirements of single-core microprocessors are increasingly higher, and logic complexity range multiples of chip implementation are increased.

As the number of instructions processed per clock cycle increases, the combinational logic chain becomes longer and longer according to the comparison and judgment of the read-after-write priorities of the instructions, and therefore the main frequency of the microprocessor is greatly limited. The method gives a method for renaming 8 instructions per clock cycle, and the implementation method of the method is not limited to the case that the bandwidth is 8 instructions, including all other bandwidths. The method is simultaneously applicable to all processor architectures such as an X86 instruction set CPU, a RISC instruction set CPU, a GPU, a DSP and the like, and is applicable to physical single cores, physical multi-Cores (CMP) and logical multi-cores (SMT).

Currently, the number of source and destination registers at the time of renaming of multiple instructions is limited. For example, the pipeline bandwidth is 6 instructions, but when the decoder schedules instructions to rename, it is limited that the 5 th and 6 th instructions do not need to read or write physical registers, otherwise, the current instruction cannot enter renaming, and can be renamed only in the next cycle. That is, by limiting the number of renamed instructions per clock cycle, the complexity of instruction dependency checking at the renaming stage is reduced.

Instructions that cannot enter renaming for the current cycle are blocked. In this case, the renaming stage pipeline performance is degraded by 1/6 or 1/3. Since the bandwidth of renaming becomes a bottleneck, not only the pipeline after renaming is affected but also the inclusion of decoders and previous modules is blocked. It is therefore important to address the above issues to provide a renaming method based on the assumption of read-after-instruction-write.

Disclosure of Invention

The invention provides a renaming method based on a related assumption of instruction writing and reading, which solves the problems that the renaming instruction bandwidth is limited and the performance is influenced in each clock period.

In order to solve the technical problems, the invention is realized by the following technical scheme:

The invention discloses a renaming method based on an instruction read-after-write related hypothesis, which comprises two stages:

stage 1: completing the reading of the RAT and judging the related attribute of the register; based on various instruction read-after-write related assumptions, obtaining a plurality of rename register maps of each source register, and simultaneously generating an onehot control signal for selecting a correct rename register in parallel;

stage 2: selecting a final renaming register of each source register according to the onehot control signal generated in the 1 st stage, and updating the mapping relation between the architecture register and the physical register of the RAT table;

the number of serial logic gates generated by comparing the read-after-write of 8 instructions according to the priority is reduced by generating a plurality of renaming register results and selecting signals of final effective results on the assumption of parallelism, so that higher main frequency is obtained under the same condition;

the method is to obtain a plurality of renaming results by assuming various read-after-write correlations of the instruction, and then obtain a final result by selecting signals.

Furthermore, the method does not need to directly judge the read-after-write correlation among the instructions, so that the problem of long path of combinational logic caused by the priority relation among the instructions is solved, and the assumption is not limited to 1 instruction as granularity, and is applicable to any instruction granularity.

Further, the multiple renaming register maps of each source register are obtained in the 1 st stage and are implemented by adopting a logic expression for judging renaming of each UOP, wherein the logic expression comprises various assumed logic expression implementation forms of each instruction.

Furthermore, the invention is applicable to all processor architectures such as an X86 instruction set CPU, a RISC instruction set CPU, a GPU, a DSP and the like, is applicable to physical single cores, physical multi-Cores (CMP) and logical multi-cores (SMT), and is applicable to servers and clusters.

Further, the invention is not limited to instruction level parallel bandwidth, but is not limited to renaming implemented architecture, pipeline stages, and implemented processes.

Compared with the prior art, the invention has the following beneficial effects:

the invention adopts renaming stage as 2 stages: stage 1, completing reading RAT and judging register related attribute; and the 2 nd stage obtains the final renaming result and the mapping relation between the architecture register and the physical register of the RAT after finishing updating. Based on various instruction read-after-write related assumptions, obtaining a plurality of rename register maps of each source register in a stage 1, and simultaneously generating an onehot control signal for selecting a correct rename register in parallel; selecting a final renaming register of each source register according to the onehot control signal generated in the stage 1 in the stage 2, and updating the mapping relation between the architecture register and the physical register of the RAT table; the serial logic gate number generated by comparing the read-after-instruction with the priority is reduced by generating a plurality of renaming register results and selecting signals of final effective results in parallel, and higher main frequency can be obtained under the same condition; renaming is carried out by an assumed method, so that the implementation complexity of renaming is reduced, the bandwidth performance of renaming is improved, and a better method is provided for realizing a high-performance processor.

Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a diagram of a multi-core CPU with N physical cores sharing L3 and memory according to an embodiment of the present invention;

FIG. 2 is a single physical core in an embodiment of the invention;

FIG. 3 illustrates a pipeline of a microprocessor in accordance with an embodiment of the present invention;

FIG. 4 is a renaming architecture in which a physical register is shared between the architecture registers and the renaming registers according to the present invention;

FIG. 5 is a diagram of information that the 8 UOP pieces of an embodiment of the invention need to examine during the renaming stage;

FIG. 6 is a diagram of a renaming process for describing the i and i+1th cycles UOP through a time axis and a space axis according to an embodiment of the present invention;

in the drawings, the list of components represented by the various numbers is as follows:

10-multicore CPU, 20-renaming module location in microprocessor, 31-renaming stage 1, 32-renaming stage 2, 41-architecture register and internal temporary register index number supported by microprocessor instruction set, 42-whether the architecture register or internal temporary register is renamed, 43-effective data width of each physical register, 44-address mapping relationship of architecture register and internal temporary register mapping to physical register, 45-representing R2 mapping to physical register 5 and data width 256bit,46-R3 mapping to physical register K-6 and data width 16bit,47-RM-4 mapping to physical register 14 and data width 64bit, 48-architecture register and internal temporary register supported by microprocessor instruction set and renaming shared physical register, 501-8 UOP numbers and the order of 8 UOP numbers is UOP0, UOP1, UOP2, UOP3, UOP4, UOP5, UOP6, UOP7, 502-UOP whether there is a 2 nd source register, 503-UOP numbers 1 st source register and default to 0, 504-1 st source register width if there is no source register, 505-UOP whether there is a 2 nd source register, 506-UOP numbers 2 nd source register, 507-2 nd source register width, 508-UOP whether there is a destination register, 509-UOP numbers destination register and default to 0, 510-destination register width if there is no source register, the renaming of the 8 UOP of the 61-i cycle is completed through 2 stages, the 2 nd stage and the 1 st stage of the 8 UOP of the i+1 cycle are the same cycle, the renaming of the 8 UOP of the 62-i+1 cycle is completed through 2 stages, and the 1 st stage and the 2 nd stage of the 8 UOP of the i cycle are the same cycle.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Referring to fig. 1-6, a renaming method based on the assumption of related instruction writing and reading in the present invention includes 2 renaming stages: stage 1, completing reading RAT and judging register related attribute; and the 2 nd stage obtains the final renaming result and the mapping relation between the architecture register and the physical register of the updated RAT table. Based on various instruction read-after-write related assumptions, obtaining a plurality of rename register maps of each source register in a stage 1, and simultaneously generating an onehot control signal for selecting a correct rename register in parallel; the final renaming register of each source register is selected in the 2 nd stage according to onehot control signals generated in the 1 st stage, and the mapping relation between the architecture register and the physical register of the RAT table is updated.

The method comprises the steps of renaming the stages into 2 stages: stage 1, completing reading RAT and judging register related attribute; and the 2 nd stage obtains the final renaming result and the mapping relation between the architecture register and the physical register of the updated RAT table.

Based on various instruction read-after-write related assumptions, obtaining a plurality of rename register maps of each source register in a stage 1, and simultaneously generating an onehot control signal for selecting a correct rename register in parallel;

the final renaming register of each source register is selected in the 2 nd stage according to onehot control signals generated in the 1 st stage, and the mapping relation between the architecture register and the physical register of the RAT table is updated.

By assuming parallel generation of multiple renaming register results and selecting the final valid result, the number of serial logic gates generated by 8 instructions after writing and reading according to priority comparison is reduced, so that higher main frequency can be obtained under the same condition.

Thus, the present approach implements a method that reduces the logic complexity of implementing high bandwidth renaming.

In FIG. 1, there is a multi-core CPU with N physical cores sharing L3 and memory, each of which may be a single-threaded or multi-threaded architecture. Each core is suitable for all instruction sets, architectures and processes.

In fig. 2, there is a single physical core, which may be a single threaded or multi-threaded architecture. The modular division of the core is given in table 1 as a functional description. The location of the renaming module in the microprocessor is indicated at 20 in figure 2.

Table 1: list of functions for single physical core

FIG. 3 shows a pipeline of a microprocessor, where 31 is renamed stage 1 and 32 is renamed stage 2.

FIG. 4 is a renaming architecture in which architecture registers share a block of physical registers with renaming registers. Reference numeral 41 denotes a retrieval number of an architecture register and an internal temporary register supported by the microprocessor instruction set. 42 indicates whether the architectural register or internal temporary register is renamed. 43 is a table representing the effective data width of each physical register supporting 8bit,16bit,32bit,48bit,64bit,80bit,128bit,256bit. By extending the WIDTH of the WIDTH field, any data WIDTH can be supported. 44 represents the address mapping of the architectural registers and internal temporary registers to physical registers. The physical register has an address width of Q, and Q satisfies 2 ^Q >=k. 45 denotes that R2 is mapped to physical register 5 and the data width is 256 bits. 46 denotes that R3 maps to the physical register K-6 and the data width is 16 bits. 47 denotes RM-4 is mapped to physical register 14 and has a data width of 64 bits. 48 denote architectural registers and internal temporary registers supported by the microprocessor instruction set and renaming shared physical registers.

In fig. 5 are 8 pieces of information that the UOP needs to check during the renaming stage. 501 denotes the number of 8 UOPs, and the order of 8 UOPs is UOP0, UOP1, UOP2, UOP3, UOP4, UOP5, UOP6, UOP 7. 502 indicates whether the UOP has a 1 st source register. 503 denotes that UOP has the 1 st source register number, and defaults to 0 if no source register is present. 504 denotes the width of the 1 st source register. 505 indicates whether UOP has a 2 nd source register. 506 indicates that UOP has the number of the 2 nd source register, and defaults to 0 if no source register is present. 507 denotes the width of the 2 nd source register. 508 indicates whether the UOP exists in the destination register. 509 indicates the number of UOP present destination register, and if no source register is present, it defaults to 0. 510 represents the width of the destination register.

Fig. 6 depicts the renaming procedure of the i and i+1 cycles UOP by the time axis and the space axis. 61 indicates that the 8 UOPs of the i-th cycle complete renaming through 2 stages, and the 2 nd stage is the same cycle as the 1 st stage of the 8 UOPs of the i+1-th cycle. 62 indicates that the 8 UOPs of the i+1th cycle complete renaming through 2 stages, and the 1 st stage is the same cycle as the 2 nd stage of the 8 UOPs of the i cycle. When the 8 UOPs in the (i+1) -th cycle read the RAT in the (1) -th stage, the numbers of the RATs written in the (2) -th stage by the 8 UOPs in the (i) -th cycle need to be compared, and the latest physical register number of each source register is obtained.

The renaming module has a processing bandwidth of 8 UOPs, each UOP having at most 2 source operands and 1 destination operand. The number of registers of the UOP is determined based on the valid bit. In fig. 5, the information of 8 UOPs, each UOP includes an architectural register number, a valid bit, and an architectural register width of 2 source operands and 1 destination operand. The method is not limited to the case of only 2 source registers per UOP, but can be extended to any number of source registers and destination registers.

In the renaming process, the source operand of each instruction obtains the physical register number corresponding to the architecture register; the destination register applies for the free physical register number and updates the RAT.

The renaming is completed in 2 stages: stage 1, completing reading RAT and judging register related attribute; and the 2 nd stage obtains the final renaming result and the mapping relation between the architecture register and the physical register of the updated RAT table. In stage 1, 8 UOPs access the RATs simultaneously in parallel and complete the register correlation determination. The (i+1) th cycle, 8 UOPs read the RAT table simultaneously, while at most there are UOPs writing RATs for the (i) th cycle, as shown in fig. 6. The correlation judgment of 8 UOPs is shown below.

At most 8 UOP (universal serial bus) updating RATs are arranged in each clock period, the UOP of the ith clock period and the UOP of the (i+1) clock period are coincident, so that in the period of reading the RAT, whether the destination register of the updating RAT of the last clock period is the same or not is required to be compared, and the correct physical register number is selected according to the priority relation. The ith cycle instructs phase 1 to generate an update RAT onehot select signal PRV _i [7:0]This signal is the value of the query RAT that selects the most recent RAT information as the source operand. Onehot select signal PRV for the i-th cycle instruction phase 2 _i _1D[7:0]。PRV _i _1D[7:0]When the i+1st cycle instructs the 1 st stage rename, the physical register number of the RAT is selected to be updated.

PRV _i [7]Indicating that the 8 th UOP7 needs to update RAT. PRV (PRV) _i [7]The logical expression of (2) is as follows:

PRV _i [7]＝VAL_7_2 _i

PRV _i [6]indicating that 7 th UOP6 needs to update RAT and that UOP7 and UOP6 do not have RAT updating the same architectural register. PRV (PRV) _i [6]The logical expression of (2) is as follows:

PRV _i [6]＝VAL_6_2 _i &

(～(VAL_6_2 _i &VAL_7_2 _i &(R_7_2 _i ＝＝R_6_2 _i )))

PRV _i [5]indicating that the 6 th UOP5 needs to update RAT and UOP7, UOP6 and UOP5 do not have RAT updating the same architectural register. PRV (PRV) _i [5]The logical expression of (2) is as follows:

PRV _i [5]＝VAL_5_2 _i &

(～(VAL_5_2 _i &VAL_7_2 _i &(R_7_2 _i ＝＝R_5_2 _i )))&

(～(VAL_5_2 _i &VAL_6_2 _i &(R_6_2 _i ＝＝R_5_2 _i )))

PRV _i [4]indicating that the 5 th UOP4 needs to update RAT, and UOP7, UOP6,UOP5 and UOP4 do not have a RAT that updates the same architectural registers. PRV (PRV) _i [4]The logical expression of (2) is as follows:

PRV _i [4]＝VAL_4_2 _i &

(～(VAL_4_2 _i &VAL_7_2 _i &(R_7_2 _i ＝＝R_4_2 _i )))&

(～(VAL_4_2 _i &VAL_6_2 _i &(R_6_2 _i ＝＝R_4_2 _i )))&

(～(VAL_4_2 _i &VAL_5_2 _i &(R_5_2 _i ＝＝R_4_2 _i )))

PRV _i [3]indicating that the 4 th UOP3 needs to update RAT and UOP7, UOP6, UOP5, UOP4 and UOP3 do not have RAT updating the same architectural register. PRV (PRV) _i [3]The logical expression of (2) is as follows:

PRV _i [3]＝VAL_3_2 _i &

(～(VAL_3_2 _i &VAL_7_2 _i &(R_7_2 _i ＝＝R_3_2 _i )))&

(～(VAL_3_2 _i &VAL_6_2 _i &(R_6_2 _i ＝＝R_3_2 _i )))&

(～(VAL_3_2 _i &VAL_5_2 _i &(R_5_2 _i ＝＝R_3_2 _i )))&

(～(VAL_3_2 _i &VAL_4_2 _i &(R_4_2 _i ＝＝R_3_2 _i )))

PRV _i [2]indicating that item 3 UOP2 needs to update RATs and UOP7, UOP6, UOP5, UOP4, UOP3 and UOP2 do not have RATs updating the same architectural registers. PRV (PRV) _i [2]The logical expression of (2) is as follows:

PRV _i [2]＝VAL_2_2 _i &

(～(VAL_2_2 _i &VAL_7_2 _i &(R_7_2 _i ＝＝R_2_2 _i )))&

(～(VAL_2_2 _i &VAL_6_2 _i &(R_6_2 _i ＝＝R_2_2 _i )))&

(～(VAL_2_2 _i &VAL_5_2 _i &(R_5_2 _i ＝＝R_2_2 _i )))&

(～(VAL_2_2 _i &VAL_4_2 _i &(R_4_2 _i ＝＝R_2_2 _i )))&

(～(VAL_2_2 _i &VAL_3_2 _i &(R_3_2 _i ＝＝R_2_2 _i )))

PRV _i [1]indicating that item 2 UOP1 needs to update RAT and UOP7, UOP6, UOP5, UOP4, UOP3, UOP2 and UOP1 do not have RAT updating the same architectural register. PRV (PRV) _i [1]The logical expression of (2) is as follows:

PRV _i [1]＝VAL_1_2 _i &

(～(VAL_1_2 _i &VAL_7_2 _i &(R_7_2 _i ＝＝R_1_2 _i )))&

(～(VAL_1_2 _i &VAL_6_2 _i &(R_6_2 _i ＝＝R_1_2 _i )))&

(～(VAL_1_2 _i &VAL_5_2 _i &(R_5_2 _i ＝＝R_1_2 _i )))&

(～(VAL_1_2 _i &VAL_4_2 _i &(R_4_2 _i ＝＝R_1_2 _i )))&

(～(VAL_1_2 _i &VAL_3_2 _i &(R_3_2 _i ＝＝R_1_2 _i )))&

(～(VAL_1_2 _i &VAL_2_2 _i &(R_2_2 _i ＝＝R_1_2 _i )))

PRV _i [0]indicating that item 1 UOP0 needs to update RATs and UOP7, UOP6, UOP5, UOP4, UOP3, UOP2, UOP1 and UOP0 do not have RATs updating the same architectural registers. PRV (PRV) _i [0]The logical expression of (2) is as follows:

PRV _i [0]＝VAL_0_2 _i &

(～(VAL_0_2 _i &VAL_7_2 _i &(R_7_2 _i ＝＝R_0_2 _i )))&

(～(VAL_0_2 _i &VAL_6_2 _i &(R_6_2 _i ＝＝R_0_2 _i )))&

(～(VAL_0_2 _i &VAL_5_2 _i &(R_5_2 _i ＝＝R_0_2 _i )))&

(～(VAL_0_2 _i &VAL_4_2 _i &(R_4_2 _i ＝＝R_0_2 _i )))&

(～(VAL_0_2 _i &VAL_3_2 _i &(R_3_2 _i ＝＝R_0_2 _i )))&

(～(VAL_0_2 _i &VAL_2_2 _i &(R_2_2 _i ＝＝R_0_2 _i )))&

(～(VAL_0_2 _i &VAL_1_2 _i &(R_1_2 _i ＝＝R_0_2 _i )))

PRV _i 1D is PRV _i The contents of the next stage pipeline of the signal are as follows:

PRV _i _1D<＝PRV _i

updating of RAT, also according to PRV _i 1D determines whether an entry of the RAT needs to be written, if so, updates the new physical register number to the corresponding architectural register row, otherwise, remains unchanged. Phy_w_0_2 _i _1D，PHY_W_1_2 _i _1D，PHY_W_2_2 _i _1D，PHY_W_3_2 _i _1D，PHY_W_4_2 _i _1D，PHY_W_5_2 _i _1D，PHY_W_6_2 _i _1D，PHY_W_7_2 _i 1D is the value of the destination register width at renaming stage 2. The logical expression is as follows:

PHY_W_0_2 _i _1D<＝W_0_2 _i

PHY_W_1_2 _i _1D<＝W_1_2 _i

PHY_W_2_2 _i _1D<＝W_2_2 _i

PHY_W_3_2 _i _1D<＝W_3_2 _i

PHY_W_4_2 _i _1D<＝W_4_2 _i

PHY_W_5_2 _i _1D<＝W_5_2 _i

PHY_W_6_2 _i _1D<＝W_6_2 _i

PHY_W_7_2 _i _1D<＝W_7_2 _i

similarly, PHY_R_0_2 _i _1D，PHY_R_1_2 _i _1D，PHY_R_2_2 _i _1D，PHY_R_3_2 _i _1D，PHY_R_4_2 _i _1D，PHY_R_5_2 _i _1D，PHY_R_6_2 _i _1D，PHY_R_7_2 _i 1D is the value of the physical register of the destination register at renaming stage 2.

The logical expression for the RAT table row 1 architecture register R0 update is:

RAT[R0]<＝({(Q+3){(PRV _i _1D[0]&(R_0_2 _i _1D＝＝R0))}}&{PHY_W_0_2 _i _1D,PHY_R_0_2 _i _1D})|

({(Q+3){(PRV _i _1D[1]&(R_1_2 _i _1D＝＝R0))}}&{PHY_W_1_2 _i _1D,PHY_R_1_2 _i _1D})|

({(Q+3){(PRV _i _1D[2]&(R_2_2 _i _1D＝＝R0))}}&{PHY_W_2_2 _i _1D,PHY_R_2_2 _i _1D})|

({(Q+3){(PRV _i _1D[3]&(R_3_2 _i _1D＝＝R0))}}&{PHY_W_3_2 _i _1D,PHY_R_3_2 _i _1D})|

({(Q+3){(PRV _i _1D[4]&(R_4_2 _i _1D＝＝R0))}}&{PHY_W_4_2 _i _1D,PHY_R_4_2 _i _1D})|

({(Q+3){(PRV _i _1D[5]&(R_5_2 _i _1D＝＝R0))}}&{PHY_W_5_2 _i _1D,PHY_R_5_2 _i _1D})|

({(Q+3){(PRV _i _1D[6]&(R_6_2 _i _1D＝＝R0))}}&{PHY_W_6_2 _i _1D,PHY_R_6_2 _i _1D})|

({(Q+3){(PRV _i _1D[7]&(R_7_2 _i _1D＝＝R0))}}&{PHY_W_7_2 _i _1D,PHY_R_7_2 _i _1D})

r1, R2, R3, … … RM-1 may have similar logical expressions which are not given here. Updating the logical expression of the RAT does not include resetting and the occurrence of a recovery logic for the branch instruction to occur in the event of an execution error or event.

1.1UOP0 renaming procedure

The 2 source operands of UOP0 need only query the RAT table according to the architectural register number of each source operand. Such as architecture register r_0_0 _i+1 The look-up-RAT table may represent RAT [ R_0_0 ] _i+1 ]And so on. The renaming is completed in 2 stages: the 1 st stage mainly completes the mapping from the architecture register to the physical register by using 2 source operands of the (i+1) -th cycle UOP, and the mapping needs to consider the 2 nd stage write RAT corresponding to the instruction of the i-th cycle at the same time. The (i+1) -th instruction stage 1 and the (i) -th instruction stage 2 are in the same pipeline.

The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

the logical expression of the 1 st source operand is as follows:

PHY_R_0_0 _i+1 ＝({Q{(PRV _i _1D[0]&(R_0_0 _i+1 ＝＝R_0_2 _i _1D))}}&PHY_R_0_2 _i _1D)|

({Q{(PRV _i _1D[1]&(R_0_0 _i+1 ＝＝R_1_2 _i _1D))}}&PHY_R_1_2 _i _1D)|

({Q{(PRV _i _1D[2]&(R_0_0 _i+1 ＝＝R_2_2 _i _1D))}}&PHY_R_2_2 _i _1D)|

({Q{(PRV _i _1D[3]&(R_0_0 _i+1 ＝＝R_3_2 _i _1D))}}&PHY_R_3_2 _i _1D)|

({Q{(PRV _i _1D[4]&(R_0_0 _i+1 ＝＝R_4_2 _i _1D))}}&PHY_R_4_2 _i _1D)|

({Q{(PRV _i _1D[5]&(R_0_0 _i+1 ＝＝R_5_2 _i _1D))}}&PHY_R_5_2 _i _1D)|

({Q{(PRV _i _1D[6]&(R_0_0 _i+1 ＝＝R_6_2 _i _1D))}}&PHY_R_6_2 _i _1D)|

({Q{(PRV _i _1D[7]&(R_0_0 _i+1 ＝＝R_7_2 _i _1D))}}&PHY_R_7_2 _i _1D)|

({Q{(～(|PRV _i _1D))}}&RAT[R_0_0 _i+1 ][Q-1:0])

PHY_VAL_0_0 _i+1 ＝VAL_0_0 _i+1

similarly, the logical expression of the 2 nd source operand is as follows:

PHY_R_0_1 _i+1 ＝({Q{(PRV _i _1D[0]&(R_0_1 _i+1 ＝＝R_0_2 _i _1D))}}&PHY_R_0_2 _i _1D)|

({Q{(PRV _i _1D[1]&(R_0_1 _i+1 ＝＝R_1_2 _i _1D))}}&PHY_R_1_2 _i _1D)|

({Q{(PRV _i _1D[2]&(R_0_1 _i+1 ＝＝R_2_2 _i _1D))}}&PHY_R_2_2 _i _1D)|

({Q{(PRV _i _1D[3]&(R_0_1 _i+1 ＝＝R_3_2 _i _1D))}}&PHY_R_3_2 _i _1D)|

({Q{(PRV _i _1D[4]&(R_0_1 _i+1 ＝＝R_4_2 _i _1D))}}&PHY_R_4_2 _i _1D)|

({Q{(PRV _i _1D[5]&(R_0_1 _i+1 ＝＝R_5_2 _i _1D))}}&PHY_R_5_2 _i _1D)|

({Q{(PRV _i _1D[6]&(R_0_1 _i+1 ＝＝R_6_2 _i _1D))}}&PHY_R_6_2 _i _1D)|

({Q{(PRV _i _1D[7]&(R_0_1 _i+1 ＝＝R_7_2 _i _1D))}}&PHY_R_7_2 _i _1D)|

({Q{(～(|PRV _i _1D))}}&RAT[R_0_1 _i+1 ][Q-1:0])

PHY_VAL_0_1 _i+1 ＝VAL_0_1 _i+1

The physical register allocated by the destination register of UOP0 is phy_r_0_2 _i+1 . The effective expression of the physical register allocated by the destination register is as follows:

PHY_VAL_0_2 _i+1 ＝VAL_0_2 _i+1

the i+1th cycle instruction phase 2 source operands and destination architecture registers map to physical register calculation process:

the logical expression of the 1 st source operand is as follows:

PHY_R_0_0 _i+1 _1D<＝PHY_R_0_0 _i+1

PHY_VAL_0_0 _i+1 _1D<＝PHY_VAL_0_0 _i+1

the logical expression of the 2 nd source operand is as follows:

PHY_R_0_1 _i+1 _1D<＝PHY_R_0_1 _i+1

PHY_VAL_0_1 _i+1 _1D<＝PHY_VAL_0_1 _i+1

the logical expression of the destination register is as follows:

PHY_R_0_2 _i+1 _1D<＝PHY_R_0_2 _i+1

PHY_VAL_0_2 _i+1 _1D<＝PHY_VAL_0_2 _i+1

R_0_2 _i _1D<＝R_0_2 _i

1.2UOP1 renaming procedure

The 2 source operands of UOP1 query the RAT table according to the architecture register number of each source operand, and it is also required to determine whether the architecture register numbers of the 2 source operands of UOP1 are the same as the architecture number of the destination register of UOP0, i.e. it is required to determine r_1_0 _i+1 And R_1_1 _i+1 Whether or not to be equal to R_0_2 _i+1 The same applies. If the architectural register number of the 2 source operands of UOP1 is the same as the architectural number of the destination register of UOP0, then the physical register mapped by the architectural register number of the 2 source operands of UOP1 is the physical register corresponding to the destination register of UOP 0.

The method is based on an assumption that the architecture register numbers of 2 source operands of the UOP1 and the architecture numbers of the destination registers of the UOP0 are the same and the architecture numbers of 2 source operands of the UOP1 are mapped to physical registers for parallel execution, and the serial execution process of logic and mapping logic which are firstly judged whether to be the same is executed in parallel. In stage 2, the correct result is selected according to the selection logic generated in parallel in stage 1.

1.2.1 assume that UOP1 is not related to UOP0 in the absence of RAW

When UOP1 and UOP0 are not related to RAW, the mapping procedure of UOP1 is similar to that of UOP 0.

The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

logical expression PHY_R_1_0 of 1 st source operand _i+1 A is as follows:

PHY_R_1_0 _i+1 _A＝({Q{(PRV _i _1D[0]&(R_1_0 _i+1 ＝＝R_0_2 _i _1D))}}&PHY_R_0_2 _i _1D)|

({Q{(PRV _i _1D[1]&(R_1_0 _i+1 ＝＝R_1_2 _i _1D))}}&PHY_R_1_2 _i _1D)|

({Q{(PRV _i _1D[2]&(R_1_0 _i+1 ＝＝R_2_2 _i _1D))}}&PHY_R_2_2 _i _1D)|

({Q{(PRV _i _1D[3]&(R_1_0 _i+1 ＝＝R_3_2 _i _1D))}}&PHY_R_3_2 _i _1D)|

({Q{(PRV _i _1D[4]&(R_1_0 _i+1 ＝＝R_4_2 _i _1D))}}&PHY_R_4_2 _i _1D)|

({Q{(PRV _i _1D[5]&(R_1_0 _i+1 ＝＝R_5_2 _i _1D))}}&PHY_R_5_2 _i _1D)|

({Q{(PRV _i _1D[6]&(R_1_0 _i+1 ＝＝R_6_2 _i _1D))}}&PHY_R_6_2 _i _1D)|

({Q{(PRV _i _1D[7]&(R_1_0 _i+1 ＝＝R_7_2 _i _1D))}}&PHY_R_7_2 _i _1D)|

({Q{(～(|PRV _i _1D))}}&RAT[R_1_0 _i+1 ][Q-1:0])

PHY_VAL_1_0 _i+1 ＝VAL_1_0 _i+1

similarly, the logical expression PHY_R_1_1 of the 2 nd source operand _i+1 A is as follows:

PHY_R_1_1 _i+1 _A＝({Q{(PRV _i _1D[0]&(R_1_1 _i+1 ＝＝R_0_2 _i _1D))}}&PHY_R_0_2 _i _1D)|

({Q{(PRV _i _1D[1]&(R_1_1 _i+1 ＝＝R_1_2 _i _1D))}}&PHY_R_1_2 _i _1D)|

({Q{(PRV _i _1D[2]&(R_1_1 _i+1 ＝＝R_2_2 _i _1D))}}&PHY_R_2_2 _i _1D)|

({Q{(PRV _i _1D[3]&(R_1_1 _i+1 ＝＝R_3_2 _i _1D))}}&PHY_R_3_2 _i _1D)|

({Q{(PRV _i _1D[4]&(R_1_1 _i+1 ＝＝R_4_2 _i _1D))}}&PHY_R_4_2 _i _1D)|

({Q{(PRV _i _1D[5]&(R_1_1 _i+1 ＝＝R_5_2 _i _1D))}}&PHY_R_5_2 _i _1D)|

({Q{(PRV _i _1D[6]&(R_1_1 _i+1 ＝＝R_6_2 _i _1D))}}&PHY_R_6_2 _i _1D)|

({Q{(PRV _i _1D[7]&(R_1_1 _i+1 ＝＝R_7_2 _i _1D))}}&PHY_R_7_2 _i _1D)|

({Q{(～(|PRV _i _1D))}}&RAT[R_1_1 _i+1 ][Q-1:0])

PHY_VAL_1_1 _i+1 ＝VAL_1_1 _i+1

the physical register allocated by the destination register of UOP1 is phy_r_1_2 _i+1 . The effective expression of the physical register allocated by the destination register is as follows:

PHY_VAL_1_2 _i+1 ＝VAL_1_2 _i+1

1.2.2 assume that UOP1 and UOP0 are RAW related

When UOP1 and UOP0 have a RAW correlation, i.e., the destination register of UOP0 is the same as the meta register architectural register number of UOP 1. The physical register number of the UOP1 source register is the physical register number newly allocated to the UOP0 destination register.

The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

logical expression PHY_R_1_0 of 1 st source operand _i+1 B is as follows:

PHY_R_1_0 _i+1 _B＝PHY_R_0_2 _i+1

similarly, the logical expression PHY_R_1_1 of the 2 nd source operand _i+1 B is as follows:

PHY_R_1_1 _i+1 _B＝PHY_R_0_2 _i+1

the valid identification of the source register is the same as that for UOP1 and UOP0, where no correlation exists.

1.2.3 determining UOP1 and UOP0 to have RAW-related logic

Judging whether the UOP1 and the UOP0 are related by RAW or not, and only comparing whether the source register number of the UOP1 is the same as the destination register number of the UOP0, wherein the 2 source register judgment logic expressions are as follows:

CMP_R_1_0 _i+1 ＝((R_1_0 _i+1 ＝＝R_0_2 _i+1 )&VAL_1_0&VAL_0_2)

CMP_R_1_1 _i+1 ＝((R_1_1 _i+1 ＝＝R_0_2 _i+1 )&VAL_1_1&VAL_0_2)

the i+1th cycle instruction phase 2 source operands and destination architecture registers map to physical register calculation process:

PHY_R_1_0 _i+1 _A_1D<＝PHY_R_1_0 _i+1 _A

PHY_R_1_0 _i+1 _B_1D<＝PHY_R_1_0 _i+1 _B

PHY_R_1_1 _i+1 _A_1D<＝PHY_R_1_1 _i+1 _A

PHY_R_1_1 _i+1 _B_1D<＝PHY_R_1_1 _i+1 _B

CMP_R_1_0 _i+1 _1D<＝CMP_R_1_0 _i+1

CMP_R_1_1 _i+1 _1D<＝CMP_R_1_1 _i+1

the final physical register PHY_R_1_0 of the 1 st source operand _i+1 1D, the correct physical register is selected according to the selection logic.

PHY_R_1_0 _i+1 _1D＝({Q{(～CMP_R_1_0 _i+1 _1D)}}&PHY_R_1_0 _i+1 _A_1D)|

({Q{CMP_R_1_0 _i+1 _1D}}&PHY_R_1_0 _i+1 _B_1D)

Physical register PHY_R_1_1 of the 2 nd source operand final _i+1 1D, the correct physical register is selected according to the selection logic.

PHY_R_1_1 _i+1 _1D＝({Q{(～CMP_R_1_1 _i+1 _1D)}}&PHY_R_1_1 _i+1 _A_1D)|

({Q{CMP_R_1_1 _i+1 _1D}}&PHY_R_1_1 _i+1 _B_1D)

PHY_VAL_1_0 _i+1 _1D<＝PHY_VAL_1_0 _i+1

PHY_VAL_1_1 _i+1 _1D<＝PHY_VAL_1_1 _i+1

The logical expression of the destination register is as follows:

PHY_R_1_2 _i+1 _1D<＝PHY_R_1_2 _i+1

PHY_VAL_1_2 _i+1 _1D<＝PHY_VAL_1_2 _i+1

R_1_2 _i _1D<＝R_1_2 _i

1.3UOP2 renaming procedure

The 2 source operands of UOP2 query the RAT table according to the architecture register number of each source operand, and it is also necessary to determine whether the architecture register numbers of the 2 source operands of UOP2 are the same as those of the destination registers of UOP1 and UOP0, i.e. it is necessary to determine r_2_0 _i+1 And R_2_1 _i+1 Whether or not to be equal to R_1_2 _i+1 Or R_0_2 _i+1 The same applies. If the architectural register number of the 2 source operands of UOP2 is the same as the architectural number of the destination register of UOP1 or UOP0, then the physical register mapped by the architectural register number of the 2 source operands of UOP2 is the physical register corresponding to the destination register of UOP1 or UOP 0. If a certain source register of UOP2 is related to the simultaneous existence of RAW for UOP1 and UOP0, the physical register of the source register of UOP2 takes the physical register number corresponding to the destination register of UOP1 according to the priority order.

The source register number of UOP2 falls into 3 cases: 1, assuming UOP2 is related to UOP1 and UOP0 without RAW; 2, assuming that UOP2 is associated with UOP0 with a RAW, and UOP2 is associated with UOP1 with no RAW; 3, suppose UOP2 is related to UOP1 that there is a RAW. 3 physical registers of each source register are obtained in the renaming stage 1, and simultaneously correlations of UOP2, UOP1 and UOP0 are judged in parallel; the correct result is selected from the 3 physical register numbers of each source register according to the dependency logic in stage 2 of renaming.

1.3.1 assume that UOP2 is related to UOP1 and UOP0 in the absence of RAW

When UOP2 is associated with UOP1 and UOP0 without a RAW, the mapping procedure of UOP2 is similar to that of UOP 0. The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

logical expression PHY_R_2_0 of 1 st source operand _i+1 A is as follows:

PHY_R_2_0 _i+1 _A＝({Q{(PRV _i _1D[0]&(R_2_0 _i+1 ＝＝R_0_2 _i _1D))}}&PHY_R_0_2 _i _1D)|

({Q{(PRV _i _1D[1]&(R_2_0 _i+1 ＝＝R_1_2 _i _1D))}}&PHY_R_1_2 _i _1D)|

({Q{(PRV _i _1D[2]&(R_2_0 _i+1 ＝＝R_2_2 _i _1D))}}&PHY_R_2_2 _i _1D)|

({Q{(PRV _i _1D[3]&(R_2_0 _i+1 ＝＝R_3_2 _i _1D))}}&PHY_R_3_2 _i _1D)|

({Q{(PRV _i _1D[4]&(R_2_0 _i+1 ＝＝R_4_2 _i _1D))}}&PHY_R_4_2 _i _1D)|

({Q{(PRV _i _1D[5]&(R_2_0 _i+1 ＝＝R_5_2 _i _1D))}}&PHY_R_5_2 _i _1D)|

({Q{(PRV _i _1D[6]&(R_2_0 _i+1 ＝＝R_6_2 _i _1D))}}&PHY_R_6_2 _i _1D)|

({Q{(PRV _i _1D[7]&(R_2_0 _i+1 ＝＝R_7_2 _i _1D))}}&PHY_R_7_2 _i _1D)|

({Q{(～(|PRV _i _1D))}}&RAT[R_2_0 _i+1 ][Q-1:0])

PHY_VAL_2_0 _i+1 ＝VAL_2_0 _i+1

similarly, the logical expression PHY_R_2_1 of the 2 nd source operand _i+1 A is as follows:

PHY_R_2_1 _i+1 _A＝({Q{(PRV _i _1D[0]&(R_2_1 _i+1 ＝＝R_0_2 _i _1D))}}&PHY_R_0_2 _i _1D)|

({Q{(PRV _i _1D[1]&(R_2_1 _i+1 ＝＝R_1_2 _i _1D))}}&PHY_R_1_2 _i _1D)|

({Q{(PRV _i _1D[2]&(R_2_1 _i+1 ＝＝R_2_2 _i _1D))}}&PHY_R_2_2 _i _1D)|

({Q{(PRV _i _1D[3]&(R_2_1 _i+1 ＝＝R_3_2 _i _1D))}}&PHY_R_3_2 _i _1D)|

({Q{(PRV _i _1D[4]&(R_2_1 _i+1 ＝＝R_4_2 _i _1D))}}&PHY_R_4_2 _i _1D)|

({Q{(PRV _i _1D[5]&(R_2_1 _i+1 ＝＝R_5_2 _i _1D))}}&PHY_R_5_2 _i _1D)|

({Q{(PRV _i _1D[6]&(R_2_1 _i+1 ＝＝R_6_2 _i _1D))}}&PHY_R_6_2 _i _1D)|

({Q{(PRV _i _1D[7]&(R_2_1 _i+1 ＝＝R_7_2 _i _1D))}}&PHY_R_7_2 _i _1D)|

({Q{(～(|PRV _i _1D))}}&RAT[R_2_1 _i+1 ][Q-1:0])

PHY_VAL_2_0 _i+1 ＝VAL_2_0 _i+1

the physical register allocated by the destination register of UOP2 is phy_r_2_2 _i+1 . The effective expression of the physical register allocated by the destination register is as follows:

PHY_VAL_2_2 _i+1 ＝VAL_2_2 _i+1

1.3.2 assume that UOP2 is related to UOP0 with no RAW, and UOP2 is related to UOP1 with no RAW

When UOP2 is associated with UOP0 with no RAW, i.e., UOP 0's destination register is the same as UOP 2's meta register architectural register number and not the same as UOP 1's destination register number. The physical register number of the UOP2 source register is the physical register number newly allocated to the UOP0 destination register.

The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

logical expression PHY_R_2_0 of 1 st source operand _i+1 B is as follows:

PHY_R_2_0 _i+1 _B＝PHY_R_0_2 _i+1

similarly, the logical expression PHY_R_1_1 of the 2 nd source operand _i+1 B is as follows:

PHY_R_2_1 _i+1 _B＝PHY_R_0_2 _i+1

the valid identification of the source register is the same as that for UOP2 and UOP0, where no correlation exists.

1.3.3 suppose UOP2 and UOP1 have a RAW correlation

When UOP2 and UOP1 are associated with a RAW, i.e., the destination register of UOP1 is the same as the meta register architectural register number of UOP 2. The physical register number of the UOP2 source register is the physical register number newly allocated to the UOP1 destination register.

The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

logical expression PHY_R_2_0 of 1 st source operand _i+1 C is as follows:

PHY_R_2_0 _i+1 _C＝PHY_R_1_2 _i+1

similarly, the logical expression PHY_R_2_1 of the 2 nd source operand _i+1 C is as follows:

PHY_R_2_1 _i+1 _C＝PHY_R_1_2 _i+1

the valid identification of the source register is the same as that for UOP2 and UOP0, where no correlation exists.

1.3.4 determining UOP2 and UOP1 and UOP0 to have RAW-related logic

Judging whether UOP2 is related to UOP0 in the presence of RAW and is related to UOP1 in the absence of RAW, only comparing whether the source register number of UOP2 is identical to the destination register number of UOP0 or not, and judging whether the source register number of UOP2 is identical to the destination register number of UOP1 or not, wherein the 2 source register judgment logic expressions are as follows:

selection logic CMP_R_2_0 of 1 st source operand _i+1 [1:0]The logical expression is as follows:

CMP_R_2_0 _i+1 [0]＝((R_2_0 _i+1 ＝＝R_0_2 _i+1 )&VAL_2_0&VAL_0_2)&

(～((R_2_0 _i+1 ＝＝R_1_2 _i+1 )&VAL_2_0&VAL_1_2))

CMP_R_2_0 _i+1 [1]＝((R_2_0 _i+1 ＝＝R_1_2 _i+1 )&VAL_2_0&VAL_1_2)

selection logic CMP_R_2_1 of 2 nd source operand _i+1 [1:0]The logical expression is as follows:

CMP_R_2_1 _i+1 [0]＝((R_2_1 _i+1 ＝＝R_0_2 _i+1 )&VAL_2_1&VAL_0_2)&

(～((R_2_1 _i+1 ＝＝R_1_2 _i+1 )&VAL_2_1&VAL_1_2))

CMP_R_2_1 _i+1 [1]＝((R_2_1 _i+1 ＝＝R_1_2 _i+1 )&VAL_2_1&VAL_1_2)

the i+1th cycle instruction phase 2 source operands and destination architecture registers map to physical register calculation process:

PHY_R_2_0 _i+1 _A_1D<＝PHY_R_2_0 _i+1 _A

PHY_R_2_0 _i+1 _B_1D<＝PHY_R_2_0 _i+1 _B

PHY_R_2_0 _i+1 _C_1D<＝PHY_R_2_0 _i+1 _C

PHY_R_2_1 _i+1 _A_1D<＝PHY_R_2_1 _i+1 _A

PHY_R_2_1 _i+1 _B_1D<＝PHY_R_2_1 _i+1 _B

PHY_R_2_1 _i+1 _C_1D<＝PHY_R_2_1 _i+1 _C

CMP_R_2_0 _i+1 _1D<＝CMP_R_2_0 _i+1

CMP_R_2_1 _i+1 _1D<＝CMP_R_2_1 _i+1

the final physical register PHY_R_2_0 of the 1 st source operand _i+1 1D, the correct physical register is selected according to the selection logic.

PHY_R_2_0 _i+1 _1D＝({Q{(～(|CMP_R_2_0 _i+1 _1D))}}&PHY_R_2_0 _i+1 _A_1D)|

({Q{CMP_R_2_0 _i+1 _1D[0]}}&PHY_R_2_0 _i+1 _B_1D)|

({Q{CMP_R_2_0 _i+1 _1D[1]}}&PHY_R_2_0 _i+1 _C_1D)

Physical register PHY_R_1_1 of the 2 nd source operand final _i+1 1D, the correct physical register is selected according to the selection logic.

PHY_R_2_1 _i+1 _1D＝({Q{(～(|CMP_R_2_1 _i+1 _1D))}}&PHY_R_2_1 _i+1 _A_1D)|

({Q{CMP_R_2_1 _i+1 _1D[0]}}&PHY_R_2_1 _i+1 _B_1D)|

({Q{CMP_R_2_1 _i+1 _1D[1]}}&PHY_R_2_1 _i+1 _C_1D)

PHY_VAL_2_0 _i+1 _1D<＝PHY_VAL_2_0 _i+1

PHY_VAL_2_1 _i+1 _1D<＝PHY_VAL_2_1 _i+1

The logical expression of the destination register is as follows:

PHY_R_2_2 _i+1 _1D<＝PHY_R_2_2 _i+1

PHY_VAL_2_2 _i+1 _1D<＝PHY_VAL_2_2 _i+1

R_2_2 _i _1D<＝R_2_2 _i

1.4UOP3 renaming procedure

The 2 source operands of UOP3 query the RAT table according to the architectural register number of each source operand, and it is also necessary to determine the architectural register numbers and the architectural register numbers of the 2 source operands of UOP3 Whether the architecture numbers of the destination registers of UOP2, UOP1 and UOP0 are the same or not, i.e. R_3_0 needs to be judged _i+1 And R_3_1 _i+1 Whether or not to be equal to R_2_2 _i+1 ，R_1_2 _i+1 Or R_0_2 _i+1 The same applies. If the architectural register number of the 2 source operands of UOP3 is the same as the architectural number of the destination registers of UOP2, UOP1 or UOP0, then the physical register mapped by the architectural register number of the 2 source operands of UOP3 is the physical register corresponding to the destination register of UOP2, UOP1 or UOP 0. If a certain source register of UOP3 is related to UOP2, UOP1 and UOP0 in the presence of a RAW at the same time, the physical register of the source register of UOP3 takes the physical register number corresponding to the destination register of UOP2 according to the priority order.

The source register number of UOP3 is divided into 4 cases: 1, assuming UOP3 is related to UOP2, UOP1 and UOP0 are not RAW related; 2, assuming that UOP3 is associated with UOP0 in the presence of RAW, and UOP3 is associated with UOP2, UOP1 in the absence of RAW; 3, assuming UOP3 is associated with UOP1 having a RAW, and UOP2 is associated with UOP2 having no RAW; 4 assume UOP3 is related to UOP2 that there is a RAW. Obtaining 4 physical registers of each source register in the renamed stage 1, and simultaneously judging the correlations of UOP3, UOP2, UOP1 and UOP0 in parallel; the correct result is selected from the 4 physical register numbers of each source register according to the dependency logic in stage 2 of renaming.

1.4.1 assuming that UOP3 is related to UOP2, UOP1 and UOP0 are not RAW related

When UOP3 is associated with UOP2, UOP1 and UOP0, there is no RAW, the mapping procedure of UOP3 is similar to that of UOP 0.

The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

logical expression PHY_R_3_0 of 1 st source operand _i+1 A is as follows:

PHY_R_3_0 _i+1 _A＝({Q{(PRV _i _1D[0]&(R_3_0 _i+1 ＝＝R_0_2 _i _1D))}}&PHY_R_0_2 _i _1D)|

({Q{(PRV _i _1D[1]&(R_3_0 _i+1 ＝＝R_1_2 _i _1D))}}&PHY_R_1_2 _i _1D)|

({Q{(PRV _i _1D[2]&(R_3_0 _i+1 ＝＝R_2_2 _i _1D))}}&PHY_R_2_2 _i _1D)|

({Q{(PRV _i _1D[3]&(R_3_0 _i+1 ＝＝R_3_2 _i _1D))}}&PHY_R_3_2 _i _1D)|

({Q{(PRV _i _1D[4]&(R_3_0 _i+1 ＝＝R_4_2 _i _1D))}}&PHY_R_4_2 _i _1D)|

({Q{(PRV _i _1D[5]&(R_3_0 _i+1 ＝＝R_5_2 _i _1D))}}&PHY_R_5_2 _i _1D)|

({Q{(PRV _i _1D[6]&(R_3_0 _i+1 ＝＝R_6_2 _i _1D))}}&PHY_R_6_2 _i _1D)|

({Q{(PRV _i _1D[7]&(R_3_0 _i+1 ＝＝R_7_2 _i _1D))}}&PHY_R_7_2 _i _1D)|

({Q{(～(|PRV _i _1D))}}&RAT[R_3_0 _i+1 ][Q-1:0])

PHY_VAL_3_0 _i+1 ＝VAL_3_0 _i+1

similarly, the logical expression PHY_R_3_1 of the 2 nd source operand _i+1 A is as follows:

PHY_R_3_1 _i+1 _A＝({Q{(PRV _i _1D[0]&(R_3_1 _i+1 ＝＝R_0_2 _i _1D))}}&PHY_R_0_2 _i _1D)|

({Q{(PRV _i _1D[1]&(R_3_1 _i+1 ＝＝R_1_2 _i _1D))}}&PHY_R_1_2 _i _1D)|

({Q{(PRV _i _1D[2]&(R_3_1 _i+1 ＝＝R_2_2 _i _1D))}}&PHY_R_2_2 _i _1D)|

({Q{(PRV _i _1D[3]&(R_3_1 _i+1 ＝＝R_3_2 _i _1D))}}&PHY_R_3_2 _i _1D)|

({Q{(PRV _i _1D[4]&(R_3_1 _i+1 ＝＝R_4_2 _i _1D))}}&PHY_R_4_2 _i _1D)|

({Q{(PRV _i _1D[5]&(R_3_1 _i+1 ＝＝R_5_2 _i _1D))}}&PHY_R_5_2 _i _1D)|

({Q{(PRV _i _1D[6]&(R_3_1 _i+1 ＝＝R_6_2 _i _1D))}}&PHY_R_6_2 _i _1D)|

({Q{(PRV _i _1D[7]&(R_3_1 _i+1 ＝＝R_7_2 _i _1D))}}&PHY_R_7_2 _i _1D)|

({Q{(～(|PRV _i _1D))}}&RAT[R_3_1 _i+1 ][Q-1:0])

PHY_VAL_3_1 _i+1 ＝VAL_3_1 _i+1

1.4.2 assume that UOP3 is related to UOP0 where there is a RAW, and UOP3 is related to UOP2 where UOP1 is not related to RAW

When UOP3 is associated with UOP0 in the presence of a RAW and UOP3 is associated with UOP2, UOP1 in the absence of a RAW, i.e., the destination register of UOP0 is the same as the meta register architectural register number of UOP3 and is not the same as the destination register number of UOP2, UOP 1. The physical register number of the UOP3 source register is the physical register number newly allocated to the UOP0 destination register.

The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

logical expression PHY_R_3_0 of 1 st source operand _i+1 B is as follows:

PHY_R_3_0 _i+1 _B＝PHY_R_0_2 _i+1

similarly, the logical expression PHY_R_3_1 of the 2 nd source operand _i+1 B is as follows:

PHY_R_3_1 _i+1 _B＝PHY_R_0_2 _i+1

The valid identification of the source register is the same as that for UOP3 and UOP0, where no correlation exists.

1.4.3 assume that UOP3 is associated with UOP1 having a RAW present and with UOP2 not having a RAW present

When UOP3 is associated with UOP1 with no RAW, i.e., UOP 1's destination register is the same as UOP 3's meta register architectural register number and not the same as UOP 2's destination register number. The physical register number of the UOP3 source register is the physical register number newly allocated to the UOP1 destination register.

The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

logical expression PHY_R_3_0 of 1 st source operand _i+1 C is as follows:

PHY_R_3_0 _i+1 _C＝PHY_R_1_2 _i+1

similarly, the logical expression PHY_R_3_1 of the 2 nd source operand _i+1 C is as follows:

PHY_R_3_1 _i+1 _C＝PHY_R_1_2 _i+1

the valid identification of the source register is the same as that for UOP3 and UOP0, where no correlation exists.

1.4.4 suppose UOP3 and UOP2 have a RAW correlation

When UOP3 and UOP2 are associated with a RAW, i.e., the destination register of UOP2 is the same as the meta register architectural register number of UOP 3. The physical register number of the UOP3 source register is the physical register number newly allocated to the UOP2 destination register.

The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

Logical expression PHY_R_3_0 of 1 st source operand _i+1 The_d is as follows:

PHY_R_3_0 _i+1 _D＝PHY_R_2_2 _i+1

similarly, the logical expression PHY_R_3_1 of the 2 nd source operand _i+1 The_d is as follows:

PHY_R_3_1 _i+1 _D＝PHY_R_2_2 _i+1

the valid identification of the source register is the same as that for UOP3 and UOP0, where no correlation exists.

1.4.5 determining UOP3 and UOP2, UOP1 and UOP0 to have RAW-related logic

Judging whether UOP3 is related to UOP0 in the presence of RAW and is related to UOP2 in the absence of RAW, and only comparing whether the source register number of UOP3 is identical to the destination register number of UOP0 or not, and judging whether the source register number of UOP3 is identical to the destination register numbers of UOP2 and UOP1, wherein the 2 source register judgment logic expressions are as follows:

selection logic CMP_R_3_0 for 1 st source operand _i+1 [2:0]The logical expression is as follows:

CMP_R_3_0 _i+1 [0]＝((R_3_0 _i+1 ＝＝R_0_2 _i+1 )&VAL_3_0&VAL_0_2)&

(～((R_3_0 _i+1 ＝＝R_1_2 _i+1 )&VAL_3_0&VAL_1_2))&

(～((R_3_0 _i+1 ＝＝R_2_2 _i+1 )&VAL_3_0&VAL_2_2))

CMP_R_3_0 _i+1 [1]＝((R_3_0 _i+1 ＝＝R_1_2 _i+1 )&VAL_3_0&VAL_1_2)&

(～((R_3_0 _i+1 ＝＝R_2_2 _i+1 )&VAL_3_0&VAL_2_2))

CMP_R_3_0 _i+1 [2]＝((R_3_0 _i+1 ＝＝R_2_2 _i+1 )&VAL_3_0&VAL_2_2)

selection logic CMP_R_3_1 of 2 nd source operand _i+1 [2:0]The logical expression is as follows:

CMP_R_3_1 _i+1 [0]＝((R_3_1 _i+1 ＝＝R_0_2 _i+1 )&VAL_3_1&VAL_0_2)&

(～((R_3_1 _i+1 ＝＝R_1_2 _i+1 )&VAL_3_1&VAL_1_2))&

(～((R_3_1 _i+1 ＝＝R_2_2 _i+1 )&VAL_3_1&VAL_2_2))

CMP_R_3_1 _i+1 [1]＝((R_3_1 _i+1 ＝＝R_1_2 _i+1 )&VAL_3_1&VAL_1_2)&

(～((R_3_1 _i+1 ＝＝R_2_2 _i+1 )&VAL_3_1&VAL_2_2))

CMP_R_3_1 _i+1 [2]＝((R_3_1 _i+1 ＝＝R_2_2 _i+1 )&VAL_3_1&VAL_2_2)

the i+1th cycle instruction phase 2 source operands and destination architecture registers map to physical register calculation process:

PHY_R_3_0 _i+1 _A_1D<＝PHY_R_3_0 _i+1 _A

PHY_R_3_0 _i+1 _B_1D<＝PHY_R_3_0 _i+1 _B

PHY_R_3_0 _i+1 _C_1D<＝PHY_R_3_0 _i+1 _C

PHY_R_3_0 _i+1 _D_1D<＝PHY_R_3_0 _i+1 _D

PHY_R_3_1 _i+1 _A_1D<＝PHY_R_3_1 _i+1 _A

PHY_R_3_1 _i+1 _B_1D<＝PHY_R_3_1 _i+1 _B

PHY_R_3_1 _i+1 _C_1D<＝PHY_R_3_1 _i+1 _C

PHY_R_3_1 _i+1 _D_1D<＝PHY_R_3_1 _i+1 _D

CMP_R_3_0 _i+1 _1D<＝CMP_R_3_0 _i+1

CMP_R_3_1 _i+1 _1D<＝CMP_R_3_1 _i+1

physical register PHY_R_3_0 for 1 st source operand final _i+1 1D, the correct physical register is selected according to the selection logic.

PHY_R_3_0 _i+1 _1D＝({Q{(～(|CMP_R_3_0 _i+1 _1D))}}&PHY_R_3_0 _i+1 _A_1D)|

({Q{CMP_R_3_0 _i+1 _1D[0]}}&PHY_R_3_0 _i+1 _B_1D)|

({Q{CMP_R_3_0 _i+1 _1D[1]}}&PHY_R_3_0 _i+1 _C_1D)|

({Q{CMP_R_3_0 _i+1 _1D[2]}}&PHY_R_3_0 _i+1 _D_1D)

Physical register PHY_R_3_1 of the 2 nd source operand final _i+1 1D, the correct physical register is selected according to the selection logic.

PHY_R_3_1 _i+1 _1D＝({Q{(～(|CMP_R_3_1 _i+1 _1D))}}&PHY_R_3_1 _i+1 _A_1D)|

({Q{CMP_R_3_1 _i+1 _1D[0]}}&PHY_R_3_1 _i+1 _B_1D)|

({Q{CMP_R_3_1 _i+1 _1D[1]}}&PHY_R_3_1 _i+1 _C_1D)|

({Q{CMP_R_3_1 _i+1 _1D[2]}}&PHY_R_3_1 _i+1 _D_1D)

PHY_VAL_3_0 _i+1 _1D<＝PHY_VAL_3_0 _i+1

PHY_VAL_3_1 _i+1 _1D<＝PHY_VAL_3_1 _i+1

The logical expression of the destination register is as follows:

PHY_R_3_2 _i+1 _1D<＝PHY_R_3_2 _i+1

PHY_VAL_3_2 _i+1 _1D<＝PHY_VAL_3_2 _i+1

R_3_2 _i _1D<＝R_3_2 _i

1.5UOP4 renaming procedure

The 2 source operands of UOP4 query the RAT table according to the architecture register number of each source operand, and it is also required to determine whether the architecture register numbers of the 2 source operands of UOP4 are the same as those of the destination registers of UOP3, UOP2, UOP1 and UOP0, i.e. it is required to determine r_4_0 _i+1 And R_4_1 _i+1 Whether or not to be equal to R_3_2 _i+1 ，R_2_2 _i+1 ，R_1_2 _i+1 Or R_0_2 _i+1 The same applies. If the architectural register number of the 2 source operands of UOP4 is the same as the architectural number of the destination registers of UOP3, UOP2, UOP1 or UOP0, then the physical register mapped by the architectural register number of the 2 source operands of UOP4 is the physical register corresponding to the destination register of UOP3, UOP2, UOP1 or UOP 0. If a certain source register of UOP4 is related to the simultaneous existence of RAW of UOP3, UOP2, UOP1 and UOP0, the physical register of the source register of UOP4 takes the physical register number corresponding to the destination register of UOP3 according to the priority order.

The source register number of UOP4 is divided into 5 cases: 1, assuming UOP4 is not related to UOP3, UOP2, UOP1 and UOP0 with no RAW; 2, assuming that UOP4 is associated with UOP0 in the presence of RAW, and UOP4 is associated with UOP3, UOP2, UOP1 in the absence of RAW; 3, assuming UOP4 is associated with UOP1 having a RAW, and UOP3, UOP2 having no RAW; 4 assume that UOP4 is associated with UOP2 that there is a RAW, and UOP4 is associated with UOP3 that there is no RAW; 5 assume that UOP4 is related to UOP3 that there is a RAW. Obtaining 5 physical registers of each source register in a renamed stage 1, and simultaneously judging the correlations of UOP4, UOP3, UOP2, UOP1 and UOP0 in parallel; the correct result is selected from the 5 physical register numbers of each source register according to the dependency logic in stage 2 of renaming.

1.5.1 assuming that UOP4 is not related to UOP3, UOP2, UOP1 and UOP0 to the absence of RAW

When UOP4 is associated with UOP3, UOP2, UOP1 and UOP0, there is no RAW correlation, the mapping procedure of UOP4 is similar to that of UOP 0. The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

logical expression PHY_R_4_0 of 1 st source operand _i+1 A is as follows:

PHY_R_4_0 _i+1 _A＝({Q{(PRV _i _1D[0]&(R_4_0 _i+1 ＝＝R_0_2 _i _1D))}}&PHY_R_0_2 _i _1D)|

({Q{(PRV _i _1D[1]&(R_4_0 _i+1 ＝＝R_1_2 _i _1D))}}&PHY_R_1_2 _i _1D)|

({Q{(PRV _i _1D[2]&(R_4_0 _i+1 ＝＝R_2_2 _i _1D))}}&PHY_R_2_2 _i _1D)|

({Q{(PRV _i _1D[3]&(R_4_0 _i+1 ＝＝R_3_2 _i _1D))}}&PHY_R_3_2 _i _1D)|

({Q{(PRV _i _1D[4]&(R_4_0 _i+1 ＝＝R_4_2 _i _1D))}}&PHY_R_4_2 _i _1D)|

({Q{(PRV _i _1D[5]&(R_4_0 _i+1 ＝＝R_5_2 _i _1D))}}&PHY_R_5_2 _i _1D)|

({Q{(PRV _i _1D[6]&(R_4_0 _i+1 ＝＝R_6_2 _i _1D))}}&PHY_R_6_2 _i _1D)|

({Q{(PRV _i _1D[7]&(R_4_0 _i+1 ＝＝R_7_2 _i _1D))}}&PHY_R_7_2 _i _1D)|

({Q{(～(|PRV _i _1D))}}&RAT[R_4_0 _i+1 ][Q-1:0])

PHY_VAL_4_0 _i+1 ＝VAL_4_0 _i+1

similarly, the logical expression PHY_R_4_1 of the 2 nd source operand _i+1 A is as follows:

PHY_R_4_1 _i+1 _A＝({Q{(PRV _i _1D[0]&(R_4_1 _i+1 ＝＝R_0_2 _i _1D))}}&PHY_R_0_2 _i _1D)|

({Q{(PRV _i _1D[1]&(R_4_1 _i+1 ＝＝R_1_2 _i _1D))}}&PHY_R_1_2 _i _1D)|

({Q{(PRV _i _1D[2]&(R_4_1 _i+1 ＝＝R_2_2 _i _1D))}}&PHY_R_2_2 _i _1D)|

({Q{(PRV _i _1D[3]&(R_4_1 _i+1 ＝＝R_3_2 _i _1D))}}&PHY_R_3_2 _i _1D)|

({Q{(PRV _i _1D[4]&(R_4_1 _i+1 ＝＝R_4_2 _i _1D))}}&PHY_R_4_2 _i _1D)|

({Q{(PRV _i _1D[5]&(R_4_1 _i+1 ＝＝R_5_2 _i _1D))}}&PHY_R_5_2 _i _1D)|

({Q{(PRV _i _1D[6]&(R_4_1 _i+1 ＝＝R_6_2 _i _1D))}}&PHY_R_6_2 _i _1D)|

({Q{(PRV _i _1D[7]&(R_4_1 _i+1 ＝＝R_7_2 _i _1D))}}&PHY_R_7_2 _i _1D)|

({Q{(～(|PRV _i _1D))}}&RAT[R_4_1 _i+1 ][Q-1:0])

PHY_VAL_4_1 _i+1 ＝VAL_4_1 _i+1

1.5.2 assume that UOP4 is related to UOP0 with no RAW, and UOP4 is related to UOP3, UOP2, UOP1 with no RAW

When UOP4 is associated with UOP0 in the presence of a RAW and UOP4 is not associated with UOP3, UOP2, UOP1 in the presence of a RAW, i.e., the destination register of UOP0 is the same as the meta register architectural register number of UOP4 and is not the same as the destination register numbers of UOP3, UOP2, UOP 1. The physical register number of the UOP4 source register is the physical register number newly allocated to the UOP0 destination register.

The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

logical expression PHY_R_4_0 of 1 st source operand _i+1 B is as follows:

PHY_R_4_0 _i+1 _B＝PHY_R_0_2 _i+1

similarly, the logical expression PHY_R_4_1 of the 2 nd source operand _i+1 B is as follows:

PHY_R_4_1 _i+1 _B＝PHY_R_0_2 _i+1

the valid identification of the source register is the same as that for UOP4 and UOP0, where no correlation exists.

1.5.3 assume that UOP4 is associated with UOP1 that there is a RAW, and UOP4 is associated with UOP3 that UOP2 is not associated with a RAW

When UOP4 is associated with UOP1 in the presence of a RAW and UOP4 is associated with UOP3, UOP2 in the absence of a RAW, i.e., the destination register of UOP1 is the same as the meta register architectural register number of UOP4 and is not the same as the destination register number of UOP3, UOP 2. The physical register number of the UOP4 source register is the physical register number newly allocated to the UOP1 destination register.

The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

logical expression PHY_R_4_0 of 1 st source operand _i+1 C is as follows:

PHY_R_4_0 _i+1 _C＝PHY_R_1_2 _i+1

similarly, the logical expression PHY_R_4_1 of the 2 nd source operand _i+1 C is as follows:

PHY_R_4_1 _i+1 _C＝PHY_R_1_2 _i+1

the valid identification of the source register is the same as that for UOP4 and UOP0, where no correlation exists.

1.5.4 it is assumed that UOP4 is correlated with UOP2 that there is a RAW, and UOP4 is correlated with UOP3 that there is no RAW

When UOP4 is associated with UOP2 with no RAW, i.e., UOP 2's destination register is the same as UOP 4's meta register architectural register number and not the same as UOP 3's destination register number. The physical register number of the UOP4 source register is the physical register number newly allocated to the UOP2 destination register.

The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

logical expression PHY_R_4_0 of 1 st source operand _i+1 The_d is as follows:

PHY_R_4_0 _i+1 _D＝PHY_R_2_2 _i+1

similarly, the logical expression PHY_R_4_1 of the 2 nd source operand _i+1 The_d is as follows:

PHY_R_4_1 _i+1 _D＝PHY_R_2_2 _i+1

1.5.5 suppose that UOP4 is related to UOP3 in the presence of a RAW

When UOP4 and UOP3 have a RAW correlation of 3, i.e. the destination register of UOP3 is the same as the meta register architecture register number of UOP 4. The physical register number of the UOP4 source register is the physical register number newly allocated to the UOP3 destination register.

The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

logical expression PHY_R_4_0 of 1 st source operand _i+1 E is as follows:

PHY_R_4_0 _i+1 _E＝PHY_R_3_2 _i+1

similarly, the logical expression PHY_R_4_1 of the 2 nd source operand _i+1 E is as follows:

PHY_R_4_1 _i+1 _E＝PHY_R_3_2 _i+1

1.5.6 determining whether UOP4 and UOP3, UOP2, UOP1 and UOP0 have RAW-related logic

Judging whether UOP4 is related to UOP0 by RAW and is related to UOP3, UOP2 and UOP1 by not RAW, only comparing whether the source register number of UOP4 is the same as the destination register number of UOP0 or not, and judging whether the source register number of UOP4 is the same as the destination register numbers of UOP3, UOP2 and UOP1 or not, wherein the 2 source register judgment logic expressions are as follows:

Selection logic CMP_R for 1 st source operand_4_0 _i+1 [3:0]The logical expression is as follows:

CMP_R_4_0 _i+1 [0]＝((R_4_0 _i+1 ＝＝R_0_2 _i+1 )&VAL_4_0&VAL_0_2)&

(～((R_4_0 _i+1 ＝＝R_1_2 _i+1 )&VAL_4_0&VAL_1_2))&

(～((R_4_0 _i+1 ＝＝R_2_2 _i+1 )&VAL_4_0&VAL_2_2))&

(～((R_4_0 _i+1 ＝＝R_3_2 _i+1 )&VAL_4_0&VAL_3_2))

CMP_R_4_0 _i+1 [1]＝((R_4_0 _i+1 ＝＝R_1_2 _i+1 )&VAL_4_0&VAL_1_2)&

(～((R_4_0 _i+1 ＝＝R_2_2 _i+1 )&VAL_4_0&VAL_2_2))&

(～((R_4_0 _i+1 ＝＝R_3_2 _i+1 )&VAL_4_0&VAL_3_2))

CMP_R_4_0 _i+1 [2]＝((R_4_0 _i+1 ＝＝R_2_2 _i+1 )&VAL_4_0&VAL_2_2)&

(～((R_4_0 _i+1 ＝＝R_3_2 _i+1 )&VAL_4_0&VAL_3_2))

CMP_R_4_0 _i+1 [3]＝((R_4_0 _i+1 ＝＝R_3_2 _i+1 )&VAL_4_0&VAL_3_2)

selection logic CMP_R_4_1 of 2 nd source operand _i+1 [3:0]The logical expression is as follows:

CMP_R_4_1 _i+1 [0]＝((R_4_1 _i+1 ＝＝R_0_2 _i+1 )&VAL_4_1&VAL_0_2)&

(～((R_4_1 _i+1 ＝＝R_1_2 _i+1 )&VAL_4_1&VAL_1_2))&

(～((R_4_1 _i+1 ＝＝R_2_2 _i+1 )&VAL_4_1&VAL_2_2))&

(～((R_4_1 _i+1 ＝＝R_3_2 _i+1 )&VAL_4_1&VAL_3_2))

CMP_R_4_1 _i+1 [1]＝((R_4_1 _i+1 ＝＝R_1_2 _i+1 )&VAL_4_0&VAL_1_2)&

(～((R_4_1 _i+1 ＝＝R_2_2 _i+1 )&VAL_4_0&VAL_2_2))&

(～((R_4_1 _i+1 ＝＝R_3_2 _i+1 )&VAL_4_0&VAL_3_2))

CMP_R_4_1 _i+1 [2]＝((R_4_1 _i+1 ＝＝R_2_2 _i+1 )&VAL_4_0&VAL_2_2)&

(～((R_4_1 _i+1 ＝＝R_3_2 _i+1 )&VAL_4_0&VAL_3_2))

CMP_R_4_1 _i+1 [3]＝((R_4_1 _i+1 ＝＝R_3_2 _i+1 )&VAL_4_1&VAL_3_2)

the i+1th cycle instruction phase 2 source operands and destination architecture registers map to physical register calculation process:

PHY_R_4_0 _i+1 _A_1D<＝PHY_R_4_0 _i+1 _A

PHY_R_4_0 _i+1 _B_1D<＝PHY_R_4_0 _i+1 _B

PHY_R_4_0 _i+1 _C_1D<＝PHY_R_4_0 _i+1 _C

PHY_R_4_0 _i+1 _D_1D<＝PHY_R_4_0 _i+1 _D

PHY_R_4_0 _i+1 _E_1D<＝PHY_R_4_0 _i+1 _E

PHY_R_4_1 _i+1 _A_1D<＝PHY_R_4_1 _i+1 _A

PHY_R_4_1 _i+1 _B_1D<＝PHY_R_4_1 _i+1 _B

PHY_R_4_1 _i+1 _C_1D<＝PHY_R_4_1 _i+1 _C

PHY_R_4_1 _i+1 _D_1D<＝PHY_R_4_1 _i+1 _D

PHY_R_4_1 _i+1 _E_1D<＝PHY_R_4_1 _i+1 _E

CMP_R_4_0 _i+1 _1D<＝CMP_R_4_0 _i+1

CMP_R_4_1 _i+1 _1D<＝CMP_R_4_1 _i+1

physical register PHY_R_4_0 for 1 st source operand final _i+1 1D, according to selection logicSelect the correct physical register.

PHY_R_4_0 _i+1 _1D＝({Q{(～(|CMP_R_4_0 _i+1 _1D))}}&PHY_R_4_0 _i+1 _A_1D)|

({Q{CMP_R_4_0 _i+1 _1D[0]}}&PHY_R_4_0 _i+1 _B_1D)|

({Q{CMP_R_4_0 _i+1 _1D[1]}}&PHY_R_4_0 _i+1 _C_1D)|

({Q{CMP_R_4_0 _i+1 _1D[2]}}&PHY_R_4_0 _i+1 _D_1D)|

({Q{CMP_R_4_0 _i+1 _1D[3]}}&PHY_R_4_0 _i+1 _E_1D)

Physical register PHY_R_4_1 of the 2 nd source operand final _i+1 1D, the correct physical register is selected according to the selection logic.

PHY_R_4_1 _i+1 _1D＝({Q{(～(|CMP_R_4_1 _i+1 _1D))}}&PHY_R_4_1 _i+1 _A_1D)|

({Q{CMP_R_4_1 _i+1 _1D[0]}}&PHY_R_4_1 _i+1 _B_1D)|

({Q{CMP_R_4_1 _i+1 _1D[1]}}&PHY_R_4_1 _i+1 _C_1D)|

({Q{CMP_R_4_1 _i+1 _1D[2]}}&PHY_R_4_1 _i+1 _D_1D)|

({Q{CMP_R_4_1 _i+1 _1D[3]}}&PHY_R_4_1 _i+1 _E_1D)

PHY_VAL_4_0 _i+1 _1D<＝PHY_VAL_4_0 _i+1

PHY_VAL_4_1 _i+1 _1D<＝PHY_VAL_4_1 _i+1

The logical expression of the destination register is as follows:

PHY_R_4_2 _i+1 _1D<＝PHY_R_4_2 _i+1

PHY_VAL_4_2 _i+1 _1D<＝PHY_VAL_4_2 _i+1

R_4_2 _i _1D<＝R_4_2 _i

1.6UOP5 renaming procedure

The 2 source operands of UOP5 query the RAT table according to the architectural register number of each source operand while also requiringTo determine whether the architectural register numbers of 2 source operands of UOP5 are identical to the architectural numbers of destination registers of UOP4, UOP3, UOP2, UOP1 and UOP0, i.e., determine r_5_0 _i+1 And R_5_1 _i+1 Whether or not to be equal to R_4_2 _i+1 ，R_3_2 _i+1 ，R_2_2 _i+1 ，R_1_2 _i+1 Or R_0_2 _i+1 The same applies. If the architectural register number of the 2 source operands of UOP5 is the same as the architectural number of the destination registers of UOP4, UOP3, UOP2, UOP1 or UOP0, then the physical register mapped by the architectural register number of the 2 source operands of UOP5 is the physical register corresponding to the destination register of UOP4, UOP3, UOP2, UOP1 or UOP 0. If a certain source register of UOP5 is related to the simultaneous existence of RAW of UOP4, UOP3, UOP2, UOP1 and UOP0, the physical register of the source register of UOP5 takes the physical register number corresponding to the destination register of UOP4 according to the priority order.

The source register number of UOP5 is divided into 6 cases: 1, assuming UOP5 is not related to UOP4, UOP3, UOP2, UOP1 and UOP0 with no RAW; 2, assuming that UOP5 is associated with UOP0 with a RAW, and UOP5 is associated with UOP4, UOP3, UOP2, UOP1 with no RAW; 3, assuming UOP5 is associated with UOP1 that there is a RAW, and UOP4, UOP3, UOP2 that there is no RAW; 4, assuming that UOP5 is associated with UOP2 in the presence of RAW, and UOP5 is associated with UOP4, UOP3 in the absence of RAW; 5, assuming that UOP5 is associated with UOP3 with a RAW, and UOP5 is associated with UOP4 with no RAW; 6, suppose UOP5 is related to UOP4 that there is a RAW. 6 physical registers of each source register are obtained in the renaming stage 1, and simultaneously correlations of UOP5, UOP4, UOP3, UOP2, UOP1 and UOP0 are judged in parallel; the correct result is selected from the 6 physical register numbers of each source register according to the dependency logic in stage 2 of renaming.

1.6.1 assume that UOP5 is not related to UOP4, UOP3, UOP2, UOP1 and UOP0 in the absence of RAW

When UOP5 is associated with UOP4, UOP3, UOP2, UOP1 and UOP0 without a RAW correlation, the mapping procedure of UOP5 is similar to that of UOP 0. The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

1 st source operationLogical expression PHY_R_5_0 of number _i+1 A is as follows:

PHY_R_5_0 _i+1 _A＝({Q{(PRV _i _1D[0]&(R_5_0 _i+1 ＝＝R_0_2 _i _1D))}}&PHY_R_0_2 _i _1D)|

({Q{(PRV _i _1D[1]&(R_5_0 _i+1 ＝＝R_1_2 _i _1D))}}&PHY_R_1_2 _i _1D)|

({Q{(PRV _i _1D[2]&(R_5_0 _i+1 ＝＝R_2_2 _i _1D))}}&PHY_R_2_2 _i _1D)|

({Q{(PRV _i _1D[3]&(R_5_0 _i+1 ＝＝R_3_2 _i _1D))}}&PHY_R_3_2 _i _1D)|

({Q{(PRV _i _1D[4]&(R_5_0 _i+1 ＝＝R_4_2 _i _1D))}}&PHY_R_4_2 _i _1D)|

({Q{(PRV _i _1D[5]&(R_5_0 _i+1 ＝＝R_5_2 _i _1D))}}&PHY_R_5_2 _i _1D)|

({Q{(PRV _i _1D[6]&(R_5_0 _i+1 ＝＝R_6_2 _i _1D))}}&PHY_R_6_2 _i _1D)|

({Q{(PRV _i _1D[7]&(R_5_0 _i+1 ＝＝R_7_2 _i _1D))}}&PHY_R_7_2 _i _1D)|

({Q{(～(|PRV _i _1D))}}&RAT[R_5_0 _i+1 ][Q-1:0])

PHY_VAL_5_0 _i+1 ＝VAL_5_0 _i+1

similarly, the logical expression PHY_R_5_1 of the 2 nd source operand _i+1 A is as follows:

PHY_R_5_1 _i+1 _A＝({Q{(PRV _i _1D[0]&(R_5_1 _i+1 ＝＝R_0_2 _i _1D))}}&PHY_R_0_2 _i _1D)|

({Q{(PRV _i _1D[1]&(R_5_1 _i+1 ＝＝R_1_2 _i _1D))}}&PHY_R_1_2 _i _1D)|

({Q{(PRV _i _1D[2]&(R_5_1 _i+1 ＝＝R_2_2 _i _1D))}}&PHY_R_2_2 _i _1D)|

({Q{(PRV _i _1D[3]&(R_5_1 _i+1 ＝＝R_3_2 _i _1D))}}&PHY_R_3_2 _i _1D)|

({Q{(PRV _i _1D[4]&(R_5_1 _i+1 ＝＝R_4_2 _i _1D))}}&PHY_R_4_2 _i _1D)|

({Q{(PRV _i _1D[5]&(R_5_1 _i+1 ＝＝R_5_2 _i _1D))}}&PHY_R_5_2 _i _1D)|

({Q{(PRV _i _1D[6]&(R_5_1 _i+1 ＝＝R_6_2 _i _1D))}}&PHY_R_6_2 _i _1D)|

({Q{(PRV _i _1D[7]&(R_5_1 _i+1 ＝＝R_7_2 _i _1D))}}&PHY_R_7_2 _i _1D)|

({Q{(～(|PRV _i _1D))}}&RAT[R_5_1 _i+1 ][Q-1:0])

PHY_VAL_5_1 _i+1 ＝VAL_5_1 _i+1

1.6.2 assume that UOP5 is related to UOP0 that there is a RAW, and that UOP5 is related to UOP4, UOP3, UOP2, UOP1 that there is no RAW

When UOP5 is associated with UOP0 in the presence of a RAW and UOP5 is associated with UOP4, UOP3, UOP2, UOP1 in the absence of a RAW, i.e., the destination register of UOP0 is the same as the meta register architectural register number of UOP5 and is not the same as the destination register numbers of UOP4, UOP3, UOP2, UOP 1. The physical register number of the UOP5 source register is the physical register number newly allocated to the UOP0 destination register.

The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

logical expression PHY_R_5_0 of 1 st source operand _i+1 B is as follows:

PHY_R_5_0 _i+1 _B＝PHY_R_0_2 _i+1

similarly, the logical expression PHY_R_5_1 of the 2 nd source operand _i+1 B is as follows:

PHY_R_5_1 _i+1 _B＝PHY_R_0_2 _i+1

the valid identification of the source register is the same as that for UOP5 and UOP0, where no correlation exists.

1.6.3 assume that UOP5 is related to UOP1 with no RAW, and UOP5 is related to UOP4, UOP3, UOP2 with no RAW

When UOP5 is associated with UOP1 in the presence of a RAW and UOP5 is not associated with UOP4, UOP3, UOP2 in the presence of a RAW, i.e., the destination register of UOP1 is the same as the meta register architectural register number of UOP5 and is not the same as the destination register numbers of UOP4, UOP3, UOP 2. The physical register number of the UOP5 source register is the physical register number newly allocated to the UOP1 destination register.

The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

logical expression PHY_R_5_0 of 1 st source operand _i+1 C is as follows:

PHY_R_5_0 _i+1 _C＝PHY_R_1_2 _i+1

similarly, the logical expression PHY_R_5_1 of the 2 nd source operand _i+1 C is as follows:

PHY_R_5_1 _i+1 _C＝PHY_R_1_2 _i+1

the valid identification of the source register is the same as that for UOP5 and UOP0, where no correlation exists.

1.6.4 it is assumed that UOP5 is associated with UOP2 that there is a RAW, and UOP5 is associated with UOP4, UOP3 that there is no RAW

When UOP5 is associated with UOP2 in the presence of a RAW and UOP5 is associated with UOP4, UOP3 in the absence of a RAW, i.e., the destination register of UOP2 is the same as the meta register architectural register number of UOP5 and is not the same as the destination register number of UOP4, UOP 3. The physical register number of the UOP5 source register is the physical register number newly allocated to the UOP2 destination register.

The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

logical expression PHY_R_5_0 of 1 st source operand _i+1 The_d is as follows:

PHY_R_5_0 _i+1 _D＝PHY_R_2_2 _i+1

similarly, the logical expression of the 2 nd source operandPHY_R_5_1 _i+1 The_d is as follows:

PHY_R_5_1 _i+1 _D＝PHY_R_2_2 _i+1

1.6.5 it is assumed that UOP5 is correlated with UOP3 that there is a RAW, and UOP5 is correlated with UOP4 that there is no RAW

When UOP5 is associated with UOP3 with no RAW, i.e., UOP 3's destination register is the same as UOP 5's meta register architectural register number and not the same as UOP 4's destination register number. The physical register number of the UOP5 source register is the physical register number newly allocated to the UOP3 destination register.

The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

logical expression PHY_R_5_0 of 1 st source operand _i+1 E is as follows:

PHY_R_5_0 _i+1 _E＝PHY_R_3_2 _i+1

similarly, the logical expression PHY_R_5_1 of the 2 nd source operand _i+1 E is as follows:

PHY_R_5_1 _i+1 _E＝PHY_R_3_2 _i+1

1.6.6 suppose that UOP5 is related to UOP4 in the presence of a RAW

When UOP5 and UOP4 are associated with a RAW, i.e., the destination register of UOP4 is the same as the meta register architectural register number of UOP 5. The physical register number of the UOP5 source register is the physical register number newly allocated to the UOP4 destination register.

The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

logical expression PHY_R_5_0 of 1 st source operand _i+1 F is as follows:

PHY_R_5_0 _i+1 _F＝PHY_R_4_2 _i+1

similarly, the logical expression PHY_R_5_1 of the 2 nd source operand _i+1 F is as follows:

PHY_R_5_1 _i+1 _F＝PHY_R_4_2 _i+1

1.6.7 determining whether UOP5 and UOP4, UOP3, UOP2, UOP1 and UOP0 have RAW-related logic

Judging whether UOP5 is related to UOP0 in the presence of RAW and is related to UOP4, UOP3, UOP2 and UOP1 in the absence of RAW, only comparing whether the source register number of UOP5 is identical to the destination register number of UOP0 or not, and judging whether the source register number of UOP5 is identical to the destination register numbers of UOP4, UOP3, UOP2 and UOP1 or not, wherein the 2 source register judgment logic expressions are as follows:

Selection logic CMP_R_5_0 for 1 st source operand _i+1 [4:0]The logical expression is as follows:

CMP_R_5_0 _i+1 [0]＝((R_5_0 _i+1 ＝＝R_0_2 _i+1 )&VAL_5_0&VAL_0_2)&

(～((R_5_0 _i+1 ＝＝R_1_2 _i+1 )&VAL_5_0&VAL_1_2))&

(～((R_5_0 _i+1 ＝＝R_2_2 _i+1 )&VAL_5_0&VAL_2_2))&

(～((R_5_0 _i+1 ＝＝R_3_2 _i+1 )&VAL_5_0&VAL_3_2))&

(～((R_5_0 _i+1 ＝＝R_4_2 _i+1 )&VAL_5_0&VAL_4_2))

CMP_R_5_0 _i+1 [1]＝((R_5_0 _i+1 ＝＝R_1_2 _i+1 )&VAL_5_0&VAL_1_2)&

(～((R_5_0 _i+1 ＝＝R_2_2 _i+1 )&VAL_5_0&VAL_2_2))&

(～((R_5_0 _i+1 ＝＝R_3_2 _i+1 )&VAL_5_0&VAL_3_2))&

(～((R_5_0 _i+1 ＝＝R_4_2 _i+1 )&VAL_5_0&VAL_4_2))

CMP_R_5_0 _i+1 [2]＝((R_5_0 _i+1 ＝＝R_2_2 _i+1 )&VAL_5_0&VAL_2_2)&

(～((R_5_0 _i+1 ＝＝R_3_2 _i+1 )&VAL_5_0&VAL_3_2))&

(～((R_5_0 _i+1 ＝＝R_4_2 _i+1 )&VAL_5_0&VAL_4_2))

CMP_R_5_0 _i+1 [3]＝((R_5_0 _i+1 ＝＝R_3_2 _i+1 )&VAL_5_0&VAL_3_2)&

(～((R_5_0 _i+1 ＝＝R_4_2 _i+1 )&VAL_5_0&VAL_4_2))

CMP_R_5_0 _i+1 [4]＝((R_5_0 _i+1 ＝＝R_4_2 _i+1 )&VAL_5_0&VAL_4_2)

selection logic CMP_R_5_1 of 2 nd source operand _i+1 [4:0]The logical expression is as follows:

CMP_R_5_1 _i+1 [0]＝((R_5_1 _i+1 ＝＝R_0_2 _i+1 )&VAL_5_1&VAL_0_2)&

(～((R_5_1 _i+1 ＝＝R_1_2 _i+1 )&VAL_5_1&VAL_1_2))&

(～((R_5_1 _i+1 ＝＝R_2_2 _i+1 )&VAL_5_1&VAL_2_2))&

(～((R_5_1 _i+1 ＝＝R_3_2 _i+1 )&VAL_5_1&VAL_3_2))&

(～((R_5_1 _i+1 ＝＝R_4_2 _i+1 )&VAL_5_1&VAL_4_2))

CMP_R_5_1 _i+1 [1]＝((R_5_1 _i+1 ＝＝R_1_2 _i+1 )&VAL_5_1&VAL_1_2)&

(～((R_5_1 _i+1 ＝＝R_2_2 _i+1 )&VAL_5_1&VAL_2_2))&

(～((R_5_1 _i+1 ＝＝R_3_2 _i+1 )&VAL_5_1&VAL_3_2))&

(～((R_5_1 _i+1 ＝＝R_4_2 _i+1 )&VAL_5_1&VAL_4_2))

CMP_R_5_1 _i+1 [2]＝((R_5_1 _i+1 ＝＝R_2_2 _i+1 )&VAL_5_1&VAL_2_2)&

(～((R_5_1 _i+1 ＝＝R_3_2 _i+1 )&VAL_5_1&VAL_3_2))&

(～((R_5_1 _i+1 ＝＝R_4_2 _i+1 )&VAL_5_1&VAL_4_2))

CMP_R_5_1 _i+1 [3]＝((R_5_1 _i+1 ＝＝R_3_2 _i+1 )&VAL_5_1&VAL_3_2)&

(～((R_5_1 _i+1 ＝＝R_4_2 _i+1 )&VAL_5_1&VAL_4_2))

CMP_R_5_1 _i+1 [4]＝((R_5_1 _i+1 ＝＝R_4_2 _i+1 )&VAL_5_1&VAL_4_2)

the i+1th cycle instruction phase 2 source operands and destination architecture registers map to physical register calculation process:

PHY_R_5_0 _i+1 _A_1D<＝PHY_R_5_0 _i+1 _A

PHY_R_5_0 _i+1 _B_1D<＝PHY_R_5_0 _i+1 _B

PHY_R_5_0 _i+1 _C_1D<＝PHY_R_5_0 _i+1 _C

PHY_R_5_0 _i+1 _D_1D<＝PHY_R_5_0 _i+1 _D

PHY_R_5_0 _i+1 _E_1D<＝PHY_R_5_0 _i+1 _E

PHY_R_5_0 _i+1 _F_1D<＝PHY_R_5_0 _i+1 _F

PHY_R_5_1 _i+1 _A_1D<＝PHY_R_5_1 _i+1 _A

PHY_R_5_1 _i+1 _B_1D<＝PHY_R_5_1 _i+1 _B

PHY_R_5_1 _i+1 _C_1D<＝PHY_R_5_1 _i+1 _C

PHY_R_5_1 _i+1 _D_1D<＝PHY_R_5_1 _i+1 _D

PHY_R_5_1 _i+1 _E_1D<＝PHY_R_5_1 _i+1 _E

PHY_R_5_1 _i+1 _F_1D<＝PHY_R_5_1 _i+1 _F

CMP_R_5_0 _i+1 _1D<＝CMP_R_5_0 _i+1

CMP_R_5_1 _i+1 _1D<＝CMP_R_5_1 _i+1

physical register PHY_R_5_0 for 1 st source operand final _i+1 1D, the correct physical register is selected according to the selection logic.

PHY_R_5_0 _i+1 _1D＝({Q{(～(|CMP_R_5_0 _i+1 _1D))}}&PHY_R_5_0 _i+1 _A_1D)|

({Q{CMP_R_5_0 _i+1 _1D[0]}}&PHY_R_5_0 _i+1 _B_1D)|

({Q{CMP_R_5_0 _i+1 _1D[1]}}&PHY_R_5_0 _i+1 _C_1D)|

({Q{CMP_R_5_0 _i+1 _1D[2]}}&PHY_R_5_0 _i+1 _D_1D)|

({Q{CMP_R_5_0 _i+1 _1D[3]}}&PHY_R_5_0 _i+1 _E_1D)|

({Q{CMP_R_5_0 _i+1 _1D[4]}}&PHY_R_5_0 _i+1 _F_1D)

Physical register PHY_R_5_1 of the 2 nd source operand final _i+1 1D, the correct physical register is selected according to the selection logic.

PHY_R_5_1 _i+1 _1D＝({Q{(～(|CMP_R_5_1 _i+1 _1D))}}&PHY_R_5_1 _i+1 _A_1D)|

({Q{CMP_R_5_1 _i+1 _1D[0]}}&PHY_R_5_1 _i+1 _B_1D)|

({Q{CMP_R_5_1 _i+1 _1D[1]}}&PHY_R_5_1 _i+1 _C_1D)|

({Q{CMP_R_5_1 _i+1 _1D[2]}}&PHY_R_5_1 _i+1 _D_1D)|

({Q{CMP_R_5_1 _i+1 _1D[3]}}&PHY_R_5_1 _i+1 _E_1D)|

({Q{CMP_R_5_1 _i+1 _1D[4]}}&PHY_R_5_1 _i+1 _F_1D)

PHY_VAL_5_0 _i+1 _1D<＝PHY_VAL_5_0 _i+1

PHY_VAL_5_1 _i+1 _1D<＝PHY_VAL_5_1 _i+1

The logical expression of the destination register is as follows:

PHY_R_5_2 _i+1 _1D<＝PHY_R_5_2 _i+1

PHY_VAL_5_2 _i+1 _1D<＝PHY_VAL_5_2 _i+1

R_5_2 _i _1D<＝R_5_2 _i

1.7UOP6 renaming procedure

2 source operands of UOP6 are registered according to the architecture of each source operandThe register number refers to the RAT table, and it is also required to determine whether the architecture register numbers of 2 source operands of UOP6 are the same as the architecture numbers of destination registers of UOP5, UOP4, UOP3, UOP2, UOP1 and UOP0, i.e. R_6_0 _i+1 And R_6_1 _i+1 Whether or not to be equal to R_5_2 _i+1 ，R_4_2 _i+1 ，R_3_2 _i+1 ，R_2_2 _i+1 ，R_1_2 _i+1 Or R_0_2 _i+1 The same applies. If the architectural register number of the 2 source operands of UOP6 is the same as the architectural number of the destination registers of UOP5, UOP4, UOP3, UOP2, UOP1 or UOP0, then the physical register mapped by the architectural register numbers of the 2 source operands of UOP6 is the physical register corresponding to the destination register of UOP5, UOP4, UOP3, UOP2, UOP1 or UOP 0. If a certain source register of UOP6 is related to the simultaneous existence of RAW of UOP5, UOP4, UOP3, UOP2, UOP1 and UOP0, the physical register of the source register of UOP6 takes the physical register number corresponding to the destination register of UOP5 according to the priority order.

The source register number of UOP6 falls into 7 cases: 1, assuming UOP6 is associated with UOP5, UOP4, UOP3, UOP2, UOP1 and UOP0 that there is no RAW correlation; 2, assuming that UOP6 is associated with UOP0 in the presence of RAW, and UOP6 is associated with UOP5, UOP4, UOP3, UOP2, UOP1 in the absence of RAW; 3, assuming UOP6 is associated with UOP1 that there is a RAW, and UOP5, UOP4, UOP3, UOP2 that there is no RAW; 4, assuming that UOP6 is associated with UOP2 in the presence of RAW, and UOP6 is associated with UOP5, UOP4, UOP3 in the absence of RAW; 5, assuming that UOP6 is associated with UOP3 with a RAW, and UOP6 is associated with UOP5, UOP4 with no RAW; 6, assuming that UOP6 is associated with UOP4 with a RAW, and UOP6 is associated with UOP5 with no RAW; 7, suppose UOP6 is related to UOP5 that there is a RAW. 7 physical registers of each source register are obtained in the renaming stage 1, and simultaneously correlations of UOP6, UOP5, UOP4, UOP3, UOP2, UOP1 and UOP0 are judged in parallel; the correct result is selected from the 7 physical register numbers of each source register according to the dependency logic in stage 2 of renaming.

1.7.1 assume that UOP6 is not related to UOP5, UOP4, UOP3, UOP2, UOP1 and UOP0 with RAW

When UOP6 is associated with UOP5, UOP4, UOP3, UOP2, UOP1 and UOP0, there is no RAW correlation, the mapping procedure of UOP6 is similar to that of UOP 0. The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

Logical expression PHY_R_6_0 of 1 st source operand _i+1 A is as follows:

PHY_R_6_0 _i+1 _A＝({Q{(PRV _i _1D[0]&(R_6_0 _i+1 ＝＝R_0_2 _i _1D))}}&PHY_R_0_2 _i _1D)|

({Q{(PRV _i _1D[1]&(R_6_0 _i+1 ＝＝R_1_2 _i _1D))}}&PHY_R_1_2 _i _1D)|

({Q{(PRV _i _1D[2]&(R_6_0 _i+1 ＝＝R_2_2 _i _1D))}}&PHY_R_2_2 _i _1D)|

({Q{(PRV _i _1D[3]&(R_6_0 _i+1 ＝＝R_3_2 _i _1D))}}&PHY_R_3_2 _i _1D)|

({Q{(PRV _i _1D[4]&(R_6_0 _i+1 ＝＝R_4_2 _i _1D))}}&PHY_R_4_2 _i _1D)|

({Q{(PRV _i _1D[5]&(R_6_0 _i+1 ＝＝R_5_2 _i _1D))}}&PHY_R_5_2 _i _1D)|

({Q{(PRV _i _1D[6]&(R_6_0 _i+1 ＝＝R_6_2 _i _1D))}}&PHY_R_6_2 _i _1D)|

({Q{(PRV _i _1D[7]&(R_6_0 _i+1 ＝＝R_7_2 _i _1D))}}&PHY_R_7_2 _i _1D)|

({Q{(～(|PRV _i _1D))}}&RAT[R_6_0 _i+1 ][Q-1:0])

PHY_VAL_6_0 _i+1 ＝VAL_6_0 _i+1

similarly, the logical expression PHY_R_6_1 of the 2 nd source operand _i+1 A is as follows:

PHY_R_6_1 _i+1 _A＝({Q{(PRV _i _1D[0]&(R_6_1 _i+1 ＝＝R_0_2 _i _1D))}}&PHY_R_0_2 _i _1D)|

({Q{(PRV _i _1D[1]&(R_6_1 _i+1 ＝＝R_1_2 _i _1D))}}&PHY_R_1_2 _i _1D)|

({Q{(PRV _i _1D[2]&(R_6_1 _i+1 ＝＝R_2_2 _i _1D))}}&PHY_R_2_2 _i _1D)|

({Q{(PRV _i _1D[3]&(R_6_1 _i+1 ＝＝R_3_2 _i _1D))}}&PHY_R_3_2 _i _1D)|

({Q{(PRV _i _1D[4]&(R_6_1 _i+1 ＝＝R_4_2 _i _1D))}}&PHY_R_4_2 _i _1D)|

({Q{(PRV _i _1D[5]&(R_6_1 _i+1 ＝＝R_5_2 _i _1D))}}&PHY_R_5_2 _i _1D)|

({Q{(PRV _i _1D[6]&(R_6_1 _i+1 ＝＝R_6_2 _i _1D))}}&PHY_R_6_2 _i _1D)|

({Q{(PRV _i _1D[7]&(R_6_1 _i+1 ＝＝R_7_2 _i _1D))}}&PHY_R_7_2 _i _1D)|

({Q{(～(|PRV _i _1D))}}&RAT[R_6_1 _i+1 ][Q-1:0])

PHY_VAL_6_1 _i+1 ＝VAL_6_1 _i+1

1.7.2 assume that UOP6 is related to UOP0 for the presence of RAW and that UOP6 is related to UOP5, UOP4, UOP3, UOP2, UOP1 for the absence of RAW

When UOP6 is associated with UOP0 in the presence of a RAW and UOP6 is associated with UOP5, UOP4, UOP3, UOP2, UOP1 in the absence of a RAW, i.e., the destination register of UOP0 is the same as the meta register architectural register number of UOP6 and is not the same as the destination register numbers of UOP5, UOP4, UOP3, UOP2, UOP 1. The physical register number of the UOP6 source register is the physical register number newly allocated to the UOP0 destination register.

The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

logical expression PHY_R_6_0 of 1 st source operand _i+1 B is as follows:

PHY_R_6_0 _i+1 _B＝PHY_R_0_2 _i+1

similarly, the logical expression PHY_R_6_1 of the 2 nd source operand _i+1 B is as follows:

PHY_R_6_1 _i+1 _B＝PHY_R_0_2 _i+1

the valid identification of the source register is the same as that for UOP6 and UOP0, where no correlation exists.

1.7.3 assume that UOP6 is related to UOP1 that there is a RAW, and that UOP6 is related to UOP5, UOP4, UOP3, UOP2 that there is no RAW

When UOP6 is associated with UOP1 with no RAW, UOP6 is associated with UOP5, UOP4, UOP3, UOP2, i.e., the destination register of UOP1 is the same as the meta register architectural register number of UOP6 and is not the same as the destination register numbers of UOP5, UOP4, UOP3, UOP 2. The physical register number of the UOP6 source register is the physical register number newly allocated to the UOP1 destination register.

The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

logical expression PHY_R_6_0 of 1 st source operand _i+1 C is as follows:

PHY_R_6_0 _i+1 _C＝PHY_R_1_2 _i+1

similarly, the logical expression PHY_R_6_1 of the 2 nd source operand _i+1 C is as follows:

PHY_R_6_1 _i+1 _C＝PHY_R_1_2 _i+1

the valid identification of the source register is the same as that for UOP6 and UOP0, where no correlation exists.

1.7.4 assume that UOP6 is related to UOP2 that there is a RAW, and UOP6 is related to UOP5, UOP4, UOP3 that there is no RAW

When UOP6 is associated with UOP2 in the presence of a RAW and UOP6 is associated with UOP5, UOP4, UOP3 in the absence of a RAW, i.e., the destination register of UOP2 is the same as the meta register architectural register number of UOP6 and is not the same as the destination register numbers of UOP5, UOP4, UOP 3. The physical register number of the UOP6 source register is the physical register number newly allocated to the UOP2 destination register.

The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

logical expression PHY_R_6_0 of 1 st source operand _i+1 The_d is as follows:

PHY_R_6_0 _i+1 _D＝PHY_R_2_2 _i+1

similarly, the logical expression PHY_R_6_1 of the 2 nd source operand _i+1 The_d is as follows:

PHY_R_6_1 _i+1 _D＝PHY_R_2_2 _i+1

1.7.5 it is assumed that UOP6 is associated with UOP3 that there is a RAW, and UOP6 is associated with UOP5, UOP4 that there is no RAW

When UOP6 is associated with UOP3 in the presence of a RAW and UOP6 is associated with UOP5, UOP4 in the absence of a RAW, i.e., the destination register of UOP3 is the same as the meta register architectural register number of UOP6 and is not the same as the destination register number of UOP5, UOP 4. The physical register number of the UOP6 source register is the physical register number newly allocated to the UOP3 destination register.

The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

logical expression PHY_R_6_0 of 1 st source operand _i+1 E is as follows:

PHY_R_6_0 _i+1 _E＝PHY_R_3_2 _i+1

similarly, the logical expression PHY_R_6_1 of the 2 nd source operand _i+1 E is as follows:

PHY_R_6_1 _i+1 _E＝PHY_R_3_2 _i+1

1.7.6 it is assumed that UOP6 is correlated with UOP4 in the presence of RAW, and UOP6 is correlated with UOP5 in the absence of RAW

When UOP6 and UOP4 are associated with a RAW, i.e., the destination register of UOP4 is the same as the meta register architectural register number of UOP6, and UOP6 and UOP5 are not associated with a RAW. The physical register number of the UOP6 source register is the physical register number newly allocated to the UOP4 destination register.

The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

logical expression PHY_R_6_0 of 1 st source operand _i+1 F is as follows:

PHY_R_6_0 _i+1 _F＝PHY_R_4_2 _i+1

similarly, the logical expression PHY_R_6_1 of the 2 nd source operand _i+1 F is as follows:

PHY_R_6_1 _i+1 _F＝PHY_R_4_2 _i+1

1.7.7 suppose that UOP6 and UOP5 are related by the existence of a RAW

When UOP6 and UOP5 are associated with a RAW, i.e., the destination register of UOP5 is the same as the meta register architectural register number of UOP 6. The physical register number of the UOP6 source register is the physical register number newly allocated to the UOP5 destination register.

The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

logical expression PHY_R_6_0 of 1 st source operand _i+1 G is as follows:

PHY_R_6_0 _i+1 _G＝PHY_R_5_2 _i+1

similarly, the logical expression PHY_R_6_1 of the 2 nd source operand _i+1 G is as follows:

PHY_R_6_1 _i+1 _G＝PHY_R_5_2 _i+1

1.7.8 determining whether UOP6 and UOP5, UOP4, UOP3, UOP2, UOP1 and UOP0 have RAW-related logic

Judging whether UOP6 is related to UOP0 by RAW and is related to UOP5, UOP4, UOP3, UOP2 and UOP1 by not RAW, only comparing whether the source register number of UOP6 is identical to the destination register number of UOP0 or not, and judging whether the source register number of UOP6 is identical to the destination register number of UOP5, UOP4, UOP3, UOP2 and UOP1, wherein the 2 source register judgment logic expression is as follows:

selection logic CMP_R_6_0 for 1 st source operand _i+1 [5:0]The logical expression is as follows:

CMP_R_6_0 _i+1 [0]＝((R_6_0 _i+1 ＝＝R_0_2 _i+1 )&VAL_6_0&VAL_0_2)&

(～((R_6_0 _i+1 ＝＝R_1_2 _i+1 )&VAL_6_0&VAL_1_2))&

(～((R_6_0 _i+1 ＝＝R_2_2 _i+1 )&VAL_6_0&VAL_2_2))&

(～((R_6_0 _i+1 ＝＝R_3_2 _i+1 )&VAL_6_0&VAL_3_2))&

(～((R_6_0 _i+1 ＝＝R_4_2 _i+1 )&VAL_6_0&VAL_4_2))&

(～((R_6_0 _i+1 ＝＝R_5_2 _i+1 )&VAL_6_0&VAL_5_2))

CMP_R_6_0 _i+1 [1]＝((R_6_0 _i+1 ＝＝R_1_2 _i+1 )&VAL_6_0&VAL_1_2)&

(～((R_6_0 _i+1 ＝＝R_2_2 _i+1 )&VAL_6_0&VAL_2_2))&

(～((R_6_0 _i+1 ＝＝R_3_2 _i+1 )&VAL_6_0&VAL_3_2))&

(～((R_6_0 _i+1 ＝＝R_4_2 _i+1 )&VAL_6_0&VAL_4_2))&

(～((R_6_0 _i+1 ＝＝R_5_2 _i+1 )&VAL_6_0&VAL_5_2))

CMP_R_6_0 _i+1 [2]＝((R_6_0 _i+1 ＝＝R_2_2 _i+1 )&VAL_6_0&VAL_2_2)&

(～((R_6_0 _i+1 ＝＝R_3_2 _i+1 )&VAL_6_0&VAL_3_2))&

(～((R_6_0 _i+1 ＝＝R_4_2 _i+1 )&VAL_6_0&VAL_4_2))&

(～((R_6_0 _i+1 ＝＝R_5_2 _i+1 )&VAL_6_0&VAL_5_2))

CMP_R_6_0 _i+1 [3]＝((R_6_0 _i+1 ＝＝R_3_2 _i+1 )&VAL_6_0&VAL_3_2)&

(～((R_6_0 _i+1 ＝＝R_4_2 _i+1 )&VAL_6_0&VAL_4_2))&

(～((R_6_0 _i+1 ＝＝R_5_2 _i+1 )&VAL_6_0&VAL_5_2))

CMP_R_6_0 _i+1 [4]＝((R_6_0 _i+1 ＝＝R_4_2 _i+1 )&VAL_6_0&VAL_4_2)&

(～((R_6_0 _i+1 ＝＝R_5_2 _i+1 )&VAL_6_0&VAL_5_2))

CMP_R_6_0 _i+1 [5]＝((R_6_0 _i+1 ＝＝R_5_2 _i+1 )&VAL_6_0&VAL_5_2)

selection logic CMP_R_6_1 of 2 nd source operand _i+1 [5:0]The logical expression is as follows:

CMP_R_6_1 _i+1 [0]＝((R_6_1 _i+1 ＝＝R_0_2 _i+1 )&VAL_6_1&VAL_0_2)&

(～((R_6_1 _i+1 ＝＝R_1_2 _i+1 )&VAL_6_1&VAL_1_2))&

(～((R_6_1 _i+1 ＝＝R_2_2 _i+1 )&VAL_6_1&VAL_2_2))&

(～((R_6_1 _i+1 ＝＝R_3_2 _i+1 )&VAL_6_1&VAL_3_2))&

(～((R_6_1 _i+1 ＝＝R_4_2 _i+1 )&VAL_6_1&VAL_4_2))&

(～((R_6_1 _i+1 ＝＝R_5_2 _i+1 )&VAL_6_1&VAL_5_2))

CMP_R_6_1 _i+1 [1]＝((R_6_1 _i+1 ＝＝R_1_2 _i+1 )&VAL_6_1&VAL_1_2)&

(～((R_6_1 _i+1 ＝＝R_2_2 _i+1 )&VAL_6_1&VAL_2_2))&

(～((R_6_1 _i+1 ＝＝R_3_2 _i+1 )&VAL_6_1&VAL_3_2))&

(～((R_6_1 _i+1 ＝＝R_4_2 _i+1 )&VAL_6_1&VAL_4_2))&

(～((R_6_1 _i+1 ＝＝R_5_2 _i+1 )&VAL_6_1&VAL_5_2))

CMP_R_6_1 _i+1 [2]＝((R_6_1 _i+1 ＝＝R_2_2 _i+1 )&VAL_6_1&VAL_2_2)&

(～((R_6_1 _i+1 ＝＝R_3_2 _i+1 )&VAL_6_1&VAL_3_2))&

(～((R_6_1 _i+1 ＝＝R_4_2 _i+1 )&VAL_6_1&VAL_4_2))&

(～((R_6_1 _i+1 ＝＝R_5_2 _i+1 )&VAL_6_1&VAL_5_2))

CMP_R_6_1 _i+1 [3]＝((R_6_1 _i+1 ＝＝R_3_2 _i+1 )&VAL_6_1&VAL_3_2)&

(～((R_6_1 _i+1 ＝＝R_4_2 _i+1 )&VAL_6_1&VAL_4_2))&

(～((R_6_1 _i+1 ＝＝R_5_2 _i+1 )&VAL_6_1&VAL_5_2))

CMP_R_6_1 _i+1 [4]＝((R_6_1 _i+1 ＝＝R_4_2 _i+1 )&VAL_6_1&VAL_4_2)&

(～((R_6_1 _i+1 ＝＝R_5_2 _i+1 )&VAL_6_1&VAL_5_2))

CMP_R_6_1 _i+1 [5]＝((R_6_1 _i+1 ＝＝R_5_2 _i+1 )&VAL_6_1&VAL_5_2)

the i+1th cycle instruction phase 2 source operands and destination architecture registers map to physical register calculation process:

PHY_R_6_0 _i+1 _A_1D<＝PHY_R_6_0 _i+1 _A

PHY_R_6_0 _i+1 _B_1D<＝PHY_R_6_0 _i+1 _B

PHY_R_6_0 _i+1 _C_1D<＝PHY_R_6_0 _i+1 _C

PHY_R_6_0 _i+1 _D_1D<＝PHY_R_6_0 _i+1 _D

PHY_R_6_0 _i+1 _E_1D<＝PHY_R_6_0 _i+1 _E

PHY_R_6_0 _i+1 _F_1D<＝PHY_R_6_0 _i+1 _F

PHY_R_6_0 _i+1 _G_1D<＝PHY_R_6_0 _i+1 _G

PHY_R_6_1 _i+1 _A_1D<＝PHY_R_6_1 _i+1 _A

PHY_R_6_1 _i+1 _B_1D<＝PHY_R_6_1 _i+1 _B

PHY_R_6_1 _i+1 _C_1D<＝PHY_R_6_1 _i+1 _C

PHY_R_6_1 _i+1 _D_1D<＝PHY_R_6_1 _i+1 _D

PHY_R_6_1 _i+1 _E_1D<＝PHY_R_6_1 _i+1 _E

PHY_R_6_1 _i+1 _F_1D<＝PHY_R_6_1 _i+1 _F

PHY_R_6_1 _i+1 _G_1D<＝PHY_R_6_1 _i+1 _G

CMP_R_6_0 _i+1 _1D<＝CMP_R_6_0 _i+1

CMP_R_6_1 _i+1 _1D<＝CMP_R_6_1 _i+1

physical register PHY_R_6_0 for 1 st source operand final _i+1 1D, the correct physical register is selected according to the selection logic.

PHY_R_6_0 _i+1 _1D＝({Q{(～(|CMP_R_6_0 _i+1 _1D))}}&PHY_R_6_0 _i+1 _A_1D)|

({Q{CMP_R_6_0 _i+1 _1D[0]}}&PHY_R_6_0 _i+1 _B_1D)|

({Q{CMP_R_6_0 _i+1 _1D[1]}}&PHY_R_6_0 _i+1 _C_1D)|

({Q{CMP_R_6_0 _i+1 _1D[2]}}&PHY_R_6_0 _i+1 _D_1D)|

({Q{CMP_R_6_0 _i+1 _1D[3]}}&PHY_R_6_0 _i+1 _E_1D)|

({Q{CMP_R_6_0 _i+1 _1D[4]}}&PHY_R_6_0 _i+1 _F_1D)|

({Q{CMP_R_6_0 _i+1 _1D[5]}}&PHY_R_6_0 _i+1 _G_1D)

Physical register PHY_R_6_1 of the 2 nd source operand final _i+1 1D, the correct physical register is selected according to the selection logic.

PHY_R_6_1 _i+1 _1D＝({Q{(～(|CMP_R_6_1 _i+1 _1D))}}&PHY_R_6_1 _i+1 _A_1D)|

({Q{CMP_R_6_1 _i+1 _1D[0]}}&PHY_R_6_1 _i+1 _B_1D)|

({Q{CMP_R_6_1 _i+1 _1D[1]}}&PHY_R_6_1 _i+1 _C_1D)|

({Q{CMP_R_6_1 _i+1 _1D[2]}}&PHY_R_6_1 _i+1 _D_1D)|

({Q{CMP_R_6_1 _i+1 _1D[3]}}&PHY_R_6_1 _i+1 _E_1D)|

({Q{CMP_R_6_1 _i+1 _1D[4]}}&PHY_R_6_1 _i+1 _F_1D)|

({Q{CMP_R_6_1 _i+1 _1D[5]}}&PHY_R_6_1 _i+1 _G_1D)

PHY_VAL_6_0 _i+1 _1D<＝PHY_VAL_6_0 _i+1

PHY_VAL_6_1 _i+1 _1D<＝PHY_VAL_6_1 _i+1

The logical expression of the destination register is as follows:

PHY_R_6_2 _i+1 _1D<＝PHY_R_6_2 _i+1

PHY_VAL_6_2 _i+1 _1D<＝PHY_VAL_6_2 _i+1

R_6_2 _i _1D<＝R_6_2 _i

1.8UOP7 renaming procedure

The 2 source operands of UOP7 query the RAT table according to the architecture register number of each source operand, and it is also necessary to determine whether the architecture register numbers of the 2 source operands of UOP7 are the same as those of the destination registers of UOP6, UOP5, UOP4, UOP3, UOP2, UOP1 and UOP0, i.e. it is necessary to determine r_7_0 _i+1 And R_7_1 _i+1 Whether or not to R_6_2 _i+1 ，R_5_2 _i+1 ，R_4_2 _i+1 ，R_3_2 _i+1 ，R_2_2 _i+1 ，R_1_2 _i+1 Or R_0_2 _i+1 The same applies. If the architectural register number of the 2 source operands of UOP7 is the same as the architectural number of the destination registers of UOP6, UOP5, UOP4, UOP3, UOP2, UOP1 or UOP0, then the physical register mapped by the architectural register number of the 2 source operands of UOP7 is the physical register corresponding to the destination register of UOP6, UOP5, UOP4, UOP3, UOP2, UOP1 or UOP 0. If a certain source register of UOP7 is related to the simultaneous existence of RAW of UOP6, UOP5, UOP4, UOP3, UOP2, UOP1 and UOP0, the physical register of the source register of UOP7 takes the physical register number corresponding to the destination register of UOP6 according to the priority order.

The source register number of UOP7 is divided into 8 cases: 1, assuming that UOP7 is not related to UOP6, UOP5, UOP4, UOP3, UOP2, UOP1 and UOP0 with no RAW; 2, assuming that UOP7 is associated with UOP0 in the presence of a RAW, and UOP7 is associated with UOP6, UOP5, UOP4, UOP3, UOP2, UOP1 in the absence of a RAW; 3, assuming UOP7 is associated with UOP1 that there is a RAW, and UOP6, UOP5, UOP4, UOP3, UOP2 that there is no RAW; 4, assuming that UOP7 is associated with UOP2 in the presence of a RAW, and UOP7 is associated with UOP6, UOP5, UOP4, UOP3 in the absence of a RAW; 5, assuming that UOP7 is associated with UOP3 in the presence of RAW, and UOP7 is associated with UOP6, UOP5, UOP4 in the absence of RAW; 6, assuming that UOP7 is associated with UOP4 in the presence of RAW, and UOP7 is associated with UOP6, UOP5 in the absence of RAW; 7, assuming that UOP7 is associated with UOP5 with a RAW, and UOP7 is associated with UOP6 with no RAW; 8, suppose UOP7 is related to UOP6 that there is a RAW. Obtaining 8 physical registers of each source register in a renaming stage 1, and simultaneously judging the correlations of UOP7, UOP6, UOP5, UOP4, UOP3, UOP2, UOP1 and UOP0 in parallel; the correct result is selected from the 8 physical register numbers of each source register according to the dependency logic in stage 2 of renaming.

1.8.1 assuming that UOP7 is not related to UOP6, UOP5, UOP4, UOP3, UOP2, UOP1 and UOP0 to have no RAW

When UOP7 is associated with UOP6, UOP5, UOP4, UOP3, UOP2, UOP1 and UOP0 without a RAW correlation, the mapping procedure of UOP7 is similar to that of UOP 0. The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

logical expression PHY_R_7_0 of 1 st source operand _i+1 A is as follows:

PHY_R_7_0 _i+1 _A＝({Q{(PRV _i _1D[0]&(R_7_0 _i+1 ＝＝R_0_2 _i _1D))}}&PHY_R_0_2 _i _1D)|

({Q{(PRV _i _1D[1]&(R_7_0 _i+1 ＝＝R_1_2 _i _1D))}}&PHY_R_1_2 _i _1D)|

({Q{(PRV _i _1D[2]&(R_7_0 _i+1 ＝＝R_2_2 _i _1D))}}&PHY_R_2_2 _i _1D)|

({Q{(PRV _i _1D[3]&(R_7_0 _i+1 ＝＝R_3_2 _i _1D))}}&PHY_R_3_2 _i _1D)|

({Q{(PRV _i _1D[4]&(R_7_0 _i+1 ＝＝R_4_2 _i _1D))}}&PHY_R_4_2 _i _1D)|

({Q{(PRV _i _1D[5]&(R_7_0 _i+1 ＝＝R_5_2 _i _1D))}}&PHY_R_5_2 _i _1D)|

({Q{(PRV _i _1D[6]&(R_7_0 _i+1 ＝＝R_6_2 _i _1D))}}&PHY_R_6_2 _i _1D)|

({Q{(PRV _i _1D[7]&(R_7_0 _i+1 ＝＝R_7_2 _i _1D))}}&PHY_R_7_2 _i _1D)|

({Q{(～(|PRV _i _1D))}}&RAT[R_7_0 _i+1 ][Q-1:0])

PHY_VAL_7_0 _i+1 ＝VAL_7_0 _i+1

similarly, the logical expression PHY_R_7_1 of the 2 nd source operand _i+1 A is as follows:

PHY_R_7_1 _i+1 _A＝({Q{(PRV _i _1D[0]&(R_7_1 _i+1 ＝＝R_0_2 _i _1D))}}&PHY_R_0_2 _i _1D)|

({Q{(PRV _i _1D[1]&(R_7_1 _i+1 ＝＝R_1_2 _i _1D))}}&PHY_R_1_2 _i _1D)|

({Q{(PRV _i _1D[2]&(R_7_1 _i+1 ＝＝R_2_2 _i _1D))}}&PHY_R_2_2 _i _1D)|

({Q{(PRV _i _1D[3]&(R_7_1 _i+1 ＝＝R_3_2 _i _1D))}}&PHY_R_3_2 _i _1D)|

({Q{(PRV _i _1D[4]&(R_7_1 _i+1 ＝＝R_4_2 _i _1D))}}&PHY_R_4_2 _i _1D)|

({Q{(PRV _i _1D[5]&(R_7_1 _i+1 ＝＝R_5_2 _i _1D))}}&PHY_R_5_2 _i _1D)|

({Q{(PRV _i _1D[6]&(R_7_1 _i+1 ＝＝R_6_2 _i _1D))}}&PHY_R_6_2 _i _1D)|

({Q{(PRV _i _1D[7]&(R_7_1 _i+1 ＝＝R_7_2 _i _1D))}}&PHY_R_7_2 _i _1D)|

({Q{(～(|PRV _i _1D))}}&RAT[R_7_1 _i+1 ][Q-1:0])

PHY_VAL_7_1 _i+1 ＝VAL_7_1 _i+1

1.8.2 assume that UOP7 is related to UOP0 for the presence of RAW and that UOP7 is related to UOP6, UOP5, UOP4, UOP3, UOP2, UOP1 for the absence of RAW

When UOP7 is associated with UOP0 in the presence of a RAW and UOP7 is associated with UOP6, UOP5, UOP4, UOP3, UOP2, UOP1 in the absence of a RAW, i.e., the destination register of UOP0 is the same as the meta register architectural register number of UOP7 and is not the same as the destination register number of UOP6, UOP5, UOP4, UOP3, UOP2, UOP 1. The physical register number of the UOP7 source register is the physical register number newly allocated to the UOP0 destination register.

The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

logical expression PHY_R_7_0 of 1 st source operand _i+1 B is as follows:

PHY_R_7_0 _i+1 _B＝PHY_R_0_2 _i+1

similarly, the logical expression PHY_R_7_1 of the 2 nd source operand _i+1 B is as follows:

PHY_R_7_1 _i+1 _B＝PHY_R_0_2 _i+1

the valid identification of the source register is the same as that for UOP7 and UOP0, where no correlation exists.

1.8.3 it is assumed that UOP7 is associated with UOP1 that there is a RAW, and that UOP7 is associated with UOP6, UOP5, UOP4, UOP3, UOP2 that there is no RAW

When UOP7 is associated with UOP1 in the presence of a RAW and UOP7 is associated with UOP6, UOP5, UOP4, UOP3, UOP2 in the absence of a RAW, i.e., the destination register of UOP1 is the same as the meta register architectural register number of UOP7 and is not the same as the destination register numbers of UOP6, UOP5, UOP4, UOP3, UOP 2. The physical register number of the UOP7 source register is the physical register number newly allocated to the UOP1 destination register.

The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

logical expression PHY_R_7_0 of 1 st source operand _i+1 C is as follows:

PHY_R_7_0 _i+1 _C＝PHY_R_1_2 _i+1

similarly, the logical expression PHY_R_7_1 of the 2 nd source operand _i+1 C is as follows:

PHY_R_7_1 _i+1 _C＝PHY_R_1_2 _i+1

the valid identification of the source register is the same as that for UOP7 and UOP0, where no correlation exists.

1.8.4 it is assumed that UOP7 is associated with UOP2 that there is a RAW, and that UOP7 is associated with UOP6, UOP5, UOP4, UOP3 that there is no RAW

When UOP7 is associated with UOP2 in the presence of a RAW and UOP7 is associated with UOP6, UOP5, UOP4, UOP3 in the absence of a RAW, i.e., the destination register of UOP2 is the same as the meta register architectural register number of UOP7 and is not the same as the destination register numbers of UOP6, UOP5, UOP4, UOP 3. The physical register number of the UOP7 source register is the physical register number newly allocated to the UOP2 destination register.

The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

logical expression PHY_R_7_0 of 1 st source operand _i+1 The_d is as follows:

PHY_R_7_0 _i+1 _D＝PHY_R_2_2 _i+1

similarly, the logical expression PHY_R_7_1 of the 2 nd source operand _i+1 The_d is as follows:

PHY_R_7_1 _i+1 _D＝PHY_R_2_2 _i+1

1.8.5 it is assumed that UOP7 is associated with UOP3 that there is a RAW, and UOP7 is associated with UOP6, UOP5, UOP4 that there is no RAW

When UOP7 is associated with UOP3 in the presence of a RAW and UOP7 is associated with UOP6, UOP5, UOP4 in the absence of a RAW, i.e., the destination register of UOP3 is the same as the meta register architectural register number of UOP7 and is not the same as the destination register numbers of UOP6, UOP5, UOP 4. The physical register number of the UOP7 source register is the physical register number newly allocated to the UOP3 destination register.

The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

logical expression PHY_R_7_0 of 1 st source operand _i+1 E is as follows:

PHY_R_7_0 _i+1 _E＝PHY_R_3_2 _i+1

similarly, the logical expression PHY_R_7_1 of the 2 nd source operand _i+1 E is as follows:

PHY_R_7_1 _i+1 _E＝PHY_R_3_2 _i+1

1.8.6 assume that UOP7 is related to UOP4 where there is a RAW, and UOP7 is related to UOP6 where UOP5 is not related to the RAW

When UOP7 is associated with UOP4 in the presence of a RAW, i.e., the destination register of UOP4 is the same as the meta register architectural register number of UOP7, and UOP7 is associated with UOP6, UOP5 is not in the presence of a RAW. The physical register number of the UOP7 source register is the physical register number newly allocated to the UOP4 destination register.

The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

logical expression PHY_R_7_0 of 1 st source operand _i+1 F is as follows:

PHY_R_7_0 _i+1 _F＝PHY_R_4_2 _i+1

similarly, the logical expression PHY_R_7_1 of the 2 nd source operand _i+1 F is as follows:

PHY_R_7_1 _i+1 _F＝PHY_R_4_2 _i+1

1.8.7 it is assumed that UOP7 is correlated with UOP5 that there is a RAW, and UOP7 is correlated with UOP6 that there is no RAW

When UOP7 is associated with UOP5 with no RAW present and UOP7 is associated with UOP6 with no RAW present, i.e. the destination register of UOP5 is the same as the meta register architectural register number of UOP7 and UOP7 is associated with UOP6 with no RAW present. The physical register number of the UOP7 source register is the physical register number newly allocated to the UOP5 destination register.

The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

logical expression PHY_R_7_0 of 1 st source operand _i+1 G is as follows:

PHY_R_7_0 _i+1 _G＝PHY_R_5_2 _i+1

similarly, the logical expression PHY_R_7_1 of the 2 nd source operand _i+1 G is as follows:

PHY_R_7_1 _i+1 _G＝PHY_R_5_2 _i+1

1.8.8 suppose that UOP7 is related to UOP6 in the presence of RAW

When UOP7 and UOP6 are associated with a RAW, i.e., the destination register of UOP6 is the same as the meta register architectural register number of UOP 7. The physical register number of the UOP7 source register is the physical register number newly allocated to the UOP6 destination register.

The i+1st cycle instruction phase 1 2 source operands and destination architecture registers map to physical register calculation process:

logical expression PHY_R_7_0 of 1 st source operand _i+1 H is as follows:

PHY_R_7_0 _i+1 _H＝PHY_R_5_2 _i+1

similarly, the logical expression PHY_R_7_1 of the 2 nd source operand _i+1 H is as follows:

PHY_R_7_1 _i+1 _H＝PHY_R_5_2 _i+1

1.8.9 determining that UOP7 is associated with UOP6, UOP5, UOP4, UOP3, UOP2, UOP1 and UOP0 has a RAW correlation logic determining that UOP7 is associated with UOP0 has a RAW correlation and is associated with UOP6, UOP5, UOP4, UOP3, UOP2, UOP1 has no RAW correlation, only the source register number of UOP7 needs to be compared with the destination register number of UOP0 to be the same, and the source register number of UOP7 needs to be compared with the destination register number of UOP6, UOP5, UOP4, UOP3, UOP2, UOP1 is the same, and the 2 source register determination logic expressions are as follows:

selection logic CMP_R_7_0 for 1 st source operand _i+1 [6:0]Logical expressions such asThe following steps:

CMP_R_7_0 _i+1 [0]＝((R_7_0 _i+1 ＝＝R_0_2 _i+1 )&VAL_7_0&VAL_0_2)&

(～((R_7_0 _i+1 ＝＝R_1_2 _i+1 )&VAL_7_0&VAL_1_2))&

(～((R_7_0 _i+1 ＝＝R_2_2 _i+1 )&VAL_7_0&VAL_2_2))&

(～((R_7_0 _i+1 ＝＝R_3_2 _i+1 )&VAL_7_0&VAL_3_2))&

(～((R_7_0 _i+1 ＝＝R_4_2 _i+1 )&VAL_7_0&VAL_4_2))&

(～((R_7_0 _i+1 ＝＝R_5_2 _i+1 )&VAL_7_0&VAL_5_2))&

(～((R_7_0 _i+1 ＝＝R_6_2 _i+1 )&VAL_7_0&VAL_6_2))

CMP_R_7_0 _i+1 [1]＝((R_7_0 _i+1 ＝＝R_1_2 _i+1 )&VAL_7_0&VAL_1_2)&

(～((R_7_0 _i+1 ＝＝R_2_2 _i+1 )&VAL_7_0&VAL_2_2))&

(～((R_7_0 _i+1 ＝＝R_3_2 _i+1 )&VAL_7_0&VAL_3_2))&

(～((R_7_0 _i+1 ＝＝R_4_2 _i+1 )&VAL_7_0&VAL_4_2))&

(～((R_7_0 _i+1 ＝＝R_5_2 _i+1 )&VAL_7_0&VAL_5_2))&

(～((R_7_0 _i+1 ＝＝R_6_2 _i+1 )&VAL_7_0&VAL_6_2))

CMP_R_7_0 _i+1 [2]＝((R_7_0 _i+1 ＝＝R_2_2 _i+1 )&VAL_7_0&VAL_2_2)&

(～((R_7_0 _i+1 ＝＝R_3_2 _i+1 )&VAL_7_0&VAL_3_2))&

(～((R_7_0 _i+1 ＝＝R_4_2 _i+1 )&VAL_7_0&VAL_4_2))&

(～((R_7_0 _i+1 ＝＝R_5_2 _i+1 )&VAL_7_0&VAL_5_2))&

(～((R_7_0 _i+1 ＝＝R_6_2 _i+1 )&VAL_7_0&VAL_6_2))

CMP_R_7_0 _i+1 [3]＝((R_7_0 _i+1 ＝＝R_3_2 _i+1 )&VAL_7_0&VAL_3_2)&

(～((R_7_0 _i+1 ＝＝R_4_2 _i+1 )&VAL_7_0&VAL_4_2))&

(～((R_7_0 _i+1 ＝＝R_5_2 _i+1 )&VAL_7_0&VAL_5_2))&

(～((R_7_0 _i+1 ＝＝R_6_2 _i+1 )&VAL_7_0&VAL_6_2))

CMP_R_7_0 _i+1 [4]＝((R_7_0 _i+1 ＝＝R_4_2 _i+1 )&VAL_7_0&VAL_4_2)&

(～((R_7_0 _i+1 ＝＝R_5_2 _i+1 )&VAL_7_0&VAL_5_2))&

(～((R_7_0 _i+1 ＝＝R_6_2 _i+1 )&VAL_7_0&VAL_6_2))

CMP_R_7_0 _i+1 [5]＝((R_7_0 _i+1 ＝＝R_5_2 _i+1 )&VAL_7_0&VAL_5_2)&

(～((R_7_0 _i+1 ＝＝R_6_2 _i+1 )&VAL_7_0&VAL_6_2))

CMP_R_7_0 _i+1 [6]＝((R_7_0 _i+1 ＝＝R_6_2 _i+1 )&VAL_7_0&VAL_6_2)

selection logic CMP_R_7_1 of 2 nd source operand _i+1 [6:0]The logical expression is as follows:

CMP_R_7_1 _i+1 [0]＝((R_7_1 _i+1 ＝＝R_0_2 _i+1 )&VAL_7_1&VAL_0_2)&

(～((R_7_1 _i+1 ＝＝R_1_2 _i+1 )&VAL_7_1&VAL_1_2))&

(～((R_7_1 _i+1 ＝＝R_2_2 _i+1 )&VAL_7_1&VAL_2_2))&

(～((R_7_1 _i+1 ＝＝R_3_2 _i+1 )&VAL_7_1&VAL_3_2))&

(～((R_7_1 _i+1 ＝＝R_4_2 _i+1 )&VAL_7_1&VAL_4_2))&

(～((R_7_1 _i+1 ＝＝R_5_2 _i+1 )&VAL_7_1&VAL_5_2))&

(～((R_7_1 _i+1 ＝＝R_6_2 _i+1 )&VAL_7_1&VAL_6_2))

CMP_R_7_1 _i+1 [1]＝((R_7_1 _i+1 ＝＝R_1_2 _i+1 )&VAL_7_1&VAL_1_2)&

(～((R_7_1 _i+1 ＝＝R_2_2 _i+1 )&VAL_7_1&VAL_2_2))&

(～((R_7_1 _i+1 ＝＝R_3_2 _i+1 )&VAL_7_1&VAL_3_2))&

(～((R_7_1 _i+1 ＝＝R_4_2 _i+1 )&VAL_7_1&VAL_4_2))&

(～((R_7_1 _i+1 ＝＝R_5_2 _i+1 )&VAL_7_1&VAL_5_2))&

(～((R_7_1 _i+1 ＝＝R_6_2 _i+1 )&VAL_7_1&VAL_6_2))

CMP_R_7_1 _i+1 [2]＝((R_7_1 _i+1 ＝＝R_2_2 _i+1 )&VAL_7_1&VAL_2_2)&

(～((R_7_1 _i+1 ＝＝R_3_2 _i+1 )&VAL_7_1&VAL_3_2))&

(～((R_7_1 _i+1 ＝＝R_4_2 _i+1 )&VAL_7_1&VAL_4_2))&

(～((R_7_1 _i+1 ＝＝R_5_2 _i+1 )&VAL_7_1&VAL_5_2))&

(～((R_7_1 _i+1 ＝＝R_6_2 _i+1 )&VAL_7_1&VAL_6_2))

CMP_R_7_1 _i+1 [3]＝((R_7_1 _i+1 ＝＝R_3_2 _i+1 )&VAL_7_1&VAL_3_2)&

(～((R_7_1 _i+1 ＝＝R_4_2 _i+1 )&VAL_7_1&VAL_4_2))&

(～((R_7_1 _i+1 ＝＝R_5_2 _i+1 )&VAL_7_1&VAL_5_2))&

(～((R_7_1 _i+1 ＝＝R_6_2 _i+1 )&VAL_7_1&VAL_6_2))

CMP_R_7_1 _i+1 [4]＝((R_7_1 _i+1 ＝＝R_4_2 _i+1 )&VAL_7_1&VAL_4_2)&

(～((R_7_1 _i+1 ＝＝R_5_2 _i+1 )&VAL_7_1&VAL_5_2))&

(～((R_7_1 _i+1 ＝＝R_6_2 _i+1 )&VAL_7_1&VAL_6_2))

CMP_R_7_1 _i+1 [5]＝((R_7_1 _i+1 ＝＝R_5_2 _i+1 )&VAL_7_1&VAL_5_2)&

(～((R_7_1 _i+1 ＝＝R_6_2 _i+1 )&VAL_7_1&VAL_6_2))

CMP_R_7_1 _i+1 [6]＝((R_7_1 _i+1 ＝＝R_6_2 _i+1 )&VAL_7_1&VAL_6_2)

the i+1th cycle instruction phase 2 source operands and destination architecture registers map to physical register calculation process:

PHY_R_7_0 _i+1 _A_1D<＝PHY_R_7_0 _i+1 _A

PHY_R_7_0 _i+1 _B_1D<＝PHY_R_7_0 _i+1 _B

PHY_R_7_0 _i+1 _C_1D<＝PHY_R_7_0 _i+1 _C

PHY_R_7_0 _i+1 _D_1D<＝PHY_R_7_0 _i+1 _D

PHY_R_7_0 _i+1 _E_1D<＝PHY_R_7_0 _i+1 _E

PHY_R_7_0 _i+1 _F_1D<＝PHY_R_7_0 _i+1 _F

PHY_R_7_0 _i+1 _G_1D<＝PHY_R_7_0 _i+1 _G

PHY_R_7_0 _i+1 _H_1D<＝PHY_R_7_0 _i+1 _H

PHY_R_7_1 _i+1 _A_1D<＝PHY_R_7_1 _i+1 _A

PHY_R_7_1 _i+1 _B_1D<＝PHY_R_7_1 _i+1 _B

PHY_R_7_1 _i+1 _C_1D<＝PHY_R_7_1 _i+1 _C

PHY_R_7_1 _i+1 _D_1D<＝PHY_R_7_1 _i+1 _D

PHY_R_7_1 _i+1 _E_1D<＝PHY_R_7_1 _i+1 _E

PHY_R_7_1 _i+1 _F_1D<＝PHY_R_7_1 _i+1 _F

PHY_R_7_1 _i+1 _G_1D<＝PHY_R_7_1 _i+1 _G

PHY_R_7_1 _i+1 _H_1D<＝PHY_R_7_1 _i+1 _H

CMP_R_7_0 _i+1 _1D<＝CMP_R_7_0 _i+1

CMP_R_7_1 _i+1 _1D<＝CMP_R_7_1 _i+1

physical register PHY_R_7_0 for 1 st source operand final _i+1 1D, the correct physical register is selected according to the selection logic.

PHY_R_7_0 _i+1 _1D＝({Q{(～(|CMP_R_7_0 _i+1 _1D))}}&PHY_R_7_0 _i+1 _A_1D)|

({Q{CMP_R_7_0 _i+1 _1D[0]}}&PHY_R_7_0 _i+1 _B_1D)|

({Q{CMP_R_7_0 _i+1 _1D[1]}}&PHY_R_7_0 _i+1 _C_1D)|

({Q{CMP_R_7_0 _i+1 _1D[2]}}&PHY_R_7_0 _i+1 _D_1D)|

({Q{CMP_R_7_0 _i+1 _1D[3]}}&PHY_R_7_0 _i+1 _E_1D)|

({Q{CMP_R_7_0 _i+1 _1D[4]}}&PHY_R_7_0 _i+1 _F_1D)|

({Q{CMP_R_7_0 _i+1 _1D[5]}}&PHY_R_7_0 _i+1 _G_1D)|

({Q{CMP_R_7_0 _i+1 _1D[6]}}&PHY_R_7_0 _i+1 _H_1D)

Physical register PHY_R_7_1 of the 2 nd source operand final _i+1 1D, the correct physical register is selected according to the selection logic.

PHY_R_7_1 _i+1 _1D＝({Q{(～(|CMP_R_7_1 _i+1 _1D))}}&PHY_R_7_1 _i+1 _A_1D)|

({Q{CMP_R_7_1 _i+1 _1D[0]}}&PHY_R_7_1 _i+1 _B_1D)|

({Q{CMP_R_7_1 _i+1 _1D[1]}}&PHY_R_7_1 _i+1 _C_1D)|

({Q{CMP_R_7_1 _i+1 _1D[2]}}&PHY_R_7_1 _i+1 _D_1D)|

({Q{CMP_R_7_1 _i+1 _1D[3]}}&PHY_R_7_1 _i+1 _E_1D)|

({Q{CMP_R_7_1 _i+1 _1D[4]}}&PHY_R_7_1 _i+1 _F_1D)|

({Q{CMP_R_7_1 _i+1 _1D[5]}}&PHY_R_7_1 _i+1 _G_1D)|

({Q{CMP_R_7_1 _i+1 _1D[6]}}&PHY_R_7_1 _i+1 _H_1D)

PHY_VAL_7_0 _i+1 _1D<＝PHY_VAL_7_0 _i+1

PHY_VAL_7_1 _i+1 _1D<＝PHY_VAL_7_1 _i+1

The logical expression of the destination register is as follows:

PHY_R_7_2 _i+1 _1D<＝PHY_R_7_2 _i+1

PHY_VAL_7_2 _i+1 _1D<＝PHY_VAL_7_2 _i+1

R_7_2 _i _1D<＝R_7_2 _i 。

the preferred embodiments of the invention disclosed above are intended only to assist in the explanation of the invention. The preferred embodiments are not exhaustive or to limit the invention to the precise form disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.

Claims (5)

1. A method of renaming based on instruction read-after-write correlation hypotheses, comprising two stages:

stage 1: completing the reading of the RAT and judging the related attribute of the register; based on various instruction read-after-write related assumptions, obtaining a plurality of rename register maps of each source register, and simultaneously generating an onehot control signal for selecting a correct rename register in parallel; judging the related attribute of the register, specifically judging whether the architecture register number of the source operand of the current instruction is the same as the architecture number of the destination register of the last instruction;

Stage 2: selecting a final renaming register of each source register according to the onehot control signal generated in the 1 st stage, and updating the mapping relation between the architecture register and the physical register of the RAT table;

multiple renaming register results and signals for selecting final effective results are generated through hypothesized parallel, the number of the read-after-write RATs of 8 instructions is reduced, serial logic gate numbers are generated according to priority comparison, and therefore higher main frequency is obtained under the same condition;

the method is to obtain a plurality of renaming results by assuming various read-after-write correlations of the instruction, and then obtain a final result by selecting signals.

2. The method of claim 1, wherein the method does not need to directly determine the read-after-write correlation among instructions, thereby eliminating the problem of long path of combinational logic caused by priority relation among instructions, and the assumption is not limited to 1 instruction as granularity, and is applicable to any instruction granularity.

3. A renaming method based on instruction read-after-write related hypotheses as claimed in claim 1 wherein the multiple renaming register maps for each source register are obtained in stage 1 using logical expression implementations that determine each UOP rename, the logical expressions comprising logical expression implementations of various hypotheses for each instruction.

4. The method according to claim 1, wherein the invention is applicable to all processor architectures of an X86 instruction set CPU, a RISC instruction set CPU, a GPU and a DSP, to physical single core and physical multi-Core (CMP) and logical multi-core (SMT), and to servers and clusters.

5. The method of renaming based on the assumption of read-after-instruction-write according to claim 1, wherein the invention is not limited to bandwidth of instruction-level parallelism, architecture of renaming implementation, pipeline stages, process of implementation.

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