GB2352876A - Recessed gate transistor with overlying silicon on insulator straucture - Google Patents

Abstract

A trench formed in a semiconductor substrate is coated with an oxide layer, the trench is then filled with polysilicon using a blanket deposition, the polysilicon layer is then planarized to the semiconductor substrate surface in a polishing operation, thereby a recessed gate structure is formed. After forming source and drain regions in the substrate to complete a MISFET structure, an epitaxial silicon layer is grown over the device, and the epitaxial silicon layer is isolated from the devices in the underlying substrate by implanting nitrogen or oxygen gas (i e. a SIMOX process) and annealing to form an insulating layer between the substrate and the epitaxial silicon layer.

Description

1 2352876 DYNAMIC RANDOM ACCESS MEMORY

BACKGROUND OF THE INVENTION

The present invention relates to the operation and manufacture off integrated circuits. More specifically, in one embodiment, the invention provides improved dynamic random access memories (DRAMs), methods of operating dynamic random access memories and methods of making dynamic random access memories.

In the attempt to increase the number of bits on present DRAMs, methods are sought for shrinking device dimensions while still maintaining high enough capacitance in the storage capacitors so that data can be reliably stored, refreshed and read. For example, new dynamic random access memories are disclosed in Application Serial No. 08/353,788, filed December 12, 1994, and U.S. patent number 5, 396,452, each of which is hereby incorporated by reference, wherein a memory cell contains separate read and write transistors.

In another example, substantial space could be saved merely by providing smaller capacitors in present DRAMs. However, smaller capacitors are generally refreshed more often than larger capacitors, as it can be assumed that the leakage current is the same. The capacitance of a bit line is proportional to the number of bits on the bit line. -The refresh power consumption is proportional to the frequency of refresh cycles multiplied by the number of bits per bit line, where the refresh. frequency is. inversely proportional to the cell capacitor size. Therefore, the space advantages of a DRAM with smaller capacitors are mitigated by the higher power consumption of the required additional refresh cycles.

From the above examples it is seen that an improved dynamic random access memory is needed, along with improved methods of o-oerating such memories and improved methods of making such memories.

2 SU11,HARY OF T-H.-E _-7;_-N-\7ENT-LON The present Jnventicn is directed, in one em.bodimen-'E., to a -memor-v structure having short- biL- line segments. Each bit line segment is coupled to a separate block of mencry cells and a corresponding amnlifier. The bit -ed by pass transistors. The l4ne segments are se-pa-Z-at - L_ amplifiers are activated in all three modes of operation:

read mode, write mode and refresh mode, while the pass L-ransistors are enabled only in connection with data in-put. and io output. Very small cell capacitors can be used in this configuration, making it possible to use conventional gate capacitors, but power consumption is not appreciably increased. Furthermore, the speed.of the memory for read and write oDerations is faster than present DRAMs with long continuous bit lines coupled to a single amplifier.

In another aspect. of the invention a memory is provided wherein the contents of the memory can he read without anv interference from ongoing writing, reading and refreshing. The memory is structured in two tiers, meaning that in addition to a first tier, a DRAM with addressing, reading, writing and refreshing, a second tier with separate addressing from the first tier is used to read the contents of the cells in the f irst tier.

Improvee!. methods of f orming a dynamic random access memory are further provided according to the present invention. For examnle, in one aspect of the invention, a method is provided for forming a memory cell for use with programmable "Logic devices that must be cont- rolled with relatively large ca-paci-tCors. in programmable logic devices, pass transistors transfer signals between locations in the device. The controlling capacitor must be significantly larger than t-he gate capacitance of the pass transistor, so that the voltage on the controlling capacitor is relatively constant during the signal transition. A multi-layer approach to forming the memory allows the con-t-rolling capacitor to he located underneath the pass transistors and the memory cell transistors.

3 A further understanding of the nature and advantages of the inventions herein may be realized by reference to the remaining portions of the specification and the attached drawings. 5

BRIEF DESCRIPTION OF THE DRAWINGS

Figs. 1A-B show simplified block diagrams of a segmented bit line memory.

Figs. 2A-E show circuit and timing diagrams of latching and inverting amplifier circuits.

Figs. 3A-J show circuit diagrams of clamp circuits according to the present invention.

Figs. 4A-C show circuit and timing diagrams of a two inverter amplifier.

Figs. 5A-B show simplified block diagrams of controi logic circuitry for the memory of the present invention.

Figs. 6A-C show circuit and timing diagrams of a single inverter amplifier.

Figs. 7A-E show circuit and timing diagrams of alternate embodiments of amplifier and control circuits according to the present invention.

Figs. 8A-H show circuit and timing diagrams of a two-tier memory.

Figs. 9A-F show process flow and layout diagrams for wafer preparation of the memory according to the present inventionFigs. 1OA-E show alternate process flow and layout diagrams for wafer preparation of the memory according to the present invention. 30 Figs. 1 1A-C show layout diagrams of a shared bit line memory. Figs. 12A- M show circuit and timing diagrams for refresh read and write cycles in the memory of the present invention. 35 Figs. 13A-G show circuit and timing diagrams of control circuitry for the memory according to the present invention.

Figs. 1AA-C show the disab-11 ing of segmen-ts alatcve selected segments.

Fig. 15 shows E3--kM- cells with separa-te read and write word lines and a clamned amnlifier.

Figs. 16A-D show memory cells according to the present invention with a full latch amplifier in each segment.

US4 Figs. 17A-M show the result of simulations -Lng a 0.5u NMOS nrocess.

Figs. 18A-D show how an ongoing refresh cycle can be W4 interrupted at any time during the cycle -t-hout destroying the stored data.

F4--.

z,- sho a ljx%li having more than one stbrage capacitor associated with a single pair o-f -read and write transistors.

DESCRIPTION 0.:;' THE PREFERRED EMBODIMENT

Fig. 1A shows a simplified block diagram of a memory including segmented bit lines 102, made up of a read bit line BLR'and a write bit line BLW. Each bit line segment 104 is coupled to a separate block of memory cells 106 and a c-orresponding amplifier 108. Bit line sagmc---.-its 104 are separated by pass transIstors 110 in line with bit lines 102.

AmDlifiers 108 are activated in all three modes of operation,.

read mode, write niode and refresh mode. 7'-azss 'transis"t-ors 110 are enabled only in connection -with data input and output.

Address lines 112 salect the particular me-mory calls 110.5 t-o ':)e accessed. A word line decode block 114 -i:, us,----d to desired word line 116, while segment decode block 1-1-8 is used to selected a desired bit line segment 1-04.

Low order address bits select one of the word lines 116 in the segment selected by a segment decoder. The higher order address bits select a bit line segment 104. In a refresh mode, the low order bits select one word in each segment, and the segment decoder is bypassed to enable all segments. It should be noted that in an aiternative embodiment, rather than separating the address lines into low and high order bits, a single set of multiplexed address lines may be implemented. The bit lines in the selected segments that are normally clamped to a clamp level of Vdd/2 may be released to float during a period when the clamp is off. The selected word line 116 is then brought to the first ramp level, and a dummy current is turned on for the selected bit line segment 104. The voltage on the read bit line in the sec %- riment changes quickly due to the low bit line capacitance. The voltage displacement due to the cell current can actually be of the same order of magnitude as the final displacement caused by the amplifier, when its power is turned on -1-ater in io the refresh cycle. The amplifier 108 will there.-;;7ore use most of its power dissipation to bring the bit lines to the power rails. Both latch type and the inverter type amplifiers, each of which will be described further herein, can be used. As described earlier, the ramp is brought to its high level for a moment, increasing voltage on word line 116, when the high bit line has reached Vdd, completing the refresh operation before power again is turned off. In the very end of the cycle the clamp signal is applied again.

In order to read data from memory 100, all bit line segments 104 are initially disconnected, and the clamp input is brought low on all segments. This permits bit lines 102 in all segments to float. only one word line 116 in only one bit line segment 104 is selected in the read mode. When the read cycle has reached a point where amplifier 108 has been turned on and amplified the signal slightly, the bit line segments 104 on one bit line 102 are connected. The interconnected segment lines initially appear as delay lines consisting of RC elements. The capacitance C corresponds to the capacitance of the individual bit line segments 104, while the -resistance R corresponds to the impedance of the coupling transistor. This is however not a regular delay line, as each segment 104 also has its own amplifier 108. This allows a signal to proceed,rom. segment to segment very quickly while also being ammolified. in a typical memory configuration, a column decoder would select the columns to be the subjectZ of the reading or writing of dat-a. The non selected columns will still- be addressed by the word line 116 selected by the word line decoder!!4. When the aMD14--- ude on the output se=ent.

6 has reached the rails, the segment is connected by the column decoder to the outputz regi;_s-ter of the memory. in a write operalCion, data is connected via -t-he column decoder to '"he. bottom segments of the selected columns.

The write circuit forces the bottom segment separation to ba much larger than the separation of the segments in the addressed and read segment at the time of coupling the segments together. If the read data is different than 'the data to be written, two signals of different polarity will proceed in o-D-Dosite directions down the "delay line". The signal with the largest amplitude will determine the final polarity of the addressed segment.

in the refresh mode, the segments remain disconnected during -the full read-restore cycle. As mentioned above, one word line in each segment is selected by the low order address bits in the word line decoders and the segment decoder is bypassed so that all segments are activated the same way. The dummy current circuit is also activated in all segments. The control circuit in Fig. 1B clearly shows how the refresh mode differs from the read and write modes in the word line decodinz. It should be noted that if the amplifie-!,. 108 in each segment 104 consists only of an inverter, the time required for refresh may be longer than the time required for reading and writi-na. The read bit line in each segment is driven only by the difference of cell.current and dummy current. This current is increased significantly a'" the end of the cycle, but the signal on the read bit line is not enhanced by amplifier 108. In reading and writing, on the other hand, segments 104 are interconnected, so that the read bit line on the first segment is connected to the write bit line of the second segment and so on. This means that the output of one segment amplifier drives the input to the next segment amplifier in the read and write modes. The delay through the "delay line" must of course be taken into account when comparing the timing requirements. It is preferred that all modes have the same timing, as this simplifies the global control circuits.

Therefore, very small cell capa C 4 tors can be used i n this configuration, making it possible to use conventional gate capacitors. The speed of the memory for reading and writing is faster than the same type of memory with long continuous bit lines.

The addressing and control of memory 100 is shown in Fig. 1B. Memory sequence generator 140 receives memory control sianals such as Memory Request and Read/Write Enable and D-Z-ovides am-oli--Pier control signals 142. Amplifier contrci 4 tS signals 142, combined with high order segment address b-j112, are input to segment decoder control block 118 (Fig. 1A) to control a selected one of memory segments 104. Refresh counter 144 initiates a refresh cycle when necessary- The output of refresh counter 144, combined with low order word address bits, are input to word line decoder block 111 (Fig. 1A) to select a particular word line in "memory 100. Memory sequence generator 140 also generates additional control signals, such as Coul 1/0, Block Address Enable and 1/0 Latch Clamp, that are input. to a column decode block (not shown) that accesses a desired column of memory 100 for reading, writing or refreshing.

The type of amplifier 108 used depends on the application for memory 100. For the highest possible speed, where disturbance on the cell capacitor voltage is permitted to he high, a basic latching amplifier 200 coupled to memory cells 202, as shown in Fig. 2A, may be used. Memory cell 202 includes a storage capacitor 204, a write transistor 206 and a read transistor 208. 2umplifier 200 includes clamping transistors 210 and cross-couzled inverters 212. The corresponding timing diagram is shown in Fig. 2B. It should be noted that for highest speed with a given transistor size in memory cells 202, a higher initial cell current can be obtained if the threshold voltage on write transistor 206 is increased. There is of course a great advantage to using a standard CMOS Drocess f o r the memory, especially if -rlixed with logic. The segmented bit line approach and small cell capacitors 204 are pre- fferred to maint"a-i-ii the highest possible me-miory speed. in that case, '"he segnents would be coupled toget-her just after amplifier 108 has been mcwe-red un. in onera---on of 4-he memory shown in Fig. 2A, at the "-L L L. %_ 4 end of a memory cycle, the power to the amDli-fiez- is tu_rned off and VC:,-AYP is turned on, clamping the bit lines to the clamp voltage level (VCLA-MPL), which is ty-pically about ha _Lff of the Vdd level. At '"he beginning of a new memory cycle, VCLAMP is brought low, allowing the b4t lines BLR and BLW to float. VWL is then brought to an intem-mediate level that is at leas-'%-high enough to draw current from t-he read bit line BLR_ if the voltage on cell capacitor 204 is high (a stored ONE). If, on the other hand, the voltage on cell capacitor 204 is low (a stored ZERO), an eXcessively high signal level on VWL will charge '"he cell capacitor through writL_-e transistor 206 during the read portion of the cycle. A slight increase of the cell voltage while reading a stored ZERO from cell capacitor 204 is acceptable since the resulting read current is minimal compared to the cell current while reading a stored ONE. At the same time the f irst word line voltage is applied, a negative going voltage is also applied to dummy transistor 214, causing it to feed a c,-_Irren1'_, to BLR which is designed to be about equal to the average current f or reading a stored ONE or for reading a stored ZERO from cell capacitor 204. As shown in Fig. 2B, BLR is pullce in the positive direction when a stored ZERO is read because the dummy current dominates. While reading a stored ONE, however, the cell current dominates and pulls BLR in the negative direction. As soon as the voltage difference between the bit lines is suff"icient for reliable operation, the supply voltages VDDA and VSSA for latching amplifier 212 are applied. Bit lines BLR and BLW will then quickly move to their respective rail voltages. Once each bit line is close to its final voltage, the vol-Eage on the word line VWL is increased to at leas"", a level of VDD. A previously stored ONE will now be refreshed to approximately one threshold voltage less than VWL, while a Dreviously stored ZERO will he restored to 0 V.

If speed is not the primary goal and the disturbance level on the cell capacitors 204 is allowed to be high, the 9 basic inverting amnli-fier 220 coupled to cells 202, as shown in Fig. 2C, may be used. The operation of the memory shown in Fig. 2C is similar to that of the memory shown in Fig. 2A. Amplifier 220 includes clamping transistor 210 and a simple inverter 222. The clamping to a common reference level, which is chosen to be close to the switching point of the amplifier, is not very accurate, as -'Che switching point of the amplifiers varies with changes in the device parameters. The timing must th--erefore be ade.--aate to allow the cell current to displace '0 the read bit line BLR at least as -much as the error before, since the bit line voltages represent the actually stored data. The Dower to the inverter amDlifier 220 should not be turned on before the worst case clamping error has been commensated. This will prevent the write bit line BLW from 1:3 temporarily going to a ground level with the word line on, which would cause a stored one to be discharged to a zero. A stored zero on the other hand would not be affected if the write bit line inadvertently went to the high level, while the word line voltage is still at its lower level. The preferred method is to wait a sufficient time until a potential clamping error has been comDensated for. The amulifier will then consistently move the write bit line in the correc-- direction. As discussed earlier, power consumption can be minimized if Dower is turned on even later in the read mcde, so that read bit line BLR has moved closer to a rail voltage. If the inverting amplifier is used in connection with segmented bit lines, the coupling can be made only when the clamping error has been comDensated and the signal has been amplified somewhat. Fig. 2D shows the timing for amplifier 220 in Fig. 2C, and Fig. 2E indicates the amplifier's performance as part of a segmented bit line configuration. Note in the latter case how the partially amplified signal on both bit nes BL'-R and B174 is temporarily reduced when the adjacent segment is connected. Again, the read bit line Bi-R on the read segnaent is connected to the write bit line BLW on the next segment. The segment'-'s together act as a plurality of latched amDlifiers. it is imDortant that all amplifiers are nowered un be-.'ffore the secmnent-s are couDied, as this guaranteSs a gradual amplification of the initially reduced signal before it progresses down the full bit line. Without amplification, the signal on the read bit line BIR of the read segment would be reduced to a small fraction of its original value. For a memory structure where a bit line is made up of eight seg-ments, then, the signal would be reduced by a factor of eight. This signal is too weak to overcome the clamping error on some of the segments.

ComT)ensation of Clamping Error In applications where the cell current is low, yet fast memory cycle times are still needed, it is desirable to minimize the clamping error. Figures 3A through 3G illustrate the different clamping devices and methods. Fig. 3A shows a preferred structure with clamping transistors 302 and 304, which was also-shown in Figs. 2A and 2C. Both bit lines will reach the reference level VCLAMPL, while VCLAMP is high, but when VCLAMP goes low, the gates of the transistors 302, 304 will couple a small negative charge to each of the bit lines.

The voltage drop on the bit lines can easily be as much as 100 mV, if a short clamp time is desired. To achieve a short clamp time, the clamp transistors 302, 304 must be relatively large. Segmented bit lines, with their lower capacitance, will have smaller clamp transistors than fulllength, unsegmented bit lines, but the ratio of gate capacitance to bit line capacitance is the same and therefore the result is a comparable disturbance. The latched amplifier 200 (Fig. 2A) is relatively immune to the clamping offsets that appears equally on both bit lines. Latched amplifier 200 suffers from a non-correctable offset error due to device parameter variations. The two cross-coupled inverters 212 may have different switching points. One of the bit lines will therefore be moving at a different rate after clamping than the other bit line. The cell current must be larger than the built-in offset current for a correct reading of the selected cell. If used in a segmented bit line configuration, there is a risk that one or more of the non-selected segments may start to switch on their own before the segments are connected, which could result in a read error. The clamp circuit in Fig. 3B addresses th 4S possibility by adding transistor 306 that directly shorts the bit lines during clamping.

The inverting amplifier 220 (Fig. 2C) is sensitive both to the difference between its switching point and the reference VCLAMPL and to the effect of turning off VCLAYIP. instead of waiting for the read bit 'Line to overcome the worst case clamp error, another approach may be taken, as shown in Fig. 3C. VCLA!,!PI again connects both bit lines to a con-nion reference voltage VCIAMPL while power is off, but VCLAMP! turned of f as soon as power is turned on. VCLAMP2, on the other hand, turns on at the same time as VCLAMP1, but stays on longer. When Dower is turned on, the bit lines are at the potential of VCLAMPL, which may be different than the switching point of the inverter. VCIAMP2 shorts the input a-id the output of the inverter, so that the bit lines are moved to the switching point, thus putting the inverter in full balance before the cell current is applied to the read bit line. Note that turning off VCLAMP2 causes a negative displacement of the bit lines. The displacement on the read bit line (the inverter input) is most critical and must be compensated by coupling a positive charge to the read bit line. The clamp shown in Fig. 3D accomplishes that objective. Here, the connection to the reference voltage is done with a P-channel transistor 308. VCLAMPB goes positive at essentially the same time that VCLAMP goes low. The P-channel transistor 308 has a relatively high on resistance compared to the N-channel clamping transistor 306 and the imDedance in the inverter associated with searching the switching point centering. The purpose of the P-channel transistor 308 is to maintain the bit lines close to the switching point at for a longer stand-by period. Sin ce the switching point is set to half the Vdd level (Vdd/2), and the bit lines before clamping are set. to the rail voltages, the potential of the bit lines after cl, amr)ina will therefore be close to Vdd/2. The width and length of the P-channel transist-or 308 can be chosen such that the requirement for both high impedance and the recraired counling of charge to the read bit- 1-ine BUR can be met.

12 Fig. 3E illustrates the addition of compensating capacitors 310 and 312 between VCLAMPB and bit lines BLR and BLW that are chosen to fully compensate at turnoff of the clamn transistor 308. in Fig. 3F, VCLAMP1 holds bit lines BLR and BLW at the reference level in standby mode, ihile VCLAMIP2 remains high after power has been turned on to inverter 220 (Fig. 2C). The charge transfer to the bit lines, when CLAMP2 is turned off, is compensated by VCLAMPB going positive. The compensation is necessary on the inverter input, but is less critical on its output, so the compensation can be limited to only one capacitor on the read bit line.

As will be discussed herein, the advantageous features of inverting amplifier 220 and segmented bit lines in Fig. 1A can also be applied to conventional DRAM cells. In that case, the DRAM cells are connected to both bit lines. This type of clamp circuit is shown in Fig. 3G. The associated amplifier includes two separately powered inverters and two separately driven compensation capacitors 314 and 316. A similar amplifier arrangement can also be used for the DRAM cells of this invention, except that a common drive signal for the compensating capacitors shown in F41g. 3F can be used. The compensating capacitors used in a conventional DRAM may serve two purposes. First, they supply the charge to compensate for the negative charge transferred when V'_'TAMP2 goes negative, but the size of the capacitor is a little larger than required for that compensation. The added charge pre-biases the bit line to which the read cell is connected, so that reading a cell will give the same absolute voltage difference between the read bit line and the switching point for both a charged and a discharged cell capacitor. In reading and writing data in a segmented bit line configuration, the segments that are not addressed must have their read bit lines BIR very close to the switching point not to cause errors. The compensating charge transfer for these segments, must therefore be less than for the selected segment. This can be accomplished by using a lower amplitude on the compensating voltage or, of course, a separate compensating capacitor can be used to add the dummy charge on the selected segment.

13 The amplitude olf the clamp signal for all the cases discussed above is the full Vdd volIC-age, resulting in a large capacitive coupling when the clamp signal is turned off. in the initial time period after clamping, the bit lines will still be close to the clamping level (Vdd/2). This means that the clamp signal need not initially go more negative than to ((Vdd/2)+Vth). As the cell current proceeds to separate the bit lines, the clamp signal must track the negative-going bit F 4 line. The arrangement in ig. 3H shows such an ccn-Eicraration.

Here, when VCLAMP is turned on, transistor 318 lifts the gate of transistor 320 to (Vdd-Vth), which clamps the bit lines together. The transistors 322 and 324 act as diodes and are designed as relatively weak transistors in order to limit how much they can pull the clamped bit lines positive while VCI_.kMP 1.5 is high. Transistors 322 and 324 are actually designed so that the positive excursion during the time of clamping is exactly as much as the negative capacitive coupling when VCLAMP goes low. When transistor 318 is turned off, transistors 322, 324 proceed "Co Dull the gate of clamip transistor 320 toward the lowest bit line voltage plus the threshold voltage of transistor 322 and transistor 324. With a normal threshold, this tends to hold a slight clamping for a short period, reducing the gain of the inverter for small cell currents. Bv terminating the clamp signal early or by using lower ti,reshold voltage on 322 and 324, this problen can be eliminated. When the bit lines eventually move, the low-going bit line will- continue to keep the gate of the clar, p transistor 320 jus-16: below its threshold voltage.

In several of the amplifiers, the assumption has been made that the amplifier power is permanently connected.

This means that the bit lines are close to Vdd or Vss between cycles. A clam-ping operation will then have to swing the bit lines a's much as Vdd/2 to the s-witching point of the amplifie--r. The time required for the clamping opezration is in this case slightly longer than when the bit lines start cut close to t-h.e clamp level. The clamping circuit as shown in Fig. 31 is used for th-is purpose and consists of one N-ch.annel clanz transis-Zor 326 and two canacitors, here shown. as 14 transistors 328 and 330 with both source and drain connected to the associated bit line, for compensation of the turnoff disturbance.

Fig. 3J shows a single N-channel clamping transistor 332, used in connection with clamping under power. Amplifier power is selectively turned on and off during a memory cycle. in cycles repeating frequently, the bit lines starl%; out very close to the switching point. At the end of each cycle the two bit lines are clamped together after having been close to the opposite rail voltages. The refresh frequency must satisfy the requirements for the small cell capacitors, so larger bit line capacitances will discharge very little between cycles.

The amplifier's VddA and VssA nodes are both connected to the reference level Vdd/2, which is the nominal switching point level. Any leakage through the transistors would go to this level. only junction leakage could cause the bit lines to drift away from the reference level. Theinverter transistors would however limit the drift to one threshold away from the reference level in either direction.

Starting from this worst case situation, the adjustment towacd the switching point after applying power to the amplifier follows the table below. The inverter has a W/L ratio for the N and P transistor--,: of 1.2/.6 and 2.4/.6, respectively, whilc the bit line capacitances are 100 fF 100E-15).

Time after power on VBLR - Vref ns mv 0 -600 2 -376 3 -163 4 - 68 - 19 6 5 7 - 1 8 0 Turning off a clamp transistor of with W/L of 2.4/.6 introduces a disturbance of -80mV. The disturbance must be considered in relation to the cell current. The rate of voltage change on the read bit line is lomv/(gAns) for the bit line capacitance of 100 fF. A differential cell current (7.cell - Idummy) of 5AA would change the bit line voltage at a rate of 50m,v/ns. Turning off the clamp after 5ns, with the cell current. on, would result in full compensation 7ns after the start of the cycle, overcoming 80mv plus 19mv. At lower cell currents the clamr-ing will be turned off about ins later, and it would take longer to compensate for the offset caused by the clamp transistor. At a differential cell cul-rent of 1AA, the total time to comDensation would he about 14ns. The pciarity of the d_is-%'.-urbanca on the read bit. line is such t,,at write bit' line for the lower cell currents may go positive to near the Vdd level. Thi's would not cause any disturbance on the addressed segment. If however the read bit line starts out at Vref + 600mV and the clamp transistor turns off while the read bit line is still more than 8OmV above the reference, the write 'bit line would go negative.

only if the clamp is turned off very early could 'he write bit line go below the word line voltage, thus turning on the write transistor and write a zero in a cell that was a one.

This case is very remote as the word line voltage would by design not be turned on that ea--ly.

A more serious problem occurs in reading and writing data in a segmented bit line configuration. The disturbance introduced by turning off the:lamp voltage would remain on the C to the write bit line non-selected segments. The curtent caused by an 80mv differential voltage on the read bit line is approximately 12pA, with the -inverter dimension as discussed above. The bit lines would be disDlaced at a rate of l20mV/ns and thus completely override the contribution from the selected segment except for rather high cell currents. A cell current of IpA will change the read hit line voltage at a rate of 10mv/ns,. The displacement on the write bit line after T nS -follows the equation Vdispi =!cell (pA) 10TSquared/2mV. cell current of 10ga would after 2ns have displaced the read bit to +120mV and the write bit line to -120mv, while at t- h e same time %the bit lines on the ncn-selected segments would have moved 240m-V positive. A simulation has shc;qn that a cell current of at leas'" 40,u.A would be recrfai_-ed to ooerate an 16 8-segment memory, assuming bi-, line capacitances of 100 -F.

t,.4. By using different clamming times for selected and non, selected segments, the problem is highly -reduced. if the clamming on the non selected segment is terminated just before the signal counling the segments together is turned on, the vo'ltaae between the non- selected segments would be approximately loo mv. Allowing the bit lines in the selected seg7ment to be disDlaced more than k100 mV be-fore counling, where k is -he number of segments, would yield more relJLable operation. Some of the amplifiers shown may use a second inverter in each segment which can be selectively engaged. Allowing the second inverter to contribute to the anMJ4 L.. I.Lfication in the selected segment before the coupling satisfies the above-stated reauirement.

It was assumed above that the power to the amp-lifiers was selectively turned on and offe during the memory cycles. The method of clamD-ing to the switching point of-the inverters used in some amplifier configurations, however, makes it natural to onerate the amplifiers under full power all the time. This means that in standby mode, the bit lines will aiways be at or close to the rail voltagcs. The clamping will, when used in connection with an inverter, bring the bit lines to the inverter switching point against the transistor that is in the holding mode. The final adjustmer-.- z to the switching point level will therefore take somewha't longer than if the bit lines start out already close to the switching point as described before.

Fig. 4A illustrates an amplifier 400 for segmented bit lines. The basic inverting amplifier consists of transistors 402 and 404 that make up the first inverter, while the second inverter with transistors 406 and 408 may be added for additional amplification later in the memory cycle. Transistor 410, when turned on by the signal VINV2 will connect the output of the second inverter to the input of the first.

The clamping is done by turning on the clamping transistor 412, thus shorting -t-he bit lines BLR and BLW and adjusting to the S'tching point level of the first inver er. The selected word WI rt lines on, the selected segments are brought to the reading level 7 essentially the Same t4 12ne as VCLAM'-) goes low. The read bit line BLR at this time has a predictable offsett.: error as discussed above, due to incomplete adjustment to the switching point duri-ng clamping and the capacitive coupling from vcI';_'mp, when it goes negative. With only the first inverter connected (VINV2 low), the cell current will both overcome the offset a:,-.d displace the bit lines sufficiently for a correct refresh level. If limited to only the first inverter and no counlina between segments, this would be a relatively slow operation 0 high power consumption.

in the refresh mode, as discussed above, the segments remain separated and refresh cells on their selected word lines. To speed up the refresh cycle, the second inverter is connected aL the time when the bit lines are seDarated an the order of 100 mV. The amplifier now acts as a conventional latching amplifier. When the memory is used in read or write mode, the offset on non-selected segment must still be considered. At the time of connecting the segments, the signals on the non-selected segments must be an order of magnitude smaller than the signal on the selected segment. As shown in the timing diagrams of F-Eig. 4B, a different approach is used that guarantees a suitable ratio between the signals. For the selected segment the clamping takes place first. in the cycle, allowing the signal to grow, driven by the first inverter. Then the second inverter is connected and t.'ie higher amplification proceeds for some time until the segments are interconne7- ted by the signal VCOUPL. A temporary drop. in the signal is followed by the mutual amplification from the crosscoupled segment inverters. Tnitially only the selected segment has its second inverter contributing. The non-selected segments as shown in the lower timing diagram all have a delaved. clamp signal that is turned off just before VCOUPL is turned on. There-;"ore, the only signal on the bit lines of the non-selected sea-ments is I:he offset signal caused by the turnoff of the clamp signal. Once the coupling has been establis-hed, the second inverte-rs on the non-selected segments are turned on, introducing additional speed to the read oneration. The botto.-m seg-4-,ients -i,- the selected columns mav use is the early clamp signal in wr_-, te mode, permi"'C_ting the 'ffull read I - cvcle to aD-oly '"he write signal, so that the sianal at the bottom segment- at the time of coupling is suf.-fficiently larger than the signal on a selected segment other than t--he bottom 5 segment., to guarantee correct writing.

Fig. 4C shows amplifier 420 that is a variation of the two inverter amplifier. In amolifier 420, the clamping A- transistors include both N transistor 412 and P transistor 422, and coupling transistors include both N transistor 410 and P transistor 424. By optimizing the design in this way, most of the clamping dis-tZurbance can be eliminated.

It has been mentioned that different timing is required for selected and non-selected segments. Figures 5A and 5B show the logic required for each segment for con-'%--rolling an associated amplifier. All segments have the same logic shown in Fig. 5A, except the bottom segment of a bit line, shown in Fig- 5B, that is used for transferring data in and out of the bit line. A memory cycle may be initiated by a separately timed refresh request or an interrupting Block Enable or Chip Enable signal. Word Line Decoder block 502 and Segment Decoder block 504 decode the incoming function and address code to select a given segment in the memory and a given operation (a read or a write) and initiate a timing sequence. The appripriate timing signals are generated and applied to the memory block. The signals are routed to all segment controllers and are used slightly differently for selected and non- selected segments. In the refresh operation, which is reauested by a free running clock, in one mode all segments are considered to be selected. The applied ti-ming signals in the figures are Early Clamp Time, Late Clamp Time, Selected Segment Inverter on Time (SelInvTime), Non-selected Segment Inverter on Time (NonSelinvTime), Word Line on Time (WLonTime) and Dummy Current on Time (DummyOnTime) The abbreviations for these signals are shown in parentheses where appropriate. A ramp signal VRAMP is also applied, which may be common for the block or be generated in each segment, with the timing controlled by common signals not shown on the diagram. The logic for the bottom segment shown in Fig. 5B operates 19 d-iffe--ent--ly than the other segments dUr4ng the write operation. The enabling of word line and dummy current is the same for all segments, but the clamp signal and the connection offf the second inverter are always early for the bottom segment in the write mode. This ensures that the written data gives a dominating signal to the connected segments. In write mode, input data is counied to BLR of the bottom segment; in read mode, output data IS COUDled to BLW of the bottom segment.

Fig. 6A illustrates a memory 600 having two segments 602 and 604 where only one inverter 606 and 608, respectively, in each segment operates under fixed power. Raad bit line BL-R from segment 602 is coupled to write bit line BLW of the next segment 604 through pass transistors 610 and 612 when VCOUPL is high. Fig. 6B shows the relative timing between selected and non-selected segments. In refresh mode, in a preferred embodiment, all segments are considered selected and the coupling signal remains low during 1--he cycle. Alternatively, the segments may cooperate in pairs, resulting in the selection of every other segment. Fig. 6C shows how the selection of segment for refresh is controlled by the odd/even bit. This decoding may be common for all segments or local as shown. The coupling signal is divided in two. one signal is used only in the refresh mode, while the other is used in read and write modes. The advantage in pairing the segments in refresh mode is that the time and power consumption is reduced due to the higher amplification for the two cooperating inverters. The structure also makes it possible to pre-amplify the signal at reading and writing, before interconnecting all segments. The coupling signal interconnecting the two secTments in the pair is made subject to early selection if one of the segments is selected. This increases the amplification of the pair of signals. When a dominating signal amplitude has been reached, all remaining coupling signals are activated. For a preferred margin, clamping is performed at three different times. The earliest ciamr) time is for the selected segment in a segment 4- pair, the next clamp time is for the non-seleci-_-ed segment in the segnentk_- pair and the third t-irue is for all remaining secrmen-'Cs.

4'0 Conventional DRAMs and Se= ented BJ ± Tdnes Conventional DP-'--Z--s also gain in speed and marcr_11-.s using the segmented bit- line approach. T.ne shorte_- bit lines used in conventional DRIis have a lower caracit-ance that gives stronger signal for given cell capacitor sizes. Mi-is approach actually pe=its the use of smaller cell capacitors and higher refresh frecruencies, as discussed for the new cell type above. The same methods for minimizing the dist-urbance caused by the clamping operation apply to conventional DRXY_s. There is, however, a slight difference in the amplifier design. The cells in a folded bit line configuration may be alternately connected to one or the other of the two bit " lines. All word lines with even addresses may, for instance, be selecting cells o.n one bit line, while all word lines with odd addresses would select cells on the other bit line. In the simnles-t- amnlifier discussed earlier having only one inverter, the coupling between segments must complete the amvli--;-ier so that the inverter output of one segment connects to the input of the inverter in the next segment. Each segment must therefore have two inverters, each selectively used according to which bit line is addressed.

Fig. 7A shows memory cell 700 including an amplifier where while reading cell 701 power is first turned on to 4 nverter 702, whose input is coupled to rea6 bit line BLR holding the cell to be addressed by the ' word line. The bit lines are clamped while power is on, adjusting to the switching point of inverter 702. Due to capacitive coup!-Lng when VCLAYiP goes low, the displacement on read bit line BLR is compensated by VCOMPODD going positive, as shown in Fig. 7B. The second inverter 704 in a selected segment'.. may be powered up before the segments are coupled together by the VCOUPL signal. For reading and writing operations, this gives a large enough signal to overcome the combined error signals -from the non-selected segments as discussed above. The non-selected segments will typically have the bit lines clamped late on the primary inverter 702 so that at time of coupling a very small signal has developed. The secondary inverter in non-selected segments is powered up only after the segments have been 21 connected. oniv in the refresh mode are both invere"s 702 and 704 used the same way in all segments. The same principles regarding the inconvenience o:ff turning power on and off appLies to conventional DIRAMs, so the same approach discussed for Figs. 5 4A and 4B above can also be used here. The only dif Iference is thatt when used in connection with a -fixed Vdd supply, the arder of connection of the inverter amplifiers is determined on which bit line holds the addressed cell.

Fig. 7C shows a memory 710 including this type of amplifier 712, with capaci-t-ive compensation of the distur-bance at the termination of the clamping. The first inverter 714, with its input connected to the first bit line BL1 has its output connected to the second bit- line BL2 when VINVEVEN goes high, while +:he second inverter 716 connects its output to the first bit line BLI at the time when VIIWODD goes high. If, for example, the input of inverter 714 is coupled to the bit line of the selected cell, then inverter 714 is activated at the start of the memory cycle and is used in the clamping operation, which adjusts the bit line voltage to become close to the switching point of the inverter. The second inverter 716 is then activated late in the cycle, when the output from the first inverter 714 is much larger than any offset error due to device variation between the first and the second inverter.

For selectad segments, the second inverter 716 is aCt4 ated -V some time before the-signal VCOUPL is applied. This signal connects the segment to the neighboring segments for read and write cperat-ions only. In the refresh mode, all segments are selected and the read restore operation 'is completed with help of both inverters. The VCOUPL signal remains low during the refresh oneration. In the read and write model as described ab ove, the second inverter in the non-selected segments is turned on after VCOUPL has connected the segments. Some time is allowe - d to permit. the first inverters in all the non-selected segments, in cooperation with the two inverters in a selected segment, -'--a amplify the -Cempolrarily reduced signal enough- to dominate over the coupling transien-t- when the seccnd inveZ--t--ers are activated. As indicated in Fig. 7C, the succeeding seg-ment miz-rars the nrevi(:us seg.-iient, so that an 22 -ed on the right bi-" line i-1: 4-- -e even addressed cell 's loca4%.even cell on the previ ous segment was located on the left. Likewise the inverter direct -4on is reversed in the succeeding segment (not. shown in the figure). The ti.ming relations --he signals for selected and -on selected between 4L. seaments are shown in Fig. 7D.

Fig. 7E shows the segment control logic for memories 700 and 710 discussed above. The segment control logic of Fig. TE' is similar to that shown in Figs. 5A, 5B and 67C above, exceDt for the separate control of odd and even inve.-A"er and clamp compensation.

Two Tier Memorv The DRAM of the present invention by its nature makes it vossible to design a memory where the content of the memory can be read without any interference from ongoing writing, reading and refreshing. The memory is structured in "t-Wo tiers," meaning that in addition to 'he first tier, a regular DRAM of the present invention with normal addressing, reading, writing and refreshing, a second tier with separate addressing is used to read the contents of the cells in the f irst tier.

Fig. SA shows a two tier memory 800 with first tier memory cell 801. The DRAM cell, which includes transistors 802, 804 and 806 wit_. -memory capacitor C1, is addressed by its word line WLi and is treated as part of. an independent memory in the reading, writing and refreshing operations. As discussed earlier, one of the features of this DRAM is that the stored data in the memory capacitor C1 is disturbed very little during the operation of the memory. As a matter of fact, the high state need not be disturbed at all, while the disturbance in 'he low state (the voltage on Cl close to zero) can be limited to around Vth. For higher operating speeds a slightly higher di sturbance is accept able - The first tier memory 801 can have any of the --features discussed above, including being 35 of the segmented bi4L- line type.

In the second tier memory cell 810, transistor 812 is used to sense the st-ate of C1 and transistor 814 acts as the read transistor. The second tier cell 810 is addressed by 23 WLTi, by applying a high signal thereon. This connects second tier cell 810 to the bit line BLT, which in turn connects to a sense amDl-ifier 816. Amplifier 816 may, merely by way of example, be a single-ended amplifier, as the signal amnlit_ude is such that folded bit lines are not necessary for common mode noise suppression. However, folded bit line configurations 820 and 830, such as those shown in Figs. 8B and 8C, respectively, are also possible. Fig. 8D shows a pair of memory cells 842 and 84 A, each having first and the second tier cells 846, 846 and 850, 352, respectively. The first and second tier calls share a common ground bus GND. The connections to the bit lines are common for neighboring primary cells. The second tier cells have separate connections to BLT, but using three level metal and different layouts, common connection points can be used.

should be noted that the sense transistor in all the previous figures has the source connected to ground as in most cells discussed above. The reversed cell, where the select transistor has the source connected to ground and the sense transistor connected between the select transistor and the BLT, can also be used. This config-uration is shown in Fig. BE. As a rule, this cell requires a larger storage capacitor C1 than the cell with both sense transistors connected to ground. The gate capacitance of the sense transistor in the second tier cell in read mode will couple a disturbance to CI, which may cause an error in the memory functions of the first tier cell. This is contrarv to the normal (non-reversed) cell, where the major part of C! actually is the sum of the gate capacitances of transistors 802 and 812 (Fig. 8A).

Again, the amplifier for the second tier ma-v be of the folded bit line type, as indicated in figures 8B and 8C.

ifier would use the same techniques discussed above in This amiol L. - - conjunction with memories having only one tier. Segment-ed bit lines may be used in this configuration as well.

A single-ended ampli-fier 850 with a data out latch 852 is indicated in Fig. BE, and a corresponding timing diagram is shown in Fig. SF. '_''he signal VBIAS is held at an 2 4 intez--mediate level concu-renlv wi-h VWLT. "'he cur-en-" -F-cr, P channel transisto_,?- 854 is anDroxima-L-ely hal-f of t-he sun of -t-he cell currents for a zero cell and a one cell. Limiting the negative swing of VBIAS makes P transistor 854 act more like a constant curren-IL: source than if the swing is larger. The circuit can be made to operate with somewhat lower margins if designed so that VBIAS goes to ground when activated. The D innut on the flip flop is designed to have its switching point close to Vdd/2, and as long as the bit line voltage in the two states deviates a minimum amount from Vdd/2, the operational margins are satisfied. The actual moment of reading may in t1ae worst- case coincide with the reading of the first tier memory. At this moment C1 may have a disturbed Zero level. The amplifier design must take this into account and also plan for changes in the charge levels on C1 between refresh due to leakage. In the amnlifier indicated in Figs. 8E and 8F, no clamping of BLT to a neutral midpoinlt_- is made. Adding this feature reduces the access time of the second tier memory 810, but would not reduce the power consumption. The folded bit.

line approach has both speed and power advantages, but the gain is highly dependent on the bit pattern in '-he -read data.

Denser layouts using a two-tiered memory may be achieved by using non-dedicated bit lines, which means that a -iven bit line can be used as a read bit or a write bit line depending on if the address is odd. or even. In this type of arrangement, the bit line capacitances remain equal. Fig. 8G shows part of such a memory using the DRAM cell of the present invention expanded to include a sense transistor and a select transistor for the second tier. In the configuration shown, each column of basic DRA_M cells is combined with two folded bit lines f or read out in the second tier. Read operations from this memory configuration are very fast. The bit lines are clamped to a mid level, the word lines swing to Vdd when reading, the amplifier is disconnected from the bit lines at an optimum time when the bit lines have just separated from the clamp level, and the reclanping iLs completed while data is read out from the amplifier. A preliminary layout for this circuit is shown in Fig. 8H. 04Cher configurations may of course yield a denser layout.

Process for Reduced Area and-Hic-h Sneed one of the features of the memory of this type is that the conventional CMOS nrocess. with three metal layers can be used for production of the memory. For dedicated memory chips, the cell area can be reduced subs-'L- anti ally if the fused and thinned wafer approach is taken, as also described in U.S, 16. 0 patent_nurber 5,396,452. in logic circuit--s rwhere memory and logic is mixed, even larger benefits can be achieved. The approach would be to prepare a wafer that, later in the process, would strictly follow a standard fabrication process.

The added cost in the wafer preparation would be well compensated by the savings in area and the gain in speed- Fig. 9A illustrates steps in the wafer preparation as -Collows:

1. A support wafer 902 of low resistivity is used. The areas 904 where capacitors are to be located are etched down. A thin dielectric layer 906 is deposited or grown- 2. Polysilicon layer 908 is deposited over thin oxide layer 906.

3. The wafer is polished, so that the support wafer 902 and the polysilicon 908 have a common smooth surface.

4. Another thin-oxide layer 910 is grown on the polished surface.

5- The epi layer 912 of a second wafer facen the top of -'Che support wafer and is fused thereto. The assembly is then processed as described above so that only the epi layer remains on top of the support wafer.

6. contact holes 914 are etched and plugs 916 are deposited to establish contact points to the embedded capacitor 918 and to the substrate.

7. If other means have not been used in the sten 35 above to isolalte the plugs from the surrounding silicon, trenc.'n,--s 920 surrounding the plugs, are defined and etched. in the same steD, the individual transistors in L_he memory cell and in the rest of the logic are alsc separat-ad from each other 26 by tz-enches 920. The tlrenches are preferably back-ff-illed wiz'_-I a form Of glass.

8. P-cinannel transistors are exposed to N-type imnlant and are heat treated to a sufficient depth. The sur-lace is next prepared for the gate oxide. If the capacitor is to be connected to the gate of a transistor, the gate oxide 922 is removed on top of the contact plug for the capacitor.

To more closely follow a standard fabrication p-rocess, the canacitor connection can wait for the metal 1 step to connect h gate and the capacitor.

0 t e - L_ The waf er is now ready to be run in a known three layer metal process. The LOCOS isolation process step need not be completed, as the area under the poly contact can be isolated by a trench in step 7 above. This results in a planar metal 1 layer.

Multi-laver Memory Cell Controlling Logic Programmable logic devices such as Field Programmiable Gate Arrays (FPGA) have devices that must be controlled with relatively large capacitors. The pass transistors transferring signals from one data bus to another must be large enough for minimum voltage drop in passing the signals. The controlling capacitor must be significantly larger than the gate capacitance of the paLs transistor, so that the voltage on the controlling capacitor is relatively constant during the signal transition. Using the multi-layer approach described above lends it-self ideally to this purpose. The total a-rea under the pass transistor and under the memory cell transistors can be used for the controlling capacitor.

Fig. 9B shows one DRAM cell 930 controlling a pass transistor N4. The cell 930 includes transistors NI, N2, N3 and a large capacitor Cl located under both the cell and the pass transistor. The source of Nl is connected to the gates of N2 and N4 through first metal layer MI, with a silicon island used to supiort a feed through to --he underlying capacitor. (The vertical connection is indicated on the left side of the figure.) The combined structure has three vertical busses, which may be in the second metal layer M2, with two busses 27 reserved for the memory bit lines and one reserved f or a vertical interconnect bus for data. The word line and local connections use layer Y_11, while ground and a horizontal data bus use the top metal layer Y.3. There are several options to 5 make the connections between the different layers, including feed-throughs in the back-filled areas between transistors. The epi layer remaining after thinning the top water is usually thicker than a normal implanted source-d-rain diffusion. The transistors therefore have a rema-Lning substrate nortion.

Provisions have therefore been made so that this substrate layer may be connected to the underlying support wafer which is at ground level for the N-channel transistors. The substrate layer may be connected to the underlying support. wafer which may be a-'%--- a ground level (Fig. 9C). The support wafer does -he have N wells to support the connection of the substrate of t P transistors for this reason.

The same procedure discussed in conjunction with Figs. 9A and 9B can also be used f or the memory cell sho,,,,-n in Fig. 9C. Adding a recessed capacitor 936 increases the storage time of the cell, which reduces therefresh frequency. The gate capacitance of the sense transistor is generally sufficient for reliable operation. With all three cell transistors in the top layer, no additional area is gained by adding a recessed capacitor.

Fig. 9D shows in greater detail a compact cell utilizing a recessed transistor and a double-sided capacitor.

The thin transistors in this figure are not fully depleted, which means that the transistor substrate must be tied Zo ground. it should also be noted that the transistor substrate is one side of a double sided capacitor and for that reason must have a relatively high conductivity. The surface of the wafer to be fused should therefore have a P+ top layer. With the transistor substrate grounded, the source and drain junction capacitances are as high as in the standard processes, while the area efficiency is increased as the devices are -op silicon laver. The separa--ed bv trenches cut through the 4L top transistor laver in this case is assumed to be formed bv defining an et-ch stop bv an eni lave-,-with a much dif-"erent 26 4mnuritv concentration and a difl'-;erent". tv-oe. The e+,cli rate n -,he bulk is therefore much higher W4 th 4--e right choice of etch-ant. The remaining layer is therefore too thick to permit -full depletion by the junct-Jon in-plants while still maintaining Cz the small device dimensions.

P.n alterna-Cive approach has been taken in Fig. 9E. Here the ton wafer used for fusion is of a SIMIOX type. The ton of this wafer has a thin silicon layer separated from the bulk by -an implanted laver of oxygen. Such a wafer after adding a relatively thick oxide layer, can be fused and thinned down to the buried oxide layer with high accuracy. The transistors formed in '"his thin layer will have fully depleted junct-ions, and small junction capacitances. They will therefore be much faster than the transistors in Fig. 9D. The recessed capacitor will however have a thicker oxide layer on top, resulting in a value close to half of the fully double sided capacitor in Fig. 9D.

Fig. 9E is a supplement to Fig. 9D, where marker line 942 denotes the location of the capacitor and marker line 944 the location of the junctions in the support wafer. In the cells of figures 9D and 9E, the bit line connec-r-ions are not side by side. This permits the layout of a narrower cell than if the connection are side by side, which must be the case f or S-ngle layer cells.

Fig. 9F. shows another construction for a capacitor in combination with a pass transistor in a programmable logic device. In Fig. 9B, the capacitor was formed underneath the pass transistor. Here, the capacitor is instead formed above the pass transistor. In Fig. 9F, a flat capacitor covers most of the pass transistor area and typically comprises two polysilicon layers separated by a thin dielectric layer. one layer is coupled to a fixed potential, for example ground or Vdd, whiie the other layer is coupled to the control node from the DRAM circuit. The gate of the pass transistor is likewise 35 coupled to the control node of the DRAM circuit.

29 multi-laver Desicms using E-oi4,--a.-,v and Sinox Figs. 1OA-10D show alternat-e methods of submerging capacitors and transistors below a thin epi laver added directly on top of a supporting wafer.

Fig. 10A shows the steps for making a capacitor with both electrodes accessible. The sequence of processing is as follows:

a) A recess 1002 is etched in the support wafer 1004, which is ass-=ed to be P-type.

b) N- -ma-terial 1006 is irmlant-ed but. not necessarily heat treated at this time. The purpose is to form an N-channel junction, which will isolate the bottom electrode of the capacitor from the support. wafer when operating at levels positive in relation to the support wafer.

C) A thin oxide 1008 is grown which will bRcome the capacitor dielectric layer. Polysilicon layer 1010 is then deposited until the recess is filled. This can be a blanket deposit (as shown) or a local deposit.

d) The wafer is polished so that the remaining surface 1012 is a continuous flat surface, but with no possibility to contact the buried N+ junction.

e) An area covering the capacitor and the intended junction contact regions is defined and another N+ implant 1006 is made.

f) An epitaxial layer 1014 is grown, which may require two steps to obtain a usable laver on top of the polysilicon. In the firs-'%- step the layer is grown ve,L-icallv and should give single crystal areas, at least where the starting surface is single crystal. In a second step some form of Zone crystallization may be used to include the areas above the poly into the single crystal.

g) in this steD 02 is implanted to a depth equal to 'ited ep- laver. After heat treatment, an insulating the depos- _L %_ - layer of Sio is formed. The remaining laver of the epi layer 2 is then used for MOS devices of the tv-oa used in Silicon on Insulator technology. Connec-ttions from the device layer to the canacit-or electrodes uses known me-lChOds.

F-Lg. IOB illustrates how a transistor such as N-1 in -IC-Ine memory ce-11 can be submerged into -the support wafe.- as follows:

a) A recess 1016 is etched in the P- wafe-r, poly is 5 de-cosited and the wafer is Dolished.

b) The transistor area is defined and N+ 1CI8 is innlanted.

C) The epi layer 1020 is grown as discussed above.

d) 02 is imDlanted. When the wafer is heat treated, Si02 is --Formed, leaving a device laver insulated from the submerged transistor. The transistor channel goes from the edge of the source implant to the edge of the drain implant. The channel will go in a vertical direction close to source and drain, if the depth of the diffusions are less than the depth of the original recess.

Since -there is some uncertainty about. the silicon cruality in the epi layer above the submerged poly laver, it is desirable to consider the approach illusIE'rated in Figs. 10C and 10D, where the capacitor electrode is made from silicon. The process for Fig. IOC is as follows:

a) A deeD Y+ diffusion 1022 defining the area of the cai)acitor and its connection regions is made in a P type support wafer.

b) To form, capacitor, dielectric layer 1024, which may be, for example, N4 or 02, is implanted in a defined area.

C) To isolate the capacitor electrode from the rest of the wafer, a trench 1026 -Js cut a-round it-_- edges. The trench is refilled with Si02 using known techniques.

d) Fields of epi layers 1028 are next grown on all silicon areas.

e) oxygen or nitrogen is now implanted to the depth of the epi layer and the completed wafer is heat treated. The top layer will be used for devices and conventional steps are taken to contact the devices to the capacitor electrodes.

The method in Fig. 10D shows the process steps used to form a transistor with a large gate capacitor. As in Fig. 10C, the capacitor electrode (gate) is in crystalline 31 silicon, isolated from the rest of the support wafer b L t- y implanting N4 or 02 and by trench isolation. it should be noted that a capacit-or can be made using the same configuration, but by excluding the drain diffusion and connection.

Fig. 10E shows a conservative layout of cells using submerged transistors.

Shared-Bi tC, Lines and -zan-plif iers In the s-;..ngle la7er cells the bit line connections are as mentioned above, side by side. Figs. 11A-C show an alternate met-hod by which bit lines are shared. This is possible if different word lines access successive cells and three metal interconnect layers are utilized. In Fig. 11A, each line can be a read or a write bit line depending on whether an odd or an even word line is addressed. For an odd word line (WL1), the left-most bit line serves as a write bi-, line and is therefore connected to the write bit line input of the amplifier (control line "odd wlns"). The middle bit line serves as a read bit line and is connected to the read bit line inDut of the same amplifier. For an even word line (WL2), on the other hand, the middle bit line serves as a write bit line and is connected to the write input of the amplifier and the third bit line serves as a read bit line and is connected to the read line in-out of the amplifier. At the same time, the left most. bit line also acts as a read bit line and is connected to the read bit line input of the amplifier on the left (only the read line input is shown) in the figure, the word lines are routed across the array in Metal 2. The Metal 1 is then used to- reach the Poly gates, with the gate connection located in the area of local oxide between the write and read transistors. In the serially segmented bit line config-uration, the outDut from each segment' ampi if ier connects to the bit jj- nes in the next segment via a pair of pass transistors as show-in for the dedicated bit line configurations discussed eal-1-Jer. In Fig. 11B the bit lines are dedicated for read line or write line, but still with the feature off sharing. Helre, the s8cond bit line is used as a write bit line both for the cell or, -its left a.-Lid the ce"I to its!:-ght. This bit line L_ _. il L_ 2 always connects to write bit line input on the same ampiLL-L.-r, while the read bit line in-put to the amplifie-- is connected to the first or the third bi-- line de ending on if an even. or an L -_ - - t- D L odd word line is addressed.

The cells in Figs. 11A and 11B were assumed to be in a single level process. Fur-t-her area savings will be achievea Lf the mull-i layer process is used also for 'he shared bit line L configuration, as shown in Fig. iiC.

I - Refresh Read-and Write-in a Secrmented Conficrurat-ion Fig. 12A indicates a portion of representative column 1202 in a segmented memory 1200 that may be selected for reading and writing. In the figure it is assumed that the first data bit in a data word of N bits can selectively be connected to one of the first eiaht columns in the memory. Three column address bits, BO, B1 and B2, and their cornplements are used for addressing. Data can be read from or written to either bit line in the last segment 1204 (SEGMENT 0) in column 1202, but there is a small advantage in writing to the read bit line and reading from the write bit line. The coupling is therefore done accordingly, controlled by the signals COPLIOIREAD AND COPLIOWRITE.

The timing of the clamping and coupling signals for '%he segments are optimized for speed and per"'crmance. in read mode, it is preferred tha"L, an addressed., segment be allowed to amplify its signal before any additional segments are connected. In one embodiment, a first increment of time is set aside for the addressed seament, such as, foor example, segment 1204, to establish a signal. At the end of this first time incrementf the second segment in the pair, which would be segment 1206 in this example, is coupled to first segment 1204 by a signal COPL. At the end of a second time increment, the remaining' segments are interconnected.

However, if an inverting amplifier is used in the memory segments, the segment pairs may be allowed to be connected at the outset of a read operation. Furthermore, if the dimensions of coupling transistors 1208 are chosen correctly, all segments may also be connected at the outset of 33 a read operation. This results in simplified logic and in a higher operating speed. In t-his simplified scheme, all segments are clamped at the same time ait the neginning of the cycle followed immediately by an active coupling signal COPL that connects the segments. With inverting amplifiers, memorv re.fresh occurs in segment pairs; all segment pairs are refreshed at the same time. The signal COPL connects the two segments in the pair. This signal may also be applied after a delay that giving the se-lect-ed segment signal time to establish 10 4tself, compansat-ing 'or any disturbance introduced by the _J_ L - L L_ L_ clamp signal. on the other hand, coupling the two segments in a pair with COPL just after the CLMP signal is active is equally reliable, as both segments are disturbed equally. The fact that read bit line BLR in one segment connects to write bit line BLW in the next segment results in nearly full comnensation, without using a compensating signal as discussed earlier. The COPLR signal, which is used to connect one segment pair to an adjacent segment pair, is not applied in the re-Eresh operation. For reading and writing, both COPL and COPLR are applied after CLMP at the beginning of a cycle. A write operation must apply a signal to segment 1204 which is larger than the signal in the addressed cell if the cell happens to hold data of opposite value. If the topmost segment in column 1202 is being written to, the written signal would have to travel through all the segments in column 1202 to reach the segment at the top of the column. At the same time, a signal of the opposite value may be travelling from the top segment in column 1202 toward the bottom segment 1204. At some point, probably near the middle of column 1202, the two opposite-going signals would meet, and the difference between the two signals would then proceed in both directions. If the written signal dominates, the addressed segment at the top of column 12'02 will have the correct data written. The larger the written signal, the faster the write bit line in the addressed D segment will reach a safe write level.

Onlv selected columns are addressed for the purposes of reading and writing data to the memory seam ent-s in the selected column. in both cerations- the stc-red data in. the tl r 3A I 1 cc!, -T-.,.ns are exposed non-seLected colurns is not modified. L o--he same orizon tal " signals such as COPL, COP!-R, CIIIKIP, WL and DUY. (defining the dummy current level) Figs. 12B through 127- are simulation out-putt-'s. A memory array was simulated that included 2:516 columhs with 16 segments Der colu-nn arranged in 8 segment pairs, where each seganent had 64 memory cells. A 0.5 micron industrial process t 4 at normal opera _Lng conditions was used. A 15ns cycle time was simulated, which provides sufficient margins for reliable I - - operation.

In Fig. 12B, the simulation shows the results when a memory cell storing zero volts on the cell capacitor is addressed by a word line in the top segment. 'I'he write signal is applied to the bottom segment, with a polarity such -'-.--.hat the stored zero will become a one. After the clamn and activation of the coupling signal, the dummy current dominates over the cell current and the read bit line for the addressed segment (BLR15) starts going positive and write bit line for the addressed segment (BLW15) goes negative. At the same time BLWO is pulled low, causing BLRO to go high, thereby initiating writing of a one in the addressed cell. After approximately 9ns the written signal reaches the top segment, causing BLR15 and BLW15 to change direction of transition. BLW15 reaches the full 5 V level at the end of the cycle and the cell is charged to about 3.3 V, which is well above the level of 2.5 V that is generally required to store a one in the cell capacitor.

Tn Fig. 12C, t-he simulation result is shown for the overation of writing a zero over a stcred one in the cell capacitor in the top segment. The cell has a s-LL--ored voltage level of 3.5 V. which is the highest stored one voltage level that can be written without boosting the word line level. This gives the highest possible gain contribution from the stored cell, whi'ch is acting against the written data input applied to the bottom segment. The direction of BLW15 starts turning around after 8ns and reaches 0.3 V at the end of the cycle. The cell voltage tracks BLW15 after 11 ns and reaches 1.5 V after 13ns. A cell voltage of 1.5 V is marginally acceptable for a stored zero level, so the 15 ns cycle time provides sufficient margin at normal operating conditions.

The stored data in non-selected columns is not disturbed, as illustrated by the simulation results shown in Figs. 12D and 12E. in Fig. 12D, a stored zero at a level of 1 V is originally present in the addressed cell in the top segment. Bitlines BLR15 and BLW15 are the first to move due to the dominance of the dummv current to the selected segment over the current from the selected cell. BLW15 falls below I V af' "er 9 ns and reaches close to 0 V at 'he end o-f the cycle.

There is less than a 2 ns delay between BLW15 and BLRO and an actual crossover between BIR15 and BLWO, caused by the fact that -the coupling signal amplitude is limited to 5 V in the simulation. The coupling transistors are not' conducting higher than one threshold voltage below 5 V. Due to a high body effect of the transistor, the threshold voltage Vth at 3.5 V is actuallv 1.5 V. As the same control signals are used for both reading and writing on non- selected columns, Fig. 12D also illustrates the read operation. The differential signal between BLWO and BLRO reDresents the stored data. Fig. 12E shows the simulated result when a stored one at 2.5 V is read. The differential signal between BLWO and BLRO also here represents the stored data.

It is apparent that the read data can be read out long bef ore the end of the 'Lull memory cycle. This is a very important f eature of t2tis type of memory. A memory read or refresh cvcle can be interruD-ted a-IC, any time in the cycle without destroying the stored data. A read cycle can threfcre be terminated as soon as a detectable differential signal between the bit lines in the bottom segment is transferred to the outr)u-L-.. The only disadvantage is that the read cell level will not be re.-Ereshed in an interrupted cycle, but the level w1__ remain the same as at the start of the cycle The voltage level in the cell will therefore remain the same until the next refresh cycle.

if an 1/0 latch 1210 is added to memory 1200 from Fig. 12A, as indicated in Fig. 12F, the delta V in Figs. 12D and 127 can be allowed to be as low at 100 mV. This would mean 6 that data could be transfe=-ed to t1ne latch a-fter only 5 ns A%dditionai t 4 me is naturally required to for-ward the dat.a to the out-nut, but- a read access time of 1 ess than. 8 ns is Dractical" for this array configuration.

The number o-Ef cells ner segment- has an a'rnnact on speed, -which makes it possible to reduce the cycle - time f or reading and refreshing if the number of cells per secment are reduced. The delay through the coupling transistors combined with 'a limited gain in the amplifiers makes it difficult to io write over nreviouslv stored data in the most remote segment without making special arrangements. Simulations run on a memory structure with 256 columns, 8 segment pairs (16 segments) and 32 cells per segment are shown in Figs. 12G-12L. If a cell in the most remote segment is addressed for writing, a read cycle to this segment will progress quite far before a write signal of opposite polaritty reaches the addressed segment. on the other hand, if the hitlines in the segments of the addressed pair are held clamped for an extended time, while awaiting the arrival of the write signal, then the change of polarity between the bit lines will he faster. In Fig. 12G, the clamp signals CLMP and CLMPR for the selected pair are allowed to stay on 2ns longer than the clamp signals for all other segments. All segments are coupled together at the same t.-Lre indicated by COPL becoming active. The write inputs are applied to the bit lines in the bottom segment (BIRRO and BLWRO). The write signal proceeds from segment to segment toward the top ofE the array. Before it reaches the addressed segment, its clamping is terminated and the write signal overcomes the small signal from the cell. At a time of 7.5 ns/ the previously stored zero has been changed to an acceptable one. After lOns, a maximum level for a stored one is reached. Fig. 12H shows the signals for writing a zero over a stored one.

It is important that the columns not selected by the column decoder for writing still preserve 'the stored data in "heir addressed cells. Fig. 121 shows how a stored one is actually restored to its maximum value in the non-selected column. BLR and BLW in the top segment still have enough time 37 to reach their full value. There is however not enough time for the signal generated in the top segment to proceed down to the bottom segment and overcome a noise-generated signal therein. The polarity of the bit line signals in this case 5 does not matter as the output is not used in this mode. Fig. 12J shows how a stored zero is restored in a non-selected column during the write operation. in this case, the noise signal in the bottom segment happened to go in the same direction as the s4Lgnal coming down the line from the addressed segment. The noise source for the bot-'Com segment will be discussed in connection with the read mode below.

Figs. 12K and 12L show simulations of the read mode. To make sure that a signal from the top segment reaches the bottom segment and is correctly presented to the 1/0 circuits some improvements have been made compared to the sequence used for the 64 cells/segment sequence described in connection with Figs. 12B-12E. The negative-going clamp signal will, as discussed earlier, introduce a small negative displacement of both bit lines. In a disconnected segment this would cause the write bit line to move positive with the read bit line remaining stationary. In a long chain of segments, write and read bit lines are alternately connected, so the inside of a long chain is more or less self compensated. The problem arises in the segments at the ends of the chain. For all 23 segments the coupling signals adds a positive compensatioT,. The top segment is exposed to one half compensation from the coupling signal, while the internal segments each are exposed to full compensation. The bottom segment in read mode is coupled to the 1/0 circuit through some form of decoder or to 3 0 an output latch. In either case the coupling transistors controlled by the signal COPLIN connect to nodes with unknown potential and capacitance. it is therefore desirable to connect these nodes to the bit lines during clamping to equalize the potentials. The COPLIN signal is turned on momentarily at the beginning of CLMP and turned on again at the same time as all other coupling signals. Using this technique, Figs. 12K and 12L show how the bottom segment bit lines B_1RR0 an,.' BL#q--Ro correctly reElect the s-Ccrid data.

in the =revious di scussion, it was assumed that s ea - L- - - L - - ments oTDe-aed L-i pairs, so Jt is reasonable to use a s eg m.

ent pair decoder 1220 shown in Fig. 121-1. The low order b-BO in the segment address is used to select one or the other segment. after the higher order bits select' the pair (B1. Bn) The dummy current for instance is applied only to the selected segment, so each segment has its own dummy voltage generator. The dummy -t-rans-istor in the selected segment actually mirrors the current floW4ng through -the dummy voltage generator. The LO current through the dummy voltage generator 1222 is primarily a Function o-- the RAMP voltage and increases the duzzamy current nroDortional to how the cell current varies with the RAMP voltage. The two transistors 1224 and 1226 between the RIUMP-controlled transistCor 1228 and ground are larger and serve mainly as switches. Transistor 1224 is used to define how long the dummy current is to stay on during the cycle and transistor 1226 is turned on only during memory activity and when the specific segment is selected. A three input NOR qat-e 1230 combines the selected pair signal with the ODD/EVEN selection by BO and its complement to select the segment and associated dummy voltage generator. The fourth N-channel transistor 1232 in the dummy voltage generator is very small and in standby barely keeps the P-channel mirror transistor 1234 conducting. A number of global timing signals are connected to all segment pairs. Specifically, DUMTM.defines the active dummy current time, ECLTM defines early clamp time, LCLTM defines late clamp tire, ECPLI-r'-M defines early coupling time, and LCPLTM defines late coupling time. The complement of the refresh command (REFR.B) is also a global signal. REFRB (low level) bypasses the segment pair decoder and applies an early clamp signal to both segments through signals CLMP and CLMPR. An early coupling signal is also applied to the top segment in each pair, connecting the two segments in the middle. The LCPLTY. signal is not delivered in the refresh cycle, thus keeping all pairs separated.

39 Control-of" Logic Cells with DR2%-M.s U.S. Patent Numbers 5,375,086 and 5,317,212, both hereby incorporated by reference, describe methods for controlling the function of logic by using the capacitors in DRAMs as the conk'-rolling element. The D_R;L11 of the Present invention lends itself to control of logic with some advantages over the previously disclosed method.

The control capacitors that are also storage ca-mac-i'Cors in the memory cells are typically larger than what, is recru-i--ed for memory functions. With the leakage currents -in 'he dielectric of the capacitors much smaller than the leakage in the write transistor, successive refresh cycles can occur less frequently. As most of the power at refresh is consumed moving the bit lines, the refresh Dower is inherently low.

However the power consumption can be further reduced by using segmented bit lines, as the Dower consumption is inversely proportional to the number of segments.

The control capacitor Cc, which principally replaces an SRAM cell, must in its high state be at least at a level of Vdd. The cell capacitor is typically connected to the gate of a large pass transistor, which has a gate capacitance of Cc.

j p Any signal Vsig passed by the pass transistor will be coupled to Cc through a capacitive voltage divider. The variation on the voltage on a programmed cell is described by Dvc = Vsig x Cgp/ (Cgp + Cc). The sigiial Vsig typically has an amplitude of Vdd. If Vdd is 5 V and Cc = 4 x Cgp, then Dv-_ will be 1 V. The programming is asynchronous to any signals in the controlled system. If programming occurs when the passed signal is at. Vdd and the programmed cell voltage is Vcellp, then the cell voltage will be reduced by Dvc, when the massed signal has returned to ground. The gate to source/drain voltage will go from (Vcellp - Vdd) to (Vcel!D Dvc) during the negative tranS4 L t on. Conversely at a following transition the gate to source/drain voltage will go from (Vcellp - Dvc) to (Vcellp - Vdd).

if the programming occurs when the passed signal is at ground level, then the cell voltage will increase by Dvc when the vassed signal goes from 0 to Vdd. The gate to source /drain voltage w- 11 go frozzi Vce! In to (Vcell-o + the design goal Dvc - Vdd) during t,- i e positive t- rans i 4" ion 7F is -o eaual the performance of S-P,4-M control, t-hen Vcel,p is a__ a level of Vdd. The SRAM has a relatively high output resistance, so in a negative transition the gate voltage w -i I drop and recover wi-'Zh a time constant off (-_R1ou4L-_-pu1L-_ x Cgo) if it. is assumed that- this slows the negative transition approximately as much as the transition would be slowed by reducing the gate to source voltage to Vdd - Dvc at the end of LO the transition, then a relatively high value such as 2 V could be chosen for Dvc. When the Dositive transit--ion occurs (assuming that the programming was done when the signal was at. Vdd level) the gate to source voltage would go from 3 V to 0 V, while the SRAM-controlled gate to source voltage would go from Vdd to a positive voltage caused by the same time constant of (Routput x Ccm) - but limited by the forward-bi.ased diode from the drain of the P- channel transistor to its N-well (approximately 0.6 V).

If the programming had occurred at a low signal, both transitions would have been faster than for the SRAM case, with the gate to source voltages (assuming Vdd - 5 -volt) 5 V and 7 V in the two extremes of the transitions. To program Vcellp to 5 V, the supply voltage to the word line of the amplifier must be anproximately 6.6 V due to the high body ef_e.:t on the short channel transistors. If Dvc = 2, the c ' ell voltage would peak at 7 V. The pass transistor gate would however be exposed to amaximum of 5 V, while the full 7 V would stress zhe gate of the sense transisto-- and the extended' storage capacitor. if 7 V is the specified maximum voltage, the word line voltage would also be permitted to go that high. The amplifier supply could then be 5.4 V and a Dvc of 1.6 would be chosen. The cell capacitance is determined by the relationship Cc = (5 1. 6 - 1) x Cg-_p 2.125 x Cgp. A pass transistor may have W 20 L and L =.5 or a total gate area of 10 psq.

The cell capacitor area would be 21.25 Asq or in the form of a full transistor with W = 4.6 u and L = 4.6 u. -The pass transistor would occupy about 70 Lsq, while the capacitor would 4 n occupy 35 ysa. A caz)acitor with a source.L the middle would 41 only occupy 25 psq. It is apparent that Dvc could be reduced even further at relatively small area cost.

The actual voltages and capacitor sizes depend on process limits and design criteria.

The DRAM cell of the present invention has been described as using three N-channel transistors, but it should be understood that three P-chainnel transistors can naturally also he used, with associated circuits and signals modified to fi4C- the reve--sed requirements.

The addressing of a memory used for control of logic need not be as f ast as for a conventional memory. Data and addresses can be fed serially through shift registers in both vertical and horizontal directions. Recent recTuirements for higher speed of loading uses byte wide data shifting and for more advanced applications random addressing for the writing of control data is used.

Fig. 13A shows a decoder 1300 that may be used to address the word lines. The decoder is operated by N pairs of signals, both tr-ue and complement, selecting a desired word line. The SEGMSEL signal may be global for non-segmented memories or may be derived from a combination of a global enabling signal and a segment decoder. The low order bit An+1 and its complement selects one segment in a pair to be fully decoded for read and write operations, while the higher order bits are bypassed for the refresh operation. The input to the first inverter 1302 in the segment select circuit is assumed to have a weak pullup device normally. With the decoder activated, the input node is pulled low and the output of the first inverter 1302 enables all word line decoders in the se lected segment. However only the word line selected by AO to An and their complements will track the global VRAMP signal. The output of second inverter 1304 goes low on the selected segment, 'thus allowing the selected word line to go high.

The active time for the cycle is superimposed on An+! and its comnlementsuch that both are low between cycles. Then at the end of the cycle, the input to the _f_rs-C_ inverter 1302 will go high, as will the output of the second inverter 1304. Transistor 1306 will t--hen Dull down the seleced word line ant-_7i 42 hold it and all other word lines to ground. To reach a wc-v-d line voltage of 7 V, -V-_R,'_MP need not go hicher than 7 V, but the address innuts and the out-Dut of -C"he first "Lnverter must reach one threshold higher, which means close to 9 volt. This type of decoder 1300 would therefore be used in connection with a large ratio between the cell capacitance and the load capaci-IC-ance (gate capacitance of the pass transistor), so that the operating voltage could be reduced.

Fig. 13B shows a decoder 1310 with a boosting feature which allows most of the circuits to onera-lCe at normal Vdd levels. A WLENABLE and a complement W=ESET is applied globally or from a segment select circuit. in the enable mode, LIN on the decoded circuit is nulled low, setting the previous reset latch. When the LIN signal is low and the LOUT signal is high, nodes DN2 and DN3 are elevated to a level that is one threshold voltage below Vdd (e.g., 3. 5 volt). The timing diagrams in Fig. 13B show the levels of the different nodes. The RAMP signal starts out at a low voltage level of approximately 1.2 V, and WL is brought to that level by fully turning on MNWL. Late in the cycle, RAMP moves from 1.2 V to 8 V, in this particular case. The capacitor MNC is much larger than the capacitance of node DN2, so DN2 will track the rise of the RAMP and the word line. DN2 will end up higher than the RAMP by one threshold voltage, so the word line will go as high as the RAMP signal (e.g., 8 volt). DN2. at 9.6 V might expose the gate oxide of MN3 to the break down limit. Thus, MIN2 acts as a barr-er in that its gate is at 5 V, as is the gate of MN1. By returning the RIAIMIP voltage to 1.2 volt before resetting the word line, the protection of the devices is maintained.

The voltage of a stored one with this conditions would be approximately 6. 4 V, provided the amplifier supply voltage is also at 6.4 V. The maximum stress on gate oxides in the cell is 6.4 volt plus Dvc.

When controlling logic, the high voltage on the cell is of most concern, even when an stored zero at a level of about 1 V may be acceptable. Another alternative is, therefore, to implement a decoder using P-channel devices only. Fig. 13C shows decoder 1320 that is the equivalent of Fig. 13B, 43- but. with the polarities reversed. The common node f or the sense transistors and cell caDacitors in the cells are connected to the 6.5 V supply indicated in the figure. The low RAM-P level is -1.5 V in relation to 6.5 V or the 5 V Vdd supply. To approach the Vss level in the controlled circuits, it is desirable for the RAMP to go to -1.5 V, thus overcoming the high threshold voltage due to the body effect of the P-channel write transistor in the cell. The negative sw-ing on the PUMP signal could be limited to 0.5 volt below Vss. The refreshed high voltage on lthe controlling capacitor will be az 6.5 V, but in the read phase of the refresh operation the voltage will drop slightly. For cells with large cazacitors that are used for controlling pass transistors, this voltage drop is very limited due to the long time constant in the combination of the write transistcr and the cell capacitor. In other words, the write bit line will reach the 6.5 V level before the cell car)acitor has been disturbed more than a small fraction of 1 V. The refresh phase with the R-kMP and word line at its negative extreme is made long enough to fully refresh both a high and a low cell level. The original storing of control data may require extra long write times or multiple write cycles for very large storage capacitors. All cells can also be procharged to an intermediate level by turning on all word lines, with the hit lines clamped to the intermediate level. The writing will then only need to displace the cell voltage slightly to indicate the stored data. The refresh operations will later gradually charge the capacitors to their full values.

Switched Power Amnlifier in order to further reduce the power consumption in the control memory, it is desirable to let the cell current or the dummy current displace the read bit line as much as possible before the amplifier is powered up. Fig. 13D shows a memory 1330 where each pair of segmentZs 1332 contains only one common clamp circuit. The associated timing diagrams are shown in Fig. 13E. CiamDing to an inter-mediate clamp level is done without r)ower -'-'-o the amolifier and fu'-rther timed so that at 44 --wo segments in each Da-Lr are cou-1ed tcge±he- du-4ng leas -"he 4" the clamping. All four bit lines will '"LIL-lere-ffore be "Eloati.ng close to the clamp level at the beginning of the memory cycle. Applying the low ramp level to the word line starts the displacement of the read bit line in the selected segment. When the selected bit line has been displaced sufficiently for good operating margins, the power is applied to the selected segment,. This is controlled by an early timing signal, EPERB, which is negative true. When the -inverting amDlifier in the selected seament- has disDlaced its write bit line a certain amount, power is applied to the non selected segment in t--he pair (controlled by LPWR) and the two segments 1332 in '"he pair are cou-Dled IL-oaether to form a full amnlifier. After - L - increasing the ramp voltage and holding it at its high level for a time, the cell is refreshed and the cycle is terminated by turning off power, clamping, and coupling all segmen-ts together. In the read and write modes, indicated as REFRB, all segments are coupled together at the early coupling time (ECPLTM). As described in connection with a regular memory, a very large signal is applied to the bottom segment of a selected column which dominates over the signal detected at the selected segment.

Mi-xz-=.d Cell Types on Common Bit Lines Typically large cell capacitors are required to control the gate level on pass transistors. At. the same time, the bit line ca-oacitances can be kept low by uti-Lizing the segmented bit line approach. The ratio of -t-he cell capacitance and the bit line capacitance will in such cases be:1:1-igh enough to impose a large bit line displacement at reading a conventional DRAM cell. In other circuits controlled by 'the control memory, such as look up tables, the cell capacitor can be very small and the preferred cell is of the new DRAM type. It is possible to have both types of cells on common bit line pairs, as indicated in memory 1340 shown in Fig. 13F. Here, an approach with non-dedicated bit lines has been used, which means that a given bit line can be used as a read bit line or a write bit line deDending on LIP the address is odd or even. in t "his type of arrangement, the bit line capacitances reimain equal The dummy current " is applied to the bit line that is active for reading a new type of cell and is applied to the bit, line to which the selected conventional DRA-M cell is connected.

The dummy charge at reading a conventional DP-kM cell is the product of the dummy current and the dummy current on time, which operates with '"he same margin as for the new DRAIM cell of the present invention. The bit lines are clamDed to an interm ed iate level (e.g., 3.5 V) at the start of the cycle, which is higher -Chan the flrst IRAMP level of 1.2 V_ A fully charged conventional cell capacitor (e.g., 5.6 V) will also be well above the word line voltage of 1.2 volt. The cell transistor is off and the dummv current increases the bit line voltage at the same rate as at reading a new type of cell.

if, on the other hand, the cell capacitor is discharged to a low level (e. g., 0 V), charge is drawn from '"he hit line, reducing the bit line voltage more than the dummy current is able to compensate before the amplifier dominates the displacement of the bit lines. With a normal RAMP signal, the word line voltage is increased later in the cycle bringing the cell capacitor to its refreshed level, also for a stored one. In the word line, addressing is sequential without regard "Co what ty-pe of cell is used. In Fig.!3F, WLAO and WIA1 indicate even and odd word lines addressing conventional cells, and WLBO and WLB1 indicate even and odd word lines addressing the neNw type of cells. The dummy voltages DUM10 and DUM1 are active negative and turn on. the dummy current on BL2 and BU resDectivelv. Note that to write a one (high voltage -on' the capacitor) on an even cell of the new type, BL1 must be forced high by the write circuit, while on the other hand BL2 must be forced high to write a one on an even cell of in a conventional DRAdX. The programner must therefore take this into account when pre'aring the control data. only if cells of the same P type are used for a given range of addresses an alternative approach can be taken. In that case, using -16-,.he -figure as a basis for the discussion, even addresses would apply to conventional cells iolaced on BL1 and DUM-1 would be activated or all even add-resses call4mg this Ivoe of cells. This would 46 however place unnecessary rest-rictions on the cell distribution.

The timing for ref--eshing a stored zero and a stored one in a conventional cell is shown in Fig. 13G. Not-e for the stored zero that the exchange of charge continues only until the cell capacitor has been charged to one threshold voltage below WLAO. This also Doints out the need for frequent refreshing as a cell charged by leakage current to close to one threshold below the initial word line voltage will cause a read error. in reality, the large cell capacitors used in this configuration at the refresh frequency dictated by the new type of DRAM cells will be charged very little between cycles. The COUPL signal and the disturbance on the early bit line signals have not been shown in this figure as '"his is of interest only in the initial write mode and in the read mode used for checking that the written data was correctly stored (mainly in production tests).

Disabling Seaments Above Selected Secments In both read and write operations, the segments above the selected segment need not be activated. This is done by forwarding the segment select signal to the segment above, as depicted in Fig. 14A. In each segment an OR is formed by the segment select signal and the selected signal from the segment below this or signal is then forwarded to the segment above, where it is treated as the select signal from the segment below.

one disadvantage with this approach is the serial delay time to thelast segments in the chain. it is desirable to be able to interrupt 'he clamping signals in all segments before they occur. A parallel approach as indicated in Fig.

14B addresses this concern. In this case each select signal is forwarded to all segments above and each segment has an OR gate as wide as the number of segments that are located below.

If power consumption is not a concern, only the segment directly above the selected one will need to be disconnected from the segment below as indicated in Fig. 14C.

Here the coupling signal is disabled for SELn-l.

47 DRA-M cells with serarate read-and write word lines and cia-nr)ed ampli. fier The DRA"M cell shown in Fig. 15 recraires a larger chit) area and more ccmr-)lex word line drivers, but offers advantages 5 in two areas. The cell has the same advantages as the simpler 4 cell described above in that the content of the cell is notdisturbed during the refresh cycle. The fact that the word line voltage at reading has the full amplitude means that the read t4",Ue is shorter than when the word line is left at an inter-m.ediate level. There is no feedback from the w--rite transistor as the write word line is low during reading. if the refresh frequency is high enough, a stored ZERO will stay very close to Vss and a stored ONE will sta-v one threshold under WLW. Boosting the voltage of WI:v7 can maintain the cell voltage of a stored ONE close to Vdd. This property makes the cell useful for control of logic, where the control node indicated in the figure connects to the logic to be controlled.

The amplifier can have all the forms as discussed before and can also be used in the segmented configuration.

Bit lines need no'" be dedicated as indicated in the figure, but will in the non-dedicated case require dummy transistors on both bit lines under control of the address logic. The assumption is that the layout is more efficient with every other cell reversed around a vertical axle. 25 The amplifier in a different mode of operation can act as a latch, which is first reset, indicating a ZERO, and at reading a ONE is set. This requires that the cell with full cell voltage is strong enough to set the amplifier flip- f1cp. The segmented memory approach can still be taken. 30 Full Amvlifier DP-XM Configurations In situations where fast access is o-f prime importance, the single inverting amplifier in each segment may be replaced with a full latch an-plifier in each segment. This 3 5 allows for simpler control with fewer control signals. The relative ti-ming is however slightly more critical.

The DR2CM with a full amplifier can operate in basically two modes. In Mode 1, shown in Fia. 16A, power is 48 always a-o-:)lied to the arzmliz.ier, and the bit lines are clamped 4- _ -Do'ential, which is the switching po nt of 4-h-e to 'he same latch. in the Mode 2, show-n in Figs.!6B and 16C, power to anwolifier is turned off during the clanning and the first nort-ion of the read cycle. In Fig. 16B, the amplilLfiez is OFF in standhy mode with the bit lines clanned to a re'erence clann level. In Fig. 16C, on the other hand, power is ON in standby leaving one hit line at Vdd and the other at Vss level. The single clamp transistor is turned an at about the same time as nower is turned off. If power is turned off before applying 'he clamp signal the bit lines will reach a voltage of approximately Vdd/2 due to charge sharing. ILI power is still on, the bit lines will eventually reach the switching point level of the amplifier latch. By designing the aniplifier for a switching point level of Vdd/2, the relative timing at. this time is not critical. Power is turned on again, when the input signal has been integrated to a safe level, to guarantee that the amplification will go in the right direction.

The bit lines as shown in Figs. 16A-C are dedicated to reading and writing, which means that all cells in a segment are oriented the same way, with the write transistors connected to the write bit line (BLW) and all read transistor connected to the read bit line (BLR). To allow more options for cell lay)rtL, it may be advantageous to have non-dedi---ated bit lines as illustrated in Fig. 16D. There is a. minor added cost in each amvlifier in having two dummy transistor and controls to select the one corresponding to the address of the selected cell.

Figs. 17A-.M show the result of simulations using a 0..5u NMOS nrocess. The memory module consists of 8 segments per column, with 64 bits/segment, and 128 columns (65,536 bits).

Fig. 17A illustrates reading a ONE in a cell located in the top segment, with the read data propagating from BLR and BLW in the top segment to BLRO and BLWO in the bottom segment.

The da' "a on BLRO and BLWO is forwarded to the 1/0 decoder at about 8 ns (not shown). Power in this case is initially turned off at the same time as clamping takes place (compare to Fig.

49 16C) and is turned on again when reading starts by bringing the wo rd line (WL) to the f irs t -ramp level (1 - 8 V). The signal in the selected segmen'L (the top segment in this case for worst case test) is amplified slightly before the COPL signal connects the selected segment to the rest of the segments that were interconnected earlier by the signal COPL.N. In this simulation the non- selected segments were clamped a little longer by the signal COPLN, which is 0.5 ns longer than COPLI he signall clam-r-ding the selected seamen-"_. The stored energy 4n L an 4 the bit lines of the selected seg-ri L. _Ls now t-ransfe-r-red to the lower segments at the same time as each of the segments contributing to the ampl Lfi cation of the transmitted signal. At about 6 ns, the delayed signal has reached the bit lines BLRO and BLWO of the bottoiv segment and is reaching half of full amplitude at a delay of less than 7.5 ns. All bit lines are very close to the supply rails at the nominal end of the cycle (10 ns). The voltage difference between BLWO and BL.R0 at 8 ns is more than 2.5 V, which is sufficient to supply an output signal via decoder and output amplifier within 2 ns.

The initial cell voltage was assumed to have degenerated due to leakage after the last refresh cycle to 2.5 V, but is refreshed in the shown read cycle to 3.5 V. The cell capacitance in the simulation is 2e-15 Farad plus the gate capacitance c-Iff the sense transistor (MS in Figures 1-3). There is a small coupling from the word line, which can be noticed in the figure, so the final cell voltage when WL reaches Vdd is slightly below 3.5 V. The maximum voltage is determined by the max value of WL less the threshold voltage. The short channel process has a strong body effect on the threshold. The cell current in the read phase increases very slowly with the cell voltage, when above 2.5 V, so boosting the WL voltage above Vdd would have a small effect on speed, but would of dou--se allow for more leakage in the cell capacitor.

Fig. 17B shows the reading o_7 a stored ZERO degenerated due to leakage from 0 V to 1 V. Onlv a limited number of control signals are shown in this figure. It is a clear indication in this figure that the switching point o:ff the amp 4 f i er is be! ow the clamp level def4ned by the charge sharing hetween the lines. This causes the bit lines to dri.-;'ftl_ in the negative direct-ion, before the nosi-Zive current,ror. the dummy transistor less the low cell current causes the L - L read bit line (BLR) to go positive. in the full amplifier this drift is accent-able as long as -the device paramet-ers in the amzli-,ie-- are consistent.

in the write operation (Fig. 17C) the data to be written is applied via the column decoder to BLWO and/c--r BLRO on the bottom segment- This signal is large enough to be !0 amplified and propagate to the selected segment, which has started a normal read sequence, and override this signal. Fig. 17C shows how a stored ZERO is written over by a ONE. BI.RO and BLWO are separated by the input signal already during the clamping operation. With all non-selected segments 1-5 interconnected, the signal is quickly propagated to the selected segment, causing the direction of BLR and BLW to reverse, so that BLW will drive the cell voltage to 3.5 V when WL goes high. Fig. 17D illustrates how a stored ONE is written over by a ZERO.

Turning off power during clamping saves power, as shown in Figs. 17E-N, but adds to circuit complexity.

Figs. 17E-G all have a first ramp level of 1.8 V, while the following simulation used a first ramp level of 1.5 V. The circuit for the dummy current control adjusts the dummy current to an optimal value for a given first r.amp level. The current difference between the cell current and the dummy current varies very little depending on the ramp level, but there is less dependence on device parameter variations at the lowe-r first ramp level value.

Comparing the initial clamp level of Fig. 17E with the previous simulations shows that the clamp level has dropped. This is caused by a change of the cell parameters equalizing the sizes of the read and write transistors and their junction areas. The higher junction capacitance at 0 V, compared to 5 V, brings the clamping level below 2.5 V. The switching point should also be set equal to the clamp level. The clanp pulses CL-NP and CLMPN in Fig. 17E terminated before the word line had reached the first ramn level. This could 51 cause the dummy current, if it had built up earlier to start the displacement of the read bit line prematurely. The margins otherwise are sufficient for correct reading of a ONE, as the figure shows. To eliminate the possibility of: the prcblem discussed above, the length of the clamp pulses in the following simulations were increased. Fig. 17F also displays the dummy voltage, that is applied to the gate of the P-channal dummN transistor. The dummy voltage is also close to its maximum negative value at the and of tha clamp signals. A CFE is read in Fig. 17F and a ZERO is read in Fig. 17G. Figs. 1U."'. and 171 show normal read restore cycles for ZERO and ONE respectively.

It should be pointed out that in a!) cases a refren'.-. cycle is the same as a read cycle except Vhat n1l segments operate simultaneously fully disconnectod from each other. TI: signals COPL and COPLN are therefore inactive in the refresh cycles. All segments are enabled and the low order address bits addresses "the same" word line in each segment. With thc timing for the clamping operaticn used in Figures 17E-Q, CLMP and CEMPN have the same duration and is in reality the same pulse. Figs. 17J and 17K illustrate refresh cycles with the segments disconnected restoring ZEROs and ONEs. comparing Figs. 17H and 17J shows how the bit lines move faster without the added load of the additional segments. This indicates that the refresh cycles can be made shorter than a read or write cycle. Figs. 17L and 17M show the write cycles for storing ZERO and ONE.

Memorv Refresh intersuntion without Delav One reasons why SRAMs are typically preferred over conventional DRAMs is that synchronous systems require that a memory;equest is served without the delays that a DRAM refresh cycle would cause. A great advantage to the DRAM of the present invention is that an ongoing refresh cycle can be interrupted at any time during the cycle without destroying the stored data. Data stored in the call capacitor remains intact most of the time or is rafzashsd during the end of the cycle. in ongoing refresh cycle can he sto7phd as long as the word 52 line is brought low as 'he first sten. vigs. -18""-B show "--he simulations of inter=-u:)'Ling re-1--esh cycles after 6 ns and starting read cycles on a address, while Figs. 18c-D show an interrupting write cycle.

In these s imulat-ions the CLIMP signal stalts 1 ns later than in the previous simulations, but ends a'" the same time. The shorter pulse is sufficient for the clamping of the bit lines and the delay makes sure 'hat the bit line voltages have not changed before the word line active during the refresh has been brought down. it is assumed that the refresh and the reading or writing is done in the top segment, with the bit lines BLR and BLW. The word line addressed during the refresh is WLA and the word line addressed during read or write is WLB. Data inDu-L-- and output connects to the bit lines of 'he bottom sea 4- -s ment BLRO and BLWO. The interrupting memory cycle sCart with signal INT, which in the simulation was used;to force the WLA low, while the decoder was selecting WLB. In Fig. 18A the cell addressed by WLA (CELLA) is in the ZERO state, starting at 0.5 V and during the read phase of the refresh cycle is lifted to 0. 6 V and returned to 0. 5 V when WLA is turned off (capacitive coupling between WLA and the cell capacitor) The cell to be read is at 2.5 V and is brought to 3.5 V at the end of the interrupting memory cycle. In Fig. 18B the cell to be refreshed (CELLA.) is at 2.5 V and the cell to be read in the interrupting cycle (CELLB) is at 0.5 V.. The reading returns CELLB to 0 V.

In Figs. ISC-D the refresh cycles are inter-rupted by write cycles. In Fig. 18C the cell to be refreshed (CELLA) is at 2.5 V and remains at the same level after interrupting the refresh before WLA has been brought to 5 V. CELLB starts at its previous value of 0. 5 V and at the end of the write cycle is at 3.5 V. In Fig. 18D CELLA remains at the 0.5 V it was at the start' of the refresh cycle, while the voltage of CELLB is changed from its previously stored value of 3.5 V to 0 V. In the write operation a signal COPLIN occurring at the same time as the signal COPLN is applying the input data to the bottom segments bit lines BLRO and BLWO. As can be seen these bit lines proceed in time the bit lines BLR and BLW in the top 53 segment, contrary to the situation in Figs. 18A-B, where BLR and BL-W come first.

Figs. 1SA-D illustrate how a me-mory cycle can interrumt. a refresh cycle wi-'C-hout destroying the stored data for an arbitrarily chosen time in the refresh cycle. In the example a previously degenerated cell voltage was chosen (some time after last refresh) An incomplete refresh due to an _Lnterrupting memory access will cause further degeneration until new uninterrupted ref.---sh cycle is per-forim-ad. The address of the cells of the int-e--rupted re-Eresh would be retained during the memory access (accesses) and would be the first, address used when the refresh cycle is resumed. With the very low refresh frequency compared to the high memory access rate very large blocks of data with very short interruptions would have to be transferred before the refresh integrity -.-ould be in danger. As a backup for all eventualities a long delay circuit could he used to interrupt the flow occasionally.

* Related to the idea of interrupting an ongoing refresh cycle at any time without destroying the stored- data is the concept of performing a fast burst read. A fast burst read operation involves reading data from the memory cell without completing a reff"resh cycle following the readoperation. In the DRAM of the present invention, this is possible since the data stored in a memory cell is not destroyed when the contents 23 of the cell are read, eliminating the need to refresh the contents of the cell. By reading data from a memory cell without a subsequent refresh cycle, the amount of time needed to perform a read operation is typically halved. Thus, the possible frequency of read cycles is doubled, improving the efficiency of memory oDeration. of course, it should be understood that a standard DRAM refresh cycle must still be performed. The fast burst read operation essentially turns the customary' read/refresh operation into a strict read operation, allowing a read operation to be performed without an associated refresh o-e-ation.

t-1 - DRLM Cluster Cell 54 in anct-her embodimen-t-, the DR-b-M o-L2 the nresent invention may include more than cne storage capacitor associated with a single pair of read and write t-ransistors.

Fig. 19A shows a simplified circuit diagram 1900 of a "cluster 5 cell" using four storage nodes C1-C4. instead of having one storacte node at the common (COM) node, any of the four node cazacitors CI-C4 can be connected to COM during a read or write oneration. The COM node can be looked upon as a very short bit line in a conventional DRAIM and all the t-echniques 'or layout and processing can be applied to t-he cells on the COM "bi-;%--line. 11 The number of cells that can be placed in the cluster denends on the relation between the memory cell capacitance and the capacitance of the COM node. The diagram in Fig. 19A shows 'Lour memory cells in the cluster, merely by way of example. The COM node capacitance includes the junction capacitance of the COM bit line, the source junction of write transistor 1902, the drain junction on CLMPCOM transistor 1904 and the gate of sense transistor 1906. The COM bit line may have relatively high resistance, so minimum active junctions can be used.

In operation, the primary DRAM cell, which normally reads and restores the charge stored in a capacitor connected to the COM node, has been modif ied so that any of the cell capacitors Cl-C4 on the COM bit line can be connected to COM bef ore the reading and restoring of the charge on the selected cell. Due to charge sharing between a cell capacitor and the COM node, %there is a slight modification of the cell voltage after the connection. The actual voltage on the COM node depends on whether a ONE or a ZERO was read in the previous cycle. in order to make the effect of the charge sharing more predictable, the COM node is clamped to a fixed level between cycles. Once the cell is connected to COM, a normal cycle is then execu'ted. Fig. 19A also shows a portion of a word line decoder 1910 coupled to master word line WL and four slave word lines WLCI, WLC2. WLC3 and WLC4. A number of global signals are also shown that define active time for the different horizontal lines. An active subcell is selected by a decoder (not shown) and applied at, a specified time on ClTIMTEB, C2=-IEB, C3TIME--B C-r C4TIMEB. An amplifier 1920 is also shown in Fig. 19A, and its performance is similar to that described L above.

Fig. 19B shows the timing relationship between the different signals. For example, the reading and restoring of a ZERO and of a ONE is shown. The charge sharing effect between the cell capacitor and the COM node, when the COM node ca'Dacit-ance when the capacilCances are equal is also ustra t ad.

With the COM node clamped at 2 V between cycles, the displacement on the stored value while reading is the same, but in opposite directions. The cell current to BLR is normally limited by the low WL voltage on read transistor 1908 and therefore increases less than linearly with the cell voltage.

1 r The cos-IL- of adding a separate write word line 1920 is minimal to address this limitation, as shown in an alternate cluster cell configuration 1950 in Fig. 19C. The high WLR voltage (5 V) renders the cell current quadratically dependent of the active voltage on sense transistor 1906 (the COM node). The much higher read current on BLR nakes for an even faster read operation and higher margins. The timing diagrams for the circuit of Fig. 19C is shown in Fig. 19D. if a cluster cell is read before a refresh cycle, the cell voltage will have been modified by charge sharing with the COM node, as described above. A second reading may still be correct if the COM node capacitance is very small compared to if4 the cell capacitor. The mod Lca4;_-ion is however progressive from cycle to cycle, so a burst read could only be permitted once or twice before the cell is refreshed. The same restriction applies to interrupted refresh cycles for reading the same or other addresses and writing to other addresses. Note that the two tier configuration described earlier is still valid in'the cluster cell as long as the second tier design takes into account the charge sharing ef"flect. 3-5 0 f thcse o --F s 'K 11 in The scone o:ff "Che invent-ion should, thila-re-fore, be dste=mined not with rafterence to the;-:--bcve descrilp-'Eicn, huti-..S-t---=d should be deter=iidned c-laims along with their.-full scone of equivalents.

Claims (4)

CLAIMS:

1. A method of submerging a transistor in a semiconductor support wafer comprising the steps of:

etching a recessed area in the support wafer; depositing a polysilicon layer in the support wafer; polishing the support wafer; implanting a dopant layer in the support wafer; growing an epitaxial layer on the support wafer; and implanting a gas in the support wafer.

2. The method of claim 1 further comprising the step of heat-treating the support wafer.

3. The method of claim 1 wherein said step of implanting a gas further comprises the step of implanting oxygen in the support wafer.

4. The method of claim 1 wherein said step of implanting a gas further comprises the step of implanting nitrogen in the support wafer.