GB2351582A - Dymanic random access memory - Google Patents

Abstract

A dynamic random access memory comprises a storage capacitor 204 for storing charge representative of a stored value, a write transistor 206 coupled to a first plate of the storage capacitor 204 and a first bit line BLW, a sense transistor having a gate coupled to the first plate of the storage capacitor 204, a read transistor 208 having a first terminal coupled to the sense transistor and a second terminal coupled to a second bit line BLR,<BR> a word line VWL or respective word lines (WLR and WLW, Fig 15) coupled to a gate of the write transistor 206 and the gate of the read transistor 208, and a sense amplifier 212 coupled to the first and second bit lines. A clamp transistor 210 may be coupled to the first bit line BLW and a clamp line.

Description

2351582 DYNAMIC RANDOM ACCESS MEMORY

BACKGROUND OF THE INVENTION

The present invention relates to the operation and manufacture of integrated circuits. More specifically, in one embodiment the invention provides improved dynamic random access memories (DRAMs), methods of operating dynamic random access memories ard methods of making dynamic random access memories.

In the attempt to increase the number of bits an present DRAMs, methods are sought for shrinking device is dimensions while still maintaining high enough capacitance in the storage capacitors so that data can be reliably stored, refreshed and read. For example, new dynamic random access memories are disclosed in Application Serial No. 08/353,788, filed December 12, 1994, and U.S. patent number 5,396,452, each of which is hereby incorporated by reference, wherein a memory cell contains separate read and write transistors.

In another example, substantial space could be saved merely by providing smaller capacitors in present DPAMsHowever, smaller capacitors are generally refreshed more often than larger capacitors, as it can be assumed that the leakage current is the same. The capacitance of a bit line is proportional to the number of bits on the bit line. -The refresh power consumption is proportional to the frequency of refresh cycles multiplied by the number of bits per bit line, where the refresh. frequency is- inversely proportional to the cell capacitor size. Therefore, the space advantages of a DRAM with smaller capacitors are mitigated by the higher power consumption of the required additional refresh cycles.

From the above examples it is seen that an improved dynamic random access memory is needed, along with imprcved methods of operatting such memories and improved methods of making such memories.

2 SWIMMAJRY CF ME-E The mresent invention is directed, in one embodiment, to a memory structure having short bilt line sec -L L. %_ r-,rLe.-,its. Each b" line segment is coupled to a separate block of memory cells and a corresponding amplifier. The bit line segments are sema--a&.-.ed by pass transistors. The amplifiers are activated in all three modes of operation: read mode, write mode and refresh mode, while the mass k-ransistors are enabled only in connection with data inDut and io output. Very small cell capacitors can be used in this configuration, making it possible to use conventional gate capacitors, but Dower consumption is not appreciably increased. Furthermore, the speed.of the memory for read and write operations is faster than present DRAMs with long continu6us bit lines coupled to a single amplifier.

In another asmectt. of the invention a memory is provided wherein the contents of the memory can be read without any interference from ongoing writing, reading and refreshing. The memory is structured in two tiers, meaning that in addition to a first tier, a DRAM with addressing, reading, writing and refreshing, a second tier with separate addressing from the first tier is used to read the contents of the cells in the first tier.

Improved methods of forming a dynamic random access memory are further provided according to the present invention. For example, in one aspect of the invention, a method is provided for -ú0c-,.- =ing a memory cell for use with programmable logic devices that must be controlled with relatively large camacitors. in progra=able logic devices, pass transistors transfer signals between locations in the device. The controlling capacitor must be significantly larger than Ithe gate capacitance of the mass transistor, so A..

that the voltage on the controlling capacitor is relatively constant during the signal transition. A multi-layer approach 1-0 forming the memory allows Che cont--olling to be located underneath the mass transistors and the memory cell transistors.

3 A further understanding of the na Cure and advantages of the inventions herein may be realized by reference to the remaining portions of the specification and the attached. drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Figs. IA-B show simplified block diagrams of a segmented bit line memory.

Figs. 2A-E show circuit and timing diagrams of latching and inverting amplifier circuits.

Figs. 3A-J.show circuit diagrams of clamp circuits according to the present invention.

Figs. 4A-C show circuit and timing diagrams of a two inverter amplifier.

13 Figs. 5A-B show simplified block diagrams of control logic circuitry for the memory of the present invention.

Figs. 6A-C show circuit and timing diagrams of a single inverter amplifier.

Figs. 7A-E show circuit and timing diagrams of alternate embodiments of amplifier and control circuits according to the present invention.

Figs. SA-H show circuit and timing diagrams of a two-tie-r memory.

Figs. 9A-F show process flow and layout diagram!j for wafer preparation of the memory according to the present invention.

Figs. 1OA-E show alternate process flow and layout the memory according to the diagrams for wafer preparation oA present invention. 30 Figs. 13-A-C show layout diagrams of a shared bit line memory. Figs. 12A-M show circuit and timing diagrams for refresh read and write cycles in the memory of the present invention. 35 Figs. 13A-G show circuit and timing diagrams of control circuitry for the memory according to the present invention.

4 -Figs. 14A-C show the dLsabling of segments abcve selected segnments. Fig. 15 shows DRAM cells wilith separa-te read and write word lines and a cla=ed ammlifier. 5 Figs. 16A-D show memory cells according to the present invention-with a full latch amplifier in each segment.

Figs. 17A-M show the result of simulations using a 0.5u NMOS orocess.

Figs. 18A-D show how an ongoing refresh cycle can he int-arrupted at any time during the cycle without destroying the stored data.

a-- -age jjRAIf ha more than one st.5 capacitor associated with a single pair of read and write transistors.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Fig. 1A shows a simplified block diagram of a memory including segmented bit lines 102, made up of a read bit line BLR'and a write bit line BLW. Each bit line segment 104 is coupled to a separate block of memory cells 106 and a corresponding amplifier 108. Bit line segments 104 are separated by pass transistors 110 in line with bit lines 1-02.

Amplifiers 108 are activated in all three modes of operationz.

read mode, write mode and refresh mode. Pass transistors -110 21 5 are enabled only in connection with data input and axtput Address lines 112 select the particular memory calls 106 -to 'ie accessed. A word line decode block 114 is usad tD za'act a desired word line -while segment decode bloc'.1k -31IS Used to selected a desired bit line segment 104.

Low order address bits select one of the word lines 116 in the segment selected by a segment decoder. The higher order address bits select a bit line segment 104. In a refresh mode, the low order bits select one word in each segment, and the segment decoder is bypassed to enable all segments. It should be noted that in an alternative embodiment, rather than separating the address lines into low nes and high order bits, a single set of multiplexed address 1.

may be implemented. The bit lines in the selected segmients that are ncr.mally clammed to a clamp level of Vdd/2 may be released to flca-t during a period when the clamp is off. The selected word line 116 is then brought to the first ra=m level, and a dummy current is turned on for the selected bit line segment 104. The voltage on the read bit line in the segment changes quickly due to the low bit line capacitance.

The voltage displacement due to the cell curreni- can actually be of the same order of 'magnitude as the final displacemenk caused by the ampliffier, when power is turned on later in ,0 the refresh cycle. The amplifier 108 will therefore use mostof. its power dissipation to bring the bit lines to the power rails. Both latch type and the inverter type amplifiers, each Off which will be described further herein, can be used. As described earlier, the ramp is brought to its high level for a is moment, increasing voltage. an ward line 116, when the high bit line has reached Vdd, completing the refresh operation before power again is turned off. In the very end of the cycle the clamp signal is applied again.

In order to read data from memory i00, all bit line segments 104 are initially disconnected, and the clamp input is brought low on all segments. This permits bilt lines 102 in all segments to f loat. Only one word line 116 in only one bit line segment 104 is selected in the read mode. When the read cycle has reached a point where amplifier 108 has been turned on and amplified the signal slightly, the bit line segments 104 on one bit line 102 are connected. The interconnected segment lines initially appear as delay lines consisting of RC elements. The capacitance c corresponds to the camacitance of the individual bitt- line segm.ents; 104, while the resistance IR corresponds to the impedance of the coumling trans-4s.L--or. This is however nct a regular delay line, as each segment 104 also has its own anplifier 108. This allows a signal to proceed ;--om segmen"L- to segment verry cruick-ly while also be-ing am-riplified. in a typical memory configuration, a column decoder would select columns to be subject- af- the reading or w-----1k--ing of data. The non selected columns will st-i-1-1 be addressed by t-he word line 116 selected by t-he wcrd =Ut ine decoder il,' Wkien 'he an-m14' a On k"Le OU4 _r 1. - - tud I-- - - 6 has the rails, the is connected by the Column deczder to t_he reg-is"k-er of memorY.

-In a write data is connected via ithe col=n. decoder ito the. bottom segments of the selected columns.

The write circuit forces the bottom segment separation to be much larger than the seoara".---Jon of the segments in the addressed and read segment at the time of coupling the segments together. If the read data is than the data to be written, two signals of different polarity will proceed in opposite directions down the "delay line". The signal with the largest amplitude will determine the final polarity of the addressed segment.

in the refresh mode, the segments remain disconnected during the full read-restore cycle. As mentioned above, one word line in each segment is selected by the. low order address bits in the word line decoders and the segment decoder is bypassed so Ithat all segments are activated the same way. The dummy current circuit is also activated in all segments- The control circuit in Fig. IB clearly shows how the refresh mode differs from the read and write modes in the word line decoding. It should be noted that -51. the amplifier 108 in each segment 104 consists only of an inverter, the time required flor refresh may be longer than the time required for reading and writing. The read bit line in each segment is driven only by the difference of cell current and dummy current. This current is increased significantly at the end of the cycle, but the sigmal on the read bit line is not enhanced by amplifier 108. In reading and writing, on 'the other hand, segments 104 are intercoruiected, so that the read bit line on the first segment is connected to the write bit line of the second segment and so on. This means that the output of one segment amplifie-r drives the input to the next segmen. amplifier in the read and write modes. The delay "hrough the "delay line" must of course be taken into account rred t when comparing the timing requirements. It is m--r-efe- L hat all modes have the same timing, as this simplifies the global control clrcuits.

7 Theref ore, very small cell capacitors can be used in this conf igura."%-ion, making lit- possible to use conventional gate car)aci"--ors. The speed of the memory far reading and writing is faster than the same type of memory with long continuous bit lines.

The addressing and control of memory 100 is shown in Fig. 1B. Memory sequence generator 140 receives memory control sig-nals such as Memory RequestC, and Read/Write Enable and provides control signals 142. Amplifie-r control signals 142. combined with hign order segment. address bits 112, are input to segment decoder control block 118 (Fig. IA) to control a selected one of memory segments 104. Refresh counter 144 initiates a refresh cycle when necessary. The output of refresh counter 144, combined with low order word is address bits, are input to ward line decoder block 114 (Fig. IA) to select a particular word line in memory 100. Memory sequence generator 140 also generates additional control signals, such as CoDl 1/0, Block Address Enable and 1/0 Latch Clamr), that are input to a column decode block (not shown) that accesses a desired column of memorly 100 for reading, writing or refreshing.

The type of amplifier 108 used depends an the application for memory 100. For the highest. possible speed, where disturbance on the cell capacitor voltage is permitted to be high, a basic latching amplifier 200 counled to memory cells 202, as shown in Fig. 2A, may be used. Memory cell 202 includes a storage capacitor 204, a write transistor 206 and a read transistor 208. Amplifier 200 includes clamping 4- -co, - t ransistors 210 and cross upled inverters 212. The corresponding timing diagram is shown in Fig. 2B. It should be noted that for highest speed with a given transistor size in memory calls 202, a higher initial cell current can be obtained if the threshold voltage on write transistor 206 is increased. There is of course a great advantage to using a standard CMOS process for ithe memor, if mixed with 1, especially logic. The segmien-'L.-.ed bit line a-.-.mroach and small call capacitors 2204 are prefer-red to maintain Ithe highest possible 8 memory speed. in that case, the sagme.-Lit-s would he coupled together just- after a=lifiier log has been powered un.

I 2A, at the I n operation of the memory sho-w-n in Fig. end of a memory cycle, Ithe power to the ampli-l"ier is turned off and VCLAYIP is turned on, clamping the bit lines to the clamp voltage level (VCLAAPL) which is typically about half of the Vdd level. At the beginning of a new memory cycle, VCIAMP is brought low, allowing the bit lines BLR and BLW to floatVWL is then brought "to an init--ermediate level that is at least high enough to draw current from the read bit line BLR. if the voltage on cell capacit-o-r 204 is high (a stored ONE). If, on the other hand, the voltage on cell capacitor 204 is low (a stored ZERO), an excessively high signal level on VWL will charge the cell capacitor through write 2.5 transistor 206 during the read portion of 'the cycle. A slight, increase of the cell voltage while reading a stored ZERO -ftrom cell capacitor 204 is acceptable since the resulting read current is minimal compared to the cell current while reading a stored ONE. At the same time the first word line voltage is applied, a negative going voltage is also applied to du=y transistor 214, causing it to feed a current to BLR which is designed to be about equal to the average current for reading a stored ONE or for reading a stored ZERO from cell capacitor 204. As shown in Fig. 2B, BLR is pulled in the positive direction when a stored ZERO is read because the dummy current dominates. While reading a stored ONE, however, the cell current dominates and pulls BLR in the negative direction. As soon as Ithe voltage difference between tl-.e bit lines is suf ficient. for reliable operation, the supply voltages VDDA and VSSA for latching amplifier 212 are applied. Bit lines BLR and BLW will then quickly move to their respective rail voltages. once each bit line is close to its final voltage, 4- %-he vol±age on the word line VWL is increased to at least a level of VDD. A previously stored ONE will now be refreshed 33 to approximately one threshold voltage less than VWL, while a previously stored ZERO will be restored to 0 V.

1JE speed is not the p,-!---imary goal and the disturbance level on the cell capacitors 204 is allowed to be high, the 9 basic inverting amplifier 220 COU'Pled to cells 202, as shown in Fig. 2C, may be used. The operation of the memory shown in Fig. 2C is similar to that of the memory shown in Fig. 2A. Amplifier 220 includes clamping transistor 210 and a simple inverter 222. The clamping to a common reference level, which is chosen to be close to the switching point of the amplifier, is not very accurate, as the -switching point of the amDlif iers varies with changes in the device paramet-ers. The timing must 'C:heref ore be ade.-aat-a. to allow the cell current to dis-olace ic the read bit line BL-R at least as much as the error be-fore, since the bit line voltages represen"t the actually stored data. The power to the inverter amplifier 220 should not be turned on before the worst case clamping error has been compensated. This will prevent the write bit line BLW from temporarily going to a ground level with the word line on, which would cause a stored one to be discharged ' "o a zero. A stored zero an the other hand would not be affected if the w=ite bit line inadvertently went to the high level, while the word line voltage is still at its lower level. The preferred method is to wait a sufficient time until a potential clamping error has been comnensated for. The amDlifier will then consistently move the write bit line in the correct direction. As discussed earlier, power consumption can be minimized if mower is turned on even later in the read mode, so that read bit line BLR has moved closer to a rail voltage. I-LE the inverting amplifier is used in connection with segmented bit lines, the coupling can be made only when the clamping error has been comiDensal:ed and the signal has been a-mplified somewhat. Fig. 2D shows the timing for amplifier 220 in Fig. 2C, and Fig. 2E indicates the amplifier's performance as 4.

part of a segmented bit line configuration. Note in the lattiter case how the partially amplif ied signal on both bit 1 ines BLIZ and BI:4 is temporarily reduced when the adjacent segment is connected. Again, the read bit line BL_R on the - is connect - ite bit line BLW on the read segmienl L-ed to the wr -ogether act as a plural-J-1y of next segmen"L The saamen'It's 4 1- %.

"-ant th-at a! a:=1 ---s are lall--chad am.mlifiers. it is imoo- _ -Enowered uz before th.e sagments are coupled, as this guarantees a gradual amplif ication o 'I the initially reduced signa 1 before it progresses down the full bit line. Without amplification, the signal on the read bit line BLR of the read segment would be reduced to a small fraction of its original value. For a memory structure where a bit line is made up of eight segments, then, the signal would be reduced by a factor of eight. This signal is too weak to overcome the clamping error on some of the segments.

Compensation of Clamping Error In applications where the cell current is low, yet fast memory cycle times are still needed, it is desirable to minimize the clamping error. Figures 3A through 3G illustrate the different clamping devices and methods. Fig 3A shows a preferred structure with clamping transistors 302 and 304, which was also-shown in Figs. 2A and 2C_ Both bit lines will reach the reference level VCLAMPL, while VCLAMP is high, but when VCLAMP goes low, the gates of the transistors 302, 304 will couple a small negative charge to each of the bit lines.

The voltage drop on the bit lines can easily be as much as 100 =V, if a short clamp time is desired. To achieve a short clamp time, the clamp transistors 302, 304 must be relatively large. Segmented bit lines, with their lower capacitance, will have smaller clamp transistors than fulllength, unsegmented bit lines, but the ratio of gate capacitance to bit line capacitance is the same and therefore the result is a comparable disturbance. The latched amplifier 200 (Fig. 2A) is relatively immune to the clamping offsets that appears equally an both bit lines. Latched amplifier 200 suffers from a non-correctable offset error due to device parameter variations. The two cross-coupled inverters 212 may have different switching points. one of the bit lines will therefore be moving at a different rate after clamping than the other bit line. The cell current must be larger than the built-in offset current for a correct reading of the selected cell. If used in a segmented bit line configuration, there is a risk that one or more of the non-selected segments may start to switch on their own before the segments are connected, 11 which could result in a read error. The clamp circuit in Fig. 3B addresses this possibility by adding transistor 306 that directly shorts the bit lines during clamping.

The inverting amplifier 220 (Fig. 2C) is sensitive both to the difference between its switching point and the reference VCL and to the effect of turning off VCLAMP. Instead of waiting for the read bit line to overcome the worst case clamp error, another approach may be taken, as shown in Fig. 3C. VC"T! again connects both bit lines to a cam. "non reference voltage VCPL while power is off, but VCl is turned of f as soon as power is turned on. VCLAMP2, an the other hand, turns on at the same time as VC"Pl, but stays an longer. When power is turned on, the bit lines are at the potential of VCL, which may be different than the is switching point of the invertez. VC"P2 shorts the input and the output of the inverter, so that the bit lines are moved to the switching point, thus putting the inverter in "11 balance before the cell current is applied to the read bit line. Note that turning off VCMP2 causes a negative displacement of the bit lines. The displacement on the read bit line (the inverter input) is most critical and must be compensated by coupling a positive charge to the read hit line. The clamp shown in Fig. 3D accomplishes that objective. Here, -the connection to the reference voltage is done with a P-channel transistor 308. VCB goes positive at essentially the same time that VCUMP goes low. The P-channel transistor 308 has a relatively high on resistance compared to the N-channel clamping transistor 306 and the impedance in the inverter associated with searching the switching pcint centering. The purpose of the Nchannel transistor Us is to maintain the bit lines close to the switching point at for a longer stand-by period. Since the switching point is set to half the Vdd level (Idd/2), and the bit lines before clamping are set to the rail voltages, the potential of the bit lines after clamping will therefore be Close to Vdd/2. The width and length of the P- channel transistor 308 can be chosen such that the requirement for ban high impedance and the req-2--ired coupling of charge to the read bit line BM can be met.

Fig. 3E illustrates the addition of compensating capacitors 310 and 312 betWeen VCLA14PB and bit lines BLR and BLW that are chosen to fully compensate at turnoff of the clamp transistor 308. In Fig. 3F, VCLAMP1 holds bit lines BLR and BLW at the reference level in standby mode, while VCLA"2 remains high after power has been turned on to inverter 220 (Fig. 2C). The charge transfer to the bit lines. when CLAKIP2 is turned off, is compensated by VCLAMPB going positive. The compensation is necessary on the inverter input, but is less 1-0 critical on its output, so the compensation can be limited to only one capacitor on the read bit line.

As will be discussed herein, the advantageous features of inverting amplifier 220 and segmented bit lines in Fig. 1A can also be applied to conventional DRAM calls. In is that case, the DRAM cells are connected to both bit lines. This type of clamp circuit is shown in Fig. 3G. The associated amplifier includes two separately powered inverters and two separately driven compensation capacitors 314 and 316. A similar amplifier arrangement can also be used for the DP-kM cells of this invention, except that a common drive signal for the compensating capacitors shown in Fig. 3F can be used. The compensating capacitors used in a conventional DRAM may serve two purposes. First, they supply the charge to compensate for the negative charge transferred when VCLAMP2 goes negative, but the size of the capacitor is a little larger than required for that compensation. The added charge pre-biases the bit line to which the read cell is connected, so that reading a cell will give the same absolute voltage difference between the read bit line and the switching point for both a charged and a discharged cell capacitor. In reading and writing data in a segmented bit line configuration, the segments that are not addressed must have their read bit lines BLR very close to the switching point not to cause errors. The compensating charge transfer for these segments, must therefore be less than for the selected segment. This can be accomplished by using a lower amplitude on the compensating voltage or, of course, a separate compensating capacitor can be used to add 1-he du=y charge on the selected segment.

The amplitude of the clamp signal for all the cases discussed above is the full Vdd vol,,'-.age, resulting in a large ca-jaci-ll-.ive coupling when the clamp signial is turned off. In the initial time period after clamming, the bit lines will still be close to the clamping level (Vdd/2). This means that the clamp signal need not initially go more negative than to ((Vdd/2)+Vth). As the cell current proceeds to separate the bit lines, the^ clamp signal must track the negative-go.4;-ng bit line. The arrangement in Fig. 3H shows such an ccnfiwara.'.'_ion.

io Here, when VCLAMP is turned on, transistor 318 lifts the gate of transistor 320 to (Vdd-Vth), which clamps the bit lines together. The transistors 322 and 324 act as diodes and are designed as relatively weak transistors in order to limit how much they can pull the clamped bit lines positive while VCLAY-P is is high. Transistors 322 and 324 are actually designed so that the positive excursion during the time of clamping is exactly as much as the negative capacitive coupling when VCLAY.P goes low. When transistor 318 is turned off, t-ransistors 322, 324 proceed to mull the gate of clamp transistor 320 %toward the lowest bit line voltage plus the threshold voltage of transistor 322 and transistor 324. With a normal threshold, this tends to hold a slight clamping for a short per-lod, reducing the gain of the inverter for small cell currents. Bv terminating the cla--.nD signal early or by using lower threshold voltage on:322 and 324,,%--his problem can be eliminated. When the bit lines eventually move, the low-going bit line will continue to keep the gate of the clamp transistor 320 justt below -4-'"-s threshold voltage.

in several of the ampliffiers, the assumption has been made that the amoli..ioier power is permanently connec411-.ed.

This means that the bit lines are close to Vdd or Vss between cycles. clam.ping onera,"%--ion will then have to swing -t-he bit lines as much as Vdd/2 to the switching point of the ammlifier. The time required for the clamping operation is in case longer than -when the bit- lines sta.L.'cull:

close to the clamp level. ',.he clantping circuitt as shown in Ficr. 31 is used for tnis mu---oose and cons c:E one N-c."-annel clanz transist-or 226 and two capacitors, here shown as 14 transistors 328 and 330 with both source and drain connected to the associated bit line, for compensation of the Lurnof-JE disturbance.

Fig. 3J shows a single N-channel clamping transistor 332, used in connection with clamping under power. Amplifier pow er -is selectively turned on and off during a memory cycle. In cycles repeating frequently, the bit lines start out very close to the switching point. At the end of each cycle the 'two bit lines are clamped together after having been close to the opposite rail voltages. The refresh frequency must satisfy the requirements for the small cell capacitors, so larger bit line capacitances will discharge very little between cycles.

The amplifier's VddA and VssA nodes are both 13 connected to the reference level Vdd/2, which is the nominal switching point level. Any leakage through the transistors would go to this level. only junction leakage could cause the bit lines to drift away from the reference level. Theinverter transistors would however limit the drift to one threshold away from the reference level in either direction.

Starting from this worst case situation, the adjustment toward the switching point after applying power to the amplifier follows the table below. The inverter has a W/L ratio for the N and P transistors of 1.2/.6 and 2.4/.6, respectively, while the bit line capacitances are 100 fF (IOOE-15).

Time after power an VBLR - Vref ns mv 0 -600 2 -376 3 -163 4 - 68 - 19 6 5 7 - 1 8 0 Turning off a clamp transistor of with W/L of 2.4/.6 introduces a disturbance of -80mV. The disturbance must be considered in relation to the cell current. The rate of voltage change on the read bit line is 10mv/(gAns) for the bit 0 line capacitance of 100 fF. A differential cell current (Icell - L. J. - - - - Idummy) of SgA would change the bit line voltage at a rate of 50mv/ns. Turning off the clamn after 5ns, with the cell current on, would result in full compensation 7ns after the start of the cycle, overcoming 80=v plus 19mv. At lower cell currents the clamming will be turned off about Ins later, and it would take longer to compensate for the offset caused by the clamp transistor. At a differential cell current of lgA., the L total time to compensation would be about 14ns. The polarity c-40- the disturbance on the read bit line is such that- the write bit line for the lower cell currents may go positive to near the Vdd level.. This would not cause any disturbance on the addressed segment. If however the read bit line starts out. alt. Vref + 60OmV and the clamp transistor turns off while the read bit line- is still more than 80tV above the reference, t_he-write..bit. line would go negative.

Only if the clamp is turned of1E very early could the write bit line go below the ward line voltage, tlius turning on the write transistor and write a zero in a cell that was a one.

This case is very remote as the word line voltage would by design not be turned on that early.

A more serious problem occurs in reading and writing data in a segmented bit line configuration. The disturbance introduced by turning off the clamp voltage would remain on the non-selected segments. The current -It--c the write bit line caused by an SOnv differential voltage on the read bit line is approximately 12gA, with the inverter dimension as discussed above. The bit lines would be displaced at a rate of 120MV/ns and thus completely override the contribution from the selected segment except for rather high cell currents. A cell current of lgA will change the read bit line voltage alk: a rate of 10mv/ns.. The displacement on the write bit line after T nS follows lEhe equation Vdispi =!cell (gA) 10TSquared/2mV. "A - of 1Oga would 2ns have displaced the read.

cell current bit to +120=V and the write b-i+ line to -120-,,iv, VInile at the same time lt-he bit lines on the ncn-selec"t"-ed segments would have moved 240tV mosilt-live. A simula.'.-.ian has sl,-c;m ithatt a cell current c-E at- least 40Lt-k would be rect-ii-ted to operat-e an 1 - - i6 8-sagment memory, ass-L--n-Ing hit line ca-pacitan.ces off!00 By Clam, Di.- g J- 4 u s 4 n q d -, If -F e r e n It for selac-ted and non. selected Ef the clamming on segments, the problem is highly reduced. I the non selected segment is tterminat-ad just before the signal coupling the segments tcgether is turned on, the volt-age between -'Che non-selected segments would be approximat-ely 100 mV. Allowing the bit lines in the selected segment to be displaced more than k100 mV before coupling, where k is the number o-E segments, would yield more reliable operation. Some !0 of the amplifiers shown, may use a second inverter in each segment which can be selectively engaged. Allowing the second inverter to con"'Cribute to the amnlification in the selected ies the above-stated segment before the coupling satisIA. requirement it was assumed above that the power to Che amplifiers was selectively turned on and off during the memory cycles. The method of clamming to the switching point of -the inverters used in some amplifier conf igura tions, however, makes it natural to omerate the amnlifiers under -full Dower all the time. This means tha't- in standby mode, the bit lines will always be at or close to the rail voltages. The clamming will, when used in connection with an inverter, bring the bit lines to the inverter switching point against the transistor that is in the holding mode. The final adjustment to the switching point level will therefore take somewha4: longer than if the bit lines start out. already close to the switching point as described before.

Fig. 4A ii-Ilust-rattes an amnli-.Eier 400 Ln-Cended for segmented bit lines. The basic inverting amplifier consists of transistors 402 and 404 that make up the first inverter, while the second inverter with transistors 406 and 408 may be added for additional amplification later in -the memory cycle. Transis-'Co r 410, w1hen turned on by the signal VIYV2 will connect the output of the second inverter to the input of the first.

The clamming is done by turning on the clamping transistor 412, thus shorting ithe bit lines BILR and BLW and adjusting to the switching point level of the first inverter. The selected word lines on+ the selected segments are brought "CO the reading level m_7 a'%.-. essen-'Cially the sa-_,t-Le time as VCLA.M-2 goes low. The read biLt line BLR at this time has a predictable o-_Ffsait error as discussed above, due to incomplete adjustment to the switching point during clamping and the capacitive coupling from VCIA.MP, when it goes negative. With only the first inverter connected (VINV2 low), the cell current will both overcome the offset and displace the bit lines sufficiently for a correct refresh level. I-ff limited to only the f irst- inverter and no coupling between se-gments, this would be a relatively slow operation of high power consumption.

In the refresh mode, as discussed above, the segments remain separated and refresh cells on their selected word lines. To speed up the refresh cycle, the second inverter is connected a" the time when the bilt lines are separated on the order of 100 mV. The amplifier now acts as a conventional latching amplifier. When the memory is used in read or write mode, ithe offset on non-selected segment must still be considered. At the time of connecting the segments, "the signals on the non-selected segments must be an order of magnitude smaller than the signal an the selected segment. As shown in the timing diagrams of Fig. 4B, a different approach is used that guarant- ees a suitable ratio between the signals. For the selected segment the clamping takes place firs'. in the cycle, allowing the signal to grow, d. riven by the first 23 inverter. Then the second inverter is connected and the higher amplification proceeds for some time until the segments are interconnected by the signal VCOUPL. A temporary drop in the signal is followed by the mutual amplification from the c--oss coupled segment inve--ters. only the selected segment has its second inverter contributing. The non-selected segments as shown in the lower timing diagram all have a delayed, clam.-p signal that is tur-ned off jusit before VCOUPL is turned on. The=efore, the only signal on the bit lines of the non-selected segments is the offset signal caused by the turnoff of the clam.-D signal. Once Ithe coupling has been estab,is.--ed, ithe second inverters on the non-select-ad segment-s are turned on, ad,_'14-%6- read . _ional smeed to the o-oeration. The bottom sagments in th--e selected cclu=.s may use mode, ithe read he early cla=p signal in w.-cycle to amply the write s.-;.gnal, so that the si--nal at, Che bottom segmeni= at h_11e time oA joficiently larger t -han the signal on a selected segment other than -the bottom 5 segment, to guarantee correct writing.

Fig. 4C shows amplilfier 420 that is a variation off the two inverter amplifier. In amplifier 420, the clamming L-rans-istors include both N transistor 412 and P transistc-- 422, and coupling transistors include both N transistor 410 and P transistor 424. By optimizing the design in this way, most off 1.he clamping disturbance can be eliminated.

it has been mentioned that different timing is required for selected and non-selected segments. Figures SA and 5B show the logic required for each segment for controlling an associated amplifier. All segments have the same' logic shown in Fig. 5A, except. the bottom segmenth of a bit. line, shown in Fig. 5B, that is used for transferring data in and out of the bit line. A memory cycle may be initiated by a separately timed refresh request or an interrupting Block Enabie or Chip Enable signal. Word Line Decoder block 502 and Segment Decoder block 504 decode the incoming function and address code to select a given segment in the memory and a given operation (a read or a write) and initiate a timing sequence. The appropriate timing signals are generated and applied to the memory block. The signals are routed to all segment controllers and are used slightly differently for selected and non- selected segment-s. In the refresh operation, which is requested by a free running clock, in one mode all segments are considered to be selected. The applied timing signals in the figures are Early Clamp Time, Late Clamp Time, Selected Segment Inverter an Time (SelInvTime), Non-selected Segment Inverter on Time (NonSellnvTime), Ward Line on Time (WLonTime) and Dummy Current on Time (Du=yCnTime). The abbreviations for these signals are shown in marenlk--heses where appropriate. A ramp signal VRAMP is also applied, which may -be common for the block or be generated in each segment, with the timming controlled by common signals not shown. on ithe diagram. The logic for tile bottom segment shown in Fig. 5B operates 1q d-fFe-enlt-.ly than the other segments during -1the writ erat-ion.

1 1 e op The enabling of word line and du=. v current is the sam.e for all he connection o.12 it-he second segments, but the clamp signal and tt inverter are always early for the bottom segment in Ithe write mode. This ensures that the written data gives a dominating signal to the connected segments. in write mode, input data is coupled to BLR of the bottom segment; in read mode, output data is coupled to BLW of the bottom segment.

---ates a memory 600 having two segment Fig. 6.A -ilius4L.-s 602 and 604 where only one inverter 606 and 608, respectively, in each segment operates under f ixed power. Raad bit line BL.R from segment. 602 is coupled to write bit line BLW of the next segment 604 through pass transistors 610 and 612 when VCOUPL is high. Fig. 6B shows the relative timing bettween selected and non-selected segments. In refresh mode, in a preferred embodiment, all segments are considered selected and the coupling signal remains low during the cycle. AlternatiVely, the segments may cooperate in pairs, resulting in the selection of every other s egment. Fig. 6C shows how the selection of segment for refresh is controlled by the add/even bit. This decoding may be common for all segments or local as shown. The coupling signal is divided in two. One signal is used only in t 1-he refresh mode, while the other is used in read and wl-ite modes. The advantage in pairing the segments in refresh mode is that the time and power consumption is reduced due to the higher amplification for the two cooperating inverters. The structure also makes it possible to pre-amplify the signal at reading and writing, before interconnecting all segments. The coupling signal interconnect ing the two seg-ments in the pair is made subject to early selection if one of the segments is selected. This increases the amplifification of the pair of signals. When a dominating signal amplitude has been reached, all remaining coupling signals are activated. For a prere--v-,oei marg-in, clamping is performed at three different Tine, earliest- cia...nm time is j2or the selected segm.en-'- in a segm.ent t in pair, the next clamp time is for the non-selec.'Led tine is for all remai- ning the segment pair a.-d the L.

secr.me'-ri.1k-s.

Conventional DRkMs and_Seqnmented Bit Lines Conventional D"R.'k1,_-,s also crain in speed and ma--cr..ns bv using the segmented bit- line approach. The sho-=e-r bit lines used in conventional DRAMs have a lower capacitance th"alt gives stronger signal for given cell capacitor sizes. This approach actually permits the use of smaller cell capacitors and higher refresh frequencies, as discussed for the new cell type above.

he same methods for minimizing the disturbance caused by the clamping operation apply conventional DPJUT-s. There is, however, a slight difference in the amplifier design. The cells in a folded bit line configuration may be alternately connected to one or the other of the two bit. lines. All word lines with even addresses may, for instance, be selecting cells on one bit line, while all word lines with odd addresses would select cells on the other bit line. In the simplest amplifier discussed earlier having only one inverter, the coupling between segments must complete the amplifier so that the inverter output of one segment connects to the input of the inverter in the next segment. E-Each segment must therefore have two inverters, each selectively used according to which bit line is addressed.

Fig. 7A shows memory cell 700 including an amplifier where while reading cell 701 power is firs"C turned on to inverter 702, whose input is coupled to read bit line BLR holding the cell to be addressed by theyord line. The bit lines are clamped while power is on, adjusting to the switching iDoint of inverter 702. Due "to capacitive coupling when VCLAY.P goes low, t-He displacement on read bit line BLR is cc-rmpensatt-ed by VCOMPODD going positive, as shown in Fig. 7B. The second inverter 704 in a selected segment may be powered up be-fore the segments are coupled together by the VCOUPL signal. For reading and writing opera- iions, this gives a large enough signal to overcome the combined error signals from the non-selected segments as discussed above. The non-selec- l'--ed segments will typically have the bit lines clamped late on the primary inverter 702 so that at t--me of coupling a very small signal has developed. The secondary inverter in non-selected segments is powe-red up only after the segments have been 21 connected. Only in the refresh mode are both inverters 702 and 704 used the same way in all segments. The same principles regarding the inconvenience of turning power on and off applies to conventional s, so the same approach discussed for Figs.

4A and 4B above can also be used here. The only dif f arence. is that, when used. in connection with a fixed Vdd supply, the order of connection of the inverter amplifiers is determined on which bit line holds the addressed cell.

Fig. 7C shows a memory 710 including this type of amplifier 712, with capacitive compensation of the disturbance at the termination of the clamping. The first inver-tter 714, with its input conn'ected to the first bit line BLI has its output connected to the second bit line BL2 when VI""N goes high, while the second inverter 716 connects its output to the first bit line BLI at the time when VI"DD goes high. If, for example, the input of inverter 714 is coupled to the bit line of the selected call, then inverter 714 is activated at the start of the memoW cycle and is used in the clamping operation, which adjusts We bit line voltage to become close to the switching point of the inverter. The second inverter 716 is then activated late in the cycle, when the output from the first inverter 714 is much larger than any offset error due to device variation between the first and the second inverter. For selected segm,ents, the second inverter 716 is activated some time before the.signal VCOUPL is applied. This signal connects the segment to We neighboring segments for read and write operations only. in the refresh made, all sagments are selected and the read restore operation 'is completed with help of both inverters. We VCOUPL signal rwains low during the refresh operation. In the read and write mode, as described above, the second inverter in the non-selected segments is turned yn after VCO"L has connected the senents. Some time is allowed to pe=it the first inverters in all the non-selected segments, in cooperation with the two inverters in a selected segment, to amplify the temporarily reduced si"al enough to dominate over the coupling transient when the second inverters are activated. As indicated in Fig. 7C, the succeeding segment mirrors the previ"s segment, so that an 22 even addressed call is located on ithe right bit line if the even cell on the Previous segment- was located on '11.1e left. Likewise the inverter direction is reversed j-,n the slucceading seg-ment- (not shown in the figure). The t_lming relations between 1Che signals for selected and non selected segments are shown in Fig. 7D.

Fig. 7E shows the segment- control logic for memories 700 and 710 discussed above. The segment control logic of -Fig. 7E is similar to that shown in Figs. 5A, 5B and 6C above, e--cap-L'-- for the separate control all- add and even -inve..Ler and clamp compensation.

Two Tier Memory The DRAM of the present invention by its nature makes it Dossible to design a memory where the content of the memorry can be read without any interference from ongoing writing, reading and refreshing. The memory is structured in "two tiers," meaning that in addition to the first tier, a regular DMAUM of the present invention with normal addressing, reading, writing and refreshing, a second tier with separate addressing is used to read the contents of the cells in the first tier.

Fig. BA shows a two tier memory 800 wilth first tier memory cell 801. The DRAM cell, which includes transistors 802, 804 and 806 with memory capacitor Cl, is addressed by its word line WLi and is treated as part of..an independent memory in the reading, writing and refreshing operations. As discussed earlier, one of the features c.L this DPAM is that the stored data in the memory capaci'%- -zr Cl is disturbed very little during the operation of the memory. As a matter of fact, the high state need not be disturbed at all, while the d_fsturbance in 1Che low state (the voltage on Cl close to zero) can be limited to around Vth. For higher operating speeds a slightly higher disturbance is acceptable. The first tier memory 801can have any of the features discussed above, including being of the segmented bit line type.

In the second tier memory, cell 810, transistor 812 is used to sense the state of Cl and transistor 814 acts as the read transistor. The second 'Itier cell 810 is addressed by 23 WLTi, by applying a high signal thereon. This connects second tier cell 810 to the bit line BLT, which in turn co..=,ec"II_-s to a sense amplifier 816. Amplifier 816 may, merely by way of example, be a single-ended amDliflier, as the signal amplitude is such that. folded bit lines are not necessary for common made noise suzioression- However, folded bit line configurations 820 and 830, such as those shown in Figs. 8B and 8C, respectively, are also possible. Fig. 8D shows a pair of memory cells 842 and 84 A 4 each having first and the second tier cells, 846, 848 and 850, 852, respectively. The first and second tier cells share a common ground bus GND. The connections to the bit lines are common for neighboring primary cells. The second tier cells have separate connections to BLT, but using three level metal and different layout-s, common connection poin4%.-.s can 13 'be used.

Ilt should be noted that the sense trans-Is-Itor in all the previous figures has the source connected to ground as in mosl- cells discussed above. The reversed cell, where the select transistor has the source connected to ground and 'Che sense transistor connected between the select transistor and the BLT, can also be used. This configuration is shown in L_ Fig. 8E. As a rule, this cell requires a larger s-Corage capacitor C1 than the cell with both sense transistors connected Ito ground. The gate capacitance of the sense transIstor In the second tier cell in read mode will couple a disturbance 'to CI, which may cause an error in the memory funcItions of the first tier cell. This is contrary to the normal (non-reversed) cell, where the major part of Ci actually is the sum of the gate capacitances of transistors 802 and 812 (Fig. 8A) Again, the ampli.:Eier for the second tier may be of the folded bit line type, as indicated in figures 8B and 8C.

This would use the same "techniques discussed above in conjunction with memories having only one tier. Segmen'ted --it 13 lines mav be used in this configuration as well.

-Oier 850 with a da-'Ca ouLt- latch A single-ended amnli._ 852 is indilicat-ed in Fig. SE, and a corresponding timing diagram is shown in Fig' SF. The signal VB7AS is held at an 2 1v ir n1termLediate level concial-rrently With VWLT. The current frcm P channel transistor 854 is approxximat-ely half oZ the sun. off 't-he "'s for a zeZ-o cell and a one call. Limiting the cell current negative swing of VBIAS makes P transistor 854 act more like a curren4- source than LE the swing is larger. The cons1 an"k circuit. can be made to operate with somewhat lower margins if designed so that VBIAS goes to ground when activated. The D input an the flip flop is designed to have its switching point line voltage in the two close to Vdd/2, and as long as the hit at-ional states deviates a minimum amount from Vdd/2, "the oper margins are satisfied. The actual moment of reading may in the worst case coincide with the reading of the first tier memory. At this moment C1 may have a disturbed Zero level. The amplifier design must take -,'-his into account and also plan for 15 changes in the charge levels on C1 between -refresh due to I leakage. In the amplifter indicated in F.Igs. BE and 8F, no clamming of BLT to a neutral midpoint is made. Adding this feature reduces the access time of the second tier memory 810, but would not reduce the Dower consumption. The folded bit line annroach has both speed and power advantages, but the gain is highly dependent on the bit pattern in the read data.

Denser layouts using a two-tiered memory may be achieved by using nondedicated bit lines, which ineans. that, a given bit line can be used as a read bil.: line or a write bit line depending on if the address is odd. or even. In this type of arrangement, the bit line capacitances remain equal. Fig. 8G shows part of such a memory using the DRAM cell of the present invention expanded to include a sense trans-istor and a select transistor for the second tier. in the configura,1Cion shown, each column of basic DRAM cells is combined with two folded bit lines for read out in the second tier. Read operations from this memory configuration are very fast. The bit lines are clamped to a mid level, the word lines swing to 4 Vdd when reading, the ampli.Affier is disconnected from the bj_t lines at an optimlim time when Ithe bit lines have just separated from the clamp level, and the reclamping is completed while data is read out from the amplifier. A preli'La-ina-ry layout for this circuit is shown, in Fig. 8H. Other configurations may of course yield a denser layout.

Process for Reduced Area and Hiah Smeed one of the features of the memory of this type is that the conventional C2,4105 process with three metal layers can be used for production of the memory. For dedicated memory chins, the cell area can be reduced anti a! ly if the fused and thinned wafer approach is taken, as also described in U.S.

matent number 5,396,452. in logic circuits where memory and logic is mixed, even larger benefits can be achieved. The approach would be to prepare a wafer ithat, later in the process, would strictly f allow a standard fabrication process.

The added cost in the waf er preparation would be well compensated by the savings in area and the gain in speed.

Fig. 9A illustrates stems in the wafer preparation as follows:

1. A support wafer 902 of low resis-ltivity is used. The areas 904 where capaci-ttors are to be located are etched dawn. A thin dielectric layer 906 is deposited or crown.

2. Polysilicon layer 908 is deposited over thin oxide layer 906.

3. The wafer is polished, so thatt the support wafer 902 and the polysilicon 908 have a common smooth surface.

4. Another thin -oxide laver 910 is grown on the polished surface.

5. The emi layer 912 of, a second wafer faces the - J1 ----_ tom of the support wafer and is fused 4Cheret-o. The asserJ:)ly is then processed as described above so that only the e-mi layer remains on top of the support wafer.

6. Contact holes G-1-4 are etched and plugs 916 are deposited to establish cont-act points to lt-he embedded capaci.-.or 918 and to the subst-rate.

7. If other means have not been used in the stem 33 above to isolate the plugs from surroundin.g silicon, t d trenches 920 surrounding the miuas are defined and etche t the same s-t.--em, the individual transist-ors in the memcry cell and in the resit of the logic are a-is,,5- separated fro-tri each ather L. - - - - I- -. -- 26 -enches 920. The trenches are preferably back-filled wit".11- by -t- a form of glass.

8. P-c-hannel transistors are exposed to N-t-YDe implant and are heat treated 'to a sufficient denth. The surface is next mremared for the aate oxide. 11& the camacitor is to be connected to the gate of a transistor, the gate oxide 922 is removed on top of the contact plug for the capacitor.

To more closely follow a standard fabrication process, the canacitor connection can wait for the metal 1 steo to connect te and the capacitor.

the gat The waf er is now ready to be run in a known three layer metal process. The LOCOS isola-t-Jon process step need not be completed, as the area under the poly contact can be isolated by a trench in step 7 above. This results in a planar tal 1 layer.

met Multi-laver Memory Cell Controlling Logic Programmable logic devices such as Field Programmable -h Gate Arrays (FPGA) have devices that must be controlled wit relatively large capacitors. The mass transistors transferring signals from one data bus to another must be large enough for minimum voltage drop in passing the signals. The controlling capacitor must be significantly larger than the gate capacitance of the pass transistor, so that the voltage on the - during the signal tor is relatively con.,Jtant controlling capaci&_ transition. using the multi-layer approach described above -o,6 -self ideally to this purpose. The 1 Cal area under the !ends i4 pass transistor and under the memory cell transistors can be used for the controlling capacitor.

Fig. 9B shows one DRAM cell 930 controlling a pass 4- transistor N4. The cell 930 includes transistors NI, N2, N3 and a large capacitor Cl located under both the cell and the pass tran sistor. The source oJE INI is connected to the gates of N2 and N4 through first metal layer MI, with a silicon island 35 used to support a feed through to -the underlying capacitor. (The vertical connection is indicated on the left side of the figure.) The combined structure has "three vertical busses, which may be in -the second metal laver M2, with 'two busses 27 reserved 1-for the memory bilt lines and one reserved for a vertical interconnect bus for data. The word line and local connections use layer M-1, while ground and a horizontal data bus use the "top metal layer H3. There are several options to 5 make the connections between the different layers, including feed-throughs in the back-filled areas between transistors. The e-Di layer remaining after thinning the top wafer is usually thicker than a normal implanted source-d-rain diffusion. The transistors therefore have a rema-Lning substrate portion.

Provisions have therefore been made so that this substrate layer may be connected to the underlying support wafer which is at ground level for the N-channel transistors. The substrate layer may be connected to the underlying support wafer which may be at a ground level (Fig. 9C). The support wafer does have N wells to support the connection of the substrate of the P transistors for this reason.

The same procedure discussed in conjunction with Figs. 9A and 9B can alsobe used for the memory cell shown in Fig. 9C. Adding a recessed capacitor 936 increases the storage time of the cell, which reduces the refresh frequency. The gate capacitance of the sense transistor is generally sufficient for reliable operation. With all three cell transistors in the top layer, no additional area is gained by adding a recessed capacitor.

Fig. 9D shows in greater detail a compact cell utilizing a recessed transistor and a double-sided capacitor.

The thin transistors in this figure are not fully depleted, which means that the transistor substrate must be tied Zo ground. It should also be noted that t27.e transistor substrate is one side of a double sided capacitor and for that reason must have a relatively high conductivity. The surface Of t1he wafer to be fused should therefore have a P+ top layer. With the transistor substrate grounded, the source and drain junction capacitances are as high as in the standard processes, while the area e.-ifffficiency is increased as the devices are separated by trenches cut Ithrouch the tam sillicon lave,,_ - The top transistor laver in this case is assumed to be for-,med, by defining an elt-ch st"op by an eni layei;- with- a much different- 28 mpurity c=centration and a dif."-eren-" The etch rate -n J_ " L-1 - Ecre much - the bulk.s theref higher with right choice 0-0 e-.'L--chan.'t-. The remaining layer is 4,.-herei.ore too thick to permit full depletion by the junction implants while still naintaining the small device dimensions.

"ernative approac An altL L. -h has been taken in Fig. 9E.

Here the top wafer used for fusion is of a SIMOX type. The tom t of this wafer has a thin silicon layer separated from k_he bulk by 1.. L t.

An implan ed layer of oxygen. Such a wafer after adding a L0 relatively thick oxide layer, can be fused and thinned down to the buried oxide layer with high accuracy. The transistors formed in this thin layer will have fully depleted junc"b--ions and small junction capacitances. They will therefore be much faster than the transistors in Fig. 9D. The recessed capacitor will however have a 1-21rlicker oxide layer on top, resulting in a value close to half of the fully double sided capacitor in Fig. 9D.

Fig. 9E is a supplement to Fig. 9D, where marker line' 942 denotes the location of the capacitor and marker line 944 the location of the junctions in the sumDort wafer. In the cells of figures 9D and 9E, the bit line connections are not side by side. This permits the layout of a narrower cell than -4f the connection are side by side, which must be the case for single layer cells.

Fig. 9F. shows another construction for a capacitor in combination with a mass transistor in a programmable logic device. In Fig. 93, the capacitor was formed underneath the pass ltransistor. Here, the is instead formed above the mass transistor. In Fig. 9F, a flat capacitor covers most h L of the pass transisti-or area and typically comprises two polysilicon layers separated by a thin dielectric layer. One layer is couple. d to a fixed potential, for example ground or Vdd, whiie the other layer is coupled to the control node from the DIRM circuit. The gate of the mass transistor is likewise coupled to the control node of the DP-kM circuit.

29 Multi-lave- Desims usina Eritaxy and Simax Figs. 10AMOD show alternate methods of submerging capacitors and transistors below a thin epi layer added directly on top of a supporting wafer.

Fig. lOA shows Me stept for making a capacitor with both electrodes accessible. Me sequence of processing is as f allows:

a) A recess 1002 is etched in Me support waf er 1004, which is ass=ed. to be P-type.

io b) N+ material 1006 is implanted but not necessarily heat treated at this time. Me purpose is to f arm an N-channel junction, which will isolate the bottom electrode of the capacitor from the support waf er when operating at levels positive in relation to the support waf er.

is c) - A thin oxide 1008 is grown which will become the.

capacitor dielectric layer. Polysilicon layer 1010 is then deposited until the recess is filled. This can be a blanket deposit (as shown) or a local deposit.

d) The waf er is polished so Mat the remaining surface 1012 is a continuous flat surface, but with no possibility to contact the buried N+ junction.

e) An area covering the capacitor and the intended junction. contact regions is defined and another N+ Mlant 1006 is made.

f) epitaxial layer 1014 is grow, which may require two steps to obtain a usable layer on top of the polysilicon. in the first step the layer is grown veMically and should give single cnstal areas, at least where lhe starting su-rface is single cnstal. In a second step some form of Zone crystallization my be used to include the areas above the poly into the single costa!.

g) In this Step 02 is implanted to a depth enal to the depodited epi layer. After heat treatment, an insulating layer of S'02 is for@med. The remaining layer of the epi!aye= is then used for MOS devices of the type used in Silicon on insulator bechnology. Connections fro= the device layer to the capacitor electrodes uses Mow methods.

F 11 I_ lg. 103 how a transistor such as NI in wa.,e- as -,-he memory cell can be submercred ini. - !-,he sumport follows:

a) A recess 1016 --,s etched in the P- wafer, poly is 5 der)osi,"Led and the wafer is polished.

b) The transistor area is defined and N+ 101s is implanted.

c) The emi layer 1020 is grown as discussed above.

d) 02 is imr)la?.i,'l-.ed. When the wafer is heat treated, S'02 is formed, leaving a device layer insulated from the submerged transistor. The transistor channel goes from the edge of "L-he source implant to the edge of the drain The channel will go in a vertical direction close to source and drain, if tthe depth of the diffusions are less than the depth of the original recess.

Since there is some uncertainty about the silicon crualA4-."-y in the emi layer above the submerged poly layer, it is desirable to consider the ancroach illustrated in Figs. IOC and IOD, where the capacitor electrode is made from silicon. The process for Fig. 10C is as follows:

a) A deem N+ diffusion 1022 defining the area of the camaciltor and its connection regions is made in a P type suDDort wafer.

b) To form a capacitor, dielectric layer 1024, which may be, for examDle, N4 or 02, is implanted in a defined area. the rest c) To isolate t-he capacitor electrode from t c--f the wafer, a trench. 1026 1..s cat". around its edges. The trench 'S refilled with S-402 using known techniques.

cl) Fields of emi layers 1028 are next grown on all silicon areas.

e) Oxygen or nitrogen is now -Implanted to the depth of the epi layer and the completed wafer is heat treated. The ton layer will be used for devices and conventional stems are taken to contact the devices to the capacitor electrodes.

The method in Fig. IOD shows the process steps used to form a transistor with a large gate capaciltor. As in Fig. 10C, the capacitor electrode (gate) is in crystalline 3-, silicon, isolated from the rest ol khe sup- E 'Do- t wafer by implanting or 02 t-ion. it should be noted N4 and by trench isolat that a capacitor can be made using the same configuration, but by excluding the drain diffusion and connection.

Fig. 1OE shows a conservative layout of cells using submerged transistors.

Shared Bi it L4 nes and iers In the s_ingle layer cells the bit line connections are as mentioned above, side by side. Figs. 11A-C show an alternate method by which bit lines are shared. This is possible if different word lines access successive cells and three metal interconnect layers are utilized. In Fig. 11A, each bit line can be a read or a write bit line depending on whet-her an odd or an even word line is addressed. For an odd word line (WL1), the left-most bit line serves as a write bit line and is therefore connected to the write bit line input of t 1-he amplifier (control line "odd wlns"). The middle bit line serves as a read bit line and is connected to the read bit line input of the same amplifier. For an even word line (WL2), on the other hand, the middle bit line serves as a write bit line and is connected to Ithe write input of the amplifier and the third bit line serves as a read bit line and is connected to 1 At the same time, the the read line input of the amplifier.

left most bit line also acts as a read bit line and is connected "%.c the read bit line input of the amplifier on the left (only the read line input is shown). in 1Che figure,. the word lines are routed across the array in Metal 2. The Metal 1 is then used to reach the Poly gates, with the gate connection located in the area of local oxide between the write and read transistors. In the se-rially segmented bit line configuration, the output from each segment' amplilfier connects to the bit lines in the next segment via a pair of pass transistors as shown for the dedicated bit line c:-,nfiguratt--icns discussed In Fia. 11B the bit lines are dedicated for read line or write line, but. still with the feature of sharing. Here, t line is used as a bit line both for the 1-he sacond bit cell or.. 1 e-f Land It"ne cell to i ts t::'L-L t. This b it 1 ine :3 2 always connects to write bit. line input on t-he same amplifier, while t-he read bit line input to the ampli-fier- is connected to the first or the third bit line de-pending an if an even or an odd word line is addressed.

3 The cells in Figs. 11A and 11B were assumed to be in a single level process. Further area savings will be achieved L. the multi layer process is used also for the shared bit line configuration, as shown in Fig. 11C.

'Refresh Read and Write in a Seamented Conficn-lration Fig. 12A indicates a portion of representative column 1202 in a segmented memory 1200 that may be selected for reading and writing. In the figure it is assumed that the f irst data bit in a data word of N bits can selectively be connecited to one of the f irst e ight columns in the memory Three column address bits, BO, B1 and B2, and their complements are used f or addressing. Data can be read from or written to either bit line in the last segment 1204 (SEGMENT 0) in column 1202, but there is a small advantage in writing to the read bit line and reading from the write bit line. The coupling is therefore done accordingly, controlled by the signals COPLIO-READ AND COPLIOWRITE.

The timing of the clamping and coupling signals for t %-he segments are optimized for speed and performance. In read mode, it is preferred that an addressed segment be allowed to am,oli.,10-y its signal before any additional segments are connected. In one embodiment, a first increment of time is set aside for the addressed seament, such as, for example, segment first time 1204, to establish a signal. At the end of this 4f increment, the second segment in the pair, which would be segment 1206 in this example, is coupled to first segment 1204 by a signal COPL. At the end of a second time increment, the remaining segments are interconnected.

However, if an inverting amplifier is used in the memory segments, the segment pairs may be allowed to be connected a-1k- the outset of a read operation. Furthermore, if the dimensions of coupling transistors 1208 are chosen correctly, all segments may also be connected at the oult-Set of 33 a read operation. This results in simplified logic and in a higher operating speed. In this simplified scheme, all segments are clamped at the same time at the beginning of the cycle followed immediately by an active coupling signal COPL that connects the segments. With inverting amplifiers, memory rezresh occurs in segment pairs; all segment pairs are refreshed at the same time. The signal COPL connects the two segments in -%"-he pair. This signal may also be applied after a delay that giving the selected sagment- signal time to establish itself, commensa-%'---ing for any disturbance introduced by the clamp signal. On the other hand, coupling the two segments in a pair with COPL just after the CLMP signal is active is equally reliable, as both segments are disturbed equally. The fact that read bit l-ine BLR in one segment connects to write bitt. line BLW in the next segment results- in nearly full compensation, without using a compensating signal as discussed earlier. The COPLP. signal, which is used to connect one segment pair to an adjacent segmen'-- pair, is not applied in the refresh operation. For reading and writing, both COPL and COPL.R are applied after CLMP at the beginning of a cycle. A write operation must apiply a signal to segment 1204 which is larger than the signal in the addressed cell if the cell happens to hold data of opposite value. If the topMost segment in coluaLi 1202 is being wrilt-ten to, the written signal would have to travel through all the segments in column 1202 to reach the segment at '&'-.he 1-op of the column. At the same time, a signal of the opposite value may be travelling from the top segment in column 1202 toward the bottom segment 1204. At SCOme point, probably near the middle of column 1202, the two opposite-going signals would meet, and the difference bet-Ween the two signals would then proceed in both d t 411 %_ 11rections. 110 e written signal dominates, the addressed segment at the top of col= 1102 will have Ithe correct data written. The larger the wri-ttten signal, the faster the write bit line in the addressed 35 segment will- reach a safe write level.

Only selected columns are addressed for 't-he purposes - in the of reading and writing data to the memory seaments.t in 'the -ions the d;:.a selec.l-ed column; In bot-11 cnera-'L I- - - 34 is not modified. úk11 columns are e=osed non-selected colurnns to the same signals such as COPL, COPLRI, WL and DUM (def- ining the dummy current. level).

Figs. 123 through 12E are simulation ou"l-nuk'--s. A memory array was simulated that included 256 columns wilth 16 segments per column arranged in 8 segment pairs, where each. segment had 64 memory cells. A 0.5 micron industrial process at normal operating conditions was used. A 15ns cycle.tim.e was simulated, wh4;.ch provides sufficient margins for reliable operation.

In Fig. 123, the simulation shows the results when a memory cell storing zero volts on the cell capacitor is addressed by a word line in the top segment.. The write signal is applied to the bottom segment, with a polarity such that ithe stored zero will become a one. After the clam.p and activation of the coupling signal, the dummy current dominates over the cell current and Ithe read bit line for the addressed segment(BLRIS) starts going positive and write bit line for the addressed segment (BLW15) goes negative. At the same time. BLWO is pulled low, causing BLRO to go high, thereby initiating writing of a one in the addressed cell. After approximately 9ns the written signal reaches the top segment, causing BLRIS and BLW15 to change direction of transition. BLWI5 reaches the full 5 V level at the end of the cycle and the cell is charged to about 3.3 V, which is well above the level of 2.5 V that is generally required to store a one in the cell capacitor.

in Fig. 12C, the simulation result is shown for the operation of writing a zero over a stcred one in the cell capacitor in the top segment. The cell has a stored voltage level of -3.5 V, which is the highest stored one voltage level, t that can be written without boosting the word line level. This gives the highest possible gain contribution from the stored cell, whi'ch is acting against the written data input applied to t 1-he bottom segment. The direcition of B1X15 starts turning around after 8ns and reaches 0.3 V at the end of the cycle.

-1.

The cell voltage tracks BILWIS!l ns and 1.5 V after =ns. A cell voltage o:E 1.5 V is marginally acceptable for a stored zero level, so the 15 ns cycle time provides sufficient margin at normal operating conditions.

The stored dal"a in non-selected columns is not disturbed, as illustrated by the simulation results shown in Figs. 12D and 12E. in Fig. 12D, a stored zero at a level of 1 v is originally present in the addressed cell in the top segment. Bitlines BLRI5 and B11P15 are the firs-'L-- to move due to the dominance of the dummy current to Ithe selected seament over the curren't- fro= -k'.-he selected call. BILPTIS falls below 1 V after 9 ns and reaches close to 0 V at the end of the cycle. There is less than a 2 ns delay between BW15 and BI-RO and an actual crossover between BLRIS and BLWO, caused by the fact that the coupling signal amplitude is limited to 5 V in the simulation. The coupling transistors are not conducting higher "5 than one threshold voltage below 5 V. Due to a high body effect of the transistor, the -threshold voltage Vth at 3.5 V is actually 1.5 V. As the same control signals are used for both reading and writing an non-selec. 4k-.ed columns, Fig. 12D also illusl-rates the read operation. The differential signal between BL-WO and BLRO represents the stored data. Fig. 12E shows the simulatted result'. when a stored one at 2.5 V is read. The differenitial signal between BLWO and BL.RO also here represents the stored data.

It is apparent that the read data can be read out.

long be-fore the end of the full memory cycle. This is a.very A memory read or important feature of this type of memory. All refresh cycle can be -inter- -uin-'%.-.ed at any time in the cycle without dest-roving the stored data. A read cycle can therefore be terminated as soon as a detectable differential signal between the bit lines in the bottom segment is transferred to the output. The only disadvantage is that the read cell level w411 not be re-freshed in an interrupted cycle, but the level wi 11 remain the same as at- the start of: the cycle The voltage level in -tt-he cell will. therefore remain the same until 33 t-ne next refresh cycle.

f an 1/0 ia'tch i210 is added to memory 1200 from Fig. 12A, as indicated in Fig. 12F, the delta V in Figs. 12D and 1212E car. be allowed to be as low a 100 mV. This would.nean tl.Lalt data could be transferred to latch after only 5 ns.

Add-44tional time is natuirally recpalired to for-ward the da-%'--a It o 2 less than 8 ns is the output, but a read access time of -his array configuration.

nracticall for It The number olf cells per segment has an impact. an possible to reduce the cycle t-i e for speed, which makes it M reading and refreshing if the number of cells per segm-ent are reduced. The delay through the coupling transistors combined with a limited gain in the amplilfiers makes it i- 1-o 7, - - !0 write over previously stored data in the most remote segmen-It without making special arrangements. Simulations run on a -h 256 columns, 8 segment pairs (!6 memory structure wit segments) and 32 cells per segment are shown in Figs. 12G-12L.

I -:' a cell in the most remote segment is addressed-f j. &or writing, is a read cycle to this segment will progress quite far before a write signal of opposite polarii-y reaches the addressed segment. on 1-he other hand, if the bitlines in the segments of the addressed mair are held clamped for an extended time, while awaiting the arrival of the write signal, then the change of polarity between the bit lines will be faster. In Fig. 12G, the clamp, signals CLY.P and CIMPR iffor the selected pair are allowed to stay on 2ns longer than the clamp signals for all other segments. All segments are coupled together at the same time indicated by COPL becoming active. The write inputs are applied to the bit lines in the bottom pegment (BLRRO and BLWRO) The write signal proceeds from segment to segment toward the top of the array. Before it reaches the addressed seament, its clamming is terminated and the write signal overcomes the small signal from the cell. At a time of 7.5 ns, the previously st-ored zero has been changed to an acceptable -ored one is reached.

one. After lOns, a maximum level for a st Fig. 12H shows the signals for writing a zero over a stored one.

It is important -that the columns not selected by the column decoder for writing still preserve the stored data in 1 121 shows how a stored one is their addressed cells. Fig. act-Ually restored to its maximun. -value in the non-selected column.. BLR and BLW in the top segment still have enough time 37 to reach their full value. There is however not enough time for the signal generated in the top segment to proceed down to om sagment and overcome a noise-generated signal the botl". L 1 therein. The polarity of the bit line signals in this case does not matter as the output is not used in this mode.

Fig. 12J shows how a stored zero is restored in a non-selec'L..ed column during the write operation. in this case, the noise signal in the bottom segment happened 'Co go in the same direc-t-ion as the signal coming down the line from the addressed segment. The noise source for the bottom segment will be discussed in connection with the read mode below.

Figs. 12K and 12L show simulations of the read mode. To make sure %that a signal fro= the top segment reaches the bottom segment and is correctly presented to the 1/0 circuits some improvements have been made compared to the sequence us.sd for the 64 cells/segment sequence described in connection with Figs. 12B-12E. The negative-going clamp signal will, as discussed earlier, introduce a small negative displacement of both bit lines. In a disconnected segment this would cause the write bit line to move positive with the read bit line remaining stationary. In a long chain of segments, write and read bit lines are alternaltely connected, so the inside of a long chain is more or less sel. J. compensated. The problem arises in the segments at the ends of the chain. For all 23 segments the coupling signals adds a positive compensation. The ton segment is exposed to one half compensation from the coupling signal, while the internal segments each are exposed to -full commensa"'tion. The bottom segment in read mode is coupled to the 1/0 circuit through some form of decoder or to -30 an output latch. In either case the coupling transistors controlled by the signal COPIZN connect to nodes with unknown potential and capacitance. it_ is therefore desirable to connec-14: %these nodes to the bit lines during clamping to eaualize Ithe notenIt -Jals. The COPLIN signal is turned on 'momentarily at, the beginning of CLMZP and turned on again at the 4 same time as all other coupling signals. Using "L-.hS technique, Figs. 12K and 12L s'now how the battom sec - e T:rient hit. lin s B_T_:RRO and BLre7_RO corrac-"k-ly reflect ths stcred data.

33 in the previous di, scussicn, it was assumed that se=.en--s operated in pairs, so it is reasonable to use a segment pair decoder 122,0 shown in Fig. 121H. The low order BO in the segmen"L-. address is used ta select one or the ct-her seg-mer.,1"- after the higher order bits select Ithe pair (31.... Bn) The dummy current for instance is applied only to the selected segment, so each segment has its own du=y voltage generator. The dummy transistor in 't-he selected secment actually mirrors -he dummy voltage generator. The the - current flowing 'through t I- L- current through ","!-,a dilmny voltage generaltor 1222 is primarily a function of the P-AM-P voltage and increases the dummy current promor.'-- ional to how the cell current varies with the PAMP voltage. The two transistors 1224 and 1226 between the RAY-P-controlled transistor 1228 and ground are larger and serve mainly as switches. Transistor 1224 is used to def ine how long the dummy current is to stay on during 4Che cycle and transistor 1226 is turned on only during memory activity and when the specific segment is selected. A three input NOR gate 1230 combines the selected Dailr signal with the ODD/EVEN selection by BO and its complement to select the segment and associated dummy voltage generator. The fourth N-channel transistor 1232 in the dummy voltage generator is very small and in siCandby barely keeps the P-channel mirror transistor 1234 conducting.

A number of global timing signals are connected to all segment pairs. Specif-ically, DUVITM.defines the active dummy current time, ECLTM defines early clamp time, LCLTM defines late clamp -ttime, ECPLTH defines early coupling time, and LC=M defines late coupling time. The comnlement of the refresh command is also a global signal. REFRB (low level) bypasses the segment pair decoder and applies an early clamp signal to bath segments through signals CLMP and CLMPR. An early coupling signal is also applied to the top segment in each pair, connecting the two segments in the middle. The LCP= signal is not delivered in the - afresh cycle, thus keeping all pairs separalted.

39 Wntrol of Logic Cells with D"s U.S. Patent Numbers 5,375,086 and 5,317,212, both hereby incorporated by reference, describe methods for controlling the function of logic by using the capacitors in 3 D"s as We controlling element. Me D" of the present invention lends itself to control of logic with some advantages over We previously disclosed method.

The control capacitors that are also storage capacitors in the memory cells are typically larger than what is required for memory functions. With the leakage currents in. the dielectric of the capacitors much smaller than We leakage in the write transistor, successive refresh cycles can occur less frequently. As most of the power at refresh is consumed moving the bit lines, We refresh power is inherently low.

However the power consumption can be further redi,,ced by using segmented bit lines, as the power consumption is inversely y proportional to the number of segments.

The control capacitor Cc, which principally replaces an SRAM cell, must in its high state be at least at a level of Vdd. The cell capacitor is typically connected to the gate of a large pass transistor, which has a gate capacitance of CgpMy signal Vsiq passed by the pass transistor will be coupled to Cc through a capacitive voltage divider. The variation on the voltage on a programmed cell is described by DVC = Vsig x Cgp/ (Cgp + Cc). The signal Vsig typically has an amplitude of Vdd. If Vdd is 5 V and Cc = 4 x Cgp, then Dvc will be I V. The programming is asynchronous to any signals in -. e the controlled system. If programming occurs when We passed signal is at Vdd and We programmed cell voltage is Vcellp, then the cell voltage will be reduced by Dvc, when the passed signal has returned to ground. The gate to source/drain voltage will go from (Vcellp - Vdd) to (Vcellp Dvc) during We negative transition. Conversely at a following transition the gate to source/drain voltage will go f rom (Vcellp - Dvc) to (Vcellp - Vdd).

if the programming occurs when the passed signal is at ground level, then We cell voltage will increase by Dvc when the. passed signal goes f rom 0 to Vdd. The gate to scurce/drain voltage will-1 go Vce-1-1m to (Vceilm + LD -he des gn goal.VC - Vdd) during the mosittive transition. _Iff t is to equal the per,-oor-iuan--e of SR.M -Control, then Vceillp is at, a level of Vdd. The SRAM has a relatively high output resistance, so in a negative.11-ransi'--ion the gate voltage will drop and recover with a time constant of (Rloutpult x Cc.)) If is assumed that this slows the negative transition approximately as much as Ithe transition would be slowed by reducing the gate to s ource voltage to Vdd - Dvc at. the end of the transition, then a relatively high value such as 2 V could be chosen for Dvc. When the Dositive transition occurs (assuming that the programming was done when It-he signal was at Vdd level) the gate to source voltage would go from 3 V to 0 V, while the SRAM-contralled gate to source voltage would go from Vdd to a positive voltage caused by the same time constant= of (Routput x Cg-p t_ ) - but limited by the forward-biased diode from the drain of the P- channel transistor to its N-well (approximately 0. 6 V).

If the programming had occurred at. a low signal, both transitions would have been faster than for the SRAM case, with the gate to source voltages (assuming Vdd + 5 volt) 5 V and 7 V in the two extremes of,'--he transitions. To program Vcellp to 5 V, the supply voltage to the word lineof the amplifier must be ar)mroxima"--ely 6-6 V due to the high body effect on the short channel trans-s--ors. If Dvc = 2, the cell voltage would peak a,'t- 7 V. The mass transistor gate would however be exposed to a maximum of 5 V, while the full 7 V would stress the gate of the sense transisto= and t_11e storage capacitor. if 7 V is the specified maximum voltage, the word line voltage would also be permitted to go that high. The amplifier supply could then be 5. 4 V and a Dvc of. 1. 6 would be chosen. The cell capacitance is determined by the relationship CC = (5 1.6 - 1) x Cgp = 2.125 x Cg-p. A pass transistor may have W 20 g and L =.5 g, or a total gate area of 10 gsa.

The cell Capacitor area would be 21.25 gsq or in the JEorm of a full "L-.r-ansis"k-or with W = 4.6 g and L = 4.6 g. The pass transistor would occulpy about 70 rescr, while the capac-ltor would t_ - - occupy 35 gsa. A capacitor wi-l-l..i a source in the middle would 41 only occupy 25 gsq. It is apparent that Dvc could be reduced even fur-ther at relatively small area cost.

The actual voltages and capacitor sizes depend on process limits and design criteria.

The DRAM cell of the present invention has been described as using three N-channel transistors, but it should be understood that t-hree P-channel transistors can naturally also be used, with associated circuits and signals modified to fit the reversed requirement I- 1-s.

The addressing of a memory used for control of logic need not be as fast as for a conventional memory. Data and addresses can be fed serially through shift registers in both vertical and horizontal directions. Recent recru-Jrements for higher speed of loading uses byte wide data shifting and for more advanced applications random addressing for the writing of control data is used.

Fig. 13A shows a decoder 1300 that may be used to address the word lines. The decoder is operated by N pairs of signals, both true and complement, selecting a desired ward line. The SEGMISEL signal may be alobal for non-segmented memories or may be derived from a combination of a global enabling signal and a segment decoder. The low order bit An+! l- selects one segment in a pair to be fully and its comDlement L- - decoded for read and write operations, while the higher order b.,Lts are bypassed for the refresh operation. The input to the first inverter 1302 in the segment select circuit is assumed to have a weak pullup device normally. With the decoder activated, the input node is pulled low and the oultput of the first inverter 1302 enables all word line decoders in the selected segment. However only the word line selected by AO to 2Ln and their complements will track the global VRAMP signal. The outnut oil. second inverter 1304 goes low on the selected segment, thus allowing the selected word line to go high.

The active time for the cycle is superimposed an An4-1 and its complemen't- such that both are low between cycles. Then '-irs' inverter 1302 at the end of the cycle, the input, to the L-- _ will go high., as will the output the second inverter 1304.

_ L.

Tran.sist-or 2.306 w-J-1-1 then mull dow-L. -1the selected word line and 4 2 hold it and all otIller word lines to ground. To reach a wcl-d lilne voltage of 7 V, VIRIA-MP need no.;-. go higner than 7 V, but- t-haddress innu.'-s and the outpult of the first inverter must reach one threshold higher, -which means close to 9 volt. This tvme of decoder 1300 would therefore be used in connection wIth a large ratio between the cell capacitance and the load caiDaci"L--ance (gate capacitance of tthe Dass transistor), so that the operating voltage could be reduced.

Fig. 13B shows a decoder 1310 with a boosting feature which allows most of the circuits t-c oDeraCe at- normal Vdd levels. A WLENABLE and a complement W=.SET is applied globally or from a segment select circuit. in the enable mode, LIN on the decoded circuit is mulled low, setting the previous reset latch. When the LIN signal is low and the LOUT signal is high, nodes DN2 and DN3 are elevated to a level that is one threshold voltage below Vdd (e.g., 3.5 volt). The timing diagrams in Fig. 13B show the levels of the different nodes. The RAMP signal starts out at a low voltage level of approximately 1.2 V, and WL is brought to that level by fully turning on MNWL. Late in the cycle, RAMP moves from 1.2 V to 8 V, in this particular case. The capacitor MNC is much larger 1-1rian the capacitance of node DN2, so DN2 will track the rise of the RRAMP and the word line. DN2 will end up higher than the RAVIP by one threshold voltage, so the ward line will go as high as the RAMP signal (e.g., 8 volt). DN2.. at 9. 6 V might expose the gate oxide of MN3.to the break down limit. Thus, 1,W2 acts as a barr-.'-e-- in that its gate is at 5 V, as is the gate of MN1.

3v re-turning the RAiri-z, i.2 volt before reset"."--ing the ward line, the protection of the devices is maintained.

The voltage of a stored one with this conditions would be approximately 6. 4 V, provided the amplifier supply voltage is also at 6.4 V. The maximum stress an gate oxides in the cell is 6.4 volt plus Dvc.

When controlling logic, the high voltage on the cell zero at a level of is cl' most ccnce-t--7i, even when an si L about 1 V may be acceptable. Another alternative is, therefore, to implement a decoder using P-channel devices only.

Fig. 13C shows decoder 1320 is the equivalent of Fig. 13B, but with the polarities reversed - The common node f or the sense transistors and cell capacitors in the cells are connected to Ithe 6.5 V supply indicated in the -Eigure. The low RAy-p level is -1.5 V in relation to 6.5 V or the 5 V Vdd 3 supply. To approach the Vss level in the controlled circuits, it is desirable f or the RAMP to go to -1. 5 V, thus overcoming the high threshold voltage due to the body ef."L"ect of the P-channel write transistor in the cell. The negative swing on the RJAMP signal could be limited to 0.5 volt be-low Vss. The refreshed high voltacre on the controlling capacitor will be at 6. 5 V, but in the read phase of the refresh operation the voltage will drop slightly. For cells with large capacitors that are used for controlling pass transistors, this voltage drop is very limited due to the long time constant in the combination of the write transistor and the cell camacitor. In other words, the write bit line will reach the 6.5 V level before the cell camacitor has been disturbed more than a small fraction of 1 V. The refresh phase with the RAMP and word line at its negative extreme is made long enough to fully refresh both a high and a low cell level. The original storing of control data may require. extra long write times or multiple write cycles for very large storage camacittars. Al" cells can also be precharged to an intermediate level by turning on all word lines, with the bi-'%-. lines clammed to '%-he intermediate level. The writing will then only need to displace the cell valtage slightly to indicate the stared data. The refresh operations will later gradually chaz-ge the capacitors to their full values.

-I- Switched Power Anmlifier urther reduce the Dower consumn4l"ion in In order to I %_ 4_ '- the call current or "he control memory, it is desirable to let the dummy current displace the read bit line as much as f ier 4 possible before the amplil__;..s powered up. Fig. 13D shows a 33 me'"nory 1330 where each pair ot' segments 1332 contains only one iated timina diagr ms are shown common clazaz circuiL. The assoc. a in Fig. 13"z'. Clamming to an intermediate clamp level is done to the ammi-43O.-Jer and fL'Czth_er tirried so Ithat at without.,mower t 4 4 !east the two segnents in each Dair are couppled the clamping. L. I- All four bit lines will be floating close to the clamp level at the beginning c-10 IC-ne memory cycle. Applying Ithe low ramp level t to the word line starts the displacement of the read bit 'line in the selected segment.

When the selected bit line has been displaced sufficiently for good onera.t--ing margins, 'the power is applied to the selected sec is conoiled by an early timing signal, EPERB, men This - C-r which is negative ttrue. When Ithe Inverting amplifier in the selected segment has displaced its write bit line a certain in 1 amount, power is applied to the non selected segment. khe pair (controlled by LPWR) and the two segments 1332 in tthe mair ter are coupled together to form a full amplifier. Aft increasing the ramp voltage and holding it at its high level for a time, the cell is re'lc-res,'.,ied and the cycle is terminated by turning off Dower, clamming, and coupling all segments t k_ogether. In the read and write modes, indicated as P-EFRB, all. segments are coupled together at the early coupling time (ECPLTM) As described in connection with a regular memory, a very large signal is applied to the bottom segment of a selected column which dominates over the signal detected at the selected segment.

Mixed Cell TY1:)es-on Common _B4t Lines Typically large cell capacitops; are required to control the gate level on mass transistors. At- the same time, t L.he bit line camacitances can be kept low by ultilizing the sec 71 a Mented bit line approach. The ratio of the cell capacita -- and the bit line canacitance will in such cases be high enough to impose a large bit line displacement at reading a conventional DRAM cell. In other circuits controlled by the control memory, such as look up tables, the cell capacitor can be very small and the preferred cell is of the new DR-M type.

It is moss-1-ble to have both ty-jes of cells on common bit line pairs, as indicated in memory 1340 shown in Frig. I3F. F-ere, an approach with non-dedicated bit lines has been used, which means thalt: a given bit line can be used as a read bit line or a write bit line depending on ii-F the address is odd or even. In this type of arrangement, the bit- line capaci-tances remain ecrual. The dummy current is applied to the bit line that is active for reading a new -1k--e of cell and is applied to the bit line to which the selected convent-lional DRAM cell is connected.

The du=y charge at reading a conventional DRAM cell is the product off the dummy current, and the dummy current ontine, which operates with the same margin as for the new DRAM cell of the present invention. The bit lines are clamped to an - the st -he cycle, intermediate level (e.g., 3.5 V) all k-art of t which is higher than 4L--.'Lr-le first RAMP level of 1.2 V. A fully charged conventional cell capacitor (e.g., 5.6 V) will also be well above the word line voltage off 1.2 volt. The cell transistor is off and the dummy current increases t-he bit line voltage at the same rate as at reading a new type of cell If, on the other hand, the cell capacitor is discharged to a low level (e. g., 0 V), charge is drawn from the bit line, reducing the bit line voltage more than the dummy current is able to compensate be-fore the amplifier dominates the displacement- of the bit lines. With a normal RAY- P signal, the word line voltage -Js increased later in the cycle bringing t_he cell capacitor to its refreshed level, also for a stored one. In the ward line, addressing is sequential without regard to what type of cell is used. In Fig. 13FE, WLAO and WLA1 indicate even and odd word lines addressing conventional cells, and WLBO and WLB1 indicate even and odd word lines addressing the new type of cells. The dummy vol-li-ages DLIM10 and DUM1 are active negative and turn an the dummy current on BL2 and BLI respectively. Note thajL- to Wr-i.'%-- -- a one (high voltage 6n the capacitor) an an even cell of the new -,,.-. y:-,e, BL1 must be forced high by the write circuit, while on the cither hand BL2 must be forced high to write a one on an even cell of in a conventional DRM. The program. mer must therefore take t-his into account. when preparing the control data. Only if cells of the same type are used fcr a given range of addresses an alternative approach can be taken. in ithat- case, -,-,sing the figure as a basis for the djscussion, even addresses would apply --c conventional cells placed on BLI and DUM-1 would- be activated C -vme oLE cells. Th- - -4 s J s would for all even addresses ca-'. ling k_ 46 however pplace unnecessary restrictions on the cell distribution.

The timing for refreshing a stored zero and a s'l--c--ed one in a conventional cell is shown in Frig. 13G. Note for the stored zero that the exchange of charge continues only untill the cell capacitor has been charged to one threshold voltage below WLAO. This also points out the need for frequen't. refreshing as a cell charged by leakage current to close to one threshold below 'h-he initial word line volt-age will cause a read error. In reality, the large cell capacitors used in this configuration at ithe refresh f -requency dictated by the new 1L.YZe of DRACM cells will be charged very little between cycles. The COUPL signal and the disturbance an the early bit line signals have not been shown in this f igure as this is of interest only is in the initial write mode and in 't-he read mode used for checking that the written data was correctly stored (mainly in production tests).

Disablina Secr-ments Above Selected Seaments In both read and write operations, the segments above t L-he selected segment need not be activated. This is done by forwarding the segment select signal to the segment above, as depicted in Fig. 14A. In each segment an OR is formed by the segment select signal and the selected. signal from the segment below this or signal is then forwarded to the segment above, where it is treated as the select signal from the segment below.

One disadvantage with this approach is the serial delay time to the ' last segments in the chain. it is desirable to be able to interrupt the clamming signals in all segrents, before they occur. A parallel approach as indicated in Fig.

14B addresses this concern. In this case each select signal is forwarded to all segments above and each segment has an OR gate as wide as the number of segments that are located below.

If mower consumption is not a concern, only the segment directly above the selected are will need to be disconnected from the segment below as lindic-ated in Fig. 14C.

Here the coupling signal is disabled for SETn-l.

47 DR2LM cells w-Lth separate read and wri te ward lines and clanred amolijOier The DRAUM cell shown in Fig.!5 recraires a larger chin area and more complex word line drivers, but offers advantages in two areas. The cell has the same advantages as the simpler cell described above in that the content of the cell is not disturbed during the refresh cycle. The fact thalt: the word line voltage at reading has the full amplitude means that the read time is sho--r----er than when Ithe word line is at an intermediate level. There is no feedback from the write transistor as the write word line is low during reading. If the refresh frequency is high enough, a stored ZERO will stay very close to Vss and a stored ONEE will stay one threshold under WLW. Boosting the voltage of WLW can maintain the cell voltage of a stored ONE close to Vdd. This property makes the cell useful for control of logic, where the control node indicated in the figure connects to the logic to be controlled.

The amplifier can have all the forms as discussed before and can also be used in the segmented configuration.

Bit lines need not be dedicated as indicated in the figure, but will in the'non-dediccated case require dummy transistors on both.bi-t- lines under control of the address logic. 'The assumption is that the layout is rore efficient with every other cell reversed around a vertical axle.

The amplifier in a different mode of operation can act as a latch, which is first reset, indicating a ZERO, and at reading a ONE is set. This reauires that the cell with full -age is strong enough, to set the amulifie"-- flip- flcz.

cell volil. The segmented memor-1 approach can still be 'Caken. 30 Full Amnlifier DRAM -Conf iwarat ions Prj In situations where f ast access is af -Mimportance, Ithe single inverting a=plifier in each segment may be replaced with a full latch anplifier in each segment. Thlis allcws for s-4-IiD!er con'k---.-ol with fewer control signals. The relative timing is howeve- slight-ly more cri. "cal.

The IDRAv-- w-lth a full a=lifier can ocera.'1-e 4n basically two -k-,iodas. in Mode 1, shown in Fig. 16A, power is 48 - lines are clarme,; always az-olied to the ammlifier, and the biL_ to the same Dotential, which is It1ne swit-ching point- c;f t-he latch. In the Mode 2, shown in Figs. 16B and 16C, Dower to 4t-he amplifier is turned off during the clamping and the first portion of the read cycle. in Fig. 16B, the amplifier is OFF in standby mode with the bit lines clamped to a reference clamn level. In Fig. 16C, on the other hand, power is ON in standby leaving one bit line at' Vdd and the other at Vss level. The single clamp transistor is turned an at about the same 1--Ime as Dower is turned off. If power is turned off before applying t If L-he clamp signal the bit lines will reach a voltage o: approximately Vdd/2 due to charge sharing. if power is still on, the bit lines will eventually reach the switching point level of the amplifier latch. By designing the amplifier for a switching point level of Vdd/2, the relative timing at this time is not critical. Power is turned on again, when the inputt signal has been integrated to a safe level, to guarantee that the amplification will go in the right direction.

The bit lines as shown in Figs. 16A-C are dedicated to reading and writing, which means that all cells in a segment are oriented the same way, with the write transistors connected to the write bit, line (BLW) and all read transistor connected to the read bit line (BLRI). To allow more options for cell 1-ayout-, it may be ad-,,rant tageous to have non-dedicated bit lines as illustrated in Fig. 16D. There is a minor added cost in each a=Dlifier in having two dummy transistor and controls to select the one corresponding to the address of the selected cell.

* Figs. 17A-M show Ithe result of simulations using a 0-5U MMOS Drocess. The memory module consists of 8 segments per column, with 64 bits/segment, and 128 columns (65,536 bits).

Fig. 17A illustrates reading a ONE in a cell located n the top segment, with the -read data propagating f rom BLR and BLW in the top segment to BLRO and BLWO in the bot-tom segment. The data on BLRO and BLWO is forwarded to the 1/0 decoder at about S ns (not shown). Power in t1his case is initiaLly turned off at the same time as clamping t-akes place (compare to Fig.

9 MC) and is turned on again Men reading starts by bringing the ward line (WL) to the first ramp level (1. 8 V). The signal in the selected segment (the top segment in this case f or worst case test) is amplified slightly before the COPL signal connects the selected segment to the rest of the segments that were interconnected earlier by the signal COPW. in this simulation the non- selected segments were clamped a little longer by the signal COPW, which is 0.5 ns longer than COPL, the signal clamping the selected segment. The stored energy in the bit lines of the selected segment is now transferred to the lower segments at the same time as each of the segments contributing to thle amplification of the transmitted signal. At about 6 ns, the delayed signal has reached the bit lines BLRO and BLWO of the bottom segment and is reaching half of full amplitude at a delay of less Man 7.5 ns. All bit lines are very close to the supply rails at the nominal end of the cycle (10 ns) - The voltage difference between BWO and BWO at 8 ns is more than 2. 5 V, which is sufficient to supply an output signal via decoder and output amplifier within 2 ns.

The initial cell voltage was assumed to have degenerated due to leakage after the last refresh cycle to 2.5 V, but is refreshed in the sham read cycle to 3.5 V. The cell capacitance in the simulation is 2e-15 Farad plus Me gate capacitance of the sense transistor (M in Figures 1-3). There is a small coupling f ram the word line, which can be noticed in the figure, so the final cell voltage Men WL reaches Vdd is slightly below 3.5 V. The maximum voltage is determined by the c max value of = less Me threshold voltage. The short channel process has a strong bay effect an Me threshold. The cell current in the read phase increases very slowly with the'cell voltage, when above 2.5 V, so boosting the WL voltage Move Vdd would have a small effect on speed, but would of dourse allow for more leakage in the cell capacitor.

Fig. 17B shows the reading of a stored ZEIRO degenerated due to leakage from 0 V to 1 V. Only a limited number of control signals are shown in this f igure. it is a clear indication in this figure that the switching paint of the amplifier is below the clamp level defined by the charge so sharing between lines. This causes ',-he bit lines to dri-fit- in, the negative direction, be-fore the current C from the dummy transistor less the low cell current causes the read bit line (BLR) to go positive. in the full am=lifier th.is 5 drift is acceptable as long as the device parameters in the ampli.ll'ie-- are consistent.

In the write operation (Fig. 17C) the data to be written is applied via the column decoder to BLWO and/cr BLRO an ',--.he bottom segment. This signal is large enough to be io amplified and propagate to the selected segment, which has started a normal read sequence, and override this signal. Fig. 17C shows how a stored ZERO is written over by a ONE. BLRO and BUY70 are separated by the input signal already during the clamming opera'tion. With all non- selected segments -interconnected, the signal is quickly propagated to the selected segment, causing the direction of B= and BLW to reverse, so that BLW will drive the cell voltage to 3.5 V when TL goes high. Fig. 17D illustrates how a stored ONE is w-riLk-en over by a ZERO.

Turning off power during clamping saves mower, as shown in Figs. 17E-N, but adds to circuit complexity.

Figs. 17E-G all have a f irst ramp level of 1. 8 V, while the following simulation used a first ramp level of 1.5 V. The circuit for the dummy current control adjusts the dummy current to an optimal value for a given first ramp level. The current difference between the cell current and the dummy current varies very little depending on the ramp level, bu44 Lhere is less dependence on device parameter varla-'k-.ions at Lhe!owe, first ramp level value.

Comparing the initial clamp level of Fig. 17E with the Drevicus simulations shows that the clamm level has drommed. This is caused by a change of the cell parameters equalizing the sizes of the read and write transistors and their junction areas. The higher junction capacitance at 0 V, commared to 5 V, brings the clampping level below 2.5 V. The switching paint should also be set equal to the clamp level. The clamp Dulses CL.NP and CL.MPN in Fig. 17E terminated before the word line had reached the first ramp level. This could M cause the dummy current, if it had bulilt up earlier to start the displacement of the read bit line prematurely The margins otherwise are sufficient for correct reading of a ONE, as the figure shows. To eliminate the possibility of-We problem discussed nave, the length of the clamp pulses in the following simulations were increased. Fig. 17F also displays the dummy voltage, that is applied to the gate of We P-channel dummy transistor. The dummy voltage is also close to its wxi negative value at the end of ths clamp signals. A OFE is read in Fig. 17F and a ZERO is read in Fig. 17G. Figs. 17,21 and 171 show normal read restore cycles for ZERO and ONE respectively.

It should be pointed out that in all cases a refresh.

cycle is the same as a read cycle except that all segments operate si=ltaneously fully disconnects? from each other. Th, signals COPL and COPM are therefore inactive in the refresh cycles. All segments are enabled and the low order address bits addresses "the same" word line in each segment. With the timing for the clamping operation used in Figures 17E-Q, CLMP mnd C"N have the same duration and is in reality the same pulse. Figs. 17a and 17X illustrate refresh cycles with the segments disconnected restoring ZEMs and ONEs. Comparing Figs. 17H and 17J shows how We bit lines move faster without We added load of the additional segiments. This indicates that the refresh cycles can be made shorter than a read or write cycle. Figs. 17L and 17M show the write cycles for storing ZERO and ONE.

Memorv Refresh intarr=tion without Delav One reasons why S"s are tMically preferred over conventional s is that synchronous systems require "at a memory 7equest is served without the delays that a DM refresh cycle would cause. A great advaniage to the D" of "a pzasent invention is that an ongoing refresh cycle can be 33 interrupted at any time during the cycle without destroying the stored data. Data stozed in the call capacitor remains intact mast of the time or is refreshed. during the end of the cycle.

1z ongoing refresh cycle can he stcyptd as long as the word 52 line is brought low as the f irst step. Figs. 18A-B show the simulations of interrupting refresh cycles after 6 ns and starting read cycles an a different address, while Figs. ISC-D show an interrupting write cycle.

In these simulations the CW2 signal stans I ns later Wan in the previous simulations, but ends at the same time. The snorter pulse is sufficient for the clamping of the bit lines and the delay makes sure "at the bit line voltages have not changed before the word line active during We refresh has been brought down. it is assumed that the ref resh and the reading or writing is done in We top segment, with the bit lines BW and BW. The word line addressed during the refresh is WM and the word line addressed during read or write is WLB. Data input and output connects to the bit lines of the bottom segment BWO and BWO. Me interrupting memory cycle starts with signal 1NT, which in the simulation was used to force the WLA low, while the decoder was selecting WLB. In Fig. 18A the cell addressed by WM (=") is in the ZERO state, sta"ing at 0. 5 V and during the read phase of the refresh cycle is lifted to 0. 6 V and returned to 0. 5 V when WM is turned of f (capacitive coupling between WIA and the cell capacitor). The cell to be read is at 2. 5 V and is brought to 3.5 V at the end of the interrupting memory cycle. In Fig. 18B the cell to be refreshed (CELM) is at 2.5 V and the cell to be read in the interrupting cycle (CEMB) is at 0.3 V.. The reading returns CELM to 0 In Figs. 1SC-D the refresh cycles are interrupted by write cycles. In Fig. 18C the cell to be refreshed (CE") is at 2.5 V and remains at the same level after interrupting the refresh before WLA has been brought to 5 V. CELLB starts at its previous value of 0.5 V and at the end of the write cycle is at 3.5 V. In Fig. 18D CE" remains at the 0.5 V it was at the start' of the refresh cycle, while the voltage of CEMB is changed from its previously stored value of 3.5 V to 0 V. in the write operation a signal COPLIN occurring at the same time as the shmal COPIN is applying the input data to the bottom segments bit lines BWO and BWO. As can be seen these bit lines proceed in time the bit lines BTR and BW in the top 53 segment, contrary to the s-i-tuat-ion in!SA-B, where BLR and BL.W come first.

Figs. 1SA-D illustrate how a memory cycle can interrupt a refresh cycle without destroying the stored data for an arbitrarily chosen time in the refresh cycle. in the example a previously degenerated cell voltage was chosen (some time after last refresh). An incomplete refresh due to an interrupting memory access will cause further degeneration ---ashc,,rcle is perfor-Lned. The until new unin-'%--ar--uc'-ed ref.1 address of. the calls of the interrupted refresh would be retained during the memory access (accesses) and would be the first address used when the refresh cycle is resumed. With the very low refresh frequency compared to the high memory access rate very large blocks of data with very short interruptions would have to be transferred before the refresh integrity would be in clanger. As a backup for all eventualities a long delay circuit could beused to interrupt the flow occasionally.

Related to the idea of interrupting an ongoing refresh cycle at any time without destroying the stored. data is the concept of performing a fast burst read. A fast burst read operattion involves reading data from 1Che memory cell without completing a refresh cycle following the read operation. In the DRAM of the present invention, this is possible since the data stored in a memory cell is not destroyed when the contents of the cell are read, eliminating the need to refresh the contents of the cell. By reading data from a memory cell without, a subsequent refresh cycle, the amount of time needed to perfo rm a read operalCion is t3-p-ically halved. Thus, 1.2 e possible frequency of read cycles is doubled, improving the 30 efficiency of memo ry operaltion. Of course, it should be unders'L-ood that a standard DRAM refresh cycle must s_411 be f - burst read operat o=ed. Tile fast perl 1-ion essentially turns 'he custo-mary read/refresh operation into a strict read oper-ation, -at J Formed without an associat allowing a read ope, -on to be perf 1-ed rejEresh operation.

DRAM- Clus-i-er Cell 54 In another embodiment-, the DRJAIM of the zresen-;,-invention may include more than cne storage ca-paccitor associated wit-J'a a single -oa-4-- of read and write transistors. Fig. 19A shows a simp.11--iffied circuit diagram 1900 of a "cluster cell" using four storage nodes C1-C4. instead of having one storage node at the common (COM) node, any of the four node capacitors CI-C4 can be connected to COM during a read or write oiDeration. The COM node can be looked upon as a very short: bilt. line in a conventional DRAM and all the techniques for layout and processing can be applied to the cells on the COM "bit line. 11 The number of cells that can be placed in the cluster depends on the relation between the memory cell capacitance and "he capacitance of the COM node. The diagram in Fig. 19A shows four memory cells in the cluster, merely by way of example.

The COM node capacitance includes the junction capacitance of t istor 1902, 4-he COM bit line, the source junct%-Jon o-LE write trans _he drain junction on CLMPCOM transistor 1904 and the ga-'Ce of sense transistor 1906. The COM bit line may have relatively high resistance, so minimum active junctions can be used.

in operation, the primary DRAM cell, which normally reads and restores the charge st-ored in a capacitor connected to the COM node, has been modified so that any of the cell ca,oacitors Cl-C4 on the COM bit line can be connected to COM before the reading and restoring of the.,charge on the selected cell. Due to charge sharing between a cell capacitor and the CO1.1f node, there is a slight modification of the cell voltage after the connection. The actual vol-'k-age on the COM node depends on whether a ONZE or a ZERO was read in the previous cycle. in order to make the effec"L- of the charge sharing more predictable, the COM node is clamped to a fixed level between cycles. Once the cell is connected to COM, a normal cycle is then executed. Fig. 19A also shows a port "ion of a word line decoder 1910 coupled to master word line WL and four slave word lines WLCI, WLC2, WLC3 and WL%--A-. A number oJff global signals are also shown that define active time ffor the different, horizontal lines. An active subcell is selected by a decoder (not- shown) and applied at a szecii-fied time on CITIMEB, C2TIMEB, C3T1Y2B cr C4TIMEE.B. An amplifier 1920 is also shown in Fig. 19A, and its performance is similar to that described above.

Flig. 19B shows the timing relationship between the different signals. For example, ithe reading and restoring oLE a ZERO and of a ONE is shown. The charge sharing effect between the cell capacitor and the COM node, when the COM node capacitance when the capacittances are equal is also i'Llustra.'-.ed.

With the COM node clammed at- 2 V between cycles, the displacement on the stored value while reading is the same, but in opposite directions. The cell current to BLR is normally limited by the low WL voltage an read %transistor 1908 and therefore increases less than linearly with the cell voltage.

The cost of adding a separate write word line 1920 is minimal to address this limitation, as shown in an alternate cluster cell configuration 195o in Fig. 19C. The high WLR voltage (5 V) renders the cell current quadratically dependent of the active voltage on sense transistor 1906 (the COM node). The much higher read current on BLR makes for an even faster read operation and higher margins. The timing diagrams for the circuit of Fig. 19C is shown in Fig. 19D_ If . a cluster cell is read bef ore a ref resh cycle, the cell voltage will have been modified by charge sharing with the COM node, as described above. A second reading may still be correct- if the COM node capacitance ils very small compared to 'he cell camacitor. The modification is however progressive from cycle to cycle, so a burst read could only be perm-Itted once or twice before the cell is refreshed. The same restriction applies to interrupted refresh cycles for readIng tne same or addresses and writing to other addresses.

Note th,at the two tier con---iguraJ&---ion described earlier is still valid in'the cluste=--- cell as long as the second tier design harge sharing effect akes into account the c, -I - 1 restrictive. Hany variations of the inventicm will saccma appareAt to those of skill in the a" upon review of this disclosure. The scope of the invention should, therefore, be determined not wi" reference to the above descrip0on, but instead should be determined with reference to the appended clans along with their full scope of equivalents.

1-57

Claims (5)

CLAIMS:

1. A dynamic random access memory comprising:

a storage capacitor for storing charge representative of a stored value; a first, write transistor coupled to a first plate of said storage capacitor and a first bit line; a second, read transistor having a first terminal coupled to a first terminal of a third transistor and a second terminal coupled to a second bit line, said third transistor comprising a gate coupled to said first plate of said storage capacitor, a gate of both said read transistor and said write transistor coupled is to a word 1 ine; a fourth transistor coupled to said first bit line and a clamp line, said clamp line having a clamp level intermediate to ground and a switching threshold of said write transistor; and a sense amplifier coupled to said first and second bit lines; wherein a refresh cycle of the dynamic random access memory may be interrupted with a memory read cycle without destroying data stored in the dynamic random access memory, and wherein a refresh cycle of the dynamic random access memory may be interrupted with a memory write cycle without destroying data stored in non-addressed columns of the dynamic random access memory.

2. The dynamic random access memory of claim 1 wherein a fast burst read cycle is performed without a subsequent associated memory refresh operation.

3. A dynamic random access memory as claimed in claim 1, wherein, during a refresh cycle said stored value remains unchanged.

4. A dynamic random access memory as claimed in claim 1, wherein a refresh cycle commences when the dynamic random access memory is not executing a memory read cycle or a memory write cycle.

5. A dynamic random access memory comprising:

a plurality of memory cells at the intersections of word lines and bit lines, each memory cell comprising:

a storage capacitor for storing charge representative of a stored value; a write transistor coupled to a first plate of said storage capacitor and a first bit line; a sense transistor having a gate coupled to said write transistor and said first plate of said storage capacitor; a read transistor having a first terminal is coupled to said sense transistor and a second terminal coupled to a second bit line; a f irst word line coupled to a gate of said write transistor; and a second word line coupled to a gate of said read transistor; and a sense amplifier coupled to said first and second bit lines.