GB2319890A

GB2319890A - Field effect transistors

Info

Publication number: GB2319890A
Application number: GB9725023A
Authority: GB
Inventors: Migaku Kobayashi
Original assignee: NEC Corp
Current assignee: NEC Corp
Priority date: 1996-11-26
Filing date: 1997-11-26
Publication date: 1998-06-03
Anticipated expiration: 2017-11-26
Also published as: GB2319890B; TW351838B; JP3123937B2; CN1185661A; JPH10163480A; GB9725023D0; KR100305625B1; KR19980042797A

Abstract

The transistor comprises a semiconductor substrate 1 of first conductivity type, an element isolation region 2 on the semiconductor substrate, an impurity diffusion layer 6 of second conductivity type, and a CVD silicon oxide insulating film 8 over the element isolation region and the impurity diffusion layer. A thermal silicon oxide insulating film 7 is formed between the impurity diffusion layer 6 and the CVD silicon oxide insulating film 8 to prevent current leakage between the CVD silicon oxide insulating film and the impurity diffusion layer. The transistor may be connected to a capacitor to form a DRAM cell.

Description

SEMICONDUCTOR DEVICE HAVING A REDUCED LEAKAGE CURRENT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME BACKGROUND OF THE INVENTION This invention relates to a semiconductor device and a method of manufacturing thereof, particularly to a serniconductor device which allows reduction of a leakage current at the PN junction of an MOS transistor, and the manufacture thereof.

With the development of highly integrated semiconductor devices, the demand for finer circuit pacterning enabling higher integration continues to be more intense. Furcher, as circuit patterning becomes rapidly finer, to maintain or improve further the functions of semiconductor elements or element isolation regions between those elements, the impurity diffusion layers constituting the source and drain regions of an MOS transistor have shallower junctions, and the lateral spread of the impurity diffusion layers on a semiconductor substrate is reduced in si2e.

The generally applied method to producing impurity diffusion layers of a semiconductor integrated circuit composed of MOS transistors consists of ion-implantation of an impurity opposite in electric conductivity to a semiconductor substrate with a thick field oxide layer and'gate electrodes used as a mask by the self-aligning method, and of activating the impurity ions by performing thermal treatment. An insulating film composed of a material such as BPGS (a silicon oxide film containing boron glass and phosphor glass) is formed on the whole surface of the semiconductor substrate after forming the impurity diffusion layer, a further thermal treatment may be applied to planerize the surface thereof. Through these thermal treatments, impurities to form the impurity diffusion layer diffuse into the substrate by thermal agitation, and the PN junction spreads from the surface of the semiconductor substrate into deeper layers and wider areas.

Accordingly, the periphery of the PN junction at the surface of the semiconductor substrate penetrates far beneath the field oxide film which has acted as a mask during ion-implantation of the impurities.

Figs. 8A-D illustrates cross-sectional views of respective steps of a method of manufacturing a conventional MOS transistor.

As shown in Fig. 8A, a field oxide film is formed on the surface of a silicon substrate 101 of, for example, p-type having an impurity concentration of 1 xlO6 atoms/cm3. A gate oxide film 103 is formed on the surface of this silicon substrate 101. Next, a gate electrode 104 is formed at a specified region on the gate oxide film 103. A low concentrated impurity diffusion layer 105 is formed using the field oxide film 102 and gate electrode 104 in a self-aligned manner. The low concentrated impurity diffusion layer 105 usually includes, for example, phosphor impurities. A silicon oxide film is formed by chemical vapor deposition (CVD) method and is anisotropically dry etched (etch-back) so that side-wall insulating films 106 are formed on the side walls of the gate electrode 104, as shown in Fig. 8C. In this etch-back process, the surface of the field oxide film 102 is also slightly etched away.

Highly concentrated impurities such as arsenic are ion-implanted, followed by a thermal treatment, to produce a source-drain diffusion layer 107 with a structure of lightly doped drain (LDD). A portion of interface of the source/drain diffusion layer 107 and the silicon substrate 101 is located beneath the field oxide film 102 at the periphery of the field oxide film 102.

The concentration of this highly concentrated impurities may be set at 1 x10L atoms/cm3. Depending on given circumstances, the source/drain diffusion layer 107 can have a lower concentration of impurities. In this case, the concentration may be set at 1 x 10ia atoms/cm3. This method is disclosed in Japanese Laid-Open Patent Application No. SHO 61-156862.

As shown in Fig. 8D, a protective insulating film 108 is formed by CvD method to cover the gate electrode 104 and side-wall insulating films 106 as well as the field oxide film 102 aDd source/drain diffusion layers 107. Next, an interlayer insulating film 109 is formed. This interlayer insulating film 109 is a stack film composed of BPSG layered by CVD method, and its surface is planerized by thermal treatment. Contact holes are formed at specified spots on the protective insulating film 108 and interlayer insulating film 109 contact holes, through which source/drain electrodes 110 are formed and connected with the source/drain diffusion layers 107.

Through these aforementioned processes, an MOS transistor is formed which has a gate oxide film 103, a gate electrode 104 and source/drain diffusion layers 107 placed on a silicon substrate 101. Noteworthy, is that the periphery 107a of the source/drain diffusion layer 107 is located beneath the periphery of the field oxide film 102 so that the two regions, 107 and 102, overlap.

However, as the semiconductor device becomes more highly integrated, semiconductor elements such as transistors become more finely fabricated. As a result, the PN junction becomes shallower and element isolation regions or inter-spaces between adjacent elements become narrower.

Further, since the MOS transistor becomes reduced in size, its reverse diode characteristic of the PN junction becomes worse.

In fact, it has been discovered by the inventor that a leakage current at the PN junction develops when a reverse bias is applied.

This problem will be further explained with reference to Figs.

9A and 9B. Figs. 9A and 93 show a cross-section of the PN junction of an MOS transistor fabricated by a conventional technique. Fig.

9A represents a conventional transistor where a source/drain diffusion layer 107 has a high concentration of impurities, while Fig. 9B represents another conventional example where a source/drain diffusion layer 107 has a lower concentration of impurities. The same numerals in Fig. 9 as used in Figs. 8A-D, represent the same elements.

Referring to Figss 9A, a field oxide film 102 is formed on a p-type silicon substrate 101. An n-type source/drain layer 107 is formed in the p-type silicon substrate 101,and a protective insulating film 108 is formed on the whole surface of the silicon substrate lol. Furthermore, on this protective insulating film 108 is formed an interlayer insulating film 109, and a source/drain electrode 110 is connected through a contact hole to the source/drain diffusion layer 107.

When etch-back of the silicon oxide film takes place in advance or behind the time initially set, or treatment with a hydrofluoric acid takes a longer time than initially set, the field oxide film 102 has its surface etched away so that the periphery 107a of the diffusion layer is not covered by the field oxide film 102, so that it gets exposed. This exposure of the periphery 107a of the diffusion layer 107 becomes more manifest as the diffusion layer 107 has a shallower junction. Accordingly, the margin or edge 111 of the field oxide film 102 becomes lower than the periphery 107a of the diffusion layer. Thus, the periphery 107a of the diffusion layer is directly covered with, and in contact with, protective insulating film 108.

When an inversion or a reverse bias is applied between the source/drain diffusion layer 107 and silicon substrate 101 with such structure, a first depletion layer 112 is produced in the silicon substrate 101 such that the first depletion layer 112 extends from the boundary of the silicon substrate 101 and the source/drain diffusion layer 107 toward the silicon substrate 101.

In this case, since the source/drain diffusion layer 107 has a high concentration of impurities, scarcely any corresponding depletion layer is produced in the source/drain diffusion layer 107 and the protective insulating film 108 is formed directly on the surface of the depletion layer 112. Therefore, a boundary potential is generated at the boundary between the protective insulating film 108 and first depletion layer 112. This boundary potential causes a leakage current based on or through the boundary.

In an alternative example, as shown in Fig. 9B, a field oxide film 102 is formed cm a silicon substrate 101. A source/drain diffusion layer 107 having a low concentration of impurities is formed, and a protective insulating film 108 is formed on the whole surface of the semiconductor substrate 101. In addition, an interlayer insulating film 109 is overlaid upon the protective insulating film 108, and a source/drain electrode 110 is connected through a contact hole to the source/drain diffusion layer 107.

In this case, the periphery 107a of the diffusion layer is positioned beneath, and lower than the edge 111 of the field oxide film 107. Although, the periphery 107a of the diffusion layer may be positioned above and higher than the edge 111 of the field oxide film 102.

The mventz have discovered that in a semiconductor with this structure having a lower concentration source/drain diffusion layer 107, when a reverse bias is applied between the source/drain diffusion layer 107 and silicon substrate 101, a first depletion layer 112 is produced in the silicon substrate 101 and the source/drain diffusionSlayer 107 such that the first depletion layer 112 extends from the boundary of the silicon substrate 101 and the source/drain diffusion layer 107 toward the silicon substrate 101. As the source/drain layer 107 has a low concentration of impurities, a second depletion layer 113 is generated on the side of the source/drain layer 107, and it has its periphery 113a positioned above the edge 111 of field oxide film 102. Therefore, the protective insulation film 108 is formed directly upon the second depletion layer 113 and causes a leakage current generated as a result of the boundary potential.

Although an increment of such leakage current at the PN junction is very small, it can be nonetheless detected with a sensitive semiconductor device. Thus, the existence of such leakage current at the PN junction and its cause were discovered by the present inventors to exist in both high and lower concentration source/drain devices having shallow junctions.

SUMMARY OF THE INVENTION e object of at least the preferred todirnent of the present invention is to provide a semiconductor device preventing the increment of leakage current generated at the PN junction and a method of manufacturing thereof.

Another such object is to provide improved semiconductor device which is able to produce a transistor having the diffusion layer which has a shallower junction which spreads less laterally and a method of manufacturing thereof.

A further such object is to provide a semiconductor which allows the production of a smaller MOS transistor with a narrow element isolation region between adjacent semiconductor elements and a production method thereof.

An additional such object is to provide a highly reliable semiconductor device and a production method thereof.

Th one aspect the invention provides a semiconductor device comprising, a semiconductor substrate of a first conductivity type, an element isolation region on the semiconductor substrate, an impurity diffusion layer of a second conductivity type, the impurity diffusion layer being coupled to said element isolation region and formed on the semiconductor substrate, and a thermal silicon dioxide film on the impurity diffusion layer.

Lo arrt:r aspeot the 'iventior provm'des a method of rnanufflcrra a semiconductor device comprising the steps of: forming an element isolation region on a semiconductor substrate; forming an impurity diffusion layer on the semiconductor substrate, said impurity diffusion layer in close proximity to an edge of the element isolation region; forming a thermal silicon dioxide film on the impurity diffusion layer; and forming a CVD silicon insulation film on the thermal silicon dioxide film and the element isolation layer.

The thermal silicon insulation film, especially, a silicon dioxide film, is denser than the CVD silicon insulation film. In particular, a thermal silicon dioxide film has fewer dangling-bonds than a CVD silicon dioxide film at the silicon-silicon dioxide interface. Therefore, a thermal silicon dioxide film has a lower flow of current than the CVD silicon dioxide film. Accordingly, the structure can achieve the object of the present invention.

In another aspect the invention provides a semiconductor device comprising: a semiconductor substrate of a first conductivity type; an clement isolation region formed on said semiconductor substrate; an impurity diffusion layer of a second conductivity type formed on said semiconductor substrate adjacent to said element isolation region; a CVD insulating layer formed on said element isolation region; and means for separating said impurity diffusion layer from said CVD insulating layer and preventing current leakage between said layers.

In another aspect the invention provides a method of manufacturing a semiconductor device comprising the steps of: forming an element isolation region on a semiconductor substrate' forming an impurity diffusion layer on said semiconductor substrate adjacent to said element isolation region; forming a CVD insulating layer over said element isolation region and said impurity diffusion layer; and forming a separating layer between the CVD silicon insulating layer and the impurity diffusion layer to prevent current leakage between said layers.

In another aspect the invention provides a method of manufacturing a semiconductor device comprising the steps of: forming a field insulating film on a first portion of said semiconductor substrate; forming a first insulating film on a second portion of said semiconductor substrate; selectively forming a gate electrode film on a part of said first insulating film; selectively forming a second insulating film on a side surfaces of said gate electrode film; introducing impurities into said second portion by using said film insulating film and said gate electrode as a mask to produce an impurity diffusion layer on said second portion of said semiconductor substrate; forming a thermal silicon insulating film on said impurity diffusion layer, forming a CVD silicon insulating film on said thermal silicon oxide layer and said field insulating film; forming an interlaycr insulating film on said CVD silicon insulating film; forming a contact hole in said interlayer insulating film, said CVD silicon insulating film, and said thermal silicon insulating film to expose said impurity diffusion layer; burying a second conductive film to connect to said impurity diffusion layer.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, advantages and features of the present invention will be more apparent from the following description by way of exemple and taken in conjunction with the accompanying drawings, in which: Fig. 1 is a cross-section view illustracive of an MOS transistor according to a first embodiment of the present invent ion.

Figs. 2A-D are cross-sectional views showing respective steps of a method of manufacturing the MOS transistor according to the first embodiment of the present invention.

Fig. 3 is a flow-chart illustrating a partial production process of the MOS transistor according to the first embodiment of the present invention.

Fig. 4A is a cross-section view illustrative of the memory cell of a DRAM according to the first embodiment of the preset invention and Fig. 4B is a equivalent circuit of the memory cell shown Fig. 4A.

Fig. 5 is a graph showing the yield of DRAMs for illustrating an advantage of the present invention.

Fig. 6 is a cross-section view illustrative of the PN junction portion of the MOS transistor according to the first embodiment of the present invention.

Fig. 7 is a cross-section view illustrative of an MOS transistor according to a second embodiment of the present invention.

Figs. 8A-D are cross-sectional views showing respective steps in the manufacture of a conventional device, and Figs. 9A and 9B are enlarged views of p & rt cf the structure of figure ED.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in Fig. 1, field insulation (oxide) films 2 are formed on selective regions on the surface of a silicon substrate 1 of one conductivity type. An active region is surrounded by the field oxide film 2. A gate insulation (oxide) film 3 is formed on a part of the active region on che surface of the silicon substrate 1. A gate electrode 4 and side-wall insulating films 5 are formed on the gate oxide film 3.

Source/drain diffusion layer 6 with conductivity opposite to that of che substrate are formed on a part of the active region.

In this example, the source/drain diffusion layer 6 is so designed as to have a low concentration of impurities with a structure of lightly doped drain (LDD). The depth of the source/drain diffusion layer 6 is 0.1 ijm. Thermal oxidized protective films ? are formed on the surface of source/drain diffusion layers 6. A protective insulating film 8 is formed to cover the thermal oxidized protective film ", field oxide films 2 and gate electrode 4. An interlayer insulating film 9 is overlaid on the protective insulating film 8.

A contact hole 50 is formed through the thermal oxidized protective film 7, protective insulating film 8 and interlayer insulating film 9 to eXpose the sorce/drain diffusion layers 6.

Source/drain electrodes 10 are formed in contact holes SO and connect with the source/drain diffusion layers 6.

It should be noted here that this method can also apply to the production of an MOS transistor having no side-wall insulating films1 as well as to the MOS transistor with those films as described above.

As shown in Fig. 2A, a field oxide film 2 with a thickness of about 300nm is selectively formed on a p-type silicon substrate 1 with an impurity concentration of 1 or0'6 atoms/cm3. The field oxide film 2 is made by the method of a Local Oxidation of Silicon (LOCOS) and surrounds an active region. Then, a gate oxide film 3 is formed on the active region of the surface of this silicon substrate 1. The gate oxide film 3 is composed of silicon and has a thickness of about lOnm.

As shown in Fig. 2B, a gate electrode 4 is formed on a specified part of the gate oxide film 3. The gate electrode 4 is composed of a polycide film having a poly-silicon filrn and a refractory metal silicide such as a tungsten silicide film. A silicon oxide film ia formed on the whole surface of the silicon substrate 1 with the use of CVD or the like. Then, the silicon oxide film is etch-backed with using a conventional technique, and, as shown in Fig. 2C, side-wall insulating films 5 are formed on the side walls of the gate electrode 4. During this etch-back process, the field oxide film 2 has its surface slightly removed.

Source/drain layers 6 are formed so as to be self-aligned with the field oxide film 2 and the gate electrode 4. That is, impurities are implanted into the silicon substrate 1 using the field oxide film 2 and the gate electrode 4 as a mask. The impurity contained in the source/drain layer 6 includes phosphorous and has a concentration of about 1018 atome/cm.

As shown in Fig. 2D, on the surface of the source/drain diffusion layer 6 is formed a thermal oxidized protective film 7 through thermal oxidization. Then, in order to cover the gate electrode 4 and side-wall insulating films 5 as well as the field oxide film 2 and source/drain diffusion layers 6 all prepared on the silicon substrate 1, a protective insulating film 8 is formed with CVD method.

The process of producing the thermal oxidized protective Lilm 7 follows the steps depicted in Fig. 3. After the source/drain diffusion layers 6 having a low concentration of arsenic impurities has been formed, the surface of silicon substrate, particularly the surface of source/drain diffusion layers 6 is cleaned. This cleaning treatment is to remove not only impurities contaminating the surface, but also native oxide films which have formed on the surface, or to inactivate the surface. The cleaning treatment is proceeded by using a first mixture of SH OH+ H2 2 and a second mixture of H, SO, + H;O,. Such inactivation prevents the surface of source/drain diffusion layers 6 from further developing native oxide films.

The silicon substrate, having undergone above treatment, is next placed in a low-pressure (LP) CVD furnace, and receives the following treatments In succession. The LD CVD furnace is maintained at about 800 OC. The lower limit of the temperature is at 750 oC. The higher limit of the temperature is at 1100 oC to prevent the impurities in the source/drain diffusion layer from diffusing again.

First, dinitrogen monoxide gas (N20) is introduced into the LP CVD furnace maintained at 800 0C to form a silicon oxide film with a thickness of about lnm on the surface of the source/drain diffusion layers 6. This ultra-thin silicon oxide film represents the thermal oxidized protective film 7. The inventor found that the thermal oxidized protective flm 7 is the best film as a film for preventing the leak current from producing between the silicon oxide film 8 and the source/drain diffusion layers 6. Another example, the thermal nitride silicon film is inferior to the thermal oxidized protective Silm w. Thus, the preferred embodiment has a thermal oxidized protective film 7 which does not include nitrogen.

Second, after forming the thermal oxidized protective film 7, a mixture comprising silane gas (six4) and dinitrogen monoxide gas is introduced into the LP CVD furnace, and allowing a silicon oxide film 8 to form by CVD on the surface of the thermal oxidized protective film 7 at a relatively high temperature.

In a subsequent process an interlayer insulating film 9 composed of BPSG is formed by C\JD method, and its surface is planerized by thermal treatment. Then, contact holes are formed through the thermal oxidized protective film 7, protective insulating film 8 and interlayer insulating film 9, through which source/drain electrodes 10 are allowed to pass and connect to the source/drain diffusion layers 6.

Advantages of the first embodiment of the present invention will be described below with reference to Figs. 4A-3.

Referring to Fig. 4A, a memory cell includes a transfer transistor which is composed of an MOS transistor, and a capacitor.

A field oxide film 12 is formed on a specified region on the surface of a p-type silicon substrate 11. A gate electrode 13 covering a gate oxide film is formed over the surface of silicon substrate 11. The gate electrode 13 has side-ail insulating films 14 formed on its side-walls.

On the surface of silicon substrate interposed between the field oxide film 12 and gate electrode 13 are first and second diffusion layers 15 and 16. The first diffusion layer 15 has a low concentration of impurities while the second diffusion layer 16 has a high concentration of impurities. The impurity concentration of the second diffusion layer 16 is 1 x 101a atom/cm3. In a similar manner to above, as shown in Fig. 4A, another pair of first and second diffusion layers 1Sa and 16a is also formed. The first diffusion layers 15 and 15a adjacent to the gate electrode act as the source/drain regions of this transfer transistor.

Thermal oxidized protective films 17 are overlaid on the surface of this pair of first diffusion layers 15 and 15a.

Within the interlayer insulating film 18, lower and upper electrodes 19 and 20 of the capacitor are formed with an capacitive insulating film in between. One first diffusion layer 15 is connected to the lower electrode of the capacitor, while the other first layer 1Sa is connected to a bit line 21. The pair of second diffusion layers 16 and 16a is formed as a result of diffusion of impurities from the lower electrode 19 and bit line 21 which contain those impurities at a high concentration. Gate electrodes 13a and 13b constitute the gate electrodes of adjacent transfer transistors of memory cells.

The equivalent circuit of a memory cell having a structure as described above is given in Fig. 42. To the gate electrode of a transfer transistor TR is connected a word line WL. One source/drain region of the transfer transistor TR is connected to a bit line sL, while the other source/drain region is connected to one electrode of a capacitor CP. The site at which the latter source/drain region connects with one electrode of the capacitor CP is termed as node N1.

Fig. 5 provides a graph of the relationship between the yield of test elemental group (TEG) of DP9N incorporating above cells, and the thickness of thermal oxidized protective film. TEG of DRAM under study is a semiconductor chip having memory cells corresponding in capacity to 16 Mega bits. The ordinate of Fig. 5 represents the percent yield of the semiconductor chips while the abscissa the thickness of thermal oxidized protective film of the present invention.

As seen from Fig. 5, the percent yield of chips rapidly increases as the thickness of thermal oxidized protective film approaches inm, and whem the latter reaches lnm, the percent yield attains a level close to loO%. This invention, as is evident from above, will have a great effect when the thermal oxidi2ed protective film is allowed to have a thickness of lnm or more.

Another advantage this invention will bring about will be discussed below with reference to Fig. 6. Fia. 6 gives a schematic cross-section of the PN junction of an MOS transistor prepared by the method of this invention.

As shown in Fig. 6, a field oxide film 2 is formed on a silicon substrate 1. A source/drain diffusion layer 6 with a low concentration of impurities is also provided. A thermal oxidized protective film 7 is formed only on the surface of this source/drain film 6. A protective insulating film 8 is formed to cover the whole surface of the, silicon substrate 1. An interlayer insulating film 9 is overlaid on this protective insulating film 8, and a source/drain electrode 10 is allowed to penetrate through a contact hole to be connected with the source/drain diffusion layer 6. As illustrated, in this device, the periphery 6a of the diffusion layer is positioned beneath the edge 22 of field oxide film.

In a transistor with above structure, when a reverse bias is applied between the source/drain diffusion layer 6 and silicon substrate 1, a first depletion layer 23 is generated on the surface of silicon substrate 1. In addition, a second depletion layer 24 is generated on the surface of source/drain diffusion layer 6. The thickness of the first deletion layer 23 and the second depletion layer 24 are substantially the same size. For example, the thickness of the first depletion layer 23 is 5 x 102 pm and the thickness of the second depletion layer 24 is 3 x 10.2 pm. The periphery 24a of the second depletion layer is positioned higher than the edge 22 of field oxide film 2. In this transistor, however, the thermal oxidized protective film 7 is so constructed as to cover the surface of the depletion layer 24 and separate it from insulating film 8. This structure, in contrast with that provided by a conventional technique, allows a boundary potential or surface level at this interface to be greatly reduced, and hence prevents generation of a leakage current which arises as a result of such boundary potential.

The Fig. 7 shows the second embodiment of the present invention.

As shown in Fig. 7, on specified regions on the surface of a silicon substrate 1 with having one type of conductiv.icy are prepared trenches, and within the cavity of these trenches is formed an insulating film 32 for circuit element isolation.

Similarly to the first example, 'on a specific spot on the surface of the silicon substrate 31 is formed a gate oxide film 33. To this gate oxide film 33 are further added a gate electrode 3t, and side-wall insulating films 35 which surround the side-walls of the electrode.

Source/drain diffusion layers 36 with conductivity opposite to that of substrate and containing a low concentration of impurities are also provided. To the surface of source/drain diffusion layer 36 and of the trench is formed oxidi2ed protective films 37.

A protective insulating film 38 is formed as if to cover the thermal oxidized film 37, field oxide film 32 and gate electrode 34, and an interlayer insulating film is overlaid upon this protective insulating film 38.

Through a specified space across the thermal oxidized protective film 37, protective insulating film 38 and interlayer insulating film 39 is opened a contact hole, and through that hole source/drain electrodes 40 are formed to connect to the source/drain diffusion layers 36.

The advantages for this second exale of this invention are the same as those described with regard to the first example and includes reduction of a leakage current at the PN junction. In this transistor, inter-spacs between adjacent elements form trenches, which allows the MOS transistor to have a finer and smaller size.

Two examples of this invention have been detailed above. This invention will be beneficial especially when it is applied to a memory cell comprising a transfer transistor and a capacitor, because it greatly improves the memory capacity of the cell, and at the same time allows the cell to have a smaller size (to have a reduced surface area).

This invention can also be applied to the production of an impurity diffusion region which acts as a node capable of holding electric capacity in a floating state as described earlier, or, for example, to a semicondnctor device which includes a circuit as disclosed in Japanese Laid-open Patent Application No. HEI 2-176810. The circuit where impurity diffusion regions are interposed at intervals between high resistance elements or resistors and transistors connected each other in series, will readily develop large leakage current at the PN junction unless treated properly, and will give an output potential different from the designed one, leading to an error in operation. This is because the output potential is determined based on the ratio of related impedances connected in series, and if a leakage current adds to the circuit, this will modify the ratio in question, which will result in the generation of an output potential larger or smaller than initially designed.

As seen from above, chis invention is useful when applied to a semiconductor device which,decermines its potentials at internal nodes according to high impedance circuits, as well as other circuits such as memory circuits.

The semiconductor device according to this invention inhibits the development of a leakage current which may arise at the PN junction formed between one main surface of a semiconductQr substrate with one type of conductivity and an impurity diffusion layer with opposite conductivity thereupon. Thus, the invention overcomes the problem preventing the impurity diffusion layer from having a shallower junction and the requirement of a wider horizontal spread, thereby contributing to the refinement of an MOS transistor and inter-spaces between circuit elements thereof and henceto the realization of a ultra-highly integrated semiconductor device.

This invention also allows the PN junction and depletion layers of a very fine MOS transistor to be placed beneath a thermal oxidized silicon film underlying the edge of a field oxide film, thercby reducing the boundary potential density between the thermal oxidized silicon layer and silicon substrate and minimizing leakage current at the PN junction.

It is apparcnt that the present invention is not limited to the above embodimcnts but may be modified and changed without removing it from the scope and spirit of the invention.

Each feature disclosed in this specification '(which term includes the claims) and/or shown in the drawings may be incorporated in the invention independently of other disclosed and/or illustrated features.

The text of the abstract filed herewith is repeated here as part of the specification.

A semiconductor device of the present invention comprises, a semiconductor substrate of first conductivity type, an element isolation region on the semiconductor substrate, an impurity diffusion layer of second conductivity type, the impurity diffusion layer couplcd to the element isolation region and formed on said semiconductor substrate, and a CVD silicon insulating film over the element isolation region and the impurity diffusion layer, wherein a thermal silicon insulating film is formed between the impurity diffusion layer and the CVD silicon insulating film to prevent current leakage between the CVD silicon insulating film and the impurity diffusion layer.

Claims

CLAIMS:

1. A semiconductor device comprising: a semiconductor substrate of a first conductivity type; an element isolation region formed on said semiconductor substrate; an impurity diffusion layer of a second conductivity type formed on said semiconductor substrate adjacent to said element isolation region; a CVD insulating layer formed on said element isolation region; and means for separating said impurity diffusion layer from said CVD insulating layer and preventing current leakage between said layers.

2. A semiconductor device according to claim 1, wherein said means for separating said impurity diffusion layer from said CVD insulating layer has fewer dangling-bonds than said CVD insulating layer.

3. A semiconductor device according to claim 1, wherein said means for separating is a separating insulator having fewer dangling-bonds than said CVD silicon insulating film.

4. A semiconductor device according to claim 1, 2 or 3 wherein said means for separating is a thermal silicon insulating film formed between said impurity diffusion layer and said CVD insulating layer.

5. A semiconductor device according to claim 4, wherein the thickness of said thermal silicon insulating film is 1 nm or more.

6. A semiconductor device according to claim 4 or 5, wherein said thermal silicon insulating film is oxidized.

7. A semiconductor device according to any preceding claim, wherein said CVD insulating layer is a silicon CVD insulating film.

8. A semiconductor device according to any prcceding claim, wherein said impurity diffusion layer is a lightly doped drain structure.

9. A semiconductor device according to any preceding claim, wherein said element isolating region is of a trench type.

10. A semiconductor device according to claims 6 and 7, further comprising a ntype interlayer insulating film formed on said CVD silicon insulating film.

11. A semiconductor device according to claim 10, wherein thickness of said impurity diffusion layer is 0.1 um or less.

12. A semiconductor device according to claim 1, further comprising a gate insulating film formed on semiconductor substrate adjacent to said impurity diffusion layer; an gate electrode formed on said gate insulating film; a side wall film formed on the side of said gate electrode; said separating means being a thermal silicon oxide insulating film formed on said impurity diffusion layer and contacting to said element isolation region; said CVD insulating layer being a silicon CVD insulating layer formed on said thermal silicon oxide film, said element isolating region, said side wall film and said gate electrode; and further comprising an interlayer insulating film on said CVD silicon insulating film; and a conductive film buried in a contact hole in said interlayer insulating film, said CVD silicon oxide film, and said thermal silicon oxide film so as to contact said impurity diffusion layer.

13. A semiconductor device according to claim 12, wherein the element isolation region is a trench type, and a thermal silicon oxide film is sandwiched between said element isolation region and said impurity diffusion layer.

14. A method of manufacturing a semiconductor device comprising the steps of: forming an element isolation region on a semiconductor substrate; forming an impurity diffusion layer on said semiconductor substrate adjacent to said element isolation region; forming a CVD insulating layer over said element isolation region and said impurity diffusion layer; and forming a separating layer between the CVD silicon insulating layer and the impurity diffusion layer to prevent current leakage between said layers.

15. A method according to claim 14, wherein the separating layer is a film having fewer dangling bonds than said CVD silicon insulating film.

16. A method according to claim 14, wherein the separating layer is a thermal silicon insulating film on said impurity diffusion layer.

17. A method of manufacturing a semiconductor device comprising the steps of: forming a field insulating film on a first portion of said semiconductor substrate; forming a first insulating film on a second portion of said semiconductor substrate; selectively forming a gate electrode film on a part of said first insulating film; selectively forming a second insulating film on a side surfaces of said gate electrode film; introducing impurities into said second portion by using said film insulating film and said gate electrode as a mask to produce an impurity diffusion layer on said second portion of said semiconductor substrate; forming a thermal silicon insulating film on said impurity diffusion layer, forming a CVD silicon insulating film on said thermal silicon oxide layer and said field insulating film; forming an interlayer insulating film on said CVD silicon insulating film; forming a contact hole in said interlayer insulating film, said CVD silicon insulating film, and said thermal silicon insulating film to contact said impurity diffusion layer; burying a second conductive film to connect to said impurity diffusion layer.

18. A method according to claim 16 or 17, wherein said thermal silicon insulating film is preferably formed at a temperature between 750" to 1100 C.

19. A method according to claim 16 or 17, wherein said thermal silicon insulating film is formed by a gas including nitrogen and oxygen.

20. A method according to claim 16 or 17, wherein said CVD silicon oxide film is formed by a mix gas including N20 and SiH4.

21. A method according to claim 16 or 17, wherein a surface of said impurity diffusion layer is cleaned before said thermal silicon insulating film is formed, to remove native oxide and inhibit further growth of native oxide.

22. A method according to claim 16 or 17, wherein a thickness of said thermal silicon insulating film is 1 nm or more.

23. A method according to claim 16 or 17, wherein said thermal silicon insulating film and said CVD silicon insulating film are formed in situ.

24. A method according to any of claims 17 to 23, wherein said thermal silicon insulating film is a thermal silicon oxide film and wherein said cVD silicon insulating film is a silicon oxide film.