GB2258051A - Determining propagation delays in signal paths - Google Patents

Abstract

Propagation delays in signal paths leading to respective pins (21,22) in an array of test system pins are determined using a probe which is wiped across the pins. Alternate timing signals (19) and pin identifying signals (18) are applied (20) to each of the signal paths in parallel such that each signal path and the pin to which it is connected receives a different pin identifying signal. When the probe (Fig 2 not shown) is wiped across the pins, it detects the signals on each of the pins and each pin is identified by the appropriate pin identifying signal. The propagation delay in the signal path to the identified pin is then calculated from the detected timing signals e.g. by comparing the timing signals with signals (26) from a clock of a different frequency. <IMAGE>

Description

TEST SYSTEM The present invention relates to a test system, and in particular to a test system which can be calibrated to take account of propagation delays which occur in signal paths leading to respective pins of the test system.

Test systems are widely used to enable circuit components such as boards or individual electronic components to be tested. The known test systems generally comprise sophisticated test electronics including signal generation circuits for producing a large number of test signals including D.C. voltage levels and timing signals. It may be necessary to provide the capacity to generate several thousand different test signals and thus the test electronics are expensive and must be adaptable so they can be used to test a variety of different components. Thus it is conventional practice to provide an interface known as a test "fixture" to connect a board or other component to be tested to the test electronics.

Typically, the test electronics is housed in a cabinet provided with an array of output pins housed in a structure known as a "receiver". When a new design of board is to be tested, a fixture is produced which acts as an interface between the board under test and the receiver. The fixture effectively plugs into the receiver, and the board under test plugs into the fixture. Signal paths are wired between fixture pins that contact the receiver and fixture pins that contact the board.

In many test operations, it is necessary to generate timing signals that arrive at the board with a predetermined phase relationship. Although the appropriate phase relationship can be established at the source of the signals in the signal generator ,these signals are propagated along different signal paths to the receiver, and along different signal paths through the fixture. The different signal paths introduce propagation delays which may vary from one path to another.

The problem of non-unifo;rm propagation delays is well known, and is conventionally addressed by incorporating calibration circuitry. Such circuitry includes delay devices arranged in the signal paths to add delays selectively such that all the propagation delays in the signal paths are substantially equal. Various proposals have been made to connect propagation delay measurement circuits either to the receiver (on the assumption that propagation delays in the fixture have been approximately equalised by careful design of the signal paths within the fixture) or to pins that contact the component under test directly.

One known system is described in the article "Closed loop error correction: a unique approach to test system calibration" by Mark Dahl, published as paper 32.2 of the 1987 International Test Conference, CH 2347-2/87/0000/0772. This paper describes calibration support circuitry which is a separate unit from the test system and can therefore be placed in a mobile calibration unit such that can be shared by many tester systems. Contacts of a test fixture are probed by a signal probe that is driven by an X-Y positioning device across the fixture. The positioner moves at a speed that enables for example 256 pin channels to be probed in less than 60 seconds. The source of signals picked up by the probe are identified by reference to the location of the positioner relative to the fixture.This arrangement avoids the conventional requirement for each tester to incorporate internal calibration circuitry to which signals are routed back from the fixture pins through a complex network of cables and switches, but this is at the expense of providing a precision piece of equipment to drive the positioner, and using a standard fixture structure that fits the positioning equipment.

It is also known to provide a simple electrical continuity detector in the form of a probe that is manually "wiped" across the pins of for example a fixture. Signals picked up by the probe enable the presence or absence of DC levels on the fixture pins to be detected. This system does not enable information to be derived from the wiped pins which could be used for example to measure propagation delays in signal paths leading to the pins.

It is an object of the present invention to provide a test system which can be used to derive timing calibration data using a simple probe to wipe pins carrying timing signals.

According to the present invention there is provided a test system for determining propagation delays in signal paths leading to respective pins in an array of pins, comprising means for applying timing signals to each of the signal paths in parallel, means for applying pin identifying signal to each of the signal paths, a different pin identifying signal being applied to each signal path, a probe which can be wiped across the pins to detect signals on each pin with which it comes into contact, means for identifying a pin with which the probe is in contact from the pin identifying signals detected by the probe, and means for calculating the propagation delay in the signal path leading to an identified pin with which the probe is in contact from the timing signals detected by the probe.

Preferably the timing signals and pin identifying signals are applied alternately to each of the signal paths. Each pin identifying signal may comprise a rectangular wave embodying a digital code allocated to the respective pin, and means may be provided to generate a strobe pulse signal synchronised with the pin identifying signals applied to the signal paths such that each strobe pulse coincides in time with a respective portion of the rectangular wave that represents one bit of the digital code.The duration of each portion of the rectangular wave is selected to be sufficient to ensure that the strobe pulses continue to coincide in time with the respective portions of the rectangular wave despite delays in propagation of the rectangular waves in the signal paths leading to the pins for which they are detected, and means are provided to sample the identifying signals in synchronism with the strobe pulses to derive the digital codes.

Preferably, the timing signals comprise a rectangular wave of fixed frequency applied in phase to each signal path, and the calculating means comprises means for comparing the phase of the timing signals detected by the probe. The calculating means may comprise means for sampling each timing signal detetected by the prober with a common clock signal having a different frequency from said fixed frequency to produce sampled data. The calculating means may further comprise means for detecting an edge in the sampled data, and means for recording a cycle count corresponding to the number of cycles in the common clock signal from the initiation of a timing signal to the detection of an edge.

Preferably, means are provided for detecting loss of electrical contact between the probe and a pin in an interval of time during which identifying or timing signals are being applied to that pin, signals detected during intervals of time in which loss of electrical contact is detected being rejected.

Preferably, each identifying signal and timing signal comprises a rectangular waveform which alternates between two voltage levels, and means are provided to maintain the probe at a third voltage level to the probe if the probe is not in electrical contact with any external voltage source, the loss of contact detecting means comprising means for detecting the said third voltage.

The invention also provides a method for determining propagation delays in signal paths leading to respective pins in an array of pins, wherein timing signals are applied to each of the signal paths in parallel, pin identifying signals are applied to each of the signal paths such that each signal path and the pin to which it is connected receives a different pin identifying signal, a probe is wiped across the pins to detect signals on each of the pins with which it comes into contact, any pin with which the probe is in contact is identified by detection of the pin identifying signal, timing signals on an identified pin are detected, and the propagation delay in the signal paths to the identified pin is calculated from the detected timing signals.

An embodiment of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which; Figure 1 is a schematic diagram of a system in accordance with the present invention; Figure 2 illustrates an array of tester pins across which a probe shown in Fig. 1 is wiped; Figure 3 illustrates signals detected by the probe of Fig. 2; Figure 4 illustrates in simplified form a circuit to which the signals detected by the probe of Fig. 2 are applied; Figure 5 illustrates waveforms output from the circuit of Fig. 4; Figure 6 is an enlarged illustration of part of the waveform of Fig. 5; Figure 7 illustrates a further enlarged first portion of the waveform of Fig. 6; Figure 8 illustrates a further enlarged second portion of the waveform of Fig. 6 and associated timing waveforms used to extract a pin identifying signal from the second portion;; Figure 9 is a schematic illustration of the operation of the system of Fig. 1; Figure 10 illustrates the calculation of skew in the system of Fig. 1; and Figure 11 is a flow diagram further illustrating the operation of the system of Fig. 1.

Referring to the drawings, Fig. 1 is a highly schematic illustration of the basic components of a circuit board tester embodying the invention. It comprises a tester 1 incorporating circuitry for generating test signals including timing signals and defining a connector or receiver 2 to which an interface or test fixture 3 can be connected. The fixture supports contacts 4 which can be interconnected with the receiver 2 and a socket 5 into which edge connectors 6 of a circuit board 7 to be tested can be inserted. It will be appreciated that other forms of test fixtures may be used, eg "bedof-nails" fixtures in which spring loaded pins enable contact to be made with selected points in the underside of a board. The fixture 3 is provided simply to make appropriate connections between contacts in the socket 5 and contacts in the receiver 2.Simple wire wrapping techniques are generally used to make the required interconnections.

Timing signals generated by the tester 1 are applied to the pins 6 of the board under test. It is generally necessary to ensure that such timing signals arrive at the pins of the board under test with a predetermined phase relationship. Propagation delays inevitably occur in the signal paths established between the timing signal generation equipment in the tester 1 and the pins 6 of the board. It is necessary to introduce controlled delays in the signal paths such that all the signals arrive at the board pins with appropriate relative phase.

Some means must be provided to enable the propagation delays to be measured, ideally by measurements taken at the board pins themselves, but alternatively at the receiver 2 if the fixture has been carefully designed to ensure substantially equal propagation delays through signal paths within the fixture.

The present invention provides a probe 8 which can be manually wiped across the pins 6 or contacts in the receiver 2. Signals detected by the probe enable appropriate delays to be introduced into the signal paths, either automatically using a closed control loop or alternatively in a separate calibration routine. The embodiment described below uses a separate calibration routine rather than a closed control loop.

Figure 2 illustrates the pins 6 of a board mounted in the socket 5 of Fig. 1. The pins 6 will typically be arranged with a pitch of 0.1 inches. The probe 8 has a tip 9 which is sufficiently small to avoid contact with two pins 6 simultaneously. The probe tip 9 is wiped across the pins 6 as indicated by arrow 10.

Figure 3 illustrates waveforms appearing on the probe tip 9 as it is wiped across the pins 6. A resistor (not shown) is connected in the probe 8 to ground such that the voltage on tip 9 is zero volts when the probe is out of contact with the pins, or when no signals are present on contacted pins. The signals applied to the pins alternate between 2 volts and 4 volts.

Figure 4 illustrates a circuit to which the voltage picked up by the probe tip is applied. The circuit comprises two comparators 11 and 12, the positive input of each comparator being connected to terminal 13 to which the probe is connected, and the negative inputs being connected to fixed potentials of 3 volts and 1 volt respectively applied to terminals 14 and 15. The circuit thus provides two outputs at terminals 16 and 17 respectively.

Referring to Figure 5, the upper waveform represents the output on terminal 16, and the lower waveform the ouput on terminal 17.

Waveforms derived from four consecutively wiped pins are illustrated.

The upper waveform follows transitions to or from 4 volts, whereas the lower waveform follows transitions to or from zero volts. Thus the lower waveform indicates whether or not the probe is in contact with a pin to which a voltage of 2 or 4 volts is being applied.

Figure 6 is an enlargement of a portion of one of the four waveforms shown in the upper part of Fig. 5. It will be seen that the signal comprises relatively short sections 18 which as described below identify the pin with which the probe is in contact, and longer sections 19 which carry timing information. The pin identifying sections 18 are interleaved with the timing sections 19. The overall cycle repeats approximately every 100 microseconds, such that twenty complete cycles will occur during a period of contact between the probe and a pin of 2 milliseconds. This period of contact will be achieved given a reasonably fast wipe of the probe across pins with a pitch of 0.1 inches.

Referring to Figure 7, this illustrates the square wave timing signals output from terminal 16 of Fig. 4 during the timing sections 19 of Fig. 6. Each cycle of the signal has a duration of 100.2 nanoseconds. All the pins carry the same timing signals. If all the signal paths leading to the pins were to have identical propagation delays, the timing section signals on the pins would be exactly in phase. Referring to Fig. 8, In contrast, the upper waveform illustrates the identifying signal output from terminal 17 of Fig. 4 applied to one only of the pins during a signal portion 18. This signal represents a pin identification code of 1011010011010010, or B4D2 in hexadecimal.

Each pin carries a respective identification code. The middle waveform of Figure 8 represents strobe signals which determine when each bit of the pin identification code should be read, and the lower waveform of Figure 8 represents a "contact made or contact lost" signal derived from terminal 17 of Fig. 4. Each bit of the pin identification waveform has a duration of 400.8 nanoseconds. Thus the pin identification signal is transmitted sufficiently slowly that the strobe signals will always line up with respective bits of the rectangular code carrying waveform regardless of propagation delays in the signal paths. If the lower waveform indicates a loss of contact between the probe and a pin during transmission of an identification code, the identification code is ignored and the circuitry simply awaits receipt of the next identification code signal section 18.

Referring now to figure 9, this schematically illustrates the overall system operation. A tester control system 20 outputs identification and timing signals to the receiver contact pins only two of which are represented by terminals 21 and 22. It is the terminals 21 and 22 that are wiped with the probe. Pin identification sections 18 carry respective pin identification codes and timing signal sections 19 carry the common timing signals. The signals are transmitted through signal paths each of which incorporates a driver 23 that can be controlled to add a propagation delay to the respective path. The tester control system also outputs the strobe signal 24 (middle waveform of Fig. 8) and a measurement control signal 25 which has a duration equal to five hundred cycles of a sampling clock waveform 26.The signal 25 defines the period of time with which measurements of the timing signal are to be made.

The sampling clock signal 26 has a cycle duration of 100 nanoseconds and is used in edge detection as described below. The logic unit searches for pin identity codes in a timing window represented by arrow 28. When a valid pin identity code is detected, this information is processed as described below. When an edge is detected in a timing window indicated by arrow 29, its position or cycle count in the five hundred cycle measurement period defined by signal 25 is detected. This edge position is then used to determine the propagation delay in the signal path to the identified pin.

Edge detection is described with reference to figure 10. To simplify the description, Fig. 10 indicates a measurement cycle of 110 nanoseconds rather than 100.2 as actually used, and an edge detection sampling clock signal with a cycle duration of 100 nanoseconds which is the cycle actually used. Waveform A represents a measurement signal derived from pin 21 having a skew of 40 nanoseconds, waveform B represents a measurement signal derived from pin 22 having a skew of zero, and waveform C represents the edge detection sampling clock signal. The signal of waveform A is sampled and the resultant sampled data is represented by waveform D. The signal of waveform B is sampled and the resultant sampled data is represented by waveform E.There is thus an apparent skew of four cycles as represented by arrow 30, that is four times the difference between the duration of the cycles of the measurement signals and the sampling clock, or 40 nanoseconds. Cycle counts are indicated at F in Fig. 10, such that the detected edges have cycle counts of 1 and 5 for waveforms B and A respectively. Cycles are counted in synchronism with wavefrom C, and this relationship between the sampling clock and the waveform count is maintained throughout a measurement period.

The edge detector is a state machine that in the illustrated example would detect a rising edge as the occurrence of a sequence 0001 in the sampled data. The cycle count would thus be logged when the edge detector detects a "1" after a series "000". the edge detector could have control inputs to detect a rising edge start (0001), a falling edge start (1110), a rising edge end (0111), or a falling edge end (1000).

Figure 10 seeks to explain essentially conventional undersampling techniques used for edge detection. Given the actual measurement signal and clock cycles used of 100.2 and 100 nanoseconds the sampled data would of course provide much greater accuracy.

Edges would also typically only be registered after say fifteen "0"'s followed by a "1".

The data obtained as described above gives a pin identity for each measurement signal, and a cycle count for an edge detected in the measurement signal (a cycle count of up to 500). The skew between any two pairs is then calculated by multiplying the difference between the cycle counts by the difference in period between the measurement signal and the sample clock signal (0.2 nanoseconds in the case described in Figs. 7 and 8). If the skew exceeds the sample clock period, aliasing results. Thus care must be taken to ensure that the skew cannot exceed this limit.

Referring now to Figure 11, this illustrates in simplified form the control flow in the described test system. After starting, the system awaits receipt of pin identification strobe signals (middle waveform of Fig. 8). Once the strobe signal is detected, any detected pin identification signal is read. If the contact test signal (lower waveform of Fig. 8) indicates a break in physical contact between the pin and the probe, the system aborts the pin identification read and awaits the next strobe cycle. If contact was not lost, the pin identification is read and compared with the last valid identification code to be read. If there is no identity, the new pin identification code is logged and the next measurement signal is monitored. If there is identity, the previously logged pin identity is maintained. Once a pin identity has been established, subsequent measurement signals are awaited and a sampled edge is detected. Assuming contact is not lost during the measurement signals, the cycle count of the detected edge is logged.

It will be appreciated that a series of cycle counts could be logged for one pin to enable averaging or the like to improve accuracy. It will also be appreciated that alternative measurement techniques to those described above could be used to measure propagation delays.

Claims (9)

1. A test system for determining propagation delays in signal paths leading to respective pins in an array of pins, comprising means for applying timing signals to each of the signal paths in parallel, means for applying pin identifying signals to each of the signal paths, a different pin identifying signal being applied to each signal path, a probe which can be wiped across the pins to detect signals on each pin with which it comes into contact, means for identifying a pin with which the probe is in contact from the pin identifying signal detected by the probe, and means for calculating the propagation delay in the signal path leading to an identified pin with which the probe is in contact from the timing signals detected by the probe.

2. A test system according to claim 1, wherein the timing signals and pin identifying signals are applied alternately to each of the signal paths.

3. A test system according to claim 1 or 2, wherein each pin identifying signal comprises a rectangular wave embodying a digital code allocated to the respective pin, means are provided to generate a strobe pulse signal synchronised with the pin identifying signals applied to the signal paths such that each strobe pulse coincides in time with a respective portion of the rectangular wave that represents one bit of the digital code, the duration of each portion of the rectangular wave being sufficient to ensure that the strobe pulses continue to coincide in time with the respective portions of the rectangular wave despite delays in the propagation of the rectangular waves in the signal paths leading to the pins for which they are detected, and means are provided to sample the identifying signals in synchronism with the strobe pulses to derive the digital codes.

4. A test system according to claim 1, 2 or 3, wherein the timing signals comprise a rectangular wave of fixed frequency applied in phase to each signal path, and the calculating means comprises means for comparing the phase of the timing signals detected by the probe.

5. A test system according to claim 4, wherein the calculating means comprises means for sampling each timing signal detected by the probe with a common clock signal having a different frequency from said fixed frequency to produce sampled data.

6. A test system according to claim 5, wherein the calculating means further comprises means for detecting an edge in the sampled data, and means for recording a cycle count corresponding to the number of cycles in the common clock signal from the initiation of a timing signal to the detection of an edge.

7. A test system according to any preceding claim, comprising means for detecting loss of electrical contact between the probe and a pin in an interval of time during which identifying or timing signals are being applied to that pin, and means for rejecting signals detected during intervals of time in which loss of electrical contact is detected.

8. A test system according to claim 7, wherein each identifying signal and timing signal comprises a rectangular waveform which alternates between two voltage levels, and means are provided to maintain the probe at a third voltage level to the probe if the probe is not in electrical contact with any external voltage source, the loss of contact detecting means comprising means for detecting the said third voltage.

9. A method for determining propagation delays in signal paths leading to respective pins in an array of pins, wherein timing signals are applied to each of the signal paths in parallel, pin identifying signals are applied to each of the signal paths such that each signal path and the pin to which it is connected receives a different pin identifying signal, a probe is wiped across the pins to detect signals on each of the pins with which it comes into contact, any pin with which the probe is in contact is identified by detection of the pin identifying signal, timing signals on an identified pin are detected, and the propagation delay in the signal path to the identified pin is calculated from the detected timing signals.