GB2215514A - Terminating dislocations in semiconductor epitaxial layers - Google Patents
Terminating dislocations in semiconductor epitaxial layers Download PDFInfo
- Publication number
- GB2215514A GB2215514A GB8805155A GB8805155A GB2215514A GB 2215514 A GB2215514 A GB 2215514A GB 8805155 A GB8805155 A GB 8805155A GB 8805155 A GB8805155 A GB 8805155A GB 2215514 A GB2215514 A GB 2215514A
- Authority
- GB
- United Kingdom
- Prior art keywords
- semiconductor assembly
- substrate
- dislocations
- mismatched
- layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 239000000463 material Substances 0.000 claims description 13
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- 238000000034 method Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 claims 19
- 239000010703 silicon Substances 0.000 claims 5
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims 3
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims 2
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 claims 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims 2
- 239000002356 single layer Substances 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 238000013459 approach Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005441 electronic device fabrication Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02428—Structure
- H01L21/0243—Surface structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Recrystallisation Techniques (AREA)
Abstract
A semiconductor assembly comprising a substrate 11 and a lattice parameter mismatched epitaxial layer (5, 7) is arranged such that dislocations (3) which span the epitaxial layer, are terminated by dislocation termination regions (10) constructed in the epitaxial layer. A region of the semiconductor assembly is thus provided having a reduced number of dislocations. Dislocation termination regions may be provided by mesas or trenches in the substrate, or regions of the substrate rendered amorphous by high dosage ion implantation, for example. <IMAGE>
Description
A SEMICON'DUCTOR ASSEMBLY
The present invention relates to a semiconductor assembly and more-particularly to such an assembly comprising a substrate with at least one epitaxial layer thereupon.
When an epitaxial layer is grown upon a substrate and there is a lattice parameter mismatch then dislocations are produced near the interface between the layer and the substrate. This will in general be true for all types of semiconductor system, including Si, Ge, III-V materials, Il-Vi materials or IV-IV-VI materials for either epitaxial layers or substrates. Specific examples of such substrate/epitaxial layer mismatch are Ge on Si, GaAS on Si, InGaAs on GaAs, InP on
GaAs, InP on Si, InGaAs on Si and GaAs on InP. These latticeparameter-mismatch relieving dislocations although often produced in the vicinity of the lattice mismatch interface, have a strong tendency to interact to form perpendicular dislocations which span or thread across the grown or growing epitaxial layer.These perpendicular dislocations, in particular; lead to a severe degradation of the epitaxial layer's structural properties which in turn will effect electronic and optical properties. Degradation of the epitaxial layer results in impaired performance of electronic, optoelectronic or optical devices constructed using the epitaxial layer.
There is frequently a requirement to produce relatively thick epitaxial layers upon lattice-parameter-mismatched substrates. The relief of lattice parameter mismatches inevitably involves the formation of dislocations. It is however, the perpendicular dislocations that span the epitaxial layer which present the greatest problem.
Previously, several approaches have been made to prevent or to hinder these perpendicular dislocations spanning the epitaxial layer. A first approach is to provide layers of graded lattice parameter material or strained layer super lattices in the epitaxial layer in order that the number of perpendicular dislocations spanning the epitaxial layer is reduced. Alternatively, layers of differing elastic properties in the epitaxial structure may be used.
Furthermore, differing thermal treatments may be used to anneal out the dislocations.
These previous approaches reduce the number of dislocations entering higher regions of the epitaxial layer. However, this is at the expense of altering the configuration of the dislocation structures.
Consider Figure 1, in part illustrating prior dislocation problems and in part illustrating the present invention. In a prior dislocation region 1, a spanning dislocation 3 is illustrated between epitaxial layers 5, 7, having respectively graded lattice parameters in accordance with the prior dislocation hindering approach described above. It may be considered that the dislocations have been "turned-out" into a direction substantially perpendicular to the epitaxial layer direction of deposition or growth. Thus, these dislocations might be expected not to adversley effect the epitaxial layer as they do not enter the higher regions of the epitaxial layer used to form electronic devices.In practise, however, subsequent influences upon the dislocation, possibly involving interactions between closely spaced adjacent dislocations, tend to redirect dislocations into a mode where the dislocation is deflected to span the higher epitaxial layers. Consequently, in Figure 1, dislocation 3 is deflected at A such that it spans not only epitaxial layer 5, but also layer 7.
It is an objective of the present invention to provide a region of epitaxial layer upon a substrate of mismatched lattice parameter, wherein that region of epitaxial layer is substantially free of dislocations that span the epitaxial layer.
According to the present invention there is provided a semiconductor assembly comprising a substrate and, superjacent thereto at least one mismatched parameter layer whereby dislocations may be formed extending parallel to said layer, characterised in that the surface of the substrate is conformed to provide predetermined regions of facile dislocation termination whereat the parallely extending dislocations may terminate.
Further in accordence with the present invention there is provided in the manufacture of semiconductors, a method of reducing dislocations in mismatched parameter layers formed on a substrate, comprising a step of conforming the substrate to provide predetermined facile dislocation termination regions whereby dislocations in the structure, extending parallel to the layers thereof, tend to terminate in said regions.
An embodiment of the present invention will now be described by way of example only with reference to the accompanying drawings, where:
Figure 1 illustrate, in cross-section, a semiconductor assembly according to the present invention;
Figure 2 illustrates, in perspective a first semiconductor substrate configuration in accordance with the present invention as illustrated in Figure l; Figure 3 illustrates, in perspective, a second semiconductor substate configuration in accordance with the present invention as illustrated in Figure 1;
Figure 4 illustrates, in plan, a third semiconductor substrate configuration in accordance with the present invention as illustrated in Figure 1; and,
Figure 5 illustrates, in plan, a fourth semiconductor substrate configuration in accordance with the present invention as illustrated in Figure 1.
In Figure 1 a semiconductor assembly according to the present invention is illustrated. As described previously in an epitaxial layer region 1 there is a likelyhood of dislocation 3 spanning the epitaxial layers 5, 7, as the dislocation 3 propagates until terminated at an outer or free surface of the epitaxial layer. It is an aspect of the present invention to provide facile dislocation or termination regions at predetermined locations such that a dislocation can be terminated in a relatively short distance of propagation. A raised section or mesa 9 in substrate It can be used to form a facile dislocation termination region 10. The mesa 9 can be formed by etching away surrounding substrate and may be, for example, circular or rectangular in plan.The size of the mesa 9 is determined by the function of the facile dislocation termination region 10; there should be sufficient curvature the of dislocation in the epitaxial layers 5, 7 to precipitate termination of the dislocation. A typical mesa 9 would thus be 200plum across with a height of a 4,us. The height of the mesa 9 must be significant compared to the epitaxial layer 5, 7 thickness, although shape, width and height are not specifically critical.
The dislocation termination region 10 comprises the layers of - epitaxial material about the mesa 9 edges, the underlying substrate mesa 9 acting to accentuate the grading of the layers of epitaxial material in the termination region 10. The nett result of accentuating the grading of the layers of epitaxial material 5, 7 is to make propagation of the dislocation 15 towards a free or amorphous outer surface 11 of the termintion region 10 most favourable.
Propagation of the dislocation 15 is terminated at the surface 11.
A dislocation 15 in the region of epitaxial layer 5, 7 above the mesa 9 will be "turned over" as previously described. This "turned over" dislocation 15 will propagate in a less harmful lateral direction, most usually at the interface between adjacent graded epitaxial layers 5, 7, until it encounters an outer surface 11 of a facile dislocation termination region 10. At the termination region 10 the dislocation 15 tends to be attracted to the "free" external surface 11 of the region 10 thus terminating the dislocation 15 without becoming perpendicular to the substrate surface. It is thus important to arrange that the mesa 9 is dimensioned whereby the lateral distance travelled by the dislocation 15 is limited such that the possiblity of deflection of the dislocation into the perpendicular is reduced. It should be appreciated that it is not essential as dislocations may naturally propagate in a direction parallel to the substrate surface.
Although a mesa 9 is illustrated in Figure 1 it will be appreciated that a trench could be used instead to provide dislocation termination at its corners. Furthermore, dislocation sinks could be provided by alternative - means other than etching structures into the substrate. An example of such an alternative means could be amorphous regions of semiconductor substrate as produced by high dosage ion implantation.
The present invention requires adaptation of the substrate or epitaxial layer in order to provide dislocation "sinks" or terminating regions 10. By such an approach or assembly the extent of dislocation propagation can be localised and the possibility of a dislocation spanning the epitaxial layer, perpendicularly to the useful surface thereof, is reduced.
Figures 2 to 5 illustrate examples alternative substrates mesa structure in accordance with the present invention. Figure 2 illustrates a raised circular mesa 21 whilst Figure 3 illustrates a similar raised square mesa 31, these mesa 21, 31 may be fabricated by etching away surrounding substrate material. In Figures 5 and 6 alternative patterning, by way of trenches, for the substrate is illustrated which allow greater use of the substrate for electronic device fabrication whilst ensuring a short distance between dislocation termination regions. It will be appreciated that mesa and trench structures in the present invention are interchangeable.
It will be appreciated that dislocation termination regions are preferably located such that these regions are maximised in the direction of most likely dislocation propagation.
In the present invention, whilst the number and effect of dislocations is reduced, the invention does not attempt to prevent dislocation nucleation.
Claims (16)
1. A semiconductor assembly comprising a substrate and, superjacent thereto, at least one mismatched parameter layer whereby dislocations may be formed extending parallel to said layer, characterised in that the surface of the substrate is conformed to provide predetermined regions of facile dislocation termination whereat the parallely extending dislocations may terminate.
2. A semiconductor assembly as claimed in claims 1 wherein the mismatched parameter layer is arranged to turn non-parallel dislocations to extend parallel to the layer.
3. A semiconductor assembly as claimed in claim 2 wherein the mismatched parameter layer comprises a plurality of graded lattice parameter mismatched layers.
4. A semiconductor assembly as claimed in claim 2 wherein the mismatched parameter layer comprises a plurality of strained lattice parameter mismatched layers.
5. A semiconductor assembly as claimed in claim 2 wherein the mismatched parameter layer comprise a plurality of different elasticity constant layers.
6. A semiconductor assembly as claimed in claim 2 wherein the mismatched parameter layer comprises a single layer of traverse graded lattice parameter material.
7. A semiconductor assembly as claimed in claim 1, wherein the facile dislocation termination region is provided by a raised area upon the substrate.
8. A semiconductor assembly as claimed in claim 1, wherein the facile dislocation termination region is provided by a trench in the substrate.
9. A semiconductor assembly as claimed in claim 1, wherein the facile dislocation termination regions is provided by an amorphous semiconductor region in the substrate.
10. A semiconductor assembly as claimed in claiml wherein the mismatched parameter layer comprises a plurality of discrete layers of material with graded respective lattice parameter values, such that any perpendicular dislocations are turned at the interface between said discrete layers.
11. A semiconductor assembly as claimed in claim 7 or 8 wherein the mesa or trench is formed by etching.
12. A semiconductor assembly as claimed in any proceding claim wherein the substrate and epitaxial layer are selected from the following, Silicon, Germanium, III-V material, II-VI material or IV
IV-VI material.
13. A semiconductor assembly as -claimed in any proceding claim wherein the substrate and epitaxial layer are respectively of the following, Germanium upon Silicon, Gallium Arsenide upon Silicon,
Indium Gallium Arsenide upon Gallium Arsenide, Indium Phosphide upon Silicon, Indium Gallium Arsenide upon Silicon, or Gallium
Arsenide upon Indium Phosphide.
14. A semiconductor assembly substantially as hereinbefore described with reference to the accompanying drawings.
15. In the manufacture of semiconductors, a method of reducing dislocations in mismatched parameter layers formed on a substrate, comprising the step of conforming the substrate to provide predetermined facile dislocation termination regions whereby dislocations in the structure, extending parallel to the layers thereof, tend to terminate in said regions.
16. A method of reducing dislocations spanning graded lattice parameter mismatched layers substantially as hereinbefore described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8805155A GB2215514A (en) | 1988-03-04 | 1988-03-04 | Terminating dislocations in semiconductor epitaxial layers |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8805155A GB2215514A (en) | 1988-03-04 | 1988-03-04 | Terminating dislocations in semiconductor epitaxial layers |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB8805155D0 GB8805155D0 (en) | 1988-04-07 |
| GB2215514A true GB2215514A (en) | 1989-09-20 |
Family
ID=10632832
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8805155A Withdrawn GB2215514A (en) | 1988-03-04 | 1988-03-04 | Terminating dislocations in semiconductor epitaxial layers |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2215514A (en) |
Cited By (28)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0469790A1 (en) * | 1990-08-02 | 1992-02-05 | AT&T Corp. | Semiconductor devices with low dislocation defects and method for making same |
| US5091767A (en) * | 1991-03-18 | 1992-02-25 | At&T Bell Laboratories | Article comprising a lattice-mismatched semiconductor heterostructure |
| FR2724487A1 (en) * | 1994-08-05 | 1996-03-15 | Daimler Benz Ag | COMPOSITE STRUCTURE WITH A SEMICONDUCTOR LAYER ARRANGED ON A DIAMOND LAYER AND / OR A DIAMOND-LIKE LAYER AND METHOD FOR THE PRODUCTION THEREOF |
| US5859864A (en) * | 1996-10-28 | 1999-01-12 | Picolight Incorporated | Extended wavelength lasers having a restricted growth surface and graded lattice mismatch |
| US5877519A (en) * | 1997-03-26 | 1999-03-02 | Picolight Incoporated | Extended wavelength opto-electronic devices |
| WO2004023536A1 (en) * | 2002-09-03 | 2004-03-18 | University Of Warwick | Formation of lattice-tuning semiconductor substrates |
| WO2011135432A1 (en) | 2010-04-27 | 2011-11-03 | Von Kaenel Hans | Dislocation and stress management by mask-less processes using substrate patterning and methods for device fabrication |
| US8216951B2 (en) | 2006-09-27 | 2012-07-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures |
| US8237151B2 (en) | 2009-01-09 | 2012-08-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Diode-based devices and methods for making the same |
| US8253211B2 (en) | 2008-09-24 | 2012-08-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor sensor structures with reduced dislocation defect densities |
| US8274097B2 (en) | 2008-07-01 | 2012-09-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reduction of edge effects from aspect ratio trapping |
| US8324660B2 (en) | 2005-05-17 | 2012-12-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
| US8329541B2 (en) | 2007-06-15 | 2012-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | InP-based transistor fabrication |
| US8344242B2 (en) | 2007-09-07 | 2013-01-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-junction solar cells |
| US8384196B2 (en) | 2008-09-19 | 2013-02-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Formation of devices by epitaxial layer overgrowth |
| US8502263B2 (en) | 2006-10-19 | 2013-08-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Light-emitter-based devices with lattice-mismatched semiconductor structures |
| US8624103B2 (en) | 2007-04-09 | 2014-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Nitride-based multi-junction solar cell modules and methods for making the same |
| US8629446B2 (en) | 2009-04-02 | 2014-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Devices formed from a non-polar plane of a crystalline material and method of making the same |
| JP2014112695A (en) * | 1998-07-31 | 2014-06-19 | Sharp Corp | Nitride semiconductor light-emitting diode element |
| US8765510B2 (en) | 2009-01-09 | 2014-07-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor diodes fabricated by aspect ratio trapping with coalesced films |
| US8822248B2 (en) | 2008-06-03 | 2014-09-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Epitaxial growth of crystalline material |
| WO2014140082A1 (en) | 2013-03-13 | 2014-09-18 | Pilegrowth Tech S.R.L. | High efficiency solar cells on silicon substrates |
| US8847279B2 (en) | 2006-09-07 | 2014-09-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Defect reduction using aspect ratio trapping |
| US8878243B2 (en) | 2006-03-24 | 2014-11-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures and related methods for device fabrication |
| US8981427B2 (en) | 2008-07-15 | 2015-03-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Polishing of small composite semiconductor materials |
| US9508890B2 (en) | 2007-04-09 | 2016-11-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Photovoltaics on silicon |
| US9859381B2 (en) | 2005-05-17 | 2018-01-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
| US9984872B2 (en) | 2008-09-19 | 2018-05-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fabrication and structures of crystalline material |
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| GB1417484A (en) * | 1972-01-10 | 1975-12-10 | Rca Corp | Semiconductor device and method of making the same |
| US3962716A (en) * | 1973-11-12 | 1976-06-08 | Bell Telephone Laboratories, Incorporated | Reduction of dislocations in multilayer structures of zinc-blend materials |
| WO1985003598A1 (en) * | 1984-02-02 | 1985-08-15 | Sri International | Integrated circuit having dislocation-free substrate |
| US4631234A (en) * | 1985-09-13 | 1986-12-23 | Texas Instruments Incorporated | Germanium hardened silicon substrate |
-
1988
- 1988-03-04 GB GB8805155A patent/GB2215514A/en not_active Withdrawn
Patent Citations (4)
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|---|---|---|---|---|
| GB1417484A (en) * | 1972-01-10 | 1975-12-10 | Rca Corp | Semiconductor device and method of making the same |
| US3962716A (en) * | 1973-11-12 | 1976-06-08 | Bell Telephone Laboratories, Incorporated | Reduction of dislocations in multilayer structures of zinc-blend materials |
| WO1985003598A1 (en) * | 1984-02-02 | 1985-08-15 | Sri International | Integrated circuit having dislocation-free substrate |
| US4631234A (en) * | 1985-09-13 | 1986-12-23 | Texas Instruments Incorporated | Germanium hardened silicon substrate |
Cited By (75)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0469790A1 (en) * | 1990-08-02 | 1992-02-05 | AT&T Corp. | Semiconductor devices with low dislocation defects and method for making same |
| US5158907A (en) * | 1990-08-02 | 1992-10-27 | At&T Bell Laboratories | Method for making semiconductor devices with low dislocation defects |
| US5285086A (en) * | 1990-08-02 | 1994-02-08 | At&T Bell Laboratories | Semiconductor devices with low dislocation defects |
| US5091767A (en) * | 1991-03-18 | 1992-02-25 | At&T Bell Laboratories | Article comprising a lattice-mismatched semiconductor heterostructure |
| EP0505093A2 (en) * | 1991-03-18 | 1992-09-23 | AT&T Corp. | Article comprising a lattice-mismatched semiconductor heterostructure |
| EP0505093A3 (en) * | 1991-03-18 | 1994-06-22 | At & T Corp | Article comprising a lattice-mismatched semiconductor heterostructure |
| FR2724487A1 (en) * | 1994-08-05 | 1996-03-15 | Daimler Benz Ag | COMPOSITE STRUCTURE WITH A SEMICONDUCTOR LAYER ARRANGED ON A DIAMOND LAYER AND / OR A DIAMOND-LIKE LAYER AND METHOD FOR THE PRODUCTION THEREOF |
| US5843224A (en) * | 1994-08-05 | 1998-12-01 | Daimler-Benz Aktiengesellschaft | Composite structure comprising a semiconductor layer arranged on a diamond or diamond-like layer and process for its production |
| US5859864A (en) * | 1996-10-28 | 1999-01-12 | Picolight Incorporated | Extended wavelength lasers having a restricted growth surface and graded lattice mismatch |
| US5877519A (en) * | 1997-03-26 | 1999-03-02 | Picolight Incoporated | Extended wavelength opto-electronic devices |
| JP2014112695A (en) * | 1998-07-31 | 2014-06-19 | Sharp Corp | Nitride semiconductor light-emitting diode element |
| WO2004023536A1 (en) * | 2002-09-03 | 2004-03-18 | University Of Warwick | Formation of lattice-tuning semiconductor substrates |
| US7179727B2 (en) | 2002-09-03 | 2007-02-20 | Advancesis Limited | Formation of lattice-tuning semiconductor substrates |
| CN100364052C (en) * | 2002-09-03 | 2008-01-23 | 阿德弗西斯有限公司 | Formation of lattice-tuned semiconductor substrates |
| US8324660B2 (en) | 2005-05-17 | 2012-12-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
| US9431243B2 (en) | 2005-05-17 | 2016-08-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
| US8987028B2 (en) | 2005-05-17 | 2015-03-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
| US9859381B2 (en) | 2005-05-17 | 2018-01-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
| US10522629B2 (en) | 2005-05-17 | 2019-12-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
| US8796734B2 (en) | 2005-05-17 | 2014-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
| US9219112B2 (en) | 2005-05-17 | 2015-12-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
| US8519436B2 (en) | 2005-05-17 | 2013-08-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
| US11251272B2 (en) | 2005-05-17 | 2022-02-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
| US8629477B2 (en) | 2005-05-17 | 2014-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
| US8878243B2 (en) | 2006-03-24 | 2014-11-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures and related methods for device fabrication |
| US10074536B2 (en) | 2006-03-24 | 2018-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures and related methods for device fabrication |
| US9818819B2 (en) | 2006-09-07 | 2017-11-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Defect reduction using aspect ratio trapping |
| US9318325B2 (en) | 2006-09-07 | 2016-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Defect reduction using aspect ratio trapping |
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