GB2175159A - Frequency dividers - Google Patents

Abstract

A frequency dividing arrangement comprises an injection-locked divider 2 arranged for receiving an incoming signal Fin and for providing a frequency divided signal Fout in response thereto, and a frequency divider 3 coupled to the injection-locked divider 2. The frequency divider 3 comprises logical circuits for providing a further frequency divided signal F''out in response to the frequency divided signal Fout provided by the injection-locked divider 2. The arrangement may be included in a frequency modulation receiver which comprises an FM detector 1. The injection-locked divider 2 comprises a multiplier 8, and a tuning circuit 10. <IMAGE>

Description

SPECIFICATION Frequency dividers This invention relates to frequency dividers, and in particular, to frequency dividers for use in frequency modulation (FM) receivers.

It is well known that before detection of an FM signal carried by an incoming radio frequency (RF) carrier wavetakes place, the RFsignal is fed through a frequency translation means, for example one or more mixing circuits, so that the radio frequency (RF) signal can be translated down to an intermediate frequency (IF) signal. The IF signal is then fed to an FM detectorwhich affords a voltage output which is proportional to the FM modulation signal carried by the carrier wave.

An alternative frequency translation means known to the applicants includes the use of a frequency divider which comprises logic circuit elements operative to frequency divide the RF signal by N,where N is an integer.

Such frequency dividers have the disadvantage that they are not well suited for use in FM detectors which are intended for fringe frequency modulation reception areas or space communication.

It is the intention of the present invention to provide a frequency divider arrangement which can operate at an improved speed so as to frequency divide signals of a relatively higherfrequency and, when coupled to an FM detector, can improve noise threshold of the FM detector.

According to the present invention there is provided a frequency dividing arrangementfor receiving an incoming signal and for providing a frequency divided signal in response thereto, and a frequency divider coupled to the injection-locked divider, which frequency divider comprises logical circuits for providing a furtherfrequency divided signal in response to the frequency divided signal provided by the injectionlocked divider.

The frequency dividing arrangement may be incorporated into a frequency modulation (FM) receiver for receiving an RF radio signal and for producing a signal indicative of the information content of the modulating wave ofthe radio signal. In this case, the furtherfrequency divided signal provided by the frequency divider is afforded to an FM detector.

FM receivers which incorporate frequency dividing arrangements according to the present invention are advantageous in that they can receive RF signals of a relatively higherfrequency, and their noise threshold is improved. Consequently, such receivers are eminently suitable for use in satellite broadcasting where FM receivers are frequently required to operate nearto the threshold at which frequency modulated signals can be detected over background noise.

The FM detector may comprise a phase sensitive detector arranged to receive thefurtherfrequency divider signal from a first path and a second path, which second path has a phase shift means located therein. The phase shift means is operative to shift the phase of the furtherfrequency divided signal from the second path relative to thefurtherfrequency divided signal from the first path in dependence upon its frequency so as to enable the phase sensitive detector to provide an output signal corresponding to the modulation carried by the incoming signal.

The frequency divider may be operative to frequency divide the frequency divided signal provided by the injection-locked divided by two.

Inthis case,thefrequency divider may be inthe form of a D-type bistable.

Coupling the injection-locked divider to the FM detector via a frequency divider has the additional advantage that mutual coupling between resonant circuits in the injection-locked divider and the FM detector is avoided.

The injection-locked divider preferably comprises a non-linearamplifying means, and a tuning circuit comprising a direct current blocking means, an alternating current coupling means and a resonance circuit, wherein the non-linear amplifying means is arranged to provide the frequency divided signal, via the direct current blocking means, in dependence upon the incoming signal and the frequency divided signal fed to a second input ofthe non-linear amplifying means via the direct current blocking means and the alternating current coupling means, and the resonance circuit couples a point between the direct current blocking means and the alternating current coupling means to ground.

The direct current blocking means and the alternating current coupling means may each comprise capacitors.

The resonance circuit may comprise an inductor connected in series with a capacitance.

The pointmayalso be coupled tothevirtual ground via a resistance means.

Such injection-locked dividers (ILD) are advantageous in that they have an improved injection-lock range, a relatively more symmetric injection range, and component values forthe ILD are more easily manufactured.

The injection-locked divider may be arranged to frequency divide the incoming signal by unity by changingthefrequencyofthetuning circuit to match the frequency of the incoming signal. In this case, the injection-locked divider acts as an injection-locked oscillator.

The invention will now befurtherdescribed byway of example with reference to the accompanying drawings, in which:~ Figure 1 is a schematic diagram of a frequency dividing arrangement embodying the present inven tion shown coupled to an FM detector; Figure 2 is a circuit diagram of a frequency divider of thefrequencydividing arrangement of Figure land Figure 3 is a circuit diagram of an injection-locked frequency divider of the frequency dividing arrange ment of Figure 1.

ReferringfirsttoFigurel,thereisshownan FM detector 1 which is suitableforuse in an FM receiver.

The FM detector 1 is preceded by a frequency dividing The claims were filed later than the filing date within the period prescribed by Rule 25(1) of the Patents Rules 1982.

arrangement embodying the present invention which comprises an injection-locked frequency divider 2 coupled with a frequency divider 3. In this arrange ment, the injection-locked frequency divider is con nected to the frequency divider3 via a coupling capacitorC1. In Figure 1,there is shown aterminal 6 provided for receiving a frequency modulated radio frequency (RF) signal FIN containing information embodied in the modulation thereof. The signal FIN is fed to a first input of a multiplier8 ofthe injectionlocked frequency divider 2 where it is mulitplied with a signal F'out received at a second input ofthe multiplier 8.

The injection-locked frequency divider also comprises a tuning circuit 10 which comprises a direct current (d.c.) blocking means in the form of a capacitor C2, an alternating current (a.c.) coupling means in the form of a capacitorC3, and a resonantcircuitwhich comprises a serially connected inductance L1 and capacitorC4in parallel with a resistorR1.

The injection-locked frequency divider is operative to frequency divide the signal FIN by two to provide a frequency divided signal Fout. A detailed description of the construction ofthe injection-locked oscillatorwill be given below with reference to Figure 3.

The frequency divided signal F0ur is fed via the coupling capacitor C1 to the frequency divider3 which, in this example, is inoperative to frequency dividethe frequency divided signal Fout by two to provide a furtherfrequency divided signal F"out at a terminal 12.

The frequency divider3 is described below in greater detail with referenceto Figure 2.

The frequency dividing arrangementfrequency divides the incoming signal FIN byfour, but may be arrangedto divide by higheror lower numbers according to requirements. Forexample,thefrequen cy ofthetuning circuit 10 could bechangedto match the frequencies ofthe signal FIN in which case the injection-locked frequency divider operates as an injection-locked oscillator with an effective division ratio of one.

The furtherfrequency divided signal F"out is fed from the terminal 1 to the FM detector 1 where it is demodulated. The signal F"out is fed to a phase sensitive detector 13 via a first path 14, and is fed to the phase sensitive detector via a second path 15. A phase shift means is located in the second path 15 and comprises a phase quadrature device consisting of a capacitor C5, and a capacitor C6 connected in parallel with a coil L2. The capacitor C6 and the coil L2 connect the second path 15 to earth thereby imposing a frequency delay on the signal F"out dependent upon its frequency.The capacitor C5 imposes a 903C phase shift on the signal F"0#ttransmitted by the second path 15. Hence, the phase sensitive detector 13 receives the furtherfrequency divided signal F"out over two sepa rate paths such thatthe signal F"out in one path varies in phase with respect of the other in depend enceuponthemodulation on the incoming signal FIN.

The phase sensitive detector 13 provides an output signal Fsig which is indicative ofthe frequency modulation content ofthe incoming signal FIN.

Referring nowto Figure 2, there is shown a detailed example of the frequency divider 3 which comprises logic circuit elements operative to frequency divide signals by 2. The frequency divider 3 is a D-type bistable and comprises a pair of latches L1 and L2. The latch L1 comprises a pairoftransistorsT1 andT2 and the latch L2 comprises a pair oftransistors T3 and T4.

The current is supplied to the latches L1 and L2 by a long tail paircomprising a pairoftransistorsT5andT6 and a current source C7. The incoming frequency divided signal Fout is fed via the terminal Vin to the transistor 75. The base of the transistorT6 is supplied with a reference voltage Vref.

Sensing gates T7, T8 and T9, T10 are operatively associated with the latches L1 and L2, respectively, and they are effective for sensing the state of the latch with which they are associated. That is to say, the sensing gate T7 and T8 senses the state ofthe latch L1 and is operative to set the state of the latch L1 into the latch L2, and the sensing gate T9 and T10 senses the state of the latch L2 (which state is the inverse of the state of the latch L1) and is operative to set the state of the latch L2 into the latch Ll. Each of the sensing gates T7, T8 and T9, T10 is supplied with currentfrom a pair of transistors Tl 1, Tl 2 and a current source C8.

The divider3 is opernti#eto provide the further frequency divided signal F"0##from the terminal 12.

Referring now to Figure 3, the injection-locked divider2will be described in detail.

The injection-locked divider comprises a current injection means 20 which comprises a transistorT20, and a means for providing direct currentwhich, in this case, consists of a constant current source 22 and a capacitor Clo. The base electrode ofthe transistorT20 receives the incoming signal FIN and the current injector provides a direct current to the emitter electrodes of a non-linear amplifying means or multiplier in dependence upon the incoming signal FIN.

The non-linear amplifying means comprises a long tail pair of transistors T23 and T24 connected as shown in Figure 3.

In this example,thetransistorsT23 and T24 are biased at a voltage determined by a potential divider consisting of resistors R2, R3, R4, R5, and a capacitors connected between a voltage rail Vac and an earth rail E.

The d.c. blocking means comprising the capacitor CZI through which the signal Foot is fed, is connected to the collector electrode of the transisitor 23, and the a.c.

coupling means, comprising the capacitor C8 is connected between the base ofthe transistorT24 and the resonance circuit. The frequency divided signal Fount is fed via the capacitor C3 to the second input of the multiplier 8, thereby providing the signal Founts A direct current (d.c.) biasing means in the form of a resistor R5 is provided for biasing the collector of the transistorT23. The biasing means may alternatively be in the form of a choke.

The resonance circuit comprises the inductor L1, the capacitor C4 and the resistor R1 as described earlier. As can be seen from Figure 3, the resonance circuit connects a point between the capacitors C2 and Csto ground, which may be virtual ground.

The resonance circuit and the capacitors C2 and C8 when incorporated into an injection-locked divider (ILD) as described above affords advantages in that the ILD has an improved injection-lock range, a more symmetric injection range, and componentvaluesare more easily manufactured, particularly in integrated circuit form, When a divider arrangement according to the present invention is implemented, it may be necessark to interface the injection-locked divider 2 to the frequency divider3 by a means in the form of an interface circuit (not shown) for providing correct direct current levels and output swing. A similar circuit may be required to interface the frequency divider3 and the FM detector 1. The construction of such interface circuits is a technique known to skilled men in the art of FM receivers.

Claims (11)

1. Afrequency dividing arrangement comprising an injection-locked divider arranged for receiving an incoming signal and for providing a frequency divided signal in response thereto, and a frequency divider coupled to the injection-locked divider, which frequently divider comprises logical circuits for providing a furtherfrequency divided signal in response to the frequency divided signal provided by the injectionlocked divider.

2. Afrequency dividing arrangement according to a claim 1, wherein the injection-locked divider comprises a non-linear amplifier means, and a tuning circuit comprising a direct current blocking means, an alternating current coupling means and a resonance circuit, wherein the non-linear amplifying means is arranged to provide the frequency divided signal, via the direct current blocking means, in dependence upon the incoming signal and the frequency divided signal fed to a second input ofthe non-linear amplifying meansvia the direct current blocking means and the alternating current coupling means, and the resonance circuit couples a point between the direct current blocking means and the alternating current coupling means to ground.

3. A frequency dividing arrangement according to claim 2, wherein the direct current blocking means and the alternating current coupling means each comprise capacitors.

4. Afrequency dividing arrangement according to claim 2 or claim 3, wherein the resonance circuit comprises an inductor connected in series with a capacitance.

5 Afrequency dividing arrangement according to any one of claims 2 to 4, wherein said point is coupled to the virtual ground via a resonance means.

6. Afrequency dividing arrangement according to any one of the preceding claims, wherein the frequency divider is operative to frequency divide the signal provided bytheinjection-lockeddividerbytwo.

7. Afrequency dividing arrangement according to any one of the preceding claims, wherein the frequency divider is in the form of a D-type bistable.

8. Afrequency modulation (FM) receiver for receiving an RF radio signal and for producing a signal indicative of the information content of the modulating wave of the radiosignal,the FM receivercompris ingafrequencydividing arrangement according to any ofthe preceding claims, wherein the further frequency divided signal provided by the frequency divider is afforded to an FM detector.

9. Afrequency modulation receiver according to claim 8, wherein the FM detector comprises a phase sensitive detectorarrangedto receive the further frequency divided signal from a first path and a second path, which second path has a phase shift means located therein, wherein the phase shift mean is operative to shift the phase ofthefurherfrequency divided signal from the second path relative to the further frequency divided signal from the first path in dependence upon its frequency so asto enable the phase sensitive detectorto provide an output signal corresponding to the modulation carried by the incoming signal.

10. Afrequency dividing arrangement substantial ly as described herein with reference to the accompanying drawings.

11. Afrequency modulation receiver substantially as described herein with reference to the accompanying drawings.