GB2150749A - Integrated circuits - Google Patents

Abstract

Discrete electrical through connections in a semiconductor wafer (1), which may include integrated circuit device components or which carries a separate element containing the integrated circuit device components, are comprised by apertures extending through the wafer and hermetically blocked by respective metallic members (9, 11). The metallic members (9, 11) are electrically isolated from the wafer (1), by e.g. electrically insulating material (2, 8) disposed therebetween or junction isolation, and extend towards both faces of the wafer where they may provide contact pads or conductive tracks. Anisotropic etching techniques from one or both faces of the wafer may be employed. Using the technique very high pin count (interconnection) densities may be achieved; this being particularly useful for VLSI devices. <IMAGE>

Description

SPECIFICATION Integrated circuits This invention relates to integrated circuits and in particular to interconnection and packaging methods therefor.

The increasing complexity of integrated circuits results in very high pin count requirements and some devices may also have very high power requirements. VLSI devices are envisaged in which single devices, up to 1 cm square silicon, have a pin count of 100 to 200 and a power dissipation of up to 10 watts, or alternatively large area devices, up to 4 cm square silicon, have a pin count of up to 1000 and a power dissipation of up to 100 watts.Packaging for such devices is unlikely to be achieved by extension of conventional packaging techniques, such as standard DIL packages used for low power VLSI devices, primarily because of yield limitations on bonding and feedthrough connections, but also due to thermal resistance problems, particu larly as a result of voids introduced when bonding large area chips to mounts therefor, such as by friction alloying. conventionally, chips may be mounted to a substrate, with interconnections to lead frame terminals made by wire bonding techniques and the chip thereafter encapsulated. Other known methods employ "flip chips", and tape bonding applied to chip carrier techniques, which introduce passivation problems and reduce chip power dissipation capabilities.

Various methods of producing electrical through connections in a semiconductor substrate are described in our co-pending Application No. 8305761 (Serial No. ) (T.M. Jackson 76). The present invention aims to provide alternative methods of achieving electrical through connections either in an integrated circuit itself or by way of a separate carrier onto which an integrated circuit chip may subsequently be bonded.

According to one aspect of the invention there is provided an integrated circuit package including a semiconductor wafer having a first surface at which integrated circuit device components are arranged, a second surface, and at least one discrete electrical connection extending through the wafer between the first and second surfaces, wherein each electrical connection includes an aperture extending through the wafer, there being a metallic member blockingly disposed in the aperture and extending towards both faces of the wafer, which metallic member is electrically isolated from the wafer at least in use of the package.

According to another aspect of the present invention there is provided a semiconductor wafer having a first surface, a second surface, and at least one discrete electrical connection extending therethrough between the first and second surfaces, wherein each electrical connection includes an aperture extending through the wafer, there being a metallic member blockingly disposed in the aperture and extending towards both faces of the wafer, which metallic member is electrically isolated from the wafer at least in use of the wafer.

According to a further aspect of the present invention there is provided a method of making at least one discrete electrical through connection in a semiconductor wafer between opposite surfaces thereof, including the steps of forming an aperture through the wafer for each through connection, forming a respective metallic member in each aperture which extends towards both surfaces of the wafer, is electrically isolated from the wafer at least in use of the wafer and serves to block the aperture.

Embodiments of the present invention will now be described with reference to the accompanying drawings, in which: Fig. 1 illustrates, somewhat schematically, a section through part of a silicon wafer after two processing stages; Fig. 2 illustrates the processed wafer of Fig.

1 after three further processing stages; Fig. 3 illustrates the processed wafer of Fig.

2 after two more processing stages; Fig. 4 illustrates the processed wafer of Fig.

3 after a further processing stage; Fig. 5 illustrates the processed wafer of Fig.

4 after three further processing stages; Fig. 6 illustrates the processed wafer of Fig.

5 after a metallisation definition processing stage: Fig. 7 shows a section through a portion of an integrated circuit package having electrical through connections in the integrated circuit itself; Fig. 8 shows a section through a portion of an integrated circuit package in which electrical through connections are provided in a carrier to which an integrated circuit chip is bonded; Figs. 9 and 10 illustrate, somewhat schematically, a perspective view and a plan view of parts of a silicon wafer after a modified processing sequence which permits higher interconnection density than the basic sequence of Figs. 1 to 6;; Figs. 11 to 16 illustrate various stages in another modified processing sequence which also permits higher interconnection density than the basic sequence of Figs. 1 to 6, and Fig. 17 illustrates the use of through connection metallisation in a silicon carrier together with orientation selective etching of the carrier and an integrated circuit chip.

Referring to Figs. 1 to 6 a process sequence for manufacturing electrically conductive through connections in a silicon wafer 1 will be described. The wafer 1 may, for example be of n-type or p-type and typically (100), orientation and initially 300 jim thick.

In a first processing stage an oxide (silicon dioxide) layer 2 is deposited or thermally grown on both sides 3 and 4 of wafer 1. Side 3 will be referred to as the rear face and side 4 as the front face. The oxide is removed from the rear face 3. The oxide layer may be of the order of 0.5 to 1 ym thick. Next silicon nitride 5 is deposited onto both faces of the wafer.

The nitride may be of the order of 500 3000A (50-300 nm) thick. The oxide 2 and the nitride 5 may be deposited, for example, by plasma deposition, thermally grown, deposited from the gas phase or sputter deposited.

An etch window 6 (Fig. 2) is defined through the nitride layer 5 on the rear face 3.

The standard techniques of photolithography or stencil masking may be used and the nitride may be etched by, for example, gas plasma or liquid etching.

A well 7 is then etched into the silicon of the wafer using an orientation selective (anisotropic) etch, such as one based on KOH, which results in a tapered well extending through the silicon to the oxide and nitride membrane comprised by layers 2 and 5 on the front face 4. This membrane acts as an etch stop. A typical KOH-based anisotropic etch bath composition comprises 170 i 50 cc isopropyl alcohol; 800 f 200 cc distilled water; 250 i 5b gm potassium hydroxide.

The bath may be continuously stirred by a nitrogen bubbler. At 56 i 2 C this will give an etch rate of 11.5 i 1 pm per hour.

Alternatively, catechol may be employed.

The nitride layer 5 on the rear face 3 is stripped using, for example, plasma etching techniques, for example C2F6, CF4 or SF6 RF gas plasmas. Plasma etching allows etching from one side only, thus the nitride on the front face 4 is retained whilst that on the rear face 3 is removed. The wafer is then oxidised (Fig. 3) in order to obtain an oxide layer (silicon dioxide) extending on the rear face 3 (oxide 2') and particularly on the walls of the etched wall (oxide 8). The oxide may be thermally grown, sputtered or plasma deposited, for example.

A metallisation layer 9 (Fig. 4) is deposited on the oxide layer on the rear face 3 to a thickness sufficient to give mechanical strength and good hermetic characteristics.

The layer 9 may, for example, be greater than 1,us. The metal may be aluminium, gold, nickel or alloys thereof, or any metal having good mechanical strength and acceptable electrical properties, for example low resistance. The metal may be deposited by, for example, chemical vapour deposition, sputtering, electron beam or filament evaporation. At this stage (that is after the metallisation layer 9 is provided) the nitride layer 5 on the front face 4 may (optionally) be removed, which additional step improves the adhesion between the wafer and metallisation subsequently deposited on the front face. Figs. 5 and 6 indicate processing in which the nitride on front face 4 has been removed.

A window 10 is opened in the oxide layer on the front face 4 in alignment with the metallised well (Fig. 5). This may be achieved by photolithographic or stencil masking techniques and any oxide and nitride etching technique which will not etch, or cause the formation of electrically insulating layers the metallisation layer 9, which is exposed at the front face 4 thereby. For example RF gas plasma etching of the nitride and oxide in C2F6. A metallisation layer 11 (Fig. 5) is then deposited on the front face 4 and in contact with layer 9 through window 10, thus providing a metallic conductor path through the wafer 1, which metallic path is insulated from the wafer by the isolating oxide 2, 2' and 8.

The metal layer 11 may be comprised of the same material as layer 9.

The metal layers 9 and 11 are then patterned as appropriate (Fig. 6) by, for example, etching through a stencil mask or by using photolithography. Thus an electrical through connection is comprised by an aperture etched through the wafer, the walls of the aperture being coated with silicon dioxide, and there being a metallic member blockingly disposed in the aperture and insulated from the remainder of the wafer by silicon dioxide.

The wafer with through connections as described above can be employed in two basic ways. Either the VLSI device components may be formed directly in the wafer in which the through connections are formed (Fig. 7) or the VLSI device components may be formed in a separate chip which is then bonded to a through-connected wafer (Fig. 8).

In the case of integral VLSI formation a VLSI device indicated generally at 40 (Fig. 7) is formed by conventional techniques in the front face 4 of wafer 1. The same reference numerals are used in Figs. 1 to 6, 7 and 8 for identical or corresponding elements. Interconnection between the VLSI device terminals and the metallic through connections provided at wells 7 is by way of metallic tracks 41, for example etched aluminium interconnections provided in a conventional manner. Such tracks 41 may be formed simultaneously with metallic layer 11. An hermetic package may simply be achieved by providing a continuous passivating layer 42 of, for example, silicon nitride over the entire front face 4 of the wafer. This construction requires no further packaging and can, for example, be directly mounted to a suitable circuit board. Soft soldering may be employed to electrically connect the through connections of the package to the circuitry of the board.

In the case of a separate chip for the VLSI device, as for example illustrated in Fig. 8, a semiconductor element or carrier 43 of silicon and with through connections such as 44 may be manufactured by the method described above with reference to Figs. 1 to 6. The oxide layer 2 is removed except where it is required for insulation (isolation) purposes such as adjacent wells 7. A thin glass bonding layer 45, such as Pyrex (RTM) glass, is deposited on the carrier 43 at positions which will subsequently be under a VLSI chip 46 and the edge of a cover 47. Then the chip 46 is diffusion bonded to the carrier 43 via glass layer 45 which comprises a glass which is conductive at the temperatures used for diffusion bonding, typically 200--400"C, which diffusion bonding process employs a high electric field, for example 500 volts.Diffusion bonding is particularly applicable to the mounting of VLSI chips of large area (padside-up) to silicon wafers since it is best suited for joining very flat surfaces and results in intimate contact of the elements to be joined, due to diffusion across the barrier therebetween, and the complete absence of voids therebetween. Subsequently to the bonding of the chip 46 to the carrier 43, wire bond connections, such as 48, are made between the metallisation layer 11 of the through connections 44 and a connection pad such as 49 on the chip 46. To seal the chip 46 the cover 47, for example of nickel iron alloy, is positioned to extend thereover and its flange 50 is diffusion bonded around its entire periphery to the carrier 43 via layer 45.This results in an hermetically sealed package which can then be employed without further processing, for example directly mounted on a suitable circuit board using soft soldering techniques to electrically connect the through connections of the package to the circuitry of the board.

The use of orientation selective etchants in the processing sequence described above with reference to Figs. 1 to 6 is such that the minimum window widths, and thus the interconnection density, is dependent on the wafer thickness. The thicker the wafer, the wider the window at the rear face and thus the smaller the number of interconnections that can be accommodated at the rear face. Thus any means by which the apparent wafer thickness can be reduced will consequently increase the interconnection density. Figs. 9 and 10 illustrate one such means. Instead of there being one metallic conduction path per well, there are a plurality, three or four being indicated in Fig. 8. A well, such as 12, is etched into the silicon as described above, its geometry being such that it extends, for example, a distance laterally along the wafer edge.In Fig. 10 two wells 12 are shown, there being a support strut 13 comprised by unetched silicon therebetween. After oxidation and metallisation of the rear face 14, as described with respect to Figs. 3 and 4, a plurality of windows 15.

rather than a single window 10, is opened from front face 16 in the oxide/nitride membrane of each well 12. In this procedure the nitride is not removed in order to provide support for subsequent conductor tracks 18.

On the front face 16 metallisation 17 is subsequently deposited and patterned as appropriate and as described above. The separation between the adjacent conductor tracks 18 on the lead-out side (rear face 14) is in this case determined by metallisation deposition and photolithographic limitations rather than orientation etch limitations. Using this approach, through connection channels, comprised by wells 12, carrying up to 200 connections per cm edge of the wafer are achievable. Reference numeral 19 indicates an optional interconnection between two tracks 18.

A further method by which the interconnection density may be increased involves double sided etching ana an embodiment of this will now be described with reference to Figs. 11 to 16. In this method 0.5-1#m of the oxidised silicon is left as a supportive member for the first applied layer of metallisation. The process sequence outlined below has the advantage of requiring no photolithographic stages within the etch wells. Both faces of a cleaned silicon wafer 21 are provided with a silicon nitride layer 22. Windows such as 23 (Fig. 11) are then opened, using photolithography and etching, in the nitride 22 on the rear face 24 of the wafer. Using an orientation selective etch, such as one based on KOH as described above, a well 25 (Fig. 12) is etched to extend substantially half-way through the wafer 21.The remaining nitride 22 on the rear face 24 is then stripped, by for example plasma etching and the exposed silicon is oxidised to provide an oxide layer 26, extending over the rear face 24 and into the wells such as 25, which is of the order of 0.5 ,um (5000 ) thick (t,). This oxide layer 26 may be provided by a thermal oxidation process or another process, for example chemical vapour deposition. Prior to the provision of oxide layer 26 the exposed silicon may, optionally, be p 4 doped in order to provide additional KOH etch resistance.

The nitride layer 22 on the front face 27 of the wafer is then provided with windows 28 therethrough (Fig. 13) using photolithographic and etching techniques. The windows 28 are aligned with the windows/wells of the rear face of the wafer. At this stage the oxide 26 on the rear face may be provided with a nitride layer (not shown) to act as an additional support for the oxide membrane at the base of the well 25. The silicon exposed by windows 28 is then etched, again using an orientation selective etch, such as one based on KOH, to provide wells 29 which extend to the oxide layer 26 at the base of the well 25.

The remaining nitride on the front face 27 is then stripped using, for example, plasma etching. The exposed silicon surface is then oxidised (Fig. 14) to provide an oxide layer 30 on the front face approximately twice as thick (t2) as layer 26 provided on the rear face, for example 1.0 #m (10000 A). During this oxidation the oxide layer on the rear face will increase in thickness to approximately 1.5 ym (15000 Â) (t, +t2). Metallisation 31 (Fig. 15) is subsequently deposited on the front face 27 as for example described with respect to the first embodiment (Fig. 4).The rear face 24 is then plasma etched for a time sufficient to remove oxide thickness t, (5000 A). This will expose the metallisation in the window provided by the wells 25 and 29 without the need for photolithography whilst leaving an oxide layer on the rear face 24, including the walls of wells such as 25, which is approximately t2 thick. The rear face is then metallised (32) and both metallisation layers are patterned as appropriate (Fig. 16) using photolithographic and etching techniques. Using such double sided etching techniques the through connections provided thereby occupy substantially the same area on both sides of the wafer, thus doubling the interconnection density. The method of increasing the interconnection density described above with respect to Figs. 9 and 10 can increase the density up to fifty times, for example.

For an embodiment with through connections described above with respect to Figs. 9 and 10 the VLSI device components may be considered as arranged at the front face 1 6 of wafer 1, that is on the other side to that shown in the plan view of Fig. 10, either in the form of a separate chip mounted to a carrier, or disposed in the wafer itself, in which case electrical contact regions of the VLSI integrated circuit are connected to respective through connections via respective electrically conductive members disposed on the front face. The rear face 14 is termed the lead-out side, and the front face is termed the connection side, of the wafer.

In the case of VLSI device components formed as a separate chip bonded to a silicon carrier in which the through connections are provided, alignment between integrated circuit metallisation pads and the through connections in the silicon carrier may be facilitated by orientation selective etching of both substrates. This is illustrated schematically in Fig.

17. An integrated circuit chip 34 having integrated circuit contact pads 35 on one side thereof is to be mounted "pad-side-down" in the manner of a "flip-chip" onto a silicon support/carrier 36 having through-connection metallisation such as 37, which extend through only part of the thickness of the carrier 36 since a large well 38 was previously formed in the carrier 36 to accommodate the chip 34. The well 38 was formed using an orientation selective etchant in order to have sloping surfaces such as 39 which mate with sloping surfaces of chip 34, which were also provided by use of the orientation selective etchant. Since orientation selective etching of silicon is capable of micrometre accuracy, so too will be the alignment accuracy of two mated (male and female) substrates.Permanent electrical connection between the contact pads 35 of the chip and the through connections 37 of the carrier 36 may be achieved by soft-soldering techniques.

The arrangement of Fig. 17 may be provided with a cover, for example corresponding to cover 47 and sealed to the carrier 36 by diffusion bonding techniques, in order to fully hermetically seal the integrated circuit chip 34. Alternatively a cover comprised by a silicon wafer anisotropically etched to produce a shape corresponding effectively to cover 47 may be diffusion bonded to hermetically seal the arrangement of Fig. 17 or employed in place of a metallic cover 47 in Fig. 8.

With regard to the bonding techniques employed between the various elements, the connections between a chip on a carrier and a through connection, such as wires 48 in Fig.

8, may be achieved by any suitable integrated circuit bonding technique, for example ultrasonic welding. In order to mount a package as illustrated in Figs. 7 or 8, for example, to a circuit board the use of soft soldering has already been suggested above. Since aluminium metallisation does not facilitate soldering, it may alternatively be replaced by any suitable metallisation which is metallurgically and process compatible with integrated circuit and printed circuit board metallisations. Alternatively aluminium metallisation may be treated to render it soft solderable, for example copper may be deposited, by evaporation, over the aluminium. Such a copper layer may extend onto a clear silicon area as that soldering may be carried out in an area without any aluminium directly underneath it.

The metallised through connections described above are electrically isolated from the wafer in which they are provided by oxide layers, such as 2 and 8 or 26 and 30, and hermetically seal the well apertures etched into the wafer, whereas oxide isolation has been described, junction isolation is alternatively possible, albeit not recommended for packages which in use are required not to fail in a neutron radiation environment.

Whereas generally the contact pads of integrated circuits are provided around the edges of the chips due to wire bond connection requirements, the use of through connections either in the chip wafer itself or a silicon carrier employed with a "pad side down" chip (flip chip) means that the contact pads do not have to be disposed around the perimeter of the integrated circuit, and some can alternatively be disposed, for example, centrally thereof.

It is not necessary that the position of the through connections at the rear face of a chip or carrier corresponds to the lands of the printed circuit board to which they are to be electrically connected, since by having metallisation tracks and contact pads on the rear face which are connected to the through connections where they emerge on the rear face, which pads correspond in position to the lands of the circuit board, the increased through connection separation achievable by use of the whole of the available rear surface rather than just the portions thereof to which the through connections extend may be used to advantage and may even facilitate layout of the printed circuit board lands. The lands and the contact pads may be soft soldered together with the use of solder balls which serve also to ensure spacing between the package and the printed circuit board.

For thermal dissipation purposes the wafer, in the case where the VLSI device components are formed directly therein, or the carrier for a VLSI chip, may be provided with channels etched in the surface thereof which is opposite that carrying the device components. Silicon has remarkably good thermal properties, approximately one third the thermal conductivity of copper. Channels, particu larly if etched by means of anisotropic etching techniques, can increase the surface area available for thermal dissipation purposes.

Such channels may be closed, by a member bonded to the surface into which they extend, in order to facilitate forced cooling by water or air circulated through the channels.

The use of the orientation selective (anisotropic) etching techniques as described above should enable the provision of 10 micrometre wide windows in a silicon substrate. Using the techniques described structures having high (approximately 200 per cm edge length) interconnection density (the number of through connections per linear edge of an integrated circuit), hermeticity and improved thermal dissipation may be fabricated.

Methods other than the anisotropic etching techniques described above may be used to form the wells, which methods should be sufficiently controllable to ensure that, for example, adjoining wells do not become connected and that required well depths can be reliably achieved. Basically the well formation technique should be such that it gives an intact membrane at the well bottom and a well profile which can be metallised. For example, it is considered that laser drilling may be employable.

Claims (30)

1. An integrated circuit package, including a semiconductor wafer having a first surface at which integrated circuit device components are arranged, a second surface, and at least one discrete electrical connection extending through the wafer between the first and second surfaces, wherein each electrical connection includes an aperture extending through the wafer, there being a metallic member blockingly disposed in the aperture and extending towards both faces of the wafer, which metallic member is electrically isolated from the wafer at least in use of the package.

2. An integrated circuit package as claimed in claim 1, wherein the metallic member is electrically isolated from the wafer by electrically insulating material disposed therebetween.

3. An integrated circuit package as claimed in claim 1 or claim 2, wherein the integrated circuit components are formed in the wafer and have electrical contact regions accessible at the first surface.

4. An integrated circuit package as claimed in claim 3, wherein at least one electrical contact region is connected to a respective discrete electrical termination via a respective electrically conductive member disposed on the first surface.

5. An integrated circuit package as claimed in claim 3 or claim 4, wherein the first surface is covered by a passivating layer.

6. An integrated circuit package as claimed in claim 1 or claim 2, wherein the integrated circuit device components are formed in a separate semiconductor element, which element is mounted at the first surface of the wafer.

7. An integrated circuit package as claimed in claim 6, wherein the integrated circuit has electrical contact regions at one surface of the separate semiconductor element, which one surface is disposed facing the first surface of the wafer.

8. An integrated circuit package as claimed in any one of claims 5 to 7, including a cover bonded to the first surface and encapsulating the semiconductor element and any electrical connections at the first surface between the semiconductor element and the discrete electrical connections.

9. An integrated circuit package as claimed in any one of the preceding claims and including cooling channels extending into the semiconductor wafer from the second surface.

10. An integrated circuit package as claimed in claim 2 or any one of claims 3 to 7 a appendent to claim 2, wherein the semiconductor wafer is of silicon and the electrically insulating material includes silicon dioxide.

11. An integrated circuit package as claimed in any one of the preceding claims, wherein the metallic member is of aluminium.

12. A semiconductor wafer having a first surface, a second surface, and at least one discrete electrical connection extending therethrough between the first and second surfaces, wherein each electrical connection includes an aperture extending through the wafer, there being a metallic member blockingly disposed in the aperture and extending towards both faces of the wafer, which metallic member is electrically isolated from the wafer at least in use of the wafer.

13. A semiconductor wafer as claimed in claim 12, wherein the metallic member is electrically isolated from the wafer by electrically insulating material disposed therebetween.

14. A semiconductor wafer as claimed in claim 13 and comprised of silicon, the electrically insulating material including silicon dioxide.

1 5. A semiconcuctor wafer as claimed in claim 12 to 14, wherein the metallic member is of aluminium.

16. A method of making at least one discrete electrical through connection in a semiconductor wafer between opposite surfaces thereof, including the steps of forming an aperture through the wafer for each through connection, forming a respective metallic member in each aperture which extends towards both surfaces of the wafer, is electrically isolated from the wafer at least in use of the wafer and serves to block the aperture.

1 7. A method as claimed in claim 16, wherein the or each metallic member is electrically isolated from the wafer by electrically insulating material disposed therebetween.

18. A method as claimed in claim 16 or claim 17, wherein the wafer is of silicon and the or each aperture in the wafer is formed by anisotropic etching techniques.

19. A method as claimed in claim 18, wherein the wafer is etched from one surface thereof.

20. A method as claimed in claim 19 as appendant to claim 17, including the steps of masking the one surface to define an etch window thereat; providing an etch stop layer at the other surface; orientation selectively etching the wafer through the etch window up to the etch stop layer whereby to etch the aperture; removing the masking from the one surface and oxidising the wafer whereby to provide an electrically insulating layer of silicon dioxide at least on the walls of the etched aperture; depositing metal into the oxidised aperture whereby to at least coat the etch stop layer; opening a window in the etch stop layer in alignment with the aperture whereby to expose the deposited metal at the other surface and depositing further metal on electrically insulating material on the other surface and in contact with the first deposited metal.

21. A method as claimed in claim 19 as appendant to claim 17, including the steps of masking the one surface to define an elongate etch window thereat; providing an etch stop layer of electrically insulating material at the other surface; orientation selectively etching the wafer through the elongate etch window up to the etch stop layer whereby to etch a well; removing the masking from the one surface and oxidising the wafer whereby to provide an electrically insulating layer of silicon dioxide at least on the walls of the etched well and adjoining portions of the one surface of the wafer: depositing a layer of metal on the one surface to extend over the silicon dioxide layer and into the well; opening two or more spaced apart windows in the etch stop layer whereby to expose the deposited metal, each of which windows comprises one said aperture; depositing further metal on the etch stop layer and in contact with the first deposited metal through the windows in the etch stop layer and patterning the first metal and the further metal whereby to define conductor tracks on both surfaces, pairs of said conductor tracks, which pairs are comprised by a conductor track on each surface, being connected via metal blocking the corresponding aperture.

22. A method as claimed in claim 18, wherein the wafer is etched from both surfaces thereof,

23. A method as claimed in claim 22.

including the steps of masking one surface whereby to define a first etch window thereat; orientation selectively etching partially through the wafer through the first etch window whereby to define a first well; removing the masking from the one surface and oxidising the wafer whereby to provide an electrically insulating layer of silicon dioxide at least on the walls and base of the first well; masking the other surface whereby to define a second etch window thereat in alignment with the first well: orientation selectively etching the wafer through the second etch window up to the layer of silicon dioxide at the base of the first well, which comprises an etch stop, whereby to define a second well in alignment with the first well; removing the masking from the other surface and oxidising the wafer whereby to oxidise exposed silicon of at least on the walls of the second well and to increase the thickness of the oxide on the walls but not the base of the first well; depositing metal into the oxidised second well whereby to at least coat the etch stop; plasma etching the oxide on the one surface for a time sufficient to remove the oxide comprising the etch stop, and depositing further metal into the first well to be in contact with the first deposited metal in the second well and to block the aperture defined by the first and second wells.

24. An integrated circuit packaging method, including the steps of providing integrated circuit device components at a first surface of a semiconductor wafer and providing at least one discrete electrical connection extending through the wafer between the first surface and a second surface thereof by a method as claimed in any one of claims 16 to 30.

25. A method as claimed in claim 24, wherein integrated circuit device components are disposed in a separate semiconductor element, and including the step of mounting the element to the first surface of the semiconductor wafer.

26. A method as claimed in claim 25, including the step of orientation selectively etching the element, whereby to slope the peripheral surfaces thereof; orientation selectively etching a further well in the semiconductor wafer from the first surface thereof, which further well is of comparable dimensions to the etched element whereby the element can be matingly inserted therein, the discrete electrical connections extending through the wafer from the base of the further etched well to the second surface and inserting the etched element into the further well, with the discrete electrical connections in alignment with contact pads for the integrated circuit device on the element.

27. An integrated circuit package substantially as herein described with reference to and as illustrated in Figs. 1 to 6, Fig.7, Fig.8, Figs. 9 and 10, Figs. 11 to 16 or Fig. 17 of the accompanying drawings.

28. A method of making discrete electrical through connections in a semiconductor wafer substantially as herein described with reference to Figs. 1 to 6, Figs. 9 and 10, or Figs.

11 to 16 of the accompanying drawings.

29. A discrete electrical through connection in a semiconductor wafer made by a method as claimed in any one of claims 16 to 23 and 28.

30. An integrated circuit package made by a method as claimed in any one of claims 24 to 26.