GB2127246A

GB2127246A - A semiconductor memory

Info

Publication number: GB2127246A
Application number: GB08317749A
Authority: GB
Inventors: Yasunori Yamaguchi
Original assignee: Hitachi Ltd
Current assignee: Hitachi Ltd
Priority date: 1982-09-10
Filing date: 1983-06-30
Publication date: 1984-04-04
Also published as: GB8317749D0; IT8322792A1; IT1167386B; GB2127246B; KR840005884A; JPS5948889A; IT8322792A0; FR2533061A1; DE3332481A1

Abstract

A memory, such as a dynamic random access memory, has a control circuit (CSG) for controlling the operation start timing of the sense amplifiers so as to make the sense amplifiers start operating at mutually different timings. According to this construction the plurality of sense amplifiers do not start operating simultaneously and consequently, the potential change of a semiconductor substrate can be minimized and the erroneous operation of the dynamic random access memory can be reduced. The sense amplifiers start operating sequentially in the order starting from those which are positioned close to the address decoder circuit to those which are spaced apart from the address decoder circuit. Hence, the operation timing of the address decoder circuit can be set easily. Application of the invention to ROMs and other types of RAM is envisaged. <IMAGE>

Description

SPECIFICATION A semiconductor memory The present invention relates to a semi-conductor memory.

A dynamic random access memory consisting of a plurality of insulated gatefieldeffecttransistors (hereinafter referred to as "MOSFETs"), such as illustrated in Figure 1 ofthe accompanying drawings), has previously been proposed.

In the dynamic random access memory shown in Figure 1,the memory cell array M-ARY consists of a plurality of memory cells each consisting of a data storage capacitor C5 and an address selection MOS FET Gm and arranged in matrix, a plurality of complementary data line pairs D, D and a plurality of word lines W.

The memory cell array M-ARY also includes dummy cells DMC that are arranged atthe points of intersection between dummy word lines and the complementary date line pairs so asto generate a reference voltage for detecting a read signal from the memory cells. Each ofthe dummy cells DMCs is produced under the same production condition and with the same design constants as those of the memorycellsexceptthatthecapacitanceofthe capacitor is about a half of that of the capacitor C5 of the memory cell.

Accordingly, when the memory cells connected to one ofthe data lines D (D) are selected, the dummy cells connected to the other data lineW(D) are simultaneously selected. The read signal level from the memory cells and the reference voltage from the dummy cells is transmitted to sense amplifiers SA and amplified by these amplifiers.

Each sense amplifier SA consists of a pair of MOSFETs Q1 and 02 which are cross-connected with each other and the positive feedback operation of these transistors differentially amplifier a weak signal.

This positive feedback operation is initiated simultaneouslywhen a MOSFET Qa which is arranged in common with the sense amplifiers ofthe other data line, is rendered conductive by a sense amplifier control signal ~pa On the basis ofthe potential difference between the read signal level from the memory cells and the reference voltage from the dummy cel Is that is given atthe time of addressing, the potential ofthe data line having a higher potential falls at a lower speed and the potential of the data line having a lower potential falls at a higher speed due to the positive feed-back operation whilst the potential difference is being increased.The positive feedback operation finishes when the potential of the data line having a lower potential falls belowthethreshold voltage of the MOSFETs, so thatthe potential of the data line having a higher potential remains at a predetermined high level whereas the potential of the data line having a lower potential finally reaches zero volts. (0 volts).

Amongst the read signals ofthe complementary data line pairs D, D thus amplified, only those which are selected by a column switch C are transmitted to the common data line pairs CD, CD and are producedthrougha main amplifier MA and a data output buffer DOB.

The circuit shown in Figure 1, also includes a decoder circuit RC-DCR which forms selection signals fortheword lines and data lines in accordance with the address signals from an address bufferADB.

As a result of experimentation, we have found that when the sense amplifiers ofthe above kind are employed, the following problems occur.

When an address strobe signal RAS changes to a low level as shown in the waveform diagram of Figure 2 of the accompanying drawings, each circuitforthe word line selecting operation starts operating. This operating current causes a voltage drop in a power feed line so that the earth potential V55 and a power circuit Vcc change.

Next, the potential Vw of the selected word line rises as the potential of the word line selection timing signal ~x rises. The word line has wiring resistance and parasitic capacitance. Forthis reason, when the potential of the word line rises, its rise is rapid in the proximity ofthe decoder circuit CR-DCR as repre sented by solid line but is slowatthe portions spaced apartfromthedecodercircuitasrepresented bythe chain line. Accordingly, the potential ofthesense amplifier control signal ~pa rises after the memory cells connected to the remote portion oftheword line are selected.

As the potential of the sense amplifier control signal ~pa is thus raised, the sense amplifiers connected to the complementary data line pairs D, D altogether start the above referred to positivefeedbackopera- tion, so thatthe potential VBB of the semiconductor substrate is reduced by the capacitance coupling with the data lines.

As a result, the reference voltage Vref produced by the voltage division ofthe voltages Vcc and V55 changes to the low level side bythe capacitance coupling with the semiconductor substrate. This reference voltage Vref is used for determining the input signal levels of the address bufferADB and the data input buffer DIB. Accordingly, the address bufferADB and the data input buffer DIB carry out such an operation that would induce misjudgement of high level, although the external address signals YA and the write data signal Din are at a low level.

The timing ofthe potential change ofthe sense amplifier control signal ~pa coincides sub-substantial- lywith the timing at which the CAS system (data line) address signals, that is, the column address signal VA, are taken into the address buffer ADB, as the address strobe signal CAS is atthe low level. For this reason, there is a high likelihood thatthe erroneous operation described above will occur.

In addition, it is necessary to generate the word line selection timing signal ~x in synchronism with the selection timing ofthe memory cells connected to the remote portions of the word line with respect to the decoder circuit CR-DCR. Hence, timing control is difficult to practise. Relatively great variance in production existsforthe wiring resistance and parasitic capacitance of the word line so that variance also occurs in the selection timing of the memory cells at the remote portions of the word line.

Accordingly, a sufficient margin is generally secured for a time delay Td from the occurrence of the word line selection timing signal ~x u until the occurr- ence of the sense amplifier control signal ~paar in view of the variance described above. The read operation s, the memories becomes slow due to this time delay.

Another problem is that since the delay time Td must be set relatively great, the number of circuit elements such as inverters forforming the delay circuit increases and the power consumption is substantially increased.

It is an object of the present invention to eliminate the problems referred to above.

According to the present invention there is provided a semiconductor memory including: (a) a memory array comprising: ; (i) a plurality of memory cells, each having a selection terminal and an outputterminal and arranged in matrix; (ii) a plurality of word lines, each provided for each row of said memory cells and having said selection terminals of said plurality of memory cells connected thereto; and (iii) a plurality of data lines, each provided for each column of said memory cells and having said output terminals of said plurality of memory cells connected thereto; (b) a selection circuit having a plurality of output terminals each connected to one end each of said word lines and forming a selection signal for selecting one memory cell rowfrom amongst a plurality of memory cell rows; (c) a plurality of sense amplifiers each provided for each of said memory cell columns and having input-putputterminals having said data linesforsaid memory cell columns connected thereto and control terminals; and (d) control means for applying control signals to the control terminals of said sense amplifiers so that the operation of said sense amplifiers is started atvarying times from one another.

The present invention will now be described in greater detail by way of example with reference to the remaining Figures ofthe accompanying drawings, wherein: Figure 3A is a circuit diagram ofthe dynamic random access memory in accordance with a preferred embodiment; Figure 3B is a waveform diagram for explaining the address set operation of the dynamic random access memory of Figure 3A; Figure 4 is a circuit diagram of the memory cell array M-ARYand sense amplifiers SAshown in Figure 3A; Figure 5 is a waveform diagram for explaining the operation of the memory cell array M-ARY and sense amplifiers SA shown in Figure4; and Figure 6 is a perspective sectional view showing one example ofthe memory cell element structure.

Referring to Figure 3, the semiconductor memory employs a so-called two-mat system, and utilizes about64-Kbit memory cells as a whole. Each of the memory cell matrices(memorycellarraysM-ARY1, M-ARY2) has memory cells arranged in 128 (row) by 256 (column) and a memory capacity of 32,768 bits (32 Kbit). The principal circuit blocks in the drawing are shown in conformity with the geometric arrangement in a practical semiconductor integrated circuit (hereinaftercalledmerely"lC").

128 decoded output signals, that are obtained by decoding external row address signals A0 to A5, are applied by row decorders (which also serve as word line drivers) R-DCR1, R-DCR2 to the row address selection lines of each memory cell array M-ARY1, M-ARY2.

Acolumn decoderC-DCR decodes external column (data line) address signals Ag to A15 and produces 128 decoded output signals. Each of these column selection decoded outputsignalsiscommonforfour columns, i.e. columns of the right and left memory arrays and adjacent upper and lower columns inside each memory array.

The external address signals A7 and A8 are used to select any one ofthesefour columns. In other words, these external address signals A7, A8 are applied to a signal generator ~y-SG. The signal generator #yirSG decodes the external address signals A7, A8 and forms four column selection signals ~yOO, ~yOl and ~y1 1 Column switch selectors CSW-S1, CSW-S2 select one column out of the four columns selected bythe external address signals Agto A15, on the basis of the column selection signals #yO0 #yO1 ~y10 ~y11- As described above, the decoder for selecting the columns of the memory cell arrays is divided into two stages, i.e. the column decoder C-DCR and the column switch selectors CSW-S1 and CSW-S2. The decoder is divided into the two stages forthe following reasons.

First, any wasteful space must be eliminated inside an IC chip. In otherwords, the distance of arrangement (pitch) of an NOR gate having a relatively large area for supporting a pair of right and left output signal lines of the column decoder C-DCR in the longitudinal direction must be brought into conformity with the column arrangement pitch of the memory cells.

If the decoder is divided into the two stages, the numberof MOSFETsforming the NOR gate can be reducedandtheirarea of occupation can also be reduced.

The second reason is that the load upon one address signal line is mitigated and the switching speed ofthe address signal is increased by reducing the number of NOR gates to be connected to one address signal line.

The address bufferADB fabricates eight each external address signals A0 to A7 and A5to A15, that are multiplexed, into eight kinds each of complementary address signals (aO, aO) to (a7,a7) and (as.# to (a15, a,5) and applies them to the decoder circuit in synchronism with the timing signal apart ~acin conformity with the circuit operation inside the IC chip.

The circuit also includes a control signal generator CSG which receives the address strobe signals RAS, CAS and write enable signalsWE and forms the various signals described above and various signals to be later described.

The circuit operation of the address setting process in the dynamic random access memory described above will now be explained with reference to the waveform diagram of Figure 3B.

First, the control signal generator CSG raises the address buffer control signal ~ratothe to the high level in accordance with the change of the address strobe signal RAS of the row system to the low level. In this instance, seven kinds of complementary pair address signals (aO, aO) the (as, as) are applied from the address bufferADB to the row decoders R-DCR1, R-DCR2 via the row address line R-ADL.

Next, the word line selection timing signal ~x is raised to the high level, so that the row decoders R-DCR1, R-DCR2 become active and one each word line is selected from a plurality of word lines of each memory cell array, M-ARV1, M-ARY2 and is raised to the high level.

In accordance with the change of the address strobe signal CAS to the low level, the control signal generator CSG raises the address buffer control signal ###ofthe column system to the high level, so that seven kinds of complementary pair address signals (a. aS) to (a15,#a15) corresponding to the external column address signals Ag to A15 are applied to the column decoder C-DCR from the address bufferADB via the column address line C-ADL.

As a result, the potential of the output signal line of one pair among 128 pairs of output lines of the column decoderC-DCR becomes the high level. The high level signal is applied to the column switch selectors CSW-S1, CSW-S2through this pair of output signal lines.

The column switch selecting timing signal ~y is then raised to the high level, so that the signal generation circuit ~yij-SG becomes operative.

On the other hand, the complementary pair address signals (a7, a7) corresponding to the external address signal A7 have been applied to the signal generation circuit ####-SG when the address buffer control signal ~ar becomes the high level, and the complementary pair address signals (a8, a8) corresponding to the external address signals A8, when the address buffer control signal ~aC becomes the high level.

When the column switch selection timing signal ~y is raised to the high level, therefore, the signal generation circuit ~y"-SG delivers the column selection signals substantially simultaneously to the column switch selectors CSW-S1, CSW-S2.

In other words, the signal generation circuit~yq-SG raises the potential of one column selection signal to the high level in accordance with the external address signals A7, A8 in synchronism with the column switch selection timing signal ~y.

In the column switch selectors CSW-S1, CSW-S2, four MOSFETs, whose gates are connected to a pair of output lines whose potential is raised to the high level among 128 pairs of output signal lines of the column decoder C-DCR, are turned on. The column selection signal of the high level is applied to the column switch C-SWa or C-SW2through one of these four MOSFETs.

In this manner, among the total of 512 MOSFET pairs in the column switches C-SW1,C-SW2, one pair of MOSFETs are selected and turned on, so that one pair of complementary data lines D, Din the memory cell array are connected to the common data line pair CD, CD.

Figure 4 shows an example ofthe memory cell array M-ARY and sense amplifiers SA. In the same way as described above, the memory cell array M-ARY consists of a plurality of memory cells MC arranged in a matrix and each consisting of a data storage capacitor C5 and an address selecting MOSFETs Gm, complementary data line pairs D, Dandword lines W.

Dummy cells DMS that form a reference voltage for detecting the read signals from the memory cells are located atthe points of intersection between dummy word lines and the complementary data line pairs described above. Each dummy cell is produced under the same production condition and with the same design constants as those of the memory cell MC except that the capacitance ofthe capacitor is substantially one half of the capacitance of the capacitor C5 of the memory cell.

When the memory cells connected to one of the data lines D,D) are selected, the dummy cells connected to the other data lines#D, (D) are simultaneously selected. Accordingly, the read signal level from the memory cells and the reference voltage from the dummy cel Is are transmitted to the sense amplifiers SA and are amplified by the amplifiers.

Each sense amplifier SA consists of a pair of cross-wired MOSFETs Q1 and Q2 and their positive feedback operation differentially amplifiers a weak signal.

In this embodiment, the sources ofthe MOSFETs Q1, O2 forming each sense amplifier are connected in common and a MOSFET Q10 for receiving the sense amplifier control signal ~pa is arranged atthe com- mon source. A similar MOSFET Q is likewise arranged atthe MOSFETs Q3, 04 forming the other sense amplifier. In the same way, a MOSFETfor receiving the sense amplifier control signal ~pa is arranged for each sense amplifier.

Wiring for applying the sense amplifiercontrol signal ~pa to the gates of the MOSFETs Olo, Q11 has the same construction as that of the word lines. When the word line is composed of an electrically conductive polysilicone layerformed integ rally with the gate electrode ofthe address selecting MOSFETofthe memory cell, for example, the gate electrodes of the MOSFETs Oleo, Qll and the common wiring for them are integrally formed by the electrically conductive polysilicone layer.

Incidentally, the positive feedback operation is started simultaneously when these MOSFETs Qic, Qii are rendered conductive by the sense amplifier control signal ###. At the time of addressing, that is, when the memory cells and the dummy cells corres pondingtothe memorycells are selected, the potential of the data line having a higher potential falls at a lower speed and the potential of the other data line having a lower potential falls at a higher speed due to the potential difference between the pair of data lines, whilst increasing the potential difference between them. The positive feedback operation finishes when the potential of the data line having a lower potential falls below the threshold voltage ofthe MOSFET, so that the potential ofthe data line having a higher potential remains at a predetermined high level while the potential of the data line having a low potential finally reaches zero volts.

Among the read signals ofthe complementary data lines D, Dthus amplified, onlythosewhich are selected by the column switch C-SW are transmitted to the common data lines CD, CD and are produced through the main amplifier MA and the data output buffer DOB.

Acontrol signal generatorCSG receives the address strobe signals RAS, CAS and the write enable signal WE and generates control signals ~pa/ ~x, ~rs and ~ar Referring to Figure 6, the structure of the memory call comprises a P-type semiconductor substrate 1, a relatively thick insulation film 2 (hereinafter referred to as the "field insulation film"); N±type semiconductor regions 4 and 5; a first conductivity type conductive polysilicone layer 6; an N-type surface inversion layer 7; a second conductivity type conductive polysilicone layer 8; a phosphosilicate glass (PSG) layer9; and an aluminium layer 10.The substrate, source region, drain region, gate insulation film and gate electrode of the address selecting MOSFET Qm are constructed by the above-mentioned P-type semiconductor substrate 1, N±type semiconductor region 4, N±type semiconductor region 5, gate insulation film 3 and second conductivity type polysilicone layer 8, respectively.

The second conductivity type conductive polysilicone layer 8 is used as the word line. The aluminium layer 10 connected to the N±type semiconductor region 5 is used as the complementary data line D or D.

One of the electrode, dielectic layer and the other electrode of the data storage capacitor C5 in the memory cell are formed by the first conductivity type conductive polysilicone layer 6, gate insulation film 3 and N-type surface inversion layer7 described above, respectively. In other words, since the power source voltage Vcc is applied to the first conductivity type conductive polysilicone layer 6, this voltage Vcc induces the N-type inversion layer 7 on the surface of the P-type semiconductor substrate 1 via the gate insulation film 3.

The gate insulation films, gate electrodes and their common wiringsforthe MOSFETs Q0, Q11 arranged in the respective sense amplifiers are formed in the same way as the insulation film 3 and the second conductivitytypeconductive polysilicone layer8 described above. When a molybdenum-silicon (Mo Si) layer is formed on the surface ofthe insulation film 3 in orderto reduce the resistance of the word line, therefore, the same Mo-Si) layer is also formed on the gate electrodes of the MOSFETs Q,0, Q11 and on their common wirings.

In Figure 4, the semse amplifier control signal ### is applied from the same direction as that of the word line selection signal. In other words, the sense amplifiercontrolsignal ~pa is appliedfrom the same side as the row decoder (serving also as the word line divider) R-DCR.

A precharge circuit PC is provided for each complementary data line pair. This circuit receives the precharge pulse ~pc ###and applies the power source voltage VcctO the complementary data line pair in the same way as the MOSFETs Qua7, Q15which are shown in Figure 4. This pre-charge pulse ~pc reaches high level when the address strobe signal is raised to the high level, and turns on the MOSFETs Q17, 018 so as to letthem precharge the complementary data lines D1, D, .

Resetting MOSFETs 013to Qie are provided on the remote side of each word line with respect to the decoder circuit R-DCR. When the address strobe signal is raised to the high level, these MOSFETs are turned on and reset rapidlytheword lines from the selection state to the non-selection state. Asimilarresetting MOSFETQ12 is arranged on the signal line of the sense amplifier control signal ~pal because the MOSFETs Q10, Q11 must be rapidly turned off lest the on-state ofthese MOSFETs Q,0, 01 1 prevents the precharge operation of the precharge circuits PC.

Thetimingsignal #,5contrnlstheoperationofthe resetting MOSFETs.

The selection operation of the memory cell and the operation of the sense amplifiers will be explained with reference to the waveform diagram of Figure 5.

The potential Vwoftheword line, which is selected bythe rise of the potential of the word line selection timing signal ~x, rises. The word line has wiring resistance and parasitic capacitance. For this reason, whereas the potential of the selected word line rapidly rises in the proximity of the output terminal of the decoder circuit R-DCR as represented by the solid line in the waveform diagram, the potential at the remote portionofthewordlinewith respect to the decoder circuit D-DCR rises belatedly, as represented bythe dotted line.In other words, the potential of the word line in the proximity ofthe output terminal of the decodercircuitwhich is connected to the word line for transmitting the selections formed therein to the word line, changes in the manner represented bythe solid line in the waveform diagram whereas the potential of theword line remotefromtheoutputterminal changes in the manner shown bythe dotted line.

The sense amplifier control signal ~pa is raised in conformity with the selection operation of the memory cells arranged on the word line in the proximity of the decoder circuit R-DCR. In this case, the sense amplifiers in the proximity of the decoder circuit R-DCR starts the positive feedback operation since the sense amplifier control signal ~pa rapidly rises, as represented by the solid line in Figure 5. On the other hand, the sense amplifiers arranged atthe remote portions with respect to the decoder circuit R-DCR belatedly startthe positive feedback operation since the sense amplifier control signal ~pa rises belatedly, as represented bythe dotted line in Figure 5.

In this manner, the sense amplifiers start the positive feedback operation in accordance with the propagation delay time of the time signal ~pa on the sense amplifier control signal line (delay line), that is, in synchronism with the selection timing of the respective word lines, over a relatively long period of time T. In other words, the memory cells and the dummy cells are sequentially selected from those located in the proximity of the decoder circuit R-DCR to those located atthe remote portions and in accordance with the selection,the sense amplifiers also sequentially startthe positive feedback operation from the sense amplifier SA256 located in the proximity of the decoder circuit R-DCR to the sense amplifier SAl located at the remote portions.

This arrangement makes it possible to reduce the potential drop ofthe potential V85 ofthe semiconductor substrate due to the capacitance coupling between the semiconductor substrate and the data line. As a result, the level change of the reference voltage Vref can also be reduced, so thatthe erroneous operation can be eliminated at the time when the column address signals and the write data signal are taken into the address bufferADB and the data input buffer DIB.

The timing at which the sense amplifier control signal ~pa is to be generated may be matched with the memory cell selection timing in the proximity ofthe word line so thattiming control becomes simple.

When the word line and the signal line fortransmit ting the sense amplifier control signal ~pa are simultaneously formed bythe known semiconductor integrated circuit fabrication techniques, the resistance and parasitic capacitance of the word line are likely to change due to a variance in the manufacturing conditions and cause a similar change in the resistance and parasitic capacitance of the signal line. In other words, when the delay characteristics ofthe word line change due to variance of the manufacturing condition, the delay characteristics of the signal line likewise change. Hence, when the selection timing of the memory cells changes due to variance in the manufacturing condition, the operation timing ofthe sense amplifiers likewise changes.Thus, variance of the section timing of the word line is offset by variance ofthe operation timing ofthe sense amplifiers.

Furthermore, the delaytime Td ofthe sense amplifier control signal #,a with respect to the word line selection timing control signal ~x can be shortened, sothatthe construction ofthe delay circuit for forming the sense amplifier control signal ~pa can be simplified and its current consumption can also be reduced.

In a modified circuit arrangement, the MOSFETs Qic, Q11 may be replaced by MOSFETs having relatively small conductance characteristics and MOS FETs having relatively large conductance characteristics in the parallel arrangement so thatthe sense amplifier control signal ~pa is applied to the MOSFETs having relatively small conductance characteristics while the delayed signal of the sense amplifier control signal ~pa is applied to the MOSFETs having relatively large conductance characteristics. This arramgement can reduce the drop ofthe high level potential of the data line atthe start ofthe positive feedback operation of the sense amplifiers.

Atthe data corresponding to the high level stored in the memory cells are read and written repeatedly, they are likely to be read out as the data corresponding to the low level. To prevent such an erroneous operation, an active restore circuit may be provided on the complementary data line pair. Such an active restore circuit is described in detail in Japanese Patent Application No. 209397/1981 by Hiromi MATSUURA dated December 25th, 1981 entitled "Dynamic RAM Integrated Circuit Device". Hence, the explanation of the circuit is hereby omitted.

The construction of the memory array can be paired in a number of different ways.

Besides the dynamic random access memory, the present invention can be widely applied to semiconductor memories such as an RAM having sense amplifiers on data lines ROM (Read Only Memory), and so forth.

Claims

1. Asemiconductor memory including (a) a memory array comprising: (i) a plurality of memory cells, each having a selection terminal and an output terminal and arranged in matrix; (ii) a plurality of word lines, each provided for each row of said memory cells and having said selection terminals of said plurality of memory cells connected thereto; and (iii) a plurality of data lines, each provided for each column of said memory cells and having said output terminals of said plurality of memory cells connected thereto; (b) a selection circuit having a plurality of output terminals each connected to one end each of said word lines and forming a selection signal for selecting one memory cell row from amongst a plurality of memory cell rows; (c) a plurality of sense amplifiers each provided for each of said memory cells columns and having input-output terminals having said data linesforsaid memory cells columns connected thereto and control terminals; and (d) control means for applying control signals to the control terminals of said sense amplifiers so that the operation of said sense amplifiers is started at varying times from one another.

2. Asemiconductor memory according to Claim 1, wherein said control means sequentially produce the control signals to said sense amplifiers in the order starting from said sense amplifiers corresponding to the said memory cell columns positioned physically close to the output terminals of said selection circuit and then to said sense amplifiers corresponding to said memory cell columns physically spaced apart from the output terminals of said selection circuit so that the operation is started sequentially in the order starting from said sense amplifiers corresponding to said memory cell columns positioned physically close to the output terminals of said selection circuit to said sense amplifiers corresponding to said memory cell columns physically spaced apart from the output terminals of said selection circuit.

3. A semiconductor memory according to Claim 2, wherein said control means include a control circuit for generating a sense amplifier control signal and a delay circuit for receiving the sense amplifier control signal and producing control signals having mutually different delay times, and said delaycircuit produces sequentially the control signal to said sense amplifiers in the order starting from said sense amplifiers corresponding to said memory cell columns positioned physically close to said outputterminals of said selection circuit to said sense amplifiers corresponding to said memory cell columns physically space apartfrom said outputterminals of said selection circuit.

4. A semiconductor memory according to Claim 3, wherein said delay consists of a delay line having a plurality of outputterminals and formed in parallel with said word lines, and the sense amplifier control signal is applied to said delaylinefrom onesideon which said selection circuit is located, sothatthe control signals having mutually different delaytimes and to be applied to said sense amplifiers are taken out from said output terminals of said outputterminals of said delay line.

5. A semiconductor memory according to Claim 4, wherein the material of an electrically conductive layer forming said delay line is substantially the same as the material of an electrically conductive layer forming said word lines so that the delay time of said delay line is substantially equal to that of said word lines.

6. Asemiconductormemoryaccordingto Claim 4, wherein each of said sense amplification circuit which the corresponding data line is connected and the other of the input-output terminals to which a reference voltage is applied, and whose operation is controlled bythe control signal applied to the control terminal thereof, and when said control signal is applied to said control terminal, said differential amplification circuit starts a positive feedback operation so as to amplify the potential difference between the signal potential from said memory cell and the reference voltage.

7. A semiconductor memory according to Claim 6, wherein said differential amplification circuit consists of a first MOSFET having its gate electrode connected to one of the input-output terminals and its drain electrode connected to the other ofthe input-output terminals, a second MOSFET having its drain electrode connected to one ofthe input-output terminals and its gate electrode connected to the other ofthe input-outputterminals, and a variable impedance element having its control electrode connected to said control terminals and positioned between the junction of the source electrodes of said first and second MOSFETs and earth potential of the circuit.

8. A semiconductor memory according to Claim 7, wherein each of said memory cells consists of an address selecting MOSFET having its gate electrode connected to said word line and one of its input-output electrodes connected to said data line and a data storage capacitor connected to the other of the input-output electrodes of said address selecting MOSFET.

9. A semiconductor memory according to Claim 8, further including precharge elements for precharging said plurality of data lines and resetting MOSFETs arranged on said delay line, so that said variable impedance element of each of said sense amplifiers is brought into the high impedance state by said resetting MOSFETwhilst said data lines are being precharged.

10. Afolded bit line arrangementtype semiconductor memory including: (a) a memory array comprising: (i) apluralityeachofmemorycellsanddummy cells, each having a selection terminal and an inputoutput terminal; (ii) a plurality of word lines to which the selection terminals of said memory cells are connected; (iii) a piuralityofdummyword linestowhichthe selection terminals of said dummy cells are connected; and (iv) a plurality of complementary data line pairs to which the input-outputtermihals of said memory cells and said dummy cells are connected; (b) a selection circuit having a plurality of output terminals connected to one end each of said word lines and said dummy words line and forming selection signalsforselecting one of said plurality of word lines and one ofsaid dummy word lines corresponding to said word line to be selected; (c) a plurality of sense amplifiers, each having a pair ofinput-outputterminals connected to said com plementary data line pair and a control terminal, and amplifying the potential difference between the signal potential from said dummy cell; and (d) control meansforapplying control signals to the control terminals of said sense amplifiers so that said sense amplifiers start operating at mutually different times.

11. A semiconductor memory according to Claim 10, wherein said control means sequentially produce the control signals to said sense amplifiers in the order starting from said sense amplifiers connected to said complementary data line pairs positioned physically close to the outputterminals of said selection circuitto said sense amplifiers connected to said complementary data line pairs phsyically spaced apart from said output terminals, so that the operation of said sense amplifiers is started in the order starting from said sense amplifiers connected to said complementary data line pairs positioned physically close to said outputterminals to said sense amplifiers connected to said complementary data line pairs physically spaced apart from said output terminals.

12. A semiconductor memory according to Claim 11, wherein said control means includes a control circuitforformingsenseamplifiercontrol signals and a delay circuit receiving said sense amplifier control signals and producing control signals having mutually different delay times, so that said delay circuit produces sequentially the control signals to said sense amplifiers in the order starting from said sense amplifiers connected to said complementary data line pairs positioned physically close to the output term inals of said selection circuitto said sense amplifiers connected to said complementary data line pairs physically spaced apart from the output terminals.

13. A semiconductor memory according to Claim 12, wherein said delay circuit consists of a delay line having a plurality of output terminals and formed in parallel with said word lines, and the sense amplifier control signals are applied to said delay line from one side on which said selection circuit is located, so that the control signals having the mutually different delay times and applied to said sense amplifiers aretaken out from the output terminals of said delay line.

14. Asemiconductor memory according to Claim 13, wherein the material of an electrically conductive layerforming said delay line is substantially the same as the material of an electrically conductive layer forming said word lines so thatthe delay time of said delay line is substantially equal to the delay time of said word lines.

15. A semiconductor memory according to Claim 13, wherein each of said sense amplifiers consists of a first MOSFET having its gate electrode connected to one of said complementary data line pair and its drain electrode connected to the other of said complementary data line pair, a second MOSFET having its gate electrode connected to the other of said complementary data line pairs and its drain electrode connected to one of said complementary data line pair and a variable impedance element which is positioned between the junction of the source electrodes of a first and second MOSFETs and earth potential ofthe circuit and whose operation is controlled by said control signal.

16. A semiconductor memory according to Claim 15, wherein said variable impedance element consists of a third MOSFET having one of its imput-output electrodes connected to the source electrodes of said first and second MOSFETs and the other of its input-output electrodes connected to earth potential ofthecircuitand receiving said control signal at its gate electrode.

17. A semiconductor memory according to Claim 16,wherein each of said memory cells consists of an address selecting MOSFET having its gate electrode connected to said word line and one of its input-output electrodes connected to either one of said complementary data line pair and a data storage capacitor connectedtotheotherofthe input-output electrodes of said address selecting MOSFET.

18. A semiconductor memory according to Claim 17, wherein each of said word lines consists of an electrically conductive layer containing an electrically conductive polysilicone layer and said delay line consists of an electrically conductive layercontaining an electrically conductive polysilicone layer.

19. A semiconductor memory according to Claim 18, wherein the said word line consists of an electrically conductive layer containing an electrically conductive polysilicone layerformed integrallywith the gate electrode of said address selecting MOSFET inside said memory cell and said delay line consists of an electrically conductive layer containing an electrically conductive polysilicone layerformed integrally with the gate electrode of said third MOSFET inside said sense amplifier.

20. A semiconductor memory according to Claim 15, wherein said variable impedance element consists of a fourth MOSFET wh ose conductance characteristics are set to a relatively small value and a fifth MOSFET whose conductance characteristics are set to a relatively large value and which is rendered conductive moreslowlythan said fourth MOSFETand is connected in parallel with said fourth MOSFET.

21. A semiconductor memory according to Claim 11, which further includes a common data line pair and a switch circuit connecting one pair of said plurality of said complementary data line pairs to said common data line pair in accordance with the selection signal produced from said selection circuit.

22. A semiconductor memory accordi ng to Claim 21 wherein said selection circuit receives two sets of address signals supplied from outside in the time division arrangement and forms the selection signals to be supplied to said word lines and said dummy word lines and the selection signals to be applied to said switch circuit.

23. A semiconductor memory constructed and arranged to operate substantially as herein described with reference to and as illustrated in Figures 3to 6 of the accompanying drawings.