GB2114783A - Cache arrangement utilizing a split cycle mode of operation - Google Patents

Abstract

A cache system includes a high speed storage unit organized into a plurality of levels, each including a number of multiword blocks and at least one multiposition address selection switch and address register. The address switch is connected to receive address signals from a plurality of address sources. The system further includes a directory organized into a plurality of levels for storing address information required for accessing blocks from the cache storage unit and timing circuits for defining first and second halves of a cache cycle of operation. Control circuits coupled to the timing circuits generate control signals for controlling the operation of the address selection switch. During the previous cycle, the control circuits condition the address selector switch to select an address which is loaded into the address register during the previous half cycle. This enables either the accessing of instructions from cache or the writing of data into cache during the first half of the next cache cycle. During the first half of the cycle, the address selected by the address switch in response to control signals from the control circuits is clocked into the address register. This permits processor operations, such as the accessing of operand data or the writing of data into cache to be performed during the second half of the same cycle. <IMAGE>

Description

1 GB 2 114 783 A 1

SPECIFICATION

Cache arrangement utilizing a split cycle mode of operation The present invention relates to data processing systems and more particularly to cache memory systems.

It is well known to provide hierarchal memory organizations in which a large slow speed main memory operates in conjunction with a small high speed buffer storage unit or cache. In such arrangements, the central processing unit (CPU) can access operand data and/or instructions at a rate which more closely approximates the machine. During normal operation, when the CPU provides the address of the information to be accessed, control circuits perform a search of a directory which stores associative addresses for specifying which blocks of information reside in cache (i.e., define hit 10 condition). When it determines that the information resides in cache, the information is accessed and transferred to the CPU. When the requested information is not in cache, the control circuits request the information from main memory and upon its receipt write the information into cache at which time it may be accessed.

Examples of such systems are disclosed in co-pending patent applications of Charles P. Ryan and15 in U.S. Patent No. 3,588,829. In the system disclosed in the Ryan applications, the cache includes four levels which were addressed by the same set of address signals for accessing of four words of a block of instruction or data.

It has been recognized that the limiting factor for the rate at which cache accesses take place is the time required to perform a directory search. In general, an entire cache cycle of operation is required to perform a directory search. In general, an entire cache cycle of operation is required to determine whether the requested information is in cache (i.e., make a directory access and compare associative addresses).

In the case of a bit condition indicating the information to be fetched or updated is in cache, further access is required for completing the processor operation of either accessing operand data or 25 writing data into the cache. Since the cache memory data must be processed on a real time basis and instruction accesses must be made from cache, the writing of memory data and instruction accesses normally interfere with such operations. To overcome such interference, prior art arrangements hold up processor operations until the memory data is written into cache or instructions are accesses. This has been found to limit the overall access rate of the CPU resulting in a decrease in CPU performance.

Accordingly, it is a primary object of the present invention to provide a cache arrangement which eliminates the interference between the different types of operations required to be performed.

According to the present invention a cache unit for use with a data processing unit for providing fast access to information fetched from a main store coupled to said cache unit in response to commands received from said data processing unit, said cache unit having a cycle of operation and 35 comprising a buffer store including a plurality of addressable word locations for storing said information, address switch selection means having a number of inputs for receiving a corresponding number of addresses from a corresponding number of address sources and an output, address register means coupled to said output and to said buffer store, said address register means for storing the address specifying the word location to be accessed during the cache cycle of operation, control circuit 40 means coupled to said address switch selection means, said control circuit means generating and supplying coded control signals to said address switch selection means for identifying which address source is connected to supply said address to said address register means, and timing means for generating timing signals for defining a number of intervals of said cache cycle of operation, said timing means being coupled to said control means, said control means being conditioned by said timing means during one of said intervals to enable said address selection means to select an address for loading into said address register means from one of said address sources and said control means being conditioned during another one of said intervals to enable said address switch selection means to select an address for loading into said address register means from another one of said address sources for enabling the accessing of the information stored in the locations specified by both address 50 sources during the same cache cycle without interference between said accesses.

In a preferred embodiment, the cache arrangement includes a high speed storage unit or cache which is organized into a plurality of levels. Each level includes a number of multiword blocks and has -associated therewith a corresponding number of address selection switches and address registers.

Each address switch has a number of different positions connected to recieve address signals 55 from a plurality of address sources and selectively applies the address signals to the address register associated therewith. In response thereto, a decoder circuit is connected to generate output signals for controlling the operation of all of the address selection switches. In response to previously established level signals coded to define a level to be written into during a cache cycle of operation, the decoder circuit conditions a specified one of the number of switches to switch from a first position to a second 60 position while the remaining address switches remain selecting the first position.

During a cache cycle of operation, an address specifying the cache location into which memory data is to be written is clocked into one address register via the second position of one address selection switch. An address specifying the cache location from which a next instruction is to be 2 GB 2 114 783 A 2 fetched is clocked into the remaining address registers via the first position of the other address selection switches.

The instruction address is clocked into the remaining address registers when no conflict between levels has been detected. That is, the cache arrangement includes a comparator circuit for comparing signals indicating the level into which memory data is to be written with signals indicating the level 5 from which a next instruction is to be fetched. When there is a conflict, the comparator circuit generates signals which delay instruction access.

The arrangement of the preferred embodiment of the present invention enables memory data to be written into one cache level while a next instruction is fetched from one of the remaining levels during a cache cycle of operation. Thus, this eliminates the need to hold off or delay the accessing of 10 instructions to write memory data. The result is increased performance.

Of course, this assumes a small number of conflicts in levels. It will be appreciated that as the number of levels is increased, there will be a corresponding decrease in the probability of conflicts. In the preferred embodiment, eight levels were selected. However, it will be appreciated that the invention is not in anyway limited to such number.

A cache cycle of operation is split into first and second halves. During the first half of the cache cycle, instruction accesses and memory data write operations are executed while CPU read and write operations are executed during the second half of the cache cycle.

In such a split cycle arrangement, when applying the teachings of the present invention, the address of the cache location into which memory data is to be written is clocked into one address register at the beginning of the cache cycle. The instruction address is clocked into the other address registers at the same time as long as there is no conflict detected. Memory data is then written into cache while the next instruction is loaded into an output register during the first half of the same cache cycle.

Normally, an address from the CPU is loaded into all of the address registers at the beginning of 25 the second half cycle to initiate a possible read or write operation at the end of the second half cycle.

Therefore, in those instances when an instruction access conflicts with the writing of memory data, the second half of the cache cycle can be used to perform a CPU read operation and a memory data write operation simultaneously. Similar to the above, at the beginning of the second half of the cycle, the write memory data address is loaded into one of the address registers. The CPU address is loaded into 30 the remaining address registers. During the second half of the cycle, the requested data is read out to the CPU while the memory data is written into cache. This arrangement also results in increased CPU performance.

Thus, in the first instance, the teachings of the present invention permits the writing of memory information/data to be executed concurrently with the accessing of instructions provided the level into 35 which memory data is to be written is different from the level from which instructions will be accessed.

In the second instance, the writing of memory information/data to be executed concurrently with the accessing of operands provided the level into which memory data is to be written is different from the level from which operands will be accessed.

A directory is organized into a plurality of levels for storing address information for accessing the 40 blocks stored within the levels of cache. Timing circuits generate timing signals for defining first and second intervals of a cache cycle.

The control circuits which are connected to the timing circuits generate output signals for controlling the operation of the address selection switch. In operation, during the second interval of a cache cycle, the control circuits, in response to timing signals from the timing circuits, generate signals 45 for loading the address from one address source into the address register. This enables either the accessing of instructions from one of the levels of cache or the writing of memory information data during the first interval of the following cache cycle.

Also, during the first interval, the address selection switch selects an address from another 5C) address source which is clocked into the address register. This enables processor operations such as 50 the accessing of operand data or the writing of CPU/processor data to be performed during the second interval of the same cache cycle.

It will be appreciated that for efficient processing, the information requested to be accessed, resides in cache. This results in a high hit ratio wherein the majority of cache accesses normally will be for instructions. Therefore, it is important that the accessing of instructions not interfere with the accessing of operand data. Accordingly, when a request for an instruction is received, it can be accessed and transferred to the processor during the first interval of the same cycle that an operard requested by the processor is accessed and transferred. This eliminates any interference or conflicts arising from having to access instructions and also transfer operands. More importantly, such conflicts are eliminated without decreasing processor performance. This is particularly desirable in cache organizations wherein accesses proceed on a single word basis rather than on a block basis.

Additionally, it is desirable to be able to write memory data transferred on a real time basis.

Accordingly, when memory data is received, it can be immediately written into cache during the first interval of the same cycle that an operand requested by the processor is accessed and transferred to 3 GB 2 114 783 A 3 the processor. This eliminates any interference or conflicts arising from having to write memory data and also transfer processor operands.

In the case of accessing instructions, the source of addresses is an instruction address register. When there is no need to write memory data, the control circuits select as the source of addresses the instruction register whose contents specify the address of the next instruction to be fetched from cache. When memory information/data is to be written, the source of addresses is a buffer. In such cases, the control circuits select as the source of addresses, the buffer whose contents specify the address in cache where the requested memory information is to be stored.

The source of addresses for processor operations is a register containing an address received from the processor. During a previous cache cycle, the directory is searched to determine whether the 10 information specified by the same address resides in cache. The results of the directory search are processed during the second half of the next cache cycle as described above utilizing the stored processor address. By controlling the address switch to select different sources of addresses during the first and second intervals of a cache cycle, the cache arrangement of the present invention eliminates 15 the kinds of interference from the number of competing sources/activities described above.

Arrangements according to the invention will now be described by way of example and with reference to the accompanying drawings, in which:- Figure 1 illustrates in block form a system employing the principles of the present invention.

Figure 2 shows in block diagram form the host processor 700 and the cache unit 750 of Figure 1.

Figures 3a through 3e show in greater detail, certain ones of blocks of Figure 2.

Figure 4 shows in block diagram form the cache unit 750 of Figure 2.

Figure 5 shows in greater detail, the cache processor interface 604.

Figure 6a illustrates the format of the control store control unit of Figure 1.

Figure 6b illustrates the format of the microinstruction words of the execution control store of Figures 2 and 3.

Figures 7a through 7e show in greater detail, different ones of the sections of cache unit 750.

Figure 8 is a timing diagram used in explaining the operation of a preferred embodiment of the present invention.

Description of the preferred embodiment 30 General description

As seen from Figure 1, the system which incorporates the principles of the present invention includes at least one input/output processor (10PP) 200, a system interface unit (SILI) 100, a highspeed multiplexer (HSMX) 300, a low-speed multiplexer (LXMX) 400, a host processor 700, a cache memory 750, at least one memory module corresponding to a local memory module 500, and at least one memory module corresponding to a memory module 800. Different ones of these modules connect to one of a number of ports of the system interface unit 100 through a plurality of lines of different types of interfaces 600 through 604. More specifically, the input/output processor 200, the cache memory 750, and the high-speed multiplexer 300 connect to ports G, E and A, respectively, while the low-speed multiplexer 400, local memory module 500, and main memory module 800 connect to ports J, LMO and RMO, respectively. The host processor 700 connects to the cache 40 memory 750.

System interfaces Before describing in detail the processor 700 and cache unit 750, constructed in accordance with principles of the present invention, each of the interfaces 600 through 604 discussed previously will now be described.

The data interface 600 is one of the interfaces which provides for exchange of information between an active module and system interface unit 100. Exchange is accomplished by controlling the logical states of various signal lines in accordance with preestablished rules implemented through a sequence of signals termed a---dialog---.

The interface 601 is a programmable interface which provides for transfer of command information from an active module and a designated module. The transfer is accomplished by controlling the logic of states of the various signal lines in accordance with pre-established rules implemented through a sequence of signals termed a "dialog".

A further interface is the interrupt interface 602 which provides for interrupt processing by the input/output processor 200. That is, the interface enables the transfer of interrupt information by an 55 active module to the SIL) 100 to the inputloutput processor 200 for processing. Similar to the other interfaces, the transfer of interrupt requests is accomplished by controlling the logical states of the various signal lines in accordance with pre-established rules implemented through a sequence of signals termed a---dialog---.

A next set of interface lines utilized by certain ones of the modules of Figure 1 corresponds to the 60 local memory interface 603. This interface provides for exchanging information between local memory 500 and the modules of the system. The exchange is accomplished by controlling logical states of the 4 GB 2 114 783 A 4 various signal interface lines in accordance with pre-established rules implemented through a diaiog sequence of signals.

Memory and programmable interface commands are transferred out of the same physical data lines of the interface. The interface does not include a set of lines for processing interrupt requests and therefore the modules connected to the local memory by the SIU 100 cannot directly cause a memory 5 interrupt.

For a more detailed description of the elements of Figure 1 and each of the interfaces 600 through 603, reference may be made to U.S. Patent No. 4,006,466.

The last interface 604 is an internal interface between the cache unit 750 and central processor 700 which corresponds to the cache/CPU interface lines of Figure 5. This interface provides for exchanging information and control signals between the processor 700 and the cache unit 750. The exchange is accomplished by controlling the logical states of the various signal interface lines. The cache/CPU interface includes a plurality of data to processor lines (ZDI 0-35, PO-P3), a plurality of ZAC and write data lines (ZADO 0-23, RADO 24-35, PO-P3), a processor request signal line (DREQ-CAC), a plurality of cache command lines (DMEM 0-3), a hold cache line (HOLD-C-CU), a cancel line (CANCEL-Q a flush line (CAC-FLUSH), a read word line (RD- EVEN), a read instruction buffer line (RD-IBUF), a read double (FRD-DBLE), an odd line (FODD), a plurality of instruction lines 0130-35, PO-P3), a control line (DSZ), a read 1-buffer data line (RDIBUI7/ZD1), a plurality of zone bit lines (DZD 0-3), a bypass cache line (BYP-CAC), a write signal line (WRT- SGN), an instruction buffer empty line (IBUF-EMPTY), an instruction buffer ready line (IBUF-RDY), an instruction buffer full line 20 (IBUF-FULL), a CP stop line (CP-STOP), a CP control line (DATA-RECOV), a descriptor control line WPIM-EIS), a transfer no-go line (NO-GO) and a plurality of word address lines (ZPTROUTO-1).

Instructions, cache commands and data are forwarded to the cache unit 750 via different ones of these lines. Additionally, the operation of the processor 700 is enabled or disabled by certain ones of these lines as explained herein. The description of the CPLI/cache interface lines are given in greater 25 detail herein.

CPUlcache interface lines Designation Description

DREQ-CAC This line extends from processor 700 to cache unit 750. When the DREQ-CAC line is set to a binary ONE, a ZAC command is transferred to cache 750. In the 30 case of a write ZAC command, write data words are transferred in the one or two cycles following the ZAC command and data words are sent from the processor 700 through the cache 750 without modification, to the SIU 100.

DMEM 0, 1, 2, 3 These lines extend from the processor 700 to cache 750. Those lines are coded to designate the command that the cache 750 is to execute. The coding is as 35 follows:

DMEM=0000 no op No action is taken and no cache request is generated.

DEMEM=0001 Direct The direct command enables the processor 700 to perform a direct transfer of an 40 operand value without action on the part of the cache 750. Hence, no cache request is generated by this type of command.

DMEM=00 1 0-Address wraparound command (ADD-WRAP) The address wrap-around command is executed to return the command given to cache 750 by processor 700. On the same cycle, the command is given to 45 processor 700 via the Z131 lines 0-35.

DMEM=0 1 00-Load instruction buffer instruction fetch 1 (LD-IBUF-IF1) The load instruction buffer command is used to load the address of the next block of instructions into the alternate instruction register RICA/RICB.

There are three possible sequences of operation for this command. 50 1. In the case of a cache hit when the cache 750 is not being by-passed, the block address and level stored in the cache 750 are loaded into the alternate instruction register. A cache access is made to fetch the desired instruction which is transferred to processor 700 via the ZDI lines 0-35 on the subsequent T clock pulse. The alternate instruction register now becomes the 55 current instruction register.

2. In the case of a cache miss when the cache 750 is not being bypassed, the block address and the level designated by the round robin circuits are loaded into the alternate instruction register. The processor is turned off or held on the subsequent T clock pulse to determine whether the generation of the IF1 60 GB 2 114 783 A 5 Designation CPU/Cache interface lines (cont'd) Description

3.

command is in response to a transfer instruction. If it is and the transfer is a NO-GO, the current instruction register is used to access the next instruction and the processor 700 is turned on. If the IF1 command is caused by a transfer instruction which is a GO, then cache 750 sends a memory request to SILI 100 for the desired block of instructions and a directory assignment is made for the missing block. The instructions received from memory are first written into the instruction buffer and then into cache. The requested instruction is transferred to processor 700 via the M1 lines and the processor 10 700 is turned on or released on the subsequent T clock pulse. The remaining instructions of the block are transferred to processor 700 from the instruction buffer via the ZIB lines.

When the cache is to be bypassed and there is a hit, the full-empty bit for that block is reset. All other operations are the same as in the cache miss case, 15 except that no directory assignment is made and the block is not written into cache.

DIVIEM=0 101 -Load instruction buffer instruction fetch 2 (LD-IBUF-IF2) The load instruction buffer command is used to load the level of the second block of instructions into the current instruction register. The processor 700 is not 20 turned off in the case of a miss condition. There are also three possible sequences of operation for this command.

1. In the case of a cache hit condition and no bypass, the level of the second block of instructions is loaded into the current instruction register.

2. In the case of a cache miss condition and no bypass, when the IF1 command 25 was found to be the result of a transfer instruction NO-GO condition, the IF1 operation is cancelled. In the case of other than a NO-GO condition, a directory assignment is made for the second block of instructions and the level obtained from the round robin circuits are written into the current instruction register. Cache 750 sends a memory request to memory for the 30 block and when the instructions are received they are first written into the instruction buffer and later into cache 750. When the instructions are needed, they are read out from the instruction buffer and transferred to processor 700 via the ZIB lines 0-35.

3. In the case of a bypass, when there is a hit condition, the full-empty bit for 35 that block is reset. All other operations bre the same as in the case of a cache miss except that there is no directory assignment and the block is not written into cache 750.

DIVIEM=01 10-Load quad The load quad command is used to load the block address for data (not 40 instructions) into the alternate instruction register. It is similar to the IF2 except that the address and level (round robin circuits provide level when a cache miss condition) are written into the alternate instruction register. When the data is not in cache 750 and processor 700 requests it before it is received from memory, the processor 700 is held or stopped until the data is received.

DM EIV11=0 111 -P re-read (P R-RD) The pre-read command is used to load cache 750 with data which the processor 700 expects to use in the near future. The three possible sequences of operation are as follows:

1. For a cache hit and no bypass, the pre-read command is executed as a no-op. 50 2. For a cache miss and no bypass, the cache 750 generates a memory request for the block and a directory assignment is made for the missing block. When the data is received from memory, it is written into cache. The processor 700 is not held for this condition.

3. For a cache bypass, the pre-read command is treated as a no-op. 55 2.

DIVIEM=1 000-Read single (RD-SNG) The read single command is used to transfer a single data word to processor 700. There are four possible sequences of operation for this command. 1. In the case of a cache hit and no bypass, the addressed word is read from cache 750 and transferred to processor 700 on the next T clock pulse via the 60 M1 lines 0-35. In the case of a cache miss and no bypass, the processor 700 is stopped and missing block is assigned in the directory. Cache 750 transfers the memory 6 GB 2 114 783 A 6 CPU/Cache interface lines (cont'd) Designation Description request to main memory. The data words are written into cache as they are received. When the requested data word is received, processor 700 is turned on upon the occurrence of the subsequent T clock pulse. 3. in the case of a cache bit and bypass, the full-empty bit of the addressed block is reset and the processor 700 is turned off or held. The cache 750 transfers the request for one word to memory and the processor 700 is turned on upon the subsequent T clock pulse following receipt of the requested data word. The data word is not written into cache 750. 4. For a cache miss and bypass, the same operations take place as in the cache hit and bypass case with the exception that the full-empty bit of the addressed block is not changed. DMEM=1 00 1 -Read clear (RD-CLR) The read clear command is used to transfer a data word from memory into processor 700 and also clear it out. There are two possible sequences of operation for this command. 1. For a cache hit, the full-empty bit for that block is reset and processor 700 is turned off. The cache 750 makes a memory request for one data word. The memory clears the location. When the word is received, the cache 750 transfers the word to processor 700 and turns on the processor 700 on the next T clock pulse. The word is not written into cache 750. 2. Fora cache miss, the same operations take place as in the cache hit with the exception of no change in full-empty bits of the addressed block. DIVIEM=1 01 O-Read double (RD-DBL) The read double command is used to transfer two data words to processor 700. There are two types of read double commands which differ in the order in which the data words are given to processor 700. When line DSZ l is a binary ZERO, the order is odd word and even word. When line MZ1 is a binary ONE, the order is even word and then odd word. There are four possible sequences of operation 30 for this command. 1. For a cache hit and no bypass, the first word is transferred to processor 700 on the subsequent T clock pulse via the ZDl lines 0-35. On the next T clock pulse, the second data word is transferred to processor 700 via the M1 lines 0-35. 2. For a cache miss and no bypass, the processor 700 is turned off and a directory assignment is made for the block containing the addressed word pair. The cache 750 transfers the memory request to SIL1 100 for the block. As the data words are received they are written into cache. When the requested word pair isavailable, the first word is transferred to processor 700 40 and it is turned on or released on the subsequent T clock pulse. The cache 750 transfers the second word to processor 700 on the next T clock pulse.

For a cache bit and bypass, the full-empty bit of the addressed block is reset and processor 700 is turned off. The cache 750 transfers the request to memory for the two data words. As soon as the two words are available, the 45 processor 700 is turned on and the first data word is transferred to it on the subsequent T clock pulse. The processor 700 receives the second data word on the next T clock pulse. The data words are not written into cache.

4. For a cache miss and bypass, the same operations take place as in the case of the cache hit and by-pass, except that there is no change in full-empty bits. 50 DIVIEM=1 011 -Read remote (RD-RMT) The read remote command is used to circumvent normal cache read actions.

When the command is received, processor 700 is turned off and the request is transferred to the main memory. When the requested word pair has been fetched from memory, the first word is given to processor 700 and it is turned on the 55 subsequent T clock pulse. The second data word is transferred to processor 700 on the next T clock pulse. The order in which the data words are transferred is even word and then odd word. No changes are made within cache 750.

DMEM=1 1 00-Write single (WRT-SNG) The write single command is used to write data into memory. There are two 60 possible sequences of operation for this command.

1. For a cache hit, the cache 750 transfers the request to memory. When it is 1 7 GB 2 1-14 783 A 7 CPU/Cache interface lines (cont'd) Designation Description

HOLD-C-M CANCEL-C CAC-FLUSH accepted the data word is transferred to memory. The data word is also written into cache 750. 2. For a cache miss, the same operations take place as the cache hit except that 5 no change, is made to the cache 750. DMEM-1 11 O-Write double (WRT-DBL) The write double command is used to write two data words into memory. This command is carried out in a manner similar to the write single command except that two words are transferred/written rather than one word. DIVIEIV1=1 111 -Write remote (WRT-RMT) The write remote command is used to circumvent normal cache write actions in that when the addressed words are in cache 750, they are not updated. The cache 750 transfers the request to memory and when accepted, the two data words are transferred to memory. This line extends from processor 700 to cache 750. When set to a binary ONE, this control signal specifies that the cache 750 is to assume a HOLD state for requests or data transfers. This line extends from processor 700 to cache 750. When set to a binary ONE, this control signal indicates that the cache 750 should abort any processor command which is currently being executed. This line extends from processor 700 to cache 750. When set to a binary ONE, it starts a flush of the cache 750 (i.e., the cache 750 is forced to look empty by resetting all of the full-empty bits).

RD-EVEN This line extends from processor 700 to cache 750. When the cache makes a 25 double word request to the SIU, the even word is saved in a special register (REVN). When RD-EVEN line is set to a binary ONE, the contents of the REVN register are gated onto the Z131 lines via the MIN switch.

ZADO 0-23, These 40 unidirectional lines extend from processor 700 to cache 750. The lines RADO 24-35, are used to transfer ZAC commands and write data words to cache 750. When 30 PO-P3 the DREQ CAC line is forced to a binary ONE, ZAC command and in the case of a write type of command, the write data words are transferred during the one or two cycles following the ZAC command. The commands encoded onto the DMEM lines may or may not be the same as the ZAC command.

RD-IBUF This line extends from the processor 700 to cache 750. When set to a binary 35 ONE, the line indicates that processor 700 is taking the instruction from the instruction register RIRA. In most cases, it is used to start the fetching of the next instruction to be loaded into RIRA.

DZ D 0-3 These four lines extend from processor 700 to cache 750. These lines transfer odd word zone bit signals for write double commands. 40 BYP-CAC This line extends from processor 700 to cache 750. When set to a binary ONE, this line causes the cache 750 to request data words from main memory for read type instructions. When a cache hit occurs, the block containing the requested data is removed from cache 750 by resetting the full-empty bit associated therewith. For write single or double commands, the data is written 45 into cache 750 when a cache hit occurs.

WIRT-SGN This line extends from the cache,750 to processor 700. It is used to signal the processor 700 during write commands that the cache 750 has completed the transfer of ZAC commands and data words to the SIU 100.

FPIM-EIS This line extends from processor 700 to cache 750. When forced to a binary 50 ONE, it signals cache 750 that processor 700 is issuing an IF1 command for additional EIS descriptors.

DSZ1 This line extends from the processor 750 to cache 750. The state of this line specifies to cache 750 the order in which words are to be sent to the processor 700 when a read double command is performed. 55 NO-GO This line extends from processor 700 to cache 750. When forced to a binary ONE, it indicates that processor 700 executed a transfer instruction which is a NO-GO. This signals cache 750 that it should cancel the IF1 command it received when it was a miss and ignore the IF2 command which is currently applied to the DMEM lines. 60 RD-IBLIF/M1 This line extends from processor 700 to cache 750. It causes the cache 750 to access the data word at the address contained in the alternate instruction 8 GB 2 114 783 A 8 CPU/Cache interface lines (cont'd) Designation Description register and put this data on the Z131 lines. For an outstanding LDQUAD command, the cache 750 holds processor 700 when line RD-IBUI7/M1 is forced to a binary ONE. 5 FRD-DBL This line extends from processor 700 to cache 750. This signals cache 750 in advance that the processor 700 is requesting that a read double operation be performed.

FODD This line extends from processor 700 to cache 750. This line is used in conjunction with the FR1)-DI3LE line to signal the order of the words being 10 requested. When this line is a binary ONE, this indicates that the order is odd followed by even.

M1 0-35 These 40 unidirectional lines extend from cache 750 to processor PO, P11 P21 P3 700. They apply data from the cache 750 to the processor 700.

ZIB 0-35 These 40 unidirectional lines extend from cache 750 to processor 15 PO, P11 P21 P3 700. They apply instructions to the processor 700.

1 BUF-EMPTY This line extends from cache 750 to processor 700. When set to a binary ONE, this line indicates that cache 750 has transferred the last instruction from the current instruction block.

1 BUF-RDY This line extends from cache 750 to processor 700. When set to a binary ONE, 20 the line indicates that there is at least one instruction in the current instruction -block in cache 750. The line is set to a binary ZERO to indicate a non- ready condition as follows:

1. Whenever the instruction address switches from the last instruction of an IF 1 block in cache to the first instruction of an IF2 block not in cache and not in 25 the IBUF2 buffer.

2. Whenever instructions are being fetched from the IBUF1 or IBUF2 buffer and the next instruction to be fetched is in a two word pair which has not been received from memory.

1 BLIF-FULL This line extends from cache 750 to processor 700. This line indicates that there 30 are at least four instructions in the currenfl nstruction block or it has at least one instruction and an outstanding 1F2 request.

CP STOP DATA-RECOV ZPTR-OUT 0-1 This line extends from cache 750 to processor 700. When forced to a binary ONE state, the line signals that the processor 700 is held or required to wait or halt its operation. In the case of a read miss condition due to a processor command, processor 700 is held on the subsequent T clock cycle pulse. When released, the DATA RECOV line is forced to a binary ONE to restrobe the affected processor register(s). When the RDIBUF/ZM line is forced to a binary ONE before the data is received from memory, processor 700 is held prior to the subsequent T clock pulse. When released, the requested data is made available to processor 40 700 on the ZDI lines and is used on the subequent T clock pulse.

This line extends from the cache 750 to processor 750. It is used to restrobe processor registers following the stopping of the processor 700 in response to the detection of a cache miss condition or read bypass condition. At the end of the cycle in which the DREQ CAC line is forced to a binary ONE, the miss 45 condition is detected but processor 700 cannot be stopped until after the subsequent T clock pulse. Therefore, bad data/instructions are strobed into the processor registers from the M1/MB lines. When the requested data/instructions become available, the DATA RECOV line is forced to a binary ONE to restrobe the registers which were strobed during the last cache request.

These two lines extend from cache 750 to processor 700. These lines are coded to specify the two least significant bits of the address of the instruction contained in the RIRA instruction register or the 1 buffer.

General description of processor 700-Fig. 2

Referring to Figure 2, it is seen that the host processor 700 includes an execution control unit 55 701, a control unit 704, an execution unit 714, a character unit 720, an auxiliary arithmetic and control unit (AAM) 722, and a multiply-divide unit 728, which are inter-connected as shown. Additionally, the control unit 704 has a number of interconnections to the cache unit 750 as shown.

The execution control unit 701 includes an execution control store address preparation and branch unit 701-1, and an execution control store 701-2. The store 701-2 and unit 701-1 are 60 interconnected via buses 701-3 and 701-6 as shown.

9 GB 2 114 783 A 9 The control unit 704 includes a control logic unit 704-1, a control store 704-2, an address preparation unit 704-3, data and address output circuits 704-4, and an XAQ register section 704 which interconnect as shown.

As seen from Figure 2, the SIU interface 600 provides a number of input lines to the cache unit 750. The lines of this interface have been described in detail previously. However, in connection with 5 the operation of cache unit 750, certain ones of these lines are specially coded as follows.

1. M ITS 0-3 for Reads are coded as follows: bits 0-1 =00; bits 23=Transit block buffer address containing the ZAC command for current read operation. For Write Operation bit 0-3=Odd word zone 2. MIFS lines are coded as follows: bit 0=0; bit 1 =0 even word pairs (words 0,1); bit 1 =1 odd word pairs (words 2,3); bis 2-3=Transit block buffer address containing the ZAC command for the data being received.

As concerns the interface lines DFS 00-35, PO-P3, these lines convey read data to cache unit 750. The lines DTS 00-35, PO-P3 are used to transfer data and commands from cache 750 to the SIU 100.

The control unit 704 provides the necessary control for performing address preparation operations, instruction fetch i ng/execution operations and the sequential control for various cycles of operation and/or machine states. The control is generated by logic circuits of block 704-1 and by the execution control unit 701 for the various portions of the control unit 704.

The XAQ register section 704-5 includes a number of program visible registers such as index 25 registers, an accumulator register, and quotient register. Other program visible registers, such as the instruction counter and address registers, are included within the address preparation unit 704-3.

As seen from Figure 2, the section 704-5 receives signals from unit 704-3 representative of the contents of the instruction counter via lines RIC 00-17. Also, lines ZRESA 00-35 apply output signals from the execution unit 714 corresponding to the results of operations performed upon various 30 operands. The section 704-5 also receives an output signal from the auxiliary arithmetic and control unit via lines MAU0-8.

The section 704-5 provides signals representative of the contents of one of the registers included within the section as an input to the address preparation unit 704-3. The address preparation unit 704-3 forwards the information through a switch to the execution unit 714 via the 35 line ZDO 0-35. Similarly, the contents of certain ones of the registers contained within section 704 can be transferred to the execution unit 714 via the lines ZEB 00-35. Lastly, the contents of selected ones of these registers can be transferred from section 704-5 to the multiply/divide unit 728 via the lines ZAQ 00-35.

The address preparation unit 704-3 generates addresses from the contents of various registers 40 contained therein and applies the resultant logical, effective and/or absolute addresses for distribution to other units along the lines ASFA 00-35. The address preparation unit 704-3 receives the results of operations performed on a pair of operands by the execution unit 714 via the linesZRESB 00-35.

The unit 704-3 receives signals representative of the contents of a pair of base pointer registers from the control logic unit 701 via the lines RBASA and RBAS130-1. Outputs from the multiply/divide unit 45 728 are applied to the address preparation unit 704-3. Lastly, the contents of a secondary instruction register (RSIR) are applied as input to the unit 704-13 via the lines RSIR 00-35.

The data and address output circuits 704-4 generate the cache memory address signals which it applies to the cache unit 750 via the lines RAD0/ZAD0 00-35. These address signals correspond to the signals applied to one of the sets of input lines M1 00-35, ASFA 00- 35 and ZRESB 00-35 50 selected by switches included within the circuits of block 704---4. These circuits will be further discussed herein i n greater detail.

The control logic unit 704-1 provides data paths which have an interface with various units included within the cache unit 750. As described in greater detail herein, the lines ZIB 00-35 provide an interface with an instruction buffer included within the cache 750. The lines M1 00-35 are used to 55 transfer data signals from the cache 750 to the control logic unit 704-1. The ZPTROUT lines are used to transfer address information from cache 750 to unit 704-1. Other signals are applied via the other data and control lines of the cache-CPU inter-face 604. These lines include the CP-STOP line shown separately in Figure 2.

GB 2 114 783 A 10 As seen from Figure 2, the control logic unit 704-1 provides a number of groups of output signals. These output signals include the contents of certain registers, as for example, a basic instruction register (RBIR) whose contents are applied as an input to control store 704-2 via the lines RBIR 18-27. The control logic unit 704-1 receives certain control signals read out from control store 704-2 via the lines CCWO 13-3 1.

The control logic unit 704-1 also includes a secondary instruction register (RSIR) which is loaded in parallel with the basic instruction register at the start of processing an instruction. The contents of the secondary instruction register RSIR 00-35, as previously mentioned, are applied as inputs to the address preparation unit 704-3. Additionally, a portion of the contents of the secondary instruction register is applied as an input to the auxiliary arithmetic control unit 722 via the lines RSIR 10 1-9 and 24-35.

The control store 704-2 as explained herein provides for an initial decoding of program instruction op-codes and therefore is arranged to include a number of storage locations (1024), one for each possible instruction op-code.

As mentioned, signals applied to lines RBIR 18-27 are applied as inputs to control store 704 2. These signals select one of the possible 1024 storage locations. The contents of the selected storage location are applied to the lines CCWO 13-31 and to CCWO 00-12 as shown in Figure 2.

The signals supplied to lines CCWO 00-12 correspond to address signals which are used to address the execution control unit 701 as explained herein.

The remaining sections of processor 700 will now be briefly described. The execution unit 714 20 provides for instruction execution wherein unit 714 performs arithmetic and/or shift operations upon operands selected from the various inputs. The results of such operations are applied to selected outputs. The execution unit 714 receives data from a data input bus which corresponds to lines RDI 00-35 which have as their source the control logic unit 704-1. The contents of the accumulator and quotient registers included within section 704-5 are applied to the execution unit 714 via the lines 25 ZEB 00-35 as mentioned previously. The signals applied to the input bus lines WO 00-35 from the address preparation unit 704-3 are applied via switches included within the execution unit 714 as output signals to the lines Z1RESA 00-35 and ZRESB 00-35, as shown in Figure 2. Additionally, execution unit 714 receives a set of scratch pad address signals from the auxiliary arithmetic and control unit 722 applied via the lines ZIRSPA 00-06. Additionally, the unit 722 also provides shift information to the unit 714 via the lines ZRSC 00-35.

The character unit 720 is used to execute character type instructions which require such operations as translation and editing of data fields. As explained herein, these types of instructions are referred to as extended instruction set (EIS) instructions. Such instructions which the character unit 720 executes include the move, scan, and compare type instructions. Signals representative of operands are applied via lines ZRESA 00-35. Information as to the type of character position within a word and the number of bits is applied to the character unit 720 via the input lines W13 00-07.

Information representative of the results of certain data operations is applied to the unit 722 via the lines ZOC 00-08. Such information includes exponent data and data in hexadecimal form. The character unit 720 applies output operand data and control information to the unit 722 and the unit 40 728 via the lines RCHU 00-35.

The auxiliary arithmetic and control unit 722 performs arithmetic operations upon control information such as exponents used in floating paint operations, calculates operand lengths and pointers and generates count information. The results of these operations are applied to execution unit 714 via the lines ZRSPA 00-06 and lines ZRSC 00-06 as mentioned previously. Information signals 45 corresponding to characters such as 9-bit characters, 6-bit characters, decimal data converted from input hexadecimal data, quotient information and sign information are applied to section 704-5 via the lines RAAU 00-08.

As seen from Figure 2, the unit 722 receives a number of inputs. Character pointer information is applied via the lines ASFA 33-36. EIS numeric scale factor information and alphanumeric field length 50 information are applied to the unit 722 via the lines RSIR 24-35. Other signals relating to fetching of specific instructions are applied via the lines RSIR 01 -09. Exponent signals for floating point data are applied to the unit 722 via the lines ZOC 00-08 while floating point exponent data signals from unit 704-1 are applied via the lines RDI 00-08. Shift count information signals for certain instructions (e.g. birary shift instructions) are applied to the unit via the lines RDI 11-17. As concerns the input 55 signals applied to the lines RCHU 00-35, lines 24-35 apply signals corresponding to the length of EIS instruction fields while 18-23 apply address modification signals to the unit 722.

The last unit is the multiply/divide unit 728 which provides for highspeed execution of multiply and divide instructions. This unit may be considered conventional in design and may take the form of the multiply unit described in U.S. Patent No. 4,041,292 which is assigned to the same assignee as 60 named herein. The unit 728 as seen from Figure 2 receives multiplier dividend and divisor input signals via the lines RCHU 00-35. The multiplicand input signals from register section 704-5 are applied via the lines ZAQ 00-35. The results of the calculations performed by the unit 728 are applied as output signals to the lines ZMD 00-35.

11 GB 2 114 783 A 11 As mentioned previously, the cache unit 750 transfers and receives data and control signals to and from the SIL1 100 via the data interface line 600. The cache unit 750 transfers and receives data and control signals to and from the processor 700 via the lines of interface 604. Lastly, the cache unit 750 receives address and data signals from the circuits 704-4 via the lines RADO/ZADO 00-35.

Detailed description of the processor 700 Certain ones of the sections which comprise the processor 700 illustrated in Figure 2 will now be discussed in greater detail with respect to Figures 3a through 3e.

Referring to Figures 3a and 3b, it is seen that the processor includes two control stores: (1) the control unit control store (CCS) 704-200 which forms part of the control unit 704; and (2) the execution control store (ECS) 701-3 which 1r, included within the execution control unit 701.

The cache oriented processor 700 of the preferred embodiment of the present invention includes a three stage pipeline. This means that the processor 700 requires at least three processor cycles to complete the processing of a given program instruction and can issue a new instruction at the beginning of each cycle. Hence, a number of program instructions may be in some stage of processing at any given instant of time.

In the preferred embodiment, the processor 700 includes the following stages: an instruction cycle (1) wherein instruction interpretation, op-code decoding and address preparation take place; a cache cycle (C) wherein access to the cache unit 750 is made ensuring high performance operation; and, an execution cycle (E) wherein instruction execution takes place under microprogram control.

As concerns control, during the 1 cycle, the op-code of the instruction applied via lines RBIR 18- 20 27 is used to access a location within control store 704-2. During a C cycle, the accessed contents from control store 704-2 are applied to lines CCS DO 00-12 and in turn used to access one of the storage locations of the execution control store 701-2. During the C cycle, the microinstructions of the microprogram used to execute the instruction are read out from the execution control store 701 - 2 into a 144-bit output register 701-4. The signals designated MEIVIDO 00- 143 are distributed to 25 the various functional units of processor 700. During an E cycle, the processor executes the operation specified by the microinstruction.

Referring specifically to Figure 2, it is seen that the control store 7042 includes a control unit control store (CCS) 704-200 which is addressed by the op-code signals applied to the lines RBIR 18-27. The CCS 704-200, as mentioned previously, includes 1024 storage locations, the contents 30 of which are read out into an output register 704-202 during an 1 cycle of operation. Figure 6a shows schematically the format of the words stored within the control store 704- 200.

Referring to Figure 6a, it is seen that each control unit control store word includes five fields. The first field is a 13-bit field which contains an ECS starting address location for the instruction having an op-code applied to lines RBIR 18-27. The next field is a three bit field (CCSO) which provides for the 35 control of certain operations. The bit interpretations of this field depend upon its destination and whether it is decoded by specific logic circuits or decoded under microprogram control. The next field is a 4-bit field which provides for certain register control operations.

The next field is a 6-bit sequence control field which is coded to specify a sequence of operations to be performed under hardwired logic circuit control as well as the type of cache operation. In the present example, this field is coded as 7 58. The last field is a 6-bit indicator field which is not pertinent to an understanding of the present invention.

As seen from Figure 3a, signals corresponding to the CCSA field of a control unit control store word arie applied via a path 704-204 as an input to the execution generation circuits 701-7. Signals corresponding to the CCSR field are applied as an input to the execution unit 714 via path 704-206. 45

Additionally, the same signals are applied as an input to the address preparation unit 704-3 via another path 704-208.

Signals representative of the sequence control field apply as an input to the sequence control logic circuits 704-101 via path 704-210. As explained herein, these circuits decode the sequence control field and generate signals for conditioning the cache unit 750 to perform the operation 50 designated.

As mentioned previously, the execution address generation circuit 701 -1 receives an input address which corresponds to field CCSA from the control store 704-2. As seen from Figure 3b, these circuits include an input address register 701-10 whose output is connected to one position of a four position switch 701-12 designated ZECSA. The output of the switch serves as an address source for the control store 701-2. The first position of the switch 701- 12 is connected to receive an address from the MICA register 701-14. The contents of register 701-14 are updated at the end of each cycle to point to the location within the ECS control store following the location whose contents were read out during that cycle.

The second position selects the address produced from the ZCS13RA branch address selector switch 701-18. The third position selects the address of the first microinstruction in each microprogram provided by the CCS control store which is loaded into the REXA register 701 -10.

When the CCS output is not available at the termination of a microprogram, a predetermined address (octal address 14) is automatically selected.

12 GB 2 114 783 A The first position of branch switch 701-18 receives signals corresponding to a branch address read out from store 701-2 into register 701-4 which is in turn forwarded to a return control register 701-20. The second, third and fourth positions of switch 701-18 receive signals from RSCR register 701-20, an MIC register 701-15 and the contents of a number of vector branch registers 701-36. The MIC register 701-15 stores an address which points to the microinstruction word following the microinstruction word being executed. This address corresponds to the address from switch 701-12 incremented by one by an increment circuit 701-12.

The vector branch registers include a 4-bit vector branch register 0 (RV130), a 2-bit vector branch register 1 (RV131) and a 2-bit vector branch register 2 (RV132). These registers are loaded during a cycle of operation with address values derived from signals stored in a number of different indicator flip-flops 10 and registers applied as inputs to the number of groups of input multiplexer selector circuits 701-32 and 701-34. The outputs of the circuits 701-32 and 7,01-34 are applied as inputs to two position selector circuits 701-30. These circuits in turn generate the output signals ZV13RO, ZV13R1 and ZV13R2 which are stored in the register 701-36.

The switch 701-36 provides an address based upon the testing of various hardware indicator 15 signals, state flip-flop signals selected via an INIDGRI? field. The branch decision is determined by masking (ANDING) the selected indicator set with the INDIVISKLI and INDIVISKI-fields of a microinstruction word. If a vector branch is selected, INDIVISKLI is treated as 4 ZERO bits. The---OR-of the 8 bits is compared to the statedefined by the TYPG and GO microinstruction fields. The hardware signals are applied via a number of data selector circuits 701-28 only one of which is shown whose 20 outputs are in turn applied as inputs to a further five position multiplexer selector circuit 701-26. The output of the multiplexer circuit 701-26 feeds a comparison circuit which- --ands- the indicator signals with the mask signals to produce the resulting signals MSKCBRO-7.

The signals MSKCBRO-7 are applied to another comparison circuit which--ands- the signals with the condition branch test signals TYPGGO to set or reset a branch decision flip-flop 701-22 25 which produces a signal RBIDG0 whose state indicates whether branching is to take place. The output signal RBIDG0 is applied as a control input to the first two positions of switch 701-12. When the branch test condition is not met (i.e., signal RBIDG0=0), then the incremented address from the MICA register 701-14 is selected.

In some instances, as seen herein, it is not possible to test the state of an indicator on the cycle 30 following its formation. For this reason, history registers HRO-HR7, not shown, are provided for register storage of the Group 2 findicators. The states of such stored indicators are selected and tested in a manner similar to that of the other indicators (i.e., mask fields).

Additionally, the unit 701 -1 includes a number of indicator circuits, certain ones of these are used to control the operation of certain portions of the processor 700 when the strings being processed by certain types of instructions have been exhausted. These indicator circuits are included in block 701-42 and are set and reset under the control of a field within the microinstruction word of

Figure 6a (i.e., IND6 field). The bits of this fleid read out from the ECS output register 701-4 are applied to an RMI register 701-38 for decoding by a decoder 701-40. Based upon the state of status indicator signals received from the various processor units (e.g. 714, 720, 722, etc.), the appropriate ones of the auxiliary flip-flops are switched to binary ONE states. The outputs of these flip flops are applied via the different positions of a 4 position switch 701- 44 to the GP3 position of switch 701-26 for testing. The same outputs are applied to a second position of a ZIR switch 701 - 43 for storage via the ZDO switch 704-340. The ZIR switch 701-43 also receives indicator signals from an indicator register (M) 701-41. This reffister is loaded via the RDI lines 18-30 and 32 in response to certain instructions.

The indicator status signals for example include the outputs of different adder circuits (AL, AM of the unit 720. These signals will set different ones of a number of exhaust flag flip-flops designated FE1 1, FE1 2, FE1 3, FE1 E, FE2E, FE2 and FE3. The FE1 E and FE2E flip- flops are set during any FPOA cycle of any instruction. These flip-flops in turn cause the FE1 1, FE1 2 and FE1 3 flip-flops to be set 50 when the outputs from and AL or AXP adder circuits of unit 720 are generated. The setting and resetting of these indicators will be described herein in further detail in connection with the description of operation. However, the exhaust flag flip-flops pertinent to the example given herein are set and - reset in accordance with the following Boolean expressions.

SET: FE 'I E=FPOA+IND6FLID field.

RESET: FE 1 E=IND6FLID field.

SET: FE2E=FPOA+IND6FLID field.

RESET: FE2E=IND6FLID field.

SET: FE1 1 =IND6FLID field. FE1 E (ALES +AXP ES+DESC 1. AP0-4=0)+IND6FLID field. FE1 E. DESC1. (APO-5=0+APZN+ALZN)+IND6FLD field.

RESET: FE 11 =POA+IND6FLID field.

SET: FE1 2=IND6FLID field. FE1 E. (ALES+AXPES+FE1 3).

RESET: FE1 2=POA+IND6FLID field.

SET: FE1 3=IND6FLID field. FE1 E. ALES+IND6FLID field.

13 GB 2 114 783 A 13 RESET: FE1 3=POA+IND6FLI) field.

SET: FE2AND6FLI) field. FE2E. ALESAND6FI-D field. FE2E. DESC2. (APO-4=0+ APO5=0+APEN+ALZN)+(IND6FLD field) FE2E. DESC2AND6FLD.

RESET: FE2=POA+IND6FLI) field.

SET: FE3=IND6FLI) field. DESC3. (APO-4=0+APO-5+APZN+ALZN)+IND6FLD field. DESC3AND6FLI).

RESET: FE3=FPOA+IND6FI-D field.

Wherein IND6FLD indicates a particular code; ALES=Al_=0 or AL-C; AXP ESAXP=0 or AXP-E; APZN=APO-70; and, ALM=Al-0-1 1:50.

1 0 The MSBRA switch 701-18 is normally enabled when the branch decision flip- flop RDD was set to a binary ONE in the previous cycle. The first position selects a 13-bit branch address from the current microinstruction applied via the RCSR register 701-20. The branch address enables any one 15 of the locations of the ECS control store to be addressed directly. The second position selectsthe concatenation of the 6 low order address bits from the current microinstruction applied via MIC register 701-15 and the 7 upper bits of the branch address from the current microinstruction applied via the RCSR register 701-20. This permits branches within a 64word page defined by the contents of the MIC register 701-15 (current location+ 1).

The third position selects the concatenation of 4 low order bits from the RVBO vector branch register, 6 bits from the branch field of the current microinstruction stored in RCSR register and the 3 upper bits of the address stored in the MIC register. This permits 16 way branches. The fourth position selects the concatenation of the 2 low order ZEROS with 4 bits from the vector branch register RVBO with the 4 most significant bits of the branch address field of the current microinstruction and the 3 upper bits of the current address stored in the MIC register. This permits 1 6-way branches with 3 control store locations between each adjacent pair of destination addresses.

The fifth position selects the concatenation of 2 low order ZEROS with 2 bits from vector branch register RM, with the 6 bits of the branch address of the current microinstruction and the upper 3 bits from the MIC register. This permits branches with 4 possible destinations with 3 control store locations between each adjacent pair of destination addresses.

The sixth position selects the concatenation of 2 low order ZEROS with 2 bits from vector branch register FIVB2 with the 6 bits of the branch address of the current microinstruction and the upper 3 bits from the MIC register. This permits 4-way branches with 3 control store locations between each adjacent pair of destination addresses.

The output of switch 701-12 addresses a specific location within control store 701-2 which causes the read out of a microinstruction word having a format illustrated in Figure 6b. Referring to that Figure, it is seen that the microinstruction word is coded to include a number of different fields which are used to control the various functional units within processor 700. Only those fields which are related to the present example will be described herein.

Bits 0-1 Bit 2 EUMT Reserved for Future Use. Defines which format the EU is to operate with. EUMT-0 specifies a first microinstruction format while EUMT=1 specifies an alternate microinstruction format.

Bits 3-5 TRL TR Low Write Control.

Write control of EU temporary regis ters TRO-TR3. 50 0XX No change Write TRO 101 Write TR 1 Write TR2 ill Write TR3 55 Bits 6-8 TRH TR High Write Control.

Write control of EU temporary registers TR4-TR7.

0XX No change 100 Write TR4 60 101 Write TR5 Write TR6 ill Write TR7 14 GB 2 114 783 A 14 Bits 9-12 ZOPA ZOPA Switch Control.

Selects the output of ZOPA switch.

0) 0000 TRO 1) 0001 TR1 2) 0010 TR2 5 3) 0011 TR3 4) 0100 TR4 5) 0101 TR5 6) 0110 TR6 7) 0111 TR7 10 8-11) 1 OXX RD1 12) 1100 ZEB 13) 1101 ZEB 14) 1110 ZEB 15) 1111 0 (disable) 15 Bits 13-16 ZOPB ZOPB Switch Control.

Selects the output of ZOPB switch.

Bits 17-18 ZRESA ZRESA Switch Control.

Selects the output of ZRESA switch.

00 ALU 20 01 Shifter Scratchpad/RDI switch 11 Z130 Bits 19-20 ZRESB ZRESB Switch Control.

Selects the output of ZFIES13 switch. 25 00 ALU 01 Shifter Scratchpad/RDI switch 11 ZDO Bit 21 RSPB Scratchpad Buffer Strobe 30 Control.

Bit 22 Bit 23 Strobes RSPB with Z11ES13 data.

0 No strobe 1 Strobe RSPB RSP Scratchpad Write Control.

0 Read scratchpad 1 Write scratchpad ZSPID1 Scratchpad/RDI Switch Control.

Selects the output of the Scratchpad/ RDI switch.

0 Scratchpad output 40 1 RDI Bits 24-25 ZSHFOP Shifter Operand Switch Control.

Selects the left operand to the Shifter.

00 ZOPA output 45 01 EIS output 0 11 Select 0 or -1 depending on bit 0 of right operand to Shifter.

Bits 24-27 ALU ALU Function Control. 50 Selects the operation applied to the two inputs (A and B) to the ALU.

Bits 24-29 N/a Bits 26-31 RFU Reserved for Future Use.

Bits 30-31 ZALU ALU Switch Control. 55 Selects the output of ZALU switch.

Bits 32-33 NXTD Next Descriptor Control.

Strobes RBAS13 and RDESC registers.

00 RBAS13 00 RDESC 00 60 01 RBAS13 01 RDESC 01 RBAS13 Alt RDESC 10 11 No strobes (default) 65 GB 2 114 783 A 15 Bits 32-35 CM Control constant field referenced by the CONTF field.

Bits 34-35 113PIPE IBUF/Pipeline Control.

Selects the reading of IBUF of the pipeline operation.

00 No operation 5 01 Read IBUF/M1 (Alt) Type 1 Restart Release or 11 Type 4 Restart Wait Bits 36-37 FMTD Selects the loading of various CU 10 registers and indicates the inter pretation to be given to the MEMADR field for small CU control.

00 No operation 01 RADO ASFA 15 RADO ZRES13 11 RADO ASFA Bits 38-40 MEMADR Cache Control.

Selects cache operations. The com plete interpretation for this control 20 is a function of the FIVITD control.

000 No operation 001 Read SgI Load Quad 011 Preread 25 Write Sgi 101 Write Dbi Read Sgi Trans (for FIVITI)=1 1 only) 111 Write Sgi Word (for FMTD= 1 1_ only) Bit 41 ZONE Zone Control. 30 Indicates zone or no zone for small CU control.

0 No zone 1 Zone Bits 42-44 TYPA. Type A Flag. 35 Indicates the type A overlayed fields being used.

000 Type A=0 fields

40 Type A=4 fields

Bits 44---46PIPE Pipeline Control Selects the type of restart to be initiated.

000 No operation 001 Type 1 Restart and Release 45 Type 2 Restart - 011 Type 3 Restart Type 4 Restart 101 TypeS Release 110 Type 6 Restart 50 Bits 44-47 AUXREG Auxiliary Register Write Control Selects an auxiliary register or combinations to be strobed with data selected by the AUXIN control field.

0) 0000 No strobe 55 1) 0001 IRRI)XA 2) 0010 R29 3) 0011 R29, RRDXA, FRL, RID 4) 0100 RRM 5) 0101 RTYP 60 6) 0110 RBASA 7) 0111 RBASA,RTYP 8) 1000 RBAS13 9) 1001 RDESC 10) RBASA, R29, 9RDM 65 16 GB 2 114 783 A 16 Bits 45-46 TYPB Type B Flag.

Indicates the Type B overlayed fields being used.

00 Type B=0 fields

11 Type B=3 fields 5

Bit 47 RSC RSC Strobe Control.

Strobes the RSC register. (Shift Count) Bit 47 RSPA RSPA Strobe Control.

Strobes the RSPA register. 10 Bits 47---48N/A Bit 47 RAAU RAAU Strobe Control.

Strobes RAAU register.

Bits 48-49 ZLX ZLX Switch Control.

Selects the output of the W switch. 15 Bits 48---49ZSPA ZSPA Switch Control.

Selects the output of the ZSPA switch.

Bits 48-50 AUXIN Auxiliary Register Input Control. 20 Selects data to be strobed into auxiliary register(s).

Bit 49 ZADSP ZADSP Switch Control.

Selects the output of ZADSP switch.

Bits 50-52 zsc ZSC Switch Control.

Selects the output of ZSC switch. 25 Bits 50-52 ZRSPA ZRSPA Switch Control.

Selects the output of ZRSPA switch.

Bits 50-52 ZAAU ZAAU Switch Control.

Bit 51 RSIR RSI R Register Strobe.

Strobes the RSIR register as a function 30 of the AUXIN field.

Bit 53 RDW R1 DW, R213W Register Strobe.

Strobes the R 'I DW or R213W register as a function of the RDESC register.

Bits 53-54 ZI-NA ZI-NA Switch Control. 35 Selects output of ZI-NA switch.

Bits 54-57 CONTF Miscellaneous Flip-Flop Control.

Selects one of four groups of control flip-flops to be set or reset by the 40 control constant field (CCM). The flip-flops include those of blocks 704-104 and 704-110.

Bits 55-56 ZI-NI3 ZI-NI3 Switch Control.

Selects the output of ZI-NI3 switch. 45 Bits 55-56 ZSPAW Type A=2 ZSAPA Switch, RSPA Register Control.

Selects ZSPA switch output and strobes RSPA register.

Bits 57-58 ZPC ZIPC Switch Control. 50 Selects the output of ZPC switch.

Bits 59-62 W W Switch, RXI Register Bank Control.

Selects W switch output and the RXI? register into which it will be 55 written.

Bits 59-63 ZI-N(1) ZLN Switch, RLN Register (Type A= 1 Bank Control Selects ZLN switch output and the RI-N register into which it will be 60 written.

17 GB 2 114 783 A 17 Bits 59-60 ZPA ZPA Switch Control.

*Selects the output of ZPA switch.

OMPO 11 =RP3 Bits 61-62 ZPB ZPB Switch Control. 5 Selects the output of ZPB switch.

00=RPO 11 =RP3 Bits 63-64 ZXPL ZXPL Switch Control.

(Type A=O) 10 Selects the output of ZM switch.

00=FIXPA 11 =FIXPID Bit 63 ZILM2) ZILN Switch, RILN Register (Type A=2) Bank Control. 15 Selects ZILM switch output and the RILN register into which it will be written.

Bits 63-66 RDIN RDI In Control.

Selects the data to be strobed into the RDI register and selects one of 20 the modification control fields (MFl

MF3, TAG) of an instruction word. RDI strobe may also be controlled by the MISCREG field.

Bit 64 ZXPLO) ZXPL Switch Control. 25 (Type A= 1) Selects the output of ZXPL switch.

Bits 64-68 ZRPAC ZRPA Switch, WC Switch, Type A=2) RPO-3 Register Bank Control.

Selects ZRPC and ZIRPA switch outputs 30 and the RPO-3 register into which the ZRPA output will be written.

Bits 65-66 ZXPR ZXPR Switch Control.

(Type A=O) Selects the output of ZXPR switch. 35 Bits 65-66 ZXPM W Switch, FIXP Register (Type A= 1) Bank Control.

Selects W switch output and the MP register into which it will be written.

Bits 67-68 ZPD ZPD Switch Control. 40 (Type A=O) Selects the-output of ZPD switch.

Bit 67 ZRPAC(4) ZRPA Switch, MPC Switch, (Type A=4) RPO-3 Register Bank Control.

Selects CP4 from ZRPA switch and strobes the 45 RP 1 register.

Bit 67 TYPID Type D Flag.

Type D Flag which indicates D over layed fields.

Bit 68 ZRP13(4) ZRPB Switch, RP4-7 Register 50 (Type A=4) Bank Control.

Selects 0 from ZRPB switch and strobes the RP4 register.

18 GB 2 114 783 A 18 Bits 68-71 MEM Cache Memory Control.

Selects the cache operation in con junction with the SZ control.

0) 0000 No operation 15) 1111 Write Remote 5 Bits 68-70 IBUF IBUF Read Control.

Selects the destination of IBUF data when reading IBUF.

Bits 69-73 AXP ZXPA Switch, ZXPB Switch, (Type A=O) AXI? Adder, ZAXO Switch, RE 10 Register Control.

Selects ZXPA and ZXPB switch outputs, the AXP adder function applied to them, and the ZAXP switch output. Also strobes the RE register. 15 Bits 69r-73 ZRPB ZRPB Switch, RP4-7 Register (TypeA=1) Bank Control.

Selects ZRPB switch output and the RP4-7 register into which it will be written. 20 Bits 69-71 ZRPAC-3 ZRPA Switch, ZRPC Switch, (Type A=3) RPO-3 Register Bank Control.

Selects ZRPC and ZRPA switch outputs and the RPO-3 register into which the ZRPA output will be written. 25 Bits 72-74 ZRPB0 Z13PB Switch, RP4-7 Register (Type A=3) Bank Control.

Selects ZRPB switch output and the RP4-7 register into which it will be written. 30 Bits 72-73 SZ Size/Zone Cache Control.

Controls cache operations in conjunction with the MEM control field.

Bits 74-78 ZF1PB0 ZRPB Switch, RP4-7 Register (Type A=O) Bank Control. 35 Selects ZRP switch outDut and the RP4-7 register into which it will be written.

Bits 74-78 AL ZALA Switch, ZALB Switch, AL (Type A=- 1) Adder Control.

Selects ZALA and ZALB switch outputs 40 and the AL adder function applied to them.

Bit 74 TYPE Type E Flag.

Type E flag which indicates the type E overlayed fields. 45

Bits 75-77 ZXPQ) ZXP Switch, RXP Register Bank (Type A=21) Control.

Selects ZXP switch output and the RXP register into which it will be written.

Bits 75-78 MISCREG Miscellaneous Register Control. 50 Selects various operations on mis cellaneous registers (e.g. RBIR, RDI, RI-EN,RSPN.

Bits 75-78 ZDO ZDO Switch Control.

Selects-the output of the ZDO switch. 55 Bit 78 ZIZN ZIZN Switch Control.

Selects the output of =N switch.

Bits 79-83 AP ZAPA Switch, ZAP B Switch, AP Adder Control.

Selects ZAPA and ZAPB switch output 60 and the AP adder function applied to them.

19 GB 2 114 783 A 19 Bits 79-81 Bits 79-83 Bits 80-81 Bits 82-83 Bit 84 Bits 85-86 Bit 86 Bit 87 Bits 88-89 Bit 90 Bits 90-93 0) 0000 No operation Bit 90 Bit 90 Bits 91-97 Bits 91-93 ZI-N(3) ZLN Switch, RI-N Register (Type A=3) Bank Control.

Selects ZLN switch output and the RLN register into which it will be written.

ZI-N(4) ZLN Switch, RI-N Register Bank (Type A=M Control.

Selects ZLN output and the RI-N regis ter into which it will be written.

RAAU RAALI/RE Register Strobe.

Selects the data to be strobed into the RAAU and RE registers by con trolling several switches and adders in the unit 722.

APQ) ZAPA Switch, ZAPB Switch, (Type A=3) AP Adder Control.

Selects ZAPA and ZAPB switch outputs and the AP adder function applied to them.

ZRSC ZRSC Switch Control.

(Type A=O) Selects the output of ZRSC Switch.

N/A RLEN RLEN Strobe Control.

(Type A=3) RLEN strobes are also controlled by hardware or by the MISCREG field.

FMT Format Flag.

Indicates the type of format.

TYPF Indicates the type of overlayed fields.

00=Scratchpad Address 01 =Character Unit Control 1 0=Multiply/Divide Control 11 =N/A RFU Reserved for Future Use.

CHROP Character Unit Op Code.

Selects main operation to be per formed by Character Unit and the interpretation to be given to the CHSUBOP field.

1 0001 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Load Data MOP Execute Compare Single Compare Double Load Register Update CN Undefined Set RCH Operation A Set RTF 'I Set RT172 Set RTF3 Set RCN 1 Set RCN2 Set Edit Flags CH Unit Clear 5) 6) 7) 8) 9) 10) 11) 12) 13) 14) 15) RCH RCH Register Strobe.

Strobes the OP 1 RCH register.

RFU Reserved for Future Use.

SPA Scratchpad Address.

Contains the address that may be used to address the EU scratchpad.

N/A GB 2 114 783 A 20 Bits 94-97 CHSUBOP Character Unit Sub-Op Code.

Selects the detailed function of the Character Unit or it may contain a con stant. The interpretation of this field is a function of the CHWOP 5 control as showii below.

CHROP=0000 No Operation CI-ISUBOP,-3 XXXX No interpretation CHROP=0001 Load Data Operation 10 CI-ISUBOP,_1 (Suboperation) 00 OP1 LoadbyCl\11 andTFl 01 OP 1 Load in Reverse by CN1 and TH 10 OP2 Load by CN2 and TF2 15 and Test Character 11 Load Sign CHSUBOP2-, (Fill Control) 1X Fill character loaded to ZCLI 20 xl Fill character loaded to ZCV CHROP=0010 MOP Execute Operation CI-ISUBOP,-, (Suboperation) 00 MOP set by CN2 25 01 MOP Execute Undefined 11 Undefined CHUBOP2-3 XX No interpretation 30 CHROP=0101 Load Register Operation CI-ISUBOP0-1 (Selects output of RCH) CHSUBOP2-3 (Selects output of ZOC switch) CHROP=1011 Set RTF3 Operation 35 CI-ISUBOP,-, (Selects data to be inspected for 00, indicat ing a 9-bit character.) CI-ISUBOP2-3 (Constant Field)

CHROP=1110 Set Edit Flags Operation 40 CI-ISUBOP0-3 (Constant selecting flags to be set) 1XXX Set ES (End suppression) xixx Set SN (sign) Xx1x Set Z (zero) 45 X= Set BZ (Blank When Zero).

Bits 94-97 RFU Reserved for Future Use.

Bits 97-97 N/A Bit 98 TYPG TYPE G FLAG.

Indicates the type of overlayed fields. 50

O=BRADRU field

1 =IND6 field

Bit 99 GO State of Conditional Branch Test.

Bits 99-106 BRADRU Branch Address Upper. 55 Bits 99-106 IND6FLD Indicator Control.

Selects an indicator.

Bits 99-106 Bit 99=0 specifies a change indica tors instruction.

Bit 99=1 specifies a set/reset indi- 60 cators instruction (set or reset indicated by X bit 0 or 1 respectively).

21 GB 2 114 783 A 21 Bits 100-104 105= 1 106=1 0000 1 100X Exhaust 1 Exhaust 2 1101X Exhaust 3 N/A 11 10X Exhaustl Exhaust 2 Eff. Eff.

Bits 107-112 BRADRL BRANCH ADDRESS LOWER.

Contains lower portion of an ECS address used for branching.

Bit 113 EXIT Selection of Exit Switch Con- 10 trol.

Selection of Exit indicates end of microprogram.

Bits 114-116 ZCS13RA ZCSBRA Switch Control.

Defines the position to be selected 15 in a Control Store Branch Address Switch.

Bits 117-118 N/A Bits 119-123 INDGRP Conditional Branch Indicator Group Control. 20 The first two bits (119-120) select the 11 group" of microprogram indicators.

The last three bits (121-123) select the "set" of indicators within each 11 group---). 25 Bit 124 TYPH Type H field.

Indicates the type H overlayed fields.

O=INDMSKU 1 =VCTR field

Bits 125-128 INDMSKU Conditional Branch Indicator 30 Mask Upper.

Contains the upper 4 bits of the indi cator mask in type H=0 field.

Bits 125-129 VCTR Vector Select.

Selects the branching vectors to be 35 strobed into the RV130, RV13 1 and RV132 registers. The most significant bit (125) determines which of two groups 0 or 1, 2 or 3 and 4 or 5 will be strobed into the FIVI30, RV13 1 and RV132 40 registers respectively. The remaining 3 bits select the vector within each group.

Bits 129-132 INDMSKI- Conditional Branch Indicator Mask Lower. 45 Contains the lower 4 bits of the indicator mask.

Bits 133-135 N/A Bits 136-139 CNSTU Constant Upper.

Contains the upper 4 bits of the con stant field. 50

Bits 140-143 CNSTL Constant Lower.

Contains the lower 4 bits of the con stant field.

Control logic unit 704-1 This unit includes the sequence decode logic circuits 704-100 as mentioned whose outputs feed a plurality of 1 cycle control state flip-flops of block 704-102. These flip-flops in response to signals from the circuits 704-100 as well as microinstruction signals from register 701-4 MMEMR038-40 which corresponds to the mem address field MEMADR of Figure 6b) generate the various required 1 cycle control states required for the execution of program instructions. It is assumed 22 GB 2 114 783 A 22 that block 704-102 also includes gate circuits which generate register hold signals (HOLDEOO) which are distributed throughout the processor 700.

As seen from Figure 3c, the 1 cycle control state flip-flops receive control input signals via control lines including a line CPSTOPOO from cache unit 750. As explained herein, the state of the CPSTOPOO line determines whether processor operation continues in that when the line is forced to a binary ZERO, 5 the hold or enabling signals for the 1 cycle control state flip-flops and other storage registers are also - forced to ZEROS. The hold signals corresponding to signals [HOLD100 and [HOLDEOO operate to hold or freeze the state of the processor 700. Since no incrementing of the control store address can take, the ECS control store reads out the same microinstruction word. The signals [HOLDI and [HOLDE are set in accordance with the following Boolean expressions: [HOLDI=CACHE HOLD+TERMB (DREQ-IF- 10 DIR)+HOLD REL wherein the state of signal CACHE HOLD corresponds to the state of signal CPSTOP, the states of signals TERMB (DREQ-IF-DIR) are binary ONES during control state FPOA when the cache command specifies an 1 fetch or direct operation and the signal HOLD REL is a binary ONE until switched to a binary ZERO by the generation of a microprogram release signal; and [HOLD E=[HOLD 1.

As seen from Figure 3c, signals corresponding to the 1 cycle control states are applied as inputs to 15 a plurality of control flip-flops of block 704-104, decoder circuits of block 704-106, a number of control logic circuits of block 704-108 and to a plurality of control flag indicator flip-flops of block 704-110. It is also seen that the various indicator flip-flops of block 704-110 also receive microinstruction input signals via lines MEMD054-57 from execution control unit 701-4.

As seen from Figure 3c, signals generated by the hardware control logic circuits 704-108 fall 20 into one of three groups as a function of the units whose operations are being controlled. That is, the groups are instruction buffer control, hardware control and hardware memory control.

In each case, each group of signals are ored together with equivalent signals generated by other sources and then decoded. The other sources correspond to fields within the two different formats of the microinstruction word of Figure 6a which are loaded into RCSR register 704-112 from the ECS 25 output register 701---4.

One field corresponds to bits 32-83 of one format (large CU) and another field (short CU) corresponds to bits 32-41 of another format. These fields are decoded by a decoder 704-114 into the sets of bits indicated and combined within the decoders 704-116, 704- 124, 704-126 and 704128 as shown. Further decoding is done by the circuits of blocks 704- 118, 704-135 and 704-120. The results of decoding such fields are either distributed throughout processor 700 or are stored in an RMEM register 704-130, an RSZ flip-flop 704-132, an FREQDIR flip-flop 704-136 and an FREQCAC flip-flop 704-134.

Additional decoding of the large and short CU fields and signals from the 1 cycle state circuits of block 704-112 is done via a decoder 704-106 and 704-107. The decoder 704- 106 generates control signals for loading different ones of the registers and for enabling various multiplexer/selector switches within the processor 700. The decoder 704-107 operates to generate signals for setting and resetting a pair (RBASB) of base pointer B flip-flops 704-144. Other combinations of these signals are used to set and reset the descriptor number flip-flops of blocks 704-140 and 704-142.

As seen from Figure 3c, the decoder 704-116 receives a control signal [EXHOO generated by 40 the decoder circuits of block 704-117. These circuits receive signals from the RDESC register 704 and signals from the exhaust flip-flops of block 70 1-1. In accordance with the states of these signals, the circuits force signal [EXHOOO to a binary ZERO to inhibit the generation of a cache memory command upon the occurrence of an exhaust condition. The signal [EXI-1000 is generated in accordance with the following Boolean expression:

[EXI-1000=DESCO. FE1 1 +DESC1. FE2+DESC2. FE3.

The flip-flop FNUM is normally set in response to the CCS-OP field of the microinstruction word. When set to a binary ONE, this indicates that the descriptor being processed is a numeric type.

The different flip-flops of block 704-104 will now be discussed in greater detail. In greater detail, the flip-flop FCHAR provides certain changes in the control of address generation. When the FCHAR flip-flop is set to a binary ONE during the processing of a load type instruction specifying character modification, then the contents of the RDI register is not changed under hardware control This allows the RDI register to be loaded with data under microprogram control prior to starting the pipeline. Also, if the FCHAR flip-flop is set to a binary ONE during a store type instruction specifying character modification, then the execution address for this instruction is modified under hardware control to point to a unique address of the microinstruction sequence in the ECS control store that is to process this type of instruction.

The flip-flop FDT-FOUR provides additional control on the readout of the address register (ZAR,_j of block 704-304. Flip-flop FADR-WD provides additional control for the ZDO switch 704-340. When this flip-flop is set to a binary ONE, then the ZAR position of the ZDO switch is forced 60 to select a word address. The flip-flop FADR-B provides additional control for the ZDO multiplexer switch. When set to a ONE, then the ZAR position of the ZDO switch is forced to select a byte address.

The flip-flop FNUM is normally set in response to the CCS-OP field of themicroinstruction word. When

23 GB 2 114 783 A 23 set to a binary ONE, this indicates that the descriptor being processed is a numeric type. The flip-flop FIG-LEN provides additional control over the loading of registers within the unit 722 (length registers) and over memory operations. When set to a binary ONE, the RXP and RI-N registers within unit 722 are not loaded from the RSIR register 704-154 during certain processor control states FPOP.

The FINH-ADR flip-flop inhibits the operation of the address preparation unit 704-3. When set to a binary ONE, an address cycle (FPOA/FPOP) consists of adding the contents of a temporary effective address register REA-T+ZERO. The register REA-T will have been loaded with the address prior to doing a FPOA/F1POP cycle. The FABS flip-f lop enables the generation of absolute addresses.

When set to a binary ONE, a 24-bit absolute address is used. As concerns the flag or indicator flip-flops of block 704-110, flip-flop FID when set to a binary ONE provides an indication that indirect address 10 modification during an instruction is required on the descriptor loaded into the RSIR register.

The FRI-flip-flop when set to a binary ONE indicates that the length is specified in a register associated with the instruction loaded into various instruction registers. The three flip-flops FINDA, FINDB and FINDC provide indications used in processing memory type instructions. Flip-flop FINDA is set to a binary ONE when length is specified in a register or when flip- flop FAH is set to a ONE. Flip-flop 15 FINDB is set to a binary ONE when the descriptor does not include nine bit characters. The flip-flop FINDC is set to a binary ONE when the descriptor does include six bit characters.

The FAH flip-flop is set to a binary ONE when the processor circuits detect that indicator bit 30 of IR register 701-41 was set to a binary ONE during the execution of an EIS instruction indicative of a mid instruction interrupt (required to adjust pointer and length values because of interrupt). The FTRGIP, 20 TTNGO and FTI1F-TST flip-flops are set to binary ONES in conjunction with transfer type instructions. More specifically, the FTRGP flip-ffop provides a microprogram indication of being set to a binary ONE when the processor circuits detect the read out of a transfer type of instruction during the execution of an execute double (XED) or repeat (RPTS) instruction. The FTNGO flip-flop provides a microprogram indication of being set to a binary ONE when the condition of transfer signalled by the execution control 25 unit 701 was transfer NO GO (i.e., transfer did not take place). The output of this flip-flop is applied to the NO GO line of interface 604. The FTRF-TST flip-f lop of this group indicates when set to a binary ONE that the previous instruction executed by processor 700 was a transfer type instruction and that the current 1 cycle is to be executed conditioned upon the presence of a transfer GO (TRGO) signal from control unit 701.

Additionally, the circuits of block 704-110 include a number of flipflops used in performing indirect addressing operations under hardwired control for other than EIS instructions. These include FIR, FIRT, FIRL and FRI flip-flops which are switched to binary ONES as functions of the different types of indirect address modifications required to be performed. For example, the FRI flip-flop signals a register then indirect address modification and is switched to a binary ONE when a register indirect (R1) indicator is a binary ONE. The FIR flip-flop is switched to a binary ONE when an indirect then register (I R) indicator is a binary ONE. This flip-flop signals the beginning of an indirect then register address modification. The FIRL flip-flop is switched to a binary ONE when an indirect then tally indirect (IT-1) indicator is a binary ONE. This flip-flop signals a last indirect operation. Another flip-f lop TEX2 provides an indication used in processing transfer and set index instructions while a STR-CP13 flip-flop Is used 40 during the processing of store instructions.

As seen from Figure 3c, the outputs from the control flag flip-flops of block 704-110 are applied as inputs to the branch indicator circuits of block 70 1-1. Also, output signals from the control flag flip-flops are also applied as inputs to the 1 cycle flip-flops of block 704-102.

Register section 704-150 45 As seen from Figure 3c, the control logic unit 704-1 further includes a register section 704 150. This section contains the basic instruction register (RBIR) 704-152, the secondary instruction register (RSIR) 704-154, a base pointer A register (RBASA) 704-156 used for selecting one of the address registers RARO through RAR7 of block 704-304, a read index register A (RRDXA) 704-158 used for selection of index registers included within section 704-5 (not shown) and for selection of 50 outputs from the ZDO multiplexer switch 704-340, a read index A save (RRIDXAS) register 704 159, and a desbriptor type register (RTYP) 704-160 indicating the type of data characters being pointed to by the descriptor value (e.g. 9-bit, 6-bit, 4-bit). The section 704-150 further includes a 1 - bit instruction/EIS descriptor register designated R29 of block 704-162. The state of this bit in conjunction with the contents of the RBAS-A register 704-158 are used to select the particular 55 address register used for address preparation. When register R29 of block 704-162 is set to a binary ZERO, this indicates that none of the address registers of block 704-304 are used during address preparation. The last registers of section 704-150 include the data in register (RDI) of block 704 164 and a read index register B (RRDXB) pointing to registers used by execution unit 714.

As seen from Figure 3c, the BRI R registir-704-1 52 is loaded via a two position switch 740- 60 connected to receive signals from the source indicated (i.e., a switch ZIB-B 704-172 and lines ZDi 0-35). The RSIR register 704-154 similarly receives signals from the Z1)l lines and switch 704-172. The RBASA register 704-156 receives signals from the ZDI line 02 in addition to a further switch ZBASA of block 704-174. The RF1DXA register and RTYP register receive signals from 24 GB 2 114 783 A 24 the M1 lines as well as switches 704-176 and 704-178 as shown. Also, the RRMA register receives signals from the RRMAS register 704-159.

The switch 704-172 is a two position switch which receives inputs from the switches ZIB and Z1RES13 from the cache unit 750 and execution unit 714 respectively. The switch 704-174 is a three input switch which receives two inputs from the execution unit 714 and the output of the ZIB switch of 5 cache unit 750.

Switch 704-176 is a four input switch which receives two of its inputs from the execution unit 714 and a single input from cache unit 750. The first position of the ZRDXA switch 704-176 selects the output of a ZRDXM switch 704-185. One position of this switch provides a tag field value from bit positions 5-8, 14-17, and 32-35 of the RBIR register 704-152 and bit positions 32-35 of 10 the RSIR register 704-154 selected from ZIDD switch 704-180 and a two postion ZMF switch 740-176.

The second position of switch 704-185 provides a constant value from the output of the ECS output register 704-1 (CCM field 32-34). The signals from the lines ZIDD 27-35 are applied as inputs to control flag flip-flops of block 704-110. The switch 704-178 receives an input from the 15 control store 704-2, an input from cache unit 750 and an input from execution unit 714.

The data input register 704-164 receives a series of input signals from a ZI DD switch 704 which connects in series to a MIA switch 704-181 whose output provides one input of a further switch 704-182 which directly loads into the RDI register 704-164. The MIA switch 704-181 provides a further input to a three input switch 704-183 which receives the other inputs indicated 20 from cache unit 750 and execution unit 714.

The ZIDD switch 704-180 receives an effective address via switch 704-186 from the address preparation unit 704-3 as well as inputs from the RBIR register 04-1 52, the RSIR register 704 154 and a two position ZMF switch 704-187. The positions 18 through 35 of the REA position of switch 704-180 are derived from the MIA switch 704-181 as shown. The MIA switch 704-181 25 receives signals from the M1 lines 0-35, a constant value generated from the inputs to a first switch position in addition to signals from the output of the ZIDD switch 704-80 and the ZRESB switch in execution unit 714. The switch 704-182 receives the output of the MIA switch and signals from the W1 lines 0-35. The RF1DX13 register 704-189 is loaded by a three position switch 704-188. The switch receives via a first position signals from a RREG register included in the execution unit, a 30 constant value from control store 701-2 via a second position and signals from the ZIDD switch via a third position.

The section 704-150 further includes a two position switch 704-185 and a scratchpad pointer register 704-186 whose output is used by the AAW 722 to form addresses for access to the scratchpad memory of the EU 714. The first switch position provides a constant value and is selected 35 under hardware control (FPOA. R29). The second switch position applies as an output the contents of the RBASA register 704-156. This position is selected under both hardware and microprogram control (i.e., FPOA. R29 or MISCREG field).

It will be appreciated that the required timing signals for operating section 704 as well as other 40sections of processor 700 and cache unit 750 are provided by centrally located clock circuits. For example, in the preferred embodiment of Figure 1, the clock circuits are located within the input/output processor system. Such clock circuits can be considered as conventional in design and can comprise a crystal controlled oscillator and counter circuits. The timing or clocking signals from such clock circuits are distributed in a conventional manner to the various portions of the system of Figure 1 for synchronized operation. From such timing signals, circuits within processor 700 derive additional clocking signals as required. This will be described in greater detail with respect to the cache unit 750 of Figure 4.

Address preparation unit 704-1 The address preparation unit 704-3 includes a number of registers and adders. The registers include a number of base registers (i.e., TBASEO through TBASEB) of block 704-300 used for storing 50 descriptor values of an instruction, a pair of temporary effective address registers (TEAO, TEA1) and a pair of instruction counters (ICBA, ICEB) included within block 704-302 used for addressing the instruction buffer and eight address registers (RARO through RAR7) of 704- 304 used during address preparation operations. The unit 704-3 also includes an instruction counter 704-310.

The adders include adder 704-312 used to update instruction counter 304310 via switches 55 704-311 and 704-314 and a pair of adders 704-320 and 704-322. The adder 704-322 is used to generate an effective address value which is stored in a register 704-342 applied as an input of the control unit 704-1. The effective address is generated from a number of sources which include ZY switch 704-326 whose output is applied via a number of AND gates of block 704-327, selected address registers of block 704-304 or selected temporary address registers TEAO and TEA1 of block 60 704-302 applied via another switch 704-328 or the index address signals ZXO-20 from unit 704-5. Additionally, adder 704-322 is used to update the contents of the instruction counter of the cache instruction buffer.

GB 2 114 783 A 25 As seen from Figure 3d, the outputs from adder 704-322 are also applied as an input of the adder 704-320. The adder 704-320 is used to combine base value stored in any one of the temporary base registers TBASEO through TBASEB with the address signals ACSOSO-1 9 from adder 704-322. The resulting bits are applied as an input to a further adder network 704- 320 which generates a logical address which is applied to the lines ASFAO-36 via an adder 704-32 1. This adder sums the operand inputs together with the carry inputs from blocks 104-300 and 704-320. The effective address is used to obtain an absolute address when the system is operated in a paged mode. Since this operation is not pertinent to the present invention, it will not be discussed further herein. For further information regarding such address development, reference may be made to U.S.

Patent No. 3,976,978.

The temporary base registers of block 704-300 are loaded via a switch 704332. The switch receives an input from the execution unit 714 and the output from block 704-300. The execution unit 714 applies further inputs to the registers of block 704-302 via a switch 704-334 as well as to the address registers of block 704-304. An output multiplexer (M0) switch 704340 enables the selection of the various registers within the address preparation unit 704-3 and unit 704-5 for 15 transfer of their contents to the execution unit 714 via lines WO 0-35. Also, the ZSO switch 704 340 enables the contents of various ones of the registers and control flip-flops of unit 704-1 to be read out via a fourth position (ZDO-A). The fifth position ena bles the states of various indicators within the control store circuits of block 701 -1 to be selected for examination.

Data/address output section 704 4 figure 3e The section 704-4 includes the registers and switches used for transferring commands and data to the cache 750. Such transfer operations normally require at least two cycles, one for sending an address and another for sending the data. Bits 5-8 of a command word are derived from the output of a four position switch 704-40. This switch receives a first constant value via a first position, the contents of a RM register 704-42 via a second position, a second constant value via a third position and a third constant value via a fourth position.

Bits 1-4 of a command are applied by the circuits of block 704-1 to an OR gate circuit 704 44 together with bits 5-8. The OR gate 704-44 also receives via a ZADO switch 704-46 bits 1 - 8 of an RADO register 704-48. The RADO register 704-48 is an address and data out register which receives via a first position of a ZADOB switch 704-48 a logical (virtual) address from address 30 preparation unit 704-3 via the lines ASFAO-35 and data output signals from the EU 714 via lines Z13ESBO-35. The positions of the ZADOB switch 704-48 are under the control of the FIVITI) field for small CU format and the RADO field in the case of large CU format.

As seen from the Figure, either the ZM 1-8 bits or the ZADO bits 1-8 are applied as outputs to the RADO/ZADO lines as a function of the state of control signal [RADO- ZADO. Bits 0 and 1 are always 35 binary ONES while bits 10-35 are furnished by the RADO register 704-46 - For additional information regarding the remaining sections of processor 700 as well as the sections of Figures 3a through 3e, reference may be made to the copending applications referenced in the introductory portion of this application.

Cache unit 750-Figure 4 General description

The cache unit 750 is divided into five primary sections: a transit buffer and command queue section 750-1, a cache section 750-3, a directory and hit control section 750-5, an instruction buffer section 750-7 and an instruction counter section 7 50-9.

Transit buffer and command queue section 750-1 The transit buffer and command queue section 750-1 includes as major elements a four word write command buffer 750-100 and a four word transit block buffer read command buffer 750-102 which are addressed via a pair of counter circuits 750-104 and 750-106 in addition to a command queue 750-107 with associated in and out address pointer and compare circuits of blocks 750-108 through 750-110. The write buffer 750-100 provides storage for two write single or one write double command while the transit block 750-102 provides storage for up to four read type commands. The transit block buffer 750-102 also stores information associated with such read commands used in controlling the writing of memory data words into assigned areas (i.e., levels) of cache section 750-3. The four registers allow up to four memory reads to be in progress at any given time.

Section 750-1 also includes a control section 750-112. This section includes sets of different control circuits such as the command decoder and control circuits of blocks 750-113 and 750-114, the interface control circuits of blocks 750-115 and 750-116 and hold control circuits of block 750-117.

The circuits of blocks 750-113 and 750-114 decode the signals applied to the DMEM lines 60 representative of commands transferred by processor 700 via-the RADO/ZADO lines of interface 604 and generate the control signals for making entries in the command queue 750-107, incrementing 26 GB 2 114 783 A 26 and setting values into the in pointer and out pointer circuits of blocks 750-108 and 750-109. Also, the circuits generate control signals for storing commands into either write buffer 750-100 or transit block buffer 750-102.

The interface control circuits of blocks 750-115 and 750-116 generate signals for controlling the transfer of data signals received from SIU 100 into section 750-7 and for commands including the transfer of such commands to the SIU respectively. The hold circuits of block 750-117 which receive signals from decoder circuit 750-113 generate control signals for holding the execution of commands in appropriate situations (e.g. directory section busy) and controlling the loading of data into section 750-7.

As seen from Figure 2, the transfer of write command control words proceed from buffer 750- 10 via the third position of four position (ZDTS) switch 750-118, a data register 750-119 and the first position of two position switch 750-120. The write data words are transferred from buffer 750-100 to SIU 100 via a write data register 750-121 and the second position of switch 750 120. The RWRT position of switch 750-120 is selected for one (write single command) or two (write double command) clock intervals following receipt of a signal from SIU 100 via the ARA line made in 15 response to a signal placed on line ACIPR by cache 750 for transfer of the write command. Read commands are transferred from the read command portion of transit block/buffer 750-102 to SIU via the fourth position (ZTBC) of the WTS switch 750-118, register 750- 119 and the first position of switch 750-120.

The multiport identifier lines MITS receive zone bit signals via a RMITS register 750-124 and a 20 two position switch 7 50-12 5 for the second data word in the case of a write double command. As seen from the Figure, this switch receives signals from command queue 750- 107 and processor 700.

That is, when cache 750 issues a read command, transit block number signals from queue 750-107 are loaded into bit positions 2 and 3 of RMS register 750-124.

The transit block number signals are returned by SlU 100 on the MIFS lines with the read data word. These signals are loaded into an RMIFS register 750-127 via a multiposition switch 750 126. Thereafter, the contents of bit positions 2 and 3 are applied via the first position of a two position switch 750-128 to a pair of address input terminals of transit block buffer 750-102. A second RMWSB register 750-129 primarily provides temporary storage of the transit block number signals for multiword transfers (i.e., quad read commands).

The output signals from switch 750-128 are also applied to the control input terminals of a four position ZTBA switch 750-130 for selecting the appropriate address signals to be applied to cache section 750-3 for storage of the data words. The address contents of the transit block buffer 750 102 are also applied to one set of input terminals of a predetermined one of a group of compare circuits 750-132 through 750-135 for comparison with the address portion of a next command 35 applied to a second set of input terminals of the comparator circuits via the RAD0/ZADO lines. The result of the comparisons generated by a NAND gate 750-136 is applied to the hold control circuits of block 750-117.

As seen from Figure 4, the zone bit signals of the ZAC command applied to the ZADOB lines 5- 8, in the case of a write single command, or for the even word of a write double command, are loaded 40 into a RZONE register 750-140 when the write command is loaded into write command data buffer 750-100. The output of RZONE register 750-140 is applied to the first position of a two position ZONE switch 750-144. The zone bit signals applied to the lines M0-3 by processor 700 for the odd word of a write double command are loaded into a R= register 750-142. The output of RDZD register 750-142 is applied to the second position of ZONE switch 750-144. The output signals 45 ZONEO-3 are applied to the circuits of section 750-9 for controlling the writing of processor data into cache 750-300 as explained herein.

Cache section 750-3 The section 750-3 includes a cache store 750-300 having 8192 (M) 36-bit word locations organized into a 128 sets of eight, eight word blocks. The unit 750-300 is constructed from bipolar 50 random access memory chips, conventional in design.

The cache storage unit 750-300 is addressed by a 1 0-bit address RADR 2433 applied via any one of a number of 4x4 crossbar switches (e.g. 750-302a), conventional in design and the address registers associated therewith. As seen from the Figure, the crossbar switch receives address signals from several sources which include section 750-5, ZTBA switch 750130 and section 750-7. The address signals appearing at the output of the crossbar switch are temporarily stored in the associated address register and applied to the address input terminals of cache storage unit 750 300.

During a write cycle of operation, the four sets of write control signals (WRT001 00-WRT701 00 through WRT03100-731 00) generated by section 750-9, are applied to the cache storage unit 60 750-300 and are used to apply or gate clocking signals to the write strobe input terminals of the memory chips. This enables from one to four bytes of either a processor 700 data word from the ZADO/RADO lines or a memory data word from section 750-7 to be written into the addressed one of eight levels of cache storage unit 750-300. For processor data, the write signals are generated by c 27 GB 2 114 783 A 27 decoding signals ZONEO-3 from switch 750-144. For memory data words, all of the zone signals are forced to binary ONES.

The appropriate level is established by the states of signals RTBLEVO 1002100 from transit block buffer 750-102 when writing memory data and by the hit level detected by directory circuits of block 750-512 when writing processor data. These signals are decoded by a decoder circuit 750- 5 303 when enabled by a signal ENBIVIEMLEV1 00 from section 750-9.

During a read cycle of operation, the 36-bit word of each of the eight blocks (levels) is applied as an input to a 1 of 8 ZCD switch 750-306. The selection of the appropriate word is established by the states of a set of hit level signals ZCD01 0-210 generated by section 750- 5. These signals are applied to the control input terminals of ZCD switch 750-306.

As seen from the Figure, the selected word is applied to a pair of registers 750-308 and 750 310, a 1 of 8 ZDI switch 750-312 and a 1 of 4 ZIB switch 750-314. The RIRA and RIRB registers 750-308 and 750-310 apply their contents to different positions of the ZIB and ZDI switches 750-312 and 750-314. The ZIB switch 750-314 selects instructions which are applied to the instruction bus (ZIB) of processor 700 while the ZDI switch 750-312 selects data or instructions which are applied to the data in bus (ZDI) of processor 700.

In addition to applying instruction word signals read out from cache 750300, the ZIB switch 750-314 also applies instruction word signals received from section 750-7 to processor 700. The ZDI switch 750-312 also applies data signals received from the ZCIDIN switch 750-304 and section 750-7 to processor 700. The states of the control signals [MB01 0-110 and [Z1)101 0-210 applied 20 to the control input terminals of switches 750-314 and 750-312 select the sources of instructions and data words to be transferred to processor 700 by such switches. The control signals are generated by the circuits of section 750-9.

In greater detail, the [M1301 0-110 signals are coded to select position #2 of switch 750-314 for a first instruction transfer in response to the detection of a directory hit for an 1 fetch 1 command or 25 a directory hit for an 1 fetch 2 command following an 1 fetch 1 command to the last word in a block. The control signals are coded to select the RIRA position #1 for subsequent instruction transfers following a directory hit generated in response to an 1 fetch 1 or 1 fetch 2 command.

Where the 1 fetch 1 or 1 fetch 2 command results in a directory miss, the [Z11301 0-110 signals are coded to select position #3 of ZIB switch 750-314 for transfer of instruction words received from 30 section 750-7.

As concerns the ZDI switch 750-312, the ZCD position #1 is selected in response to the detection of directory hits and signals applied to the RIDIBUF/ZM line in response to a directory hit generated for a LDQUAD command. Memory data words are transferred to processor 700 via the ZDIN position #3 of the switch 750-312 following a directory miss. Following holding processor 700 for 35 an instruction fetch from main memory, the signals [Z1)101 0-210 are coded to select the ZDIN position of switch 750-312 for transfer of the first instruction upon its receipt by section 750-7.

The remaining instructions are transferred via ZIB switch 750-314.

The ZCDIN position #2 of switch 750-312 is used for diagnostic purposes to transfer signals from the ZADO-13/RADO lines. The remaining positions of ZDI switch 750- 312 are used for display 40 purposes (i.e., positions RIRB, ZRIB and RIRA). Also, position RIRB is selected to transfer data words to processor 700 in the case of a LDQUAD command when there is a directory hit.

Directory and hit control section 750-5 This section includes an eight, level control directory 750-500 and eight level set associative address directory 750-502. The directory 750-502 contains 128 locations, each location containing a 14-bit associative address for each level. A four position ZDAD switch 750-530 provides the random access memory (RAM) addresses for addressing directories 750- 500 and 750-502 in addition to cache storage unit 750-300.

During a directory search cycle of operation, switch 750-530 under the control of signals SELZDADC0100-1 100 generated by circuits within a block 750-526 selects RADO position 0. This 50 applies the 14-bit address signals of a ZAC command from lines RADO 24-33 from processor 700 to the output terminals of the ZDAD switch 750-530. These signals are applied to the address input terminals of directories 750-500 and 750-502. During the search cycle, the contents of eight block/level addresses are read out and applied as one input of each of a group of eight comparator circuits 750-536 through 750-543. Each comparator circuit compares its block/level address with 55 bits 10-23 of the ZAC command to determine a hit or miss condition. The results generated by the circuits 750-536 through 750-543 are applied to corresponding inputs of a group of AND gates 750-545 through 750-552. Each comparator circuit is made up of four sections, the results of which are combined in one of the AND gates 750-545 through 750-552. The final result hit signals ZHT01 00 through ZHT71 00 are applied as inputs to hit/miss network circuits of block 750-512 as 60 explained herein.

The ZAC address signals are also saved in an RDAD register 750-532 when no hold condition is detected (i.e., signal [HOLD-DIVIEM from 750-112 is a binary ZERO). During the directory assignment cycle following the search cycle which detected a miss condition, signals SELZDADCO 100-100 28 GB 2 114 783 A 28 select RDAD position 1 of MAD switch 750-530. Also, a RDRINregister 750- 534 is loaded with the 14-bit associative address signals from the ZADO-B lines 10-23 when the directory search cycle is completed for writing into the directory 750-502.

The control directory 750-500 also includes 128 locations, each having a predetermined number of bit positions for storing control information. Such information includes the full-empty (F/E) 5 bits for the eight levels and round robin (M) count bits in addition to parity check bits (not shown).

The full-empty bits indicate whether the pafticular directory addresses have any significance (i.e., are valid). For a cache hit to occur, the F/E bit must be set to a binary ONE. A binary ZERO indicates the presence of an empty block or portion thereof. The round robin bits provide a count which indicates which block was replaced last. This count when read out via the switch 750-504 is normally incremented by one by an increment adder circuit 750-508. The resulting signals MTRRO-RR2 are written into directory 750-500 to identify the next block to be replaced.

As seen from the Figure, the F/E bit contents of the location are read out via the positions of a two position ZFER selector switch 750-506 and applied as inputs to the directory hit/miss and hit control circuits of block 750-512. The ZFER switch 750-506 selects which half of a group of F/E bits are to be used by the circuits of block 7 50-512 for a hit/miss indication and which half of the group of F/E bits are to be used by such circuits for an alternate hit determination. An address bit signal ZDAD31 controls the selection of switch positions.

The circuits of block 750-510 include a multisection multiplexer circuit which generates the output signals FEDATO1 00 and FEDAT1 100 as a function of the hit and miss data pattern.

Accordingly, these signals are set in response to the ALTHIT signal from the circuits of block 750 512. A pair of decoder circuits 750-520 and 750-521 operate to decode the level information signals ZLEV01 00-2100 for generating appropriate sets of write enable strobe signals R/WFE01 0 210 and R/WLVO1 0-710 for control directory 750-500 and address directory 750-502. Thus, level (ZLEV) switch 750-522 operates to control the level at which F/E bits are set or reset and the level in the address directory 750-502 at which new addresses are written during a directory assignment cycle of operation. - As seen from the Figure, the first position of ZLEV switch 750-522 when selected, applies to its output terminals signals OLDRI'l01 0-210 from directory 750-500. The second position of switch 750-522 when selected applies to its output terminals signals RLEVRO-R2 from a level register 750-524. The level register 750-524 is used to save the last set of hit level signals generated by the hit/miss level network circuits of block 750-512. This permits the hit level value to distribute to other sections of cache 750 for subsequent use (i.e., signals RHITLEVO-2).

The third position of switch 750-522 when selected applies to its output terminals, signals LEVRO-R2 generated by the circuits of block 750-512. The switch 750-522 is controlled by signals from control flip-flops included within block 750-526 (i.e., signals FBYPCAC and DIRBUSY).

As seen from the Figure, the complements of the level signals stored in register 750-524 corresponding to signals RHITLEV01 0-210 are applied via a group of AND gates to control circuits within section 750-9.

During the search cycle of operation, the hit/miss level network circuits detect which level, if any, 40 contains an address which matches the ZAC address. In the case of a match, it forces signal RAWHIT1 00 to a binary ONE and generates therefrom the sets of hit level signals ZCD01 0-210 and HITLEVC7010-721 0 through an encoding circuit. The signals are generated in accordance with the states of the F/E bit signals ZFE01 0-710. That is, for a cache hit to occur at a given level, the F/E bit must be a binary ONE. As mentioned above, a binary ZERO indicates the presence of an empty block 45 level. Each encoder circuit includes AND/OR gating circuits, conventional in design which generate the level signals in accordance with the Boolean expression L i=,01 1 Ej=, ZHTj. ZFEj. Additionally, the signals ZCD01 0-210 also may be generated from the level signals ZNICLEVOOO-21 00 provided by section 750-9 during instruction fetches.

The block 750-512 also includes an alternate hit network which can also be used in the 50 assignment of an eight word block by generating an alternate hit signal ALTHIT1 00 and a set of signals ALTHITLEVO 100-2100 for loading into register 750-504 in place of the round robin assignment signals C7RRO1 00-2100. For the purpose of the present invention, such arrangements can be considered conventional in design. Reference may be made to U.S. Patent No. 3,820,078 listed in the introductory portion of this application.

As seen from the Figure, the circuits of block 750-512 generate other hit signals HITTOTB 100, HITTOC71 00 and HITTOIC1 00. These signals are derived from signal RAWHIT1 00 in accordance with the following Boolean expressions:

1. HITTOC71 00=RAWHIT1 00. BYPCACOOO.

2. HITTOIC 1 00=HITTOC71 00.

3. HITTOTB1 00=RAWHIT1 00. BYPCACOOO+PRERD1 00. BYPCAC1 00.

The circuits of block 750-512 receive the cache bypass signals BYPCACOOO and BYPCAC1 00 from block 750-526. As mentioned, this block includes a number of control state flip-flops which generate signals for sequencing the section 750-5 through various required operations for the processing of the various types of commands. Additionally, block 750-512 includes logic circuits for 65 k c 29 GB 2 114 783 A 29 generating required control signals during such operations. For the purpose of the present invention, these circuits may be implemented in a conventional manner. Therefore, in order to simplify the description herein, only a brief description and the Boolean expressions will be given for certain control state flip-flops and control logic circuits as required for an understanding of the operation of the 5 present invention.

Control state flip-flops The FJAM 1 flip-flop is set in response to a hit condition at the end of a directory search cycle for a read double command. The flip-flop holds the lower address bits in register(s) 750-32 enabling the accessing of the second word from cache storage unit 750-300 in the case of a read double command. Also, the flip-flop is set in response to a write single command to cause the selection of the 10 RDAD position of the MAD switch 750-530 for providing or causing the same address to be applied to cache storage unit 750-500 for one more clock interval or cycle. In the absence of a hold condition (signal [HOLDDMEM=1), the FJAM 'I flip-flop remains set for one cycle in accordance with the following Boolean expression:

SET=FJAM1=REQCOMB.RAWHIT.BYPCAC.(RDDBL+WRTSNG)+ HOLDDMEM. 17JAIV12+ HOWDIVIEM. FJAM1.

The FJAM2 flip-flop is set in response to a hit condition at the end of a directory search cycle for a write double command. The setting of the FJAM2 flip-flop causes the setting of the FJAM 1 flip-flop at the end of the next clock interval. The control state of the FAM2 flip- flop together with the FAM 1 flip-flop causes the selection of the RDAD position of MAD switch 750-530 for providing the proper 20 address for writing data into cache storage unit 750-300.

The FAM2 flip-flop also remains set for one cycle in accordance with the following Boolean expression:

SET=FJAM2=REWOMBO. RAWHIT. BYPCAC. WRTDBL+HOLDDMEM. FJAM2.

Aflip-flop NRIVIPTC1 directly controls the MAD switch 750-530 and is set in accordance with 25 the states of signals generated by the other control state flip-flops.

The NRMPTC1 flip-flop normally remains set for one cycle in accordance with the following Boolean expression:

SET=NRMPTC1=(WRTDBL. REWOMBO. RAWHIT. BYPCAC)+ FJAM2+SETI7JAM1 +REQCOMBO. (RDTYPE. BYPCAC+R13TYP. RAWHIT). (17JAM1. FAM2+ HOLD).

The MIRASN flip-flop specifies a directory assignment cycle of operation wherein an associative address entry is written into address directory 750-500 in the case of miss 6onditions or cache bypass operations for read type commands.

The MIRASN flip-flop is set for one cycle in accordance with the following Boolean expression:

SET=MIRASN=REWOMBO. RDTYP. (BYPCAC+RAWHIT).

The FICENAB flip-flop enables the loading of the instruction register and is set for one cycle in response to a 1/2 T clock pulse in accordance with the following Boolean expression.

SET=FI-IT100.

The FRCIC flip-f lop is set for one cycle in response to a 1/2 T clock pulse in accordance with the following Boolean expression.

SET=FJAWNICLEV.

Control logic signals 45 1. The ALTHIT signal indicates the presence of a pseudo hit condition. ALTHIT=ALTLEVO+ALTLEV1 ±--ALTLEV7. 2. The signals ALTHITLEVO, ALTHITLEV1 and ALTHITLEV2 provide a three bit code which specifies the level at which a pseudo hit condition occurred. The signals are coded as follows:

a. ALTHITLEVO=ALTLEV4+ALTLEV5+ALTLEV6+ALTLEV7.

b.ALTHITLEV1=ALTLEV2+ALTLEV3+ALTLEV6+ALTLEV7. c. ALTH ITLEV2=ALTLEV 1 + ALTLEV3 +ALTLEV5 +ALTLEV7.

GB 2 114 783 A 30 3. The signals ALTLEVO through ALTLEV7 indicate which one of the eight levels, if any, has detected a pseudo hit condition. a. ALTLEVO=ZI-ITO. ZFEO.

b. ALTLIEW=ZI-IT7. ZFE 4. The DIRADDE signal is an enabling signal for decoder 750-521 which allows the generation 5 of write strisi nals applied to address directory 750-500.

DIRADDE=NOGO. FIDIRASN.

5. The DIRBUSY signal indicates when the directories 750-500 and 750-502 are busy.

DIRBUSY=FI-SH+FAM2+FAM1 +FIDIRASN.

6. The FEDCODE signal is an enabling signal for decoder 750-520 which allows the generation 10 of write strobe signals applied to control directory 750-500.

FIEDCODE=MIRASN. NOW.

7. The FORCEBYP signal enables a cache bypass operation to take place.

FORCEBY1"=FSKIPIRR+FBMAC.

8. The GSRCH signal indic tes when a search cycle of operation is to take place.

GSRCH=RIDDBUCIDE. FICENAB. FRCIC.

9. The signals HITLEVC 70, HITLEVC71 and HITLEVC72 provide a 3-bit code which specifies the level at which a bit condition has occurred.

a. HITLEVC70=HITLEV4+HITLEV5+HITLEV6+HITLEV7.

b. Ht'TLEVC71=HITLEV2+HITLEV3+HITLEV6+HITLEV7.

c. HITLEW72=HITLEV1 +HITLEV3+HITLEV5+HITLEV7.

10. The signals HITLEVO through HITLEV7 indicate which one of the eight levels, if any, has detected a bit condition.

a. HITLEVO=ZFEO. ZHTO.

b. HITLIEW=ZFE7. ZHT7.

11. The RAWHIT signal indicates the detection of a hit condition. RAWHIT=HITLEV0±--+HITLEV7.

12. The HITTOC7 and HITTOIC signals each indicates the detection of a hit condition to certain circuits within section 750-9.

HITTOW=HITTOIC=RAWHIT. BYPCAC.

13. The HITTOTB signal indicates the detection of a bit condition of a pre-read command when in the bypass mode to the transit block buffer circuits. HITTOTB=RAWHIT. BYPCAC+PRIERID. BYPCAC.

14. The LDRAD signal enables the loading of the RDAD register 750-532.

I-DRIDAD=HOLDDMEM.

15. The I-DRIDRIN signal enables the loading of RDRIN register 750-534. LDRDRIN=FDIRASN.

16. The signal RIDIDBUME is used to enable the ZCD switch 750-306 in the case of a read double command.

RDDBLZCDE=FICENAB. (FIDIRASN+FAM 1 +FJAM2).

17. The REQCOMBO signal indicates the resence of a cache request.

REQCOMBO=RO-GO'. HC)LDDMEM. [CANCELC. DREWAC.

18. The ZCDO, ZCD1 and ZCD2 signals are used to control the operation of the W1) switch 750-306.

a. ZCDO=ZCDL4+ZCDL5+ZCDL6+ZCDL7+ZNICLEVO. WDICENAB+RDIDBLI-0.

b. ZCD1=ZCDL2+ZCDL3+ZCDL6+ZCDL7+ZNICLEV1. WIDICENAB+RDIDELL1.

c. ZCD2=ZCDLl +ZCDL3+ZCDL5+ZCDL7+ZNICLEV2. WIDICENAB+RIDDBLI-2 wherein the term(s) WIDU is WDLEVi.

19. The ZFEDATWT1 signal is a data write strobe signal used for writing F/E bit signals FEDATO 100 and FEDAT1 100 into directory 750-500.

ZFIEDAWT1 =FIDIRASN. MAD3 1.

20. The FEDATO1 00 signal corresponds to the first full/empty bit.

FEDATO1 00=FBYPCACOOO+FALTHIT1 00.

2 1. The FEDAT1 100 signal corresponds to the second full/empty bit.

FEDAT1 1 00=FALTHIT1 00+FBYPCACOOO.

22. The SELWADC1 signal controls the operation of the MAD switch 750-530.

*SELZDADC1=NRMPTC1.

91 1 1 31 GB 2 114 783 A 31 23. The RWRR signal is a round robin write signal used for writing the RR bit signals back into directory 750-500. IRWIRR=FIDIRASN. NOGO. SCLOERK.

It will be seen from the Figure that the different decoded command signals are generated by a decoder circuit 750-528 in response to the signals applied to the DMEM lines 0-3 by processor 700. The decoder 750- 528 is enabled by a signal from the DREQCAC line. The decoded command signals (e.g. WRTID131-, WRTSNIG, PRERD, RIDTYPE) together with other control signals such as [HOLIDDIVIEM, FSKIPIRROO and those from the lines [CANCELC and BYPCAC are applied as inputs to the circuits of block 750- 526.

Instruction buffer section 750-7 This section receives memory data and instructions from the DFS lines which are transferred to processor 700 via the W1 switch 750-312 and ZIB switch 750-314 respectively. The memory signals are loaded into an RDFS register 750-702 via one position of a two position switch 750700.

Memory data fetched as a result of amiss condition upon receipt applied to the W1 switch 750-15 312 via the RDFS position #0 of a 1 of 4 position (WIN) switch 750-708. In the case of a load quad command, memory data is loaded into the 4 location (WBUF) buffer 750-706 when the [WBUF signal is forced to a binary logical ONE. The write/read address signals [WRTBUFO1 011 0/[RDIBUFO1 0-110 from section 750-112 control the writing and reading of data into and from the locations of buffer 750-706.

The memory data stored in the WBUF buffer 750-706 is then transferred to the W1 via the IRWBUF position #2 of the WIN switch 750-708.

In the case of a read double command, the even word of the pair is transferred into a REVN register 750-710. Thereafter, the even word is transferred to the Z131 switch 750-312 via position #1 of WIN switch 750-708 for execution of a read double odd command request or upon receipt of 25 a RD-EVEN signal from processor 700.

As seen from the Figure, each memory data word is also loaded into the IRDFS13 register 750 712 and thereafter written into cache storage unit 750-300 via the WIDIN switch 750-304 at the level specified by the contents of the RADR register 750-32.

In the case of instruction transfers, each instruction received from memory is loaded into one of 30 the 4 storage locations of a specified one (IBUF1/IBUF2) of a pair of instruction buffers 750-715 and 750-717. The IBUF1 and IBUF2 buffers 750-715 and 750-717 are used to buffer up to two four word blocks that can be accessed from memory in response to 1 fetch 1 or 1 fetch 2 commands for which a miss condition has been detected.

The instructions are written into the location of one of the IBUFl and IBUF2 buffers 750-715 and 750-717 specified by signals [WIRTBUFO1 00-1100 under the control of write strobe signals [IBUFl/[IBUF2. Read control signals [RDBUFO1 00-1100 enable the read out of such instructions for transfer to processor 700 whenever the IBUFl or IBUF2 location specified by the signals [ZEXT01 00 1100 contains an instruction. The instruction is transferred to processor 700 via positions 1 or 2 of a two position switch 750-720 and the ZRIB switch position of the ZIB switch 750-314.

ThelBUFl and IBUF2 buffers 750-715 ahd 750-717 apply output valid signals IBUF1V100 and IBUF2V1 00 to IBUFREADY circuits of block 750-722. These circuits force IBUFRIDY line to a binary ONE indicating that there is at least one instruction in the 1 buffer being addressed (current instruction block). As seen from the Figure, the IBUFREADY circuits receive input signals (e.g.

USET13RDY, IFETCHRIDY) from control circuits within section 750-9.

Instruction counter section 750-9 This section stores cache address signals (24-33) for indicating the next instruction to be accessed, in one of two instruction address registers (RICA/RICB) 750-900 and 750-902. The cache address signals 24-33 are loaded into the instruction register RICA/RICB not being used when an IFETCH 1 command is received from processor 700. The cache address is transferred via the RADO 50 position of WAID switch 750-530 and a WAID position #0 of a 4 position Z1 CIN switch 750-904.

Each time processor 700 accesses an instruction, the contents of the instruction register RICA/RICB read out via one position of a two\position ZIC switch 750-906 are incremented by one via an increment circuit 750-908. The incremented contents are returned to the instruction register RICA/RICB via the RNIC position #1 of ZICIN switch 750-904.

As seen from the Figure, each instruction register stores two level fields for fetching first and second blocks of instructions in response to WETCH l and IFETCH2 commands. The two pairs of level field signals are applied to the different switch positions of a 4 position crossbar switch 750-910. The selected level signals ZNICLEV01 00-2100 applied as inputs to block 750- 512 are used to control the operation of ZCD switch 750-306 for accessing the instructions specified by the instruction 60 register RICA/131C13. The level field signals correspond to signals HITLEVC70100-21 00 which are generated by the circuit of block 750-512. These signals are loaded into one of the instruction registers following a directory assignment cycle of operation.

32 GB 2 114 783 A 32 In addition to the level field signals, the RICA and RICB instruction address registers store other signals used for various control purposes which will be discussed herein to the extent necessary.

The incoming cache address signals from the ZDAD switch 750-530 are incremented by one via another increment circuit 750-913. The incremented address signals are loaded into the RICA/RICB instruction register via the INC position #3 of ZICIN switch 750-904. The least significant two bits 32-33 of the cache address provide the IBUFl or IBUF2 address (i.e., signals ZEXT01 001100) to read out instruction blocks accessed from memory.

It will be noted that the pair of level field signals LEV1 and LEV2 from other outputs of switch 750-910 are applied as inputs to a pair of comparator circuits 750-912 and 750-914. The circuits 750-912 and 750-914 compare the level signals LEV1 and LEV2 of the current instruction 10 blockfrom switch 750-910 with the input level signals C7RRO1 00-2100 corresponding to the round robin count for the next available block. Also, the comparator circuit 750-912 receives as inputs memory level signals RTBLEV01 00-2100 and instruction level signals ZNICLEV01 00-2100 from switch 750-910 for comparison in addition to level signals Z1C01 00-2100 for comparison with signals C7RRO1 00-2100. The cache address signals are incremented by 4 by an increment circuit 750-918 and applied as an input to the round robin skip control circuits of block 750-916. These circuits receive as another pair of inputs the input cache address signals 24-30 from ZDAD switch 750-530 and the cache address signals of the current instruction block from ZIC switch 750-906 for comparison by circuits included therein.

The results of the pairs of cache address signals and level signal comparison are combined within 20 other circuits within the round robin skip control circuits of block 750- 916. The circuits of block 750-916, in response to decoded signals from a decoder circuit 750-922, generate output control signals which avoid addressing conflicts. For a further discussion of the operation of such circuits, reference may be made to the copending application of Marion G. Porter, et al titled---CacheUnit Information Replacement Apparatus" referenced in the introduction of this application.

The output control signals from block 7 50-916 are applied as inputs to the circuits of IC control block 750-920. Additionally, the control circuits of block 750-920 receive the results of the decoding of command signals applied to the DMEM lines by the decoder circuit 750-922 when it is enabled by a signal from the DREOCAC line. These decoded signals together with the other signals from sections 750-1 and 750-5 are applied to block 750-920. The control circuits of block 750- 30 920 generate address and control signals for sequencing section 750-9 through the required cycles of operation for processing certain types of commands (e.g. IFETCH 1, IFETCH2 and LDQUAD commands).

The block 750-920 includes a number of control state flip-flops and logic circuits for generating the required control signals. For the same reasons mentioned in connection with section 750-5, only 35 a brief description and the Boolean expressions will be given for certain state flip-flops and control circuits.

Control state flip-flops FABCURLEV1 flip-flop defines the current level for the RICA/RICB instruction register. This flip- flop is set and reset in response to a T clock timing signal in accordance with the following Boolean 40 expressions. The set condition overrides the reset condition. When FA/F13CURLEV is a binary ZERO, it selects level 1 and when a binary ONE, it selects level 2.

SET =DECODE] F 1. --PPIM EIS. [HOLDDM EM. -[UA- -NCELC.

ZDAD08. ZDAD09. HIT. FACTVRIC 1 00/000+ZEXTO.

ZEXT1. RDIBUF.HOLDEXECRDIBUF. FA/FDCURLEVOOO.

DECODELDQUAD, FLDQUAD. DECODEEIS. FACTVRIC100/000.

NOGO+ZEXTO. ZEXT1. FI-DQUAD - RDIBUF. HOLDEXECRDIBUF.

FACTVRIC100 O. NOGO.

RESET=DECODE1F1. FFPIME1S. [HOLUD-MEM. [CANCELC.

FACTVRIC1 00/000+DECODELDQUAD. [-HOLDDMEM.

[EA7-NcELc. FACTVRIC 100/0 O+ZEXTO. ZEXT1.

DECODELDQUAD. FI-DOUAD. DECODE1F1. FA/P13CM1PLEV1 00.

FACTVRICOOO/1 00. RDIBUF. HOLDEXECRDIBUF. NOGO.

The FACTVRIC flip-flop specifies the currently active instruction register RICA/RIC13. When the flip-flop is set to a binary ONE, it specifies the RICA register and when a binary ZERO, it specifies the 55 RICB register. It is set and reset in response to a T clock timing pulse signal in accordance with the following Boolean expressions.

FACTVRIC =FACTVRIC. TGLACTVRIC wherein TGLACTVRIC=QECODE1F1. [HOLDDMEM. [CANCELC.

F17PIMEIS+FNEWIF1. NOGO.

FACTVRIC =FACTVRTEC. TGLACTVRIC wherein TG LACTVRIC =(DECODE1 F 1+ [HOLD MEM+[ ANCELC+ FFPIMEIS). (FNEWIF1 +NOGO).

33 GB 2 114 783 A 33 The FCPLIWIRTIREQ flip-flop defines the time during which processor data is to be written into cache. It is set and reset in response to a T clock timing pulse in accordance with the following Boolean expressions.

SET =(DECODEWRTSNGL+DECODEWRTDBL). HIT. [HOLDDMEM.

CANCELC.

RESET=FWIRTI3BIL. HOLDICACHECIPUWIRTSEQ.

The FDBLMISS flip-flop defines a read double type miss condition and is used to select the WIN position of W1 switch 750-312 during the cycle following data recovery. It is set and reset in response to a T clock timing pulse in accordance with the following Boolean expressions.

SET =(DECODERDDBL+DECODERDRMT). [HOLDDMEM. [UA-NCELC. MISS. RESET=FIRDMISS.

The FEVENODD flip-flop specifies which word of the two word pairs processor 700 is waiting fot when a read single type miss condition occurs. The flip-flop also defines the order that the data words are to be returned to processor 700 in the case of a read double type miss condition.

Further, the flip-flop is used during a read double hit condition to access the second data word. It is set and reset in response to a T clock timing pulse in accordance with the following Boolean expressions.

SET =(DECODERDSNGL+DECODE1F1. IFFIPIMEIS).

F_ 11 ZDAD09+DECODERDDBL [HOLDDMEM. [CANCELC. IDSZ1.

RESET=MECODERDSNG1_+DECODEIF1). [HOLDDMEM.

[CANCELC. ZDAD09+DECODERDDBL. [HOLDDMEM.

[CANCEL DSZ1+DECODERDRMT.[OLDDMEM.

[CANCELC.

The IFFIPIMEIS flip-flop specifies that the last processor state was an F1PIMEIS state which means that the IF1 command on the DMEM lines is a request for additioniii EIS descriptors. This flip-flop is set and reset in response to a T clock pulse in accordance with the following Boolean expressions.

SET =FPIMEIS.

RESET=DECODEIF1. [CANCELC. [HOLDDMEM.

The FHOLDIF1 flip-flop defines when processor 700 is being held because of an IF1 miss condition so that when the instruction is received from memory, the current instruction register RICA/RIC13 can be updated by the FDATARECOV flip-flop. The flip-flop is set and reset in response to a T clock pulse in accordance with the following Boolean expressions.

SET =DECODEIF1. WPIME1S. [HOLDDMEM. [CANCELC.. MISS. R5SET=FNEWIF1. NOGO+ FDATARECOV.

The FINHRIDY flip-flop is used to inhibit the signaling of an IBILIFIRDY condition to processor 700 when a conflict occurs between the instruction (IC) level and memory data level at the time processor 700 took the instruction loaded into RIRA/RIRB from cache. It is set in response to a T clock pulse and is reset unconditionally on the next T clock pulse when no set condition is present. It is set in accordance with 40 the following Boolean expression.

SET =SETIRTERM. READIBUF. [HOLDDMEM. NOGO.

wherein SETIRTERM=CMPDATAICLEV+MEMWRTREQ.

(ZEXTO. ZEXT1. IF2. [CANCELCMD+ DECODE1F1. IFFIPIMEIS+FINI-IFIDY).

RESET =SE.

The FAWNICILEV flip-flop is used to force the level signals ZNICLEVOOO-21 00 of the next instruction to be applied to the control input terminals of ZCD switch 750-306 (i.e., signals ZCD01 0-210) following an IF1 command which did not specify the last word in the block. The flip- 50 flop is set in response to a T clock pulse in accordance with the following Boolean expression. It is reset on the occurrence of the next T clock pulse.

SET=DECODEIF1. FFPIMEIS. HIT. [HOLDDMEM. [CANCELC.

[CANCELC. (WAD08. WAD09).

34 GB 2 114 783 A 34 The FNEWIF1 flip-flop defines the cycle after an IF1 command is received from processor 700. It is set for one cycle in response to a T clock pulse in accordance with the following Boolean expression.

SET=DECODEIF1. FFPIME1S. [HOLDDMEM. [CANCELC.

The FRDIBUF flip-flop is used to specify that a signal on the RDIBUF line was received from processor 700 during the last cycle of operation. It is set in accordance with the following Boolean 5 expression. It is reset during the next cycle in the absence of a set condition.

SET=RDIBUI=. HOLDEXECRDIBUI=. NOGO.

The FRDMISS flip-flop is used to cause the holding of processor 700 upon detecting a miss condition for any read type command. It is set and reset in response to a T clock pulse in accordance with the following Boolean expressions.

SET =(DECODERDSNGL+(DECODE1F1. FFPIMEI-S)+DECODERDRIVIT+ DECODERDC1-R+DECODERI3D131---). [HOLDDMEM.

[CANCELC. MISS.

RESET=FDATARECOV+FNEWIF1. NOGO.

The FRDREQfiip-flop defines when the second word fetched in response to a FIDDI3Lcommand 15 for a hit condition is to be read out from cache. It is set and reset in response to a T clock pulse in accordance with the following Boolean expressions.

SET =DECODEFIDDI3L. HIT. [HOLDDMEM. [CANCELC. RESET=[HOWDIVIEM.

The FDATARECOV flip-flop inhibits the incrementing of the instruction register RICA/RICB when -20 the IF1 command is to the last word in the block and the IF2 command is cancelled. It is set and reset in response to a T clock pulse in accordance with the following Boolean expressions:

SET =DATARECOV. FLASTINST. [HOLDDMEM. [CANCELC+DATARECOV FLASTINST. [CANCELC. [7H-OLDDMEM+DATARECOV. 25 FLASTINST. FIESET=[HOWDIVIEM. FDATARECOV.

Control logic signals 1. The FA/FBI-EV1VAL signal is used to define the state of a first valid bit position of the RICA/RICB instruction register. It is set and reset on a T clock pulse in accordance with the following Boolean expressions. The reset condition overrides the set condition. 30 a. FA/17BLEV1VALSET =DECODEIF1. FFPIMEIS. [HOLDDMEM.

[CANCELC. FACTVRIC100/00+DECODE1F1 FFPIMEIS. [HOLDDMEM. [CANCELC.

EISIF2. FACIVEIPP0.0/1 00+DECODELDQUAD. [HOLDDMEM [CANCELC FACTVRIC 100/000.

b. FA/FBI-EVIVAI RESET =DECODE IF 1. FF-PIME1S. [HOLDDMEM.

[CANCEL. HIT. WAD08. WAD09.

FACTVRIC 1 00/000+ZEXTO. ZEXT1.

DECODE IF1. DECODELDCUAD. FI-DQUAD.

FIDIBUF. HOLDEXECRDIBUF. FAUVRIC000/ 100. FA/F13CIVIPLEV000. NOGO+ZEXTO.

ZEXT1. FI-DQUAD. FIDIBUF. HOLDEXECRDIBUI7.

FACTVRIC 100/000 NOGO.

wherein RICA=FAUVRIC=1 and RIC13=FAUVRIC=1.

2. The FA/FBI-EV2VAL signal is used to define the state of a second valid bit position of the 45 RICA/RICB instruction register. It is set and reset on a T clock pulse in accordance with the following Boolean expressions.

a. FA/F13LEV2VALSET z =DCODE]F2. [HOLDDMEM. [CANCELC.

FAUVRIC000/1 00. NOGO+DECODEIF1 FFPIME1S. [HOLDDMEM. [CANCELC.

FACTVRICOOQl O. EISIF2.

b. FA/FBI-EV2VALRESET =DECODEIF1. FFPIMEIS. [HOLDDMEM. [CANCELC. FACTVRIC100/000+ GB 2 114 783 A 35 DECODELDQUAD. [HOLDDMEM. tCANCELC.

FACTVRIC1 00/000+ZEXTO. ZEXT1. DECODE1F1. DECODELDQUAD. FILDQUAD. FA/F13CURILEV. FACTVRICO 0/100. RDIBUF. HOLDEXECRI)@UN_.N5-GO.

wherein RICA=FAUVRIC=1 and RICB=FACTVRIC=1.

3. The [ZIBO and [MB1 signals control the ZIB switch for transfers of instructions from cache 750 to processor 700 via the ZIB lines.

a. 0130=1 FETCH RDY. FNEWIF1.

b. [Z11311=1FETCHRDY.

4. The [ZDIO, [M1 1 and [M12 signals control the Z131 switch for transfers of instructions and data from cache 750 to processor 700 via the W1 lines. Control signal [ZDIO, which corresponds to the most significant bit of the three bit code, can be assigned to be a binary ZERO unless positions 4 through 7 are being used for display purposes.

a. [ZD11=2ATARECOV+FDBLMISS+RDEVEN. b. [ZD12=RDIBUF/ZDI. (HITTOIC+FRDREQ).

5. The OCIN0 and [MCIN1 signals control the ZICIN switch for loading address signals into the RICA and RICB instruction address registers 750900 and 750-902.

a. [ZICINO=ALTCMD10O.FDFN2HT.[HOLDDMEM.

b. [ZIC]Nl=FDFN1HT.FNEWIF1+FDFN2HT.

6. The signals ENABRIC l and ENABRIC2 are used to enable the loading RICA and RICB registers.

a. ENABRIC1 =FIAOLDIF1. FNEWIF1. 17JAMMICILEV. [HOLDDMEA4. FDATARECOV+ FHOLDiFl DATARECOV.

b. ENABRIC2=FINHMY. SETINHIRDY. DFN12HT wherein SETINIHIRDY=WN2T. [MEMWRTREQ (ZEXTO. ZEXT1. EXECIF2. [CANCILCIVID+ FINIHIRDY+PSUE 1 +PSUEDOIF2)+ CIVIPDATA/ICLEVI.

7. The signal DATARECOV defines the time that new data has been loaded into the processor's 30 registers (e.g. RDI or RBIR) and when the processor is released. This signal is generated by a flip-flop of section 750-1 which is set to a binary ONE in response to a T clock pulse upon detecting an identical comparison between the address signals specifying the word requested to be accessed by processor 700 and signals indicating the word being transferred to cache unit 750. The comparison indicates that signals DATA, MIFS2, MIFS3, MIFS 1 and DATAODD are identical to signals FHT, FHOLDT130, 35 FHOLDTB 1, RADR32 and DOUBLEODD respectively wherein signal FHOLDT130 =FRDMISS. LIDT13VAILID.

FIF2ASSIGN. FTBPTRO; signal FHOLDT131 =FRDMISS. ILDT13VAILID.

FIF2ASSIGN. MPTR1; signal DbUBLEODD =FEVENODD. FDP FS; and signal DATA =FARDA+FDPFS.

Detailed description of section 750-1

Figure 7a shows in greater detail different ones of the blocks of section 750-1. It will be noted 45 that for the purpose of facilitating understanding of the present invention, the same reference numbers have been used to the extent possible for corresponding elements in Figure 4. In many cases, a single block depicted in Figure 4 includes several groupings of circuits for controlling the operation thereof and/or for generating associated control signals. Therefore, some blocks with appropriate reference numbers are included as part of the different blocks of section 750-1.

Referring to the Figure, it is seen that certain portions of block 750102 are shown in greater detail. The transit block buffer 750-102 is shown as including a first group of circuits for keeping track of data words received from memory in response to a read quad type command. These circuits include a plurality of clocked pair count flip-flops which comprise a four-bit position register 750- 36 GB 2 114 783 A 36 10200, a multiplexer circuit 750-10202, a plurality of NAND gates 750- 10204 through 750 10210 and a decoder circuit 750-10212. It will be noted that there is a pair count flip-flop for each transit buffer location.

Additionally, the first group of circuits includes a plurality of clocked transit block valid flip-flops which comprise a four-bit position register 750-10214. The binary ONE outputs of each of the flip flops are connected to a corresponding one of the four pair count flip- flops as shown.

In response to a read quad command, a first pair of words is sent to cache 750. This is followed by a gap and then the second pair is sent to cache 750. The pair count flip-flop associated with the transit block buffer location being referenced as specified by the states of signals MIFS21 10 and MIFS31 10 is switched to a binary ONE via a first AND gate in response to T clock signal [CILKT022 when signal DATAODD1 00 is forced to a binary ONE by the circuits of block 750-114. Signal RESETT13V1 00 is initially a binary ZERO and decoder circuit 750-10212 operates to force one of the first four output signals SETPC01 00 through SETPC31 00 in accordance with the states of the MIFS21 10 and MIFS31 10 from switch 750-128.

The pair count flip-f lop is held in a binary ONE state via the other input AND gate by a transit block valid signal associated therewith being forced to a binary ONE. The appropriate one of the transit block valid bit flip-flops designated by decoder circuit 750-10601 (i.e., signals IN01 00 through IN31 00) is set to a binary ONE via a first AND gate. When switching takes place, increment signal INCTBIN 100 is forced to a binary ONE state in response to T clock signal [CLKT022.

The multiplexer circuit 750-10202 in accordance with the states of the signals DMIFS21 00 20 and DMIFS31 00 from switch 750-128 selects the appropriate binary ONE out of the four pair count flip-flops to be applied to NAND gate 750-10204. This causes NAND gate 750-10204 to force signal LASTODD1 00 to a binary ZERO. This results in NAND gate 750-10206 forcing signal LASTDTAODDOOO to a binary ONE.

When the next pair of data words are received, this causes NAND gate 75010206 to force signal LASTDTAODDOOO to a binary ZERO. This, in turn, causes NAND gate 750-10210 to force reset signal RESETT13V1 100 to a binary ONE. The decoder circuit 750- 10212 is conditioned by signal RESETT13V1 00 to force one of the four output terminals 4 through 7 to a binary ONE. This, in turn, resets the appropriate one of the transit block valid bit flip- flops via the other AND gate. As soon as the TB valid flip-flop resets, it resets the pair count flip-flop associated therewith via its other AND 30 gate. It will be appreciated that such switch! ncl occurs in response to T clock signal [C1-KT022.

As seen from Figure 7a, the first group of circuits of block 750-102 further includes a plurality of NAND gates 750-10216 through 750-10222, each of which is connected to receive a different one of the binary ONE outputs from register 750-10214. The binary ONE outputs FT13V01 00 through FTBV31 00 are also connected to the control input terminals of the transit block address comparator 35 circuits 750-132 through 750-136.

Each of the NAND gates 750-10216 through 750-10222 also are connected to receive a different one of the signals IN01 00 through IN31 00 from decoder circuit 750-10601. The outputs from these gates are applied to an AND gate 750-10224. The signals VALIDOOO through 4G VALID3000 are used to indicate when a transit block register location is available for writing. That is, 40 when a selected transit block valid bit flip-flop is in a reset state, AND gate 750-10224 maintains signal VALIDINOOO in a binary ONE state.

The VALIDINOOO signal conditions a further AND/NAND gate 750-10226 to force a control signal [RTB 100 to a binary ONE during the second half of a cycle of operation (i.e., signal FHT020 is a binary ONE) in the case of a read command (i.e., signal DREQREAD1 00 is a binary ONE) at the time a 45 directory assignment is not being made (i.e., signal FLDTBVALIDOOO is a binary ONE).

As seen from Figure 7a, control signal [RTB1 00 is applied via a driver circuit 750-10228 to a decoder circuit 750-10230. The control signal [RTB1 10 causes the decoder circuit 750-10230 to force an appropriate one of the output signals [RTB01 00 through [M31 00 designated by the states of signals MPTRO1 00 and MPTR 1100 applied via a pair of driver circuits 750-10232 and 750 10234 to a binary ONE state. This in turn causes bit positions 24-31 of one of the transit block register locations to be loaded with address signals applied via the RADO lines 24-3 1. The complement signal [M000 is applied as an input to block 750-107 for controlling the loading of command queue 750-107.

A second group of circuits of block 750-102 shown in greater detail includes the transit block 55 buffer flag storage section 750-10238 of buffer 750-102. This section as well as the section of buffer 750-102, not shown, is constructed from a 4x4 simultaneous dual read/write memory. The memory is a 1 6bit memory organized as 4 words of 4 bits each, only three bits of which are shown.

Words may be independently read from any two locations at the same time as information is being written into any location. The signals FT13PTR01 00 and MPTP1 100 are applied to the write address 60 terminals while the read addresses are enabled by the VCC signal applied to the G 1 and G2 terminals.

The Y bit locations are selected in accordance with the states of read address signals M] FS31 00 and MIFS21 00 from switch 750-128. The Z bit locations are selected in accordance with the states of signals DIVI1F31 00 and DMIF21 00 from switch 750-128. Since these locations are not pertinent they will not be discussed further herein.

37 GB 2 114 783 A 37 The memory may be considered conventional in design, for example, it may take the form of the circuits disclosed in U.S. Patent No. 4,070,657 which is assigned to the same assignee as named herein. Upon the receipt of memory data, the flag bit contents of the transit block location specified by signals MIFS21 00 and MIFS31 00 are applied to the Y output terminals. These signals are in turn applied to blocks 750-102, 750-115 and 750-117, as shown. During the directory assignment cycle for a cache read miss, the flag bit positions of the transit block location specified by signals MPTRO1 00 and MPTR1 100 are loaded with the signals FORCEBYPOOO, FFIDQUAD1 00 and FI-DQUAD1 00 generated by the circuits of blocks 750-5 and 750-114.

It is also seen from Figure 7a that block 750-102 further includes a group of instruction fetch flag circuits which are associated with the operation of transit block buffer 750-102. These circuits 10 include two sets of input AND gates 750-10240 through 750-10243 and 750- 10250 through 750-10253, a pair of multiplexer selector circuits 750-10255 and 75010256, an IF1 and IF2 flag storage register 750-10258 and an output multiplexer circuit 750- 10260 arranged as shown.

The binary ONE outputs of the individual IF1 and IF2 flip-flops are connected to corresponding ones of the sets of AND gates 750-10240 through 750-10243 and 750-10250 through 750- 15 10253. These AND gates also receive input signals from the circuits of block 750-106 generated in response to the in pointer signals FT13PTR0000 and FTBPTR 1000 used for addressing the different register locations within the buffer 750-102 as mentioned previously.

The multiplexer circuit 750-10255 is connected to receive as a control input, signal FIF1 ASSIGN 100 from FIF1 ASSIGN flip-flop 750-11418. The multiplexer circuit 750-10256 is 20 connected to receive as a control input signal FIF2ASSIGN 100 and FIF2ASSIGN flip-flop 750-1410.

This enables the setting and/or resetting of the IF1 and IF2 flip-flops of register 750-10258 in response to the signals FIF1 ASSIGN1 00 and FIF2ASSIGN 100. The switching occurs in response to T clock signal [C1-KT022 during the loading of a transit block register location when a control signal ILDT13VAILID1 00 is switched to a binary ONE via an AND gate 750-11428.

It will be noted that register 750-10258 contains an IF1 and IF2 flag bit position for each transit block register location. That is, the register includes flip- flops FIF10, FIF20 through FIF1 3, F[F23 for transit block register locations 0 through 3 respectively. Each of the binary ONE outputs from the IF1 and IF2 flag flip-flops are also applied to the different input terminals of the output multiplexer circuit 750-10260. The circuit 750-11450 contains two sections. This permits DMIFS21 00 and 30 DMIFS31 00 signals applied to the control terminals of the multiplexer circuit 750-10260 from block 750-128 to select as outputs, input signals from both an IF1 and IF2 flag flip-flop. The selected pair of signals, in turn, provide flag signals Z1F1 FLG 100 and Z1F2FLG 100 which are applied to block 750 115. These signals are used to control the writing of memory information into the IBUFl and IBUF2 buffers 750-715 and 750-717. Additionally, the complements of the outputs from multiplexer circuit 750-10260 which correspond to signals Z1F1 FILG000 and Z1F2FLGOOO are applied to a pair of input terminals of a multisection comparator circuit 750-110/750-11435.

It will be noted that the last section of each of multiplexer circuits 750-10255 and 750 10256 are connected in series for generating the enable transit block buffer ready signal ENABT13RDY1 00 applied to block 750-114. As shown, the 'V' input terminal of the last section of 40 multiplexer circuit 750-10255 connects to a voltage VCC (representative of a binary ONE) while the " 1 " input terminal connects to ground (representative of a binary ZERO). The output terminal of the last section of multiplexer circuit 750-10255 connects to the -0- input terminal of the last section of multiplexer circuit 750-10256 while the---11 " input terminal connects to ground. The multiplexer circuits 750-10255 and 750-10256 operate to force signal ENABT13RDY1 00 to a binary ONE only 45 after the completion of an instruction fetch assignment cycle when both signals FIF1 ASSIGN1 00 and FIF2ASSIGN1 00 are binary ZEROS. Therefore, the "0" input terminals are selected as outputs by the multiplexer circuits 750-10255 and 750-10256 which results in signal ENABTI3RDY1 00 being forced to a binary ONE. This presents the inadvertent generation of the IBUFRDY1 00 signal as explained herein.

As seen from Figure 7a, the circuits of the transit buffer in pointer block 750-106 include a clocked two-bit position register 750-10600 and a decoder circuit 750- 10601. The register 750 10600 has associated therewith a NAND/AND gate 750-10602 and a two input AND/OR gate 750-10604 connected in a counter arrangement. That is, the NAND gate 750- 10602 in response to load signal FILDT13VALID1 11 from block 750-114 and signal NOG0020 forces an increment signal 55 INCTI3IN1 00 to a binary ONE. This causes the address value stored in register 750-10600 to be incremented by one. The increment signal INCTI3IN1 00 is applied to the circuits of block 750-102.

The most significant high order bit position of register 750-10600 is set to a binary ONE via the gate 750-10604 in response to either signals MPTRO1 00 and FT13PM 000 or signals MPTR1 100 and FT13PM00 being forced to binary ONES. The complemented binary ONE output 60 signals of the register bit positions corresponding to signals FT13PM000 and FT13PTR1 000 are decoded by decoder circuit 750-10601. The circuit 750-1061 in response to the FT13PM000 and MPTR1 000 signals forces one of the four pairs of output terminals to a binary ONE.

The command control circuit block 750-114 includes an instruction fetch 2 search 38 GB 2 114 783 A 38 (FIF2SEARCH) synchronous D type flip-flop 750-11400. The flip-flop 750- 11400 is set to a binary ONE state in response to T clock signal [C1- KT020 when a two input AND/OR gate 750-11402 and an AND gate 750-11404 force a set signal SETIF2SEARCH 100 to a binary ONE. This occurs when either an IF1 command which is a hit or an IF2 command is received from processor 700 during an IF1 5 assignment cycle.

In the case of an IF1 command, this presumes that there is no hold condition (i.e., signal [HOLDDIVIEM000 from block 750-117 is a binary ONE) and that a directory search generated a hit (i.e., signal HITTOTB '100 is a binary ONE) indicating that the requested instruction block resides in cache store 750-300. For an IF2 command, it is assumed that there has been a directory assignment cycle following a directory search in which there was a miss made in response to the IF 1 command 10 (i.e., signal FIF1 ASSIGN 100 is a binary ONE).

In either of the situations mentioned, the gate 750-11402 forces the signal SETIF2TIME1 00 to a binary ONE. When the instruction fetch command was caused by a transfer or branch instruction, which is not a NOGO (i.e., signal NOG0030 is a binary ONE) indicating that it should process the IF2 command currently being applied to the command lines (i.e., indicated by signal DREQCAC1 12 being 15 forced to a binary ONE), AND gate 750-11404 forces signal SETIF2SEARCH1 00 to a binary ONE.

This switches flip-flop 750-11400 to a binary ONE when signal [CANCEL01 2 is a binary ONE.

As seen from Figure 7a, the binary ZERO output from flip-flop 750-11400 is applied as an input to the hold circuits of block 750-117. The signal FIF2SEARCHOOO is delayed by a buffer circuit 750-11406 and applied to one input of an input NAND gate 750-11408 of an instruction fetch 2 20 assignment (IFIF2ASSIGN) flip-flop 750-11410.

The signal FIF2SEARCH01 0 together with the signal EISIF2000 (indicates a non-EIS type instruction) causes the NAND gate 750-11408 to switch FIF2ASSIGN flip- flop 750-11410 to a binary ONE in response to a gating signal SET13VALID 100 and T clock signal [CLI(T020. The state of this flip-flop as the others is gated as an output when signal FLI3TI3VALID 111 is a binary ONE.

It will be noted that signal FMVALID1 11 is switched to a binary ONE via an AND gate 750 11412, a clocked flip-flop 750-11414 and a delay buffer circuit 750-11416 in the case of a miss condition (i.e., signal HITTOTB01 0 is a binary ONE) generated in response to a directory search made for a read type command (e.g. IF2). This assumes that there is no hold condition (i.e., signal [HOLDDMEMOOO is a binary ONE), that in the case of an IF2 command it was not due to a transfer 30 NOGO (i.e., sign-ii NOG0020 is a binary ONE) and that there is no cancel condition (i.e., signal [CANCELC01 0 is a binary ONE) for a read type operation decoded by the circuits of block 750-113 in response to the read command applied to the command lines (i.e., signal DREQREAD1 00 is a binary ONE wherein DREOREAD1 00=READ1 00. DREQCAC1 12).

Under similar conditions, an instruction fetch 1 assignment (FIF1 ASSIGN) flip-flop 750-11418 35 is switched to a binary ONE via an input AND gate 750-11420 in response to an IF1 command (i.e., when signal IF1 100 is a binary ONE) in which there was a miss detected (i.e., signal SETT13VALID1 00 is a binary ONE). The load transit buffer valid flip-flop 750-11414 remains set until signal SETI-DT13VALID1 00 switches to a binary ZERO. It will be noted that the binary ZERO output signal FLDT13VALID000 is applied to circuits included as part of block 750-102.

The other pair of flip-flops 750-11422 and 750-11424 are set in response to signal SETLDT13VALID1 00 in the case of a miss condition. The load quad flip- flop 750-11424 is set to a binary ONE state when the command applied to the DMEM command lines is decoded as being a LDGUAD command (i.e., signal LDQUAD1 00 from decoder 750-113 is a binary ONE) and that the ZAC command applied to the ZADOB lines is coded as requiring a read quad operation (e.g. 1171, 1172, 45 LDGUAD, PRERD and RDSNGLE commands specified by signal ZADOB041 00 being set to a binary ONE).

The RDQUAD flip-flop 750-11422 is set to a binary ONE via an AND gate 75011426 when a signal MIN1 100 from the circuits included within command queue block 750- 107 is a binary ONE indicative of a double precision command (i.e., signal ZADOB021 00 is a binary ONE).

As seen from Figure 7a, block 750-114 further includes a comparator circuit 750-11435.

This circuit may be considered conventional in design and, for example, may take the form of the circuits disclosed in U.S. Patent No. 3,955,177.

The comparator circuit 750-11435 is enabled by si gnals USETBRDY1 00 and DATA1 00. The signal USET13P13Y1 00 indicates that the cache is waiting for instructions from memory to be loaded into the IBUFl or IBUF2 buffers. The signal DATA1 00 is forced to a binary ONE by a NAND gate 75011436 indicating receipt of information from memory. The comparator circuit includes two sections. One section compares the command queue input pointer signals and output pointer signals from blocks 750-108 and 750109 respectively. This section forces signals MCIVIP 100 and M13MP000 to a binary ONE and binary ZERO respectively when the pointer signals are equal. The section corresponds to block 750-110 in Figure 4.

The other section compares input terminals Al, A2 and B1, B2, the control signals [ZRIB1 00, [M11301 0 applied to input terminals Al, A2 to the states of the 1 fetch 1 and 1 fetch 2 flag signals Z1F1 FI-GO00, Z1F2FLGOOO applied to terminals B1, B2. When equal, this indicates that the information n 39 GB 2 114 783 A 39 being received from memory at this time is either in response to an 1 fetch 1 or 1 fetch 2 command. It will be noted that control signal [ZRIB1 00 controls ZRIB switch 750-720.

The input terminals A4, A8 compare signals ZEXT01 00, ZEXT1 100 against signals MIFS1 100 and DATAODD 100 applied to the B4, B8 terminals. This indicates whether the information being addressed within the instruction buffer equals the information being received. More specifically, signals 5 ZEXT01 00 and ZEXT1 100 are generated by the circuits of block 750-920 from the least two significant bit address of the instruction stored in the RIRA register. Thus, they specify the word location being addressed within the 1 buffer. Signal MIFS1 100 is coded to specify whether the first or second half of the block is being received. Signal DATAODD '100 specifies whether the first or second word of the first two word pairs is being received. The signal DATAODD '100 is generated by an AND 10 gate 750-11437.

Lastly, the comparator circuit 750-11435 compares a signal ENABT13RDY1 00 applied to terminal A1 6 from block 750-102 with the voltage VCC representative of a binary ONE applied to terminal B1 6. In the presence of a true comparison between the two sets of all six signals, the circuit 750-11435 forces its output to a binary ONE. This results in the complement output terminal forcing 15 signal IBUFCIVIPRO00 to a binary ZERO. This causes block 750-722 to force the IBLIFRDY1 00 signal to a binary ONE as explained herein.

Additionally, section 750-114 includes an AND gate 750-11417. During the first half of a cache cycle (i.e., signal FHT1 20 from delay circuit 750-11810 is a binary ONE) when the FLDT13VALID flip-flop 750-11414 is a binary ONE, the AND gate 750-11417 forces control signal 20 [RT135-81 00 to a binary ONE. This signal is applied as a clock strobe input to the level storage section of transit block buffer 750-102. This section is constructed from a 4x4 simultaneous dual read/write 16-bit memory organized as four words each 4 bits in length similar to the memory device of block 750-10238 and the memory devices used in constructing the 36-bit read command buffer section of block 750-102 as well as the write command/data buffer 750-100.

Figure 7a shows that the data reception afid control block 750-115 includes a plurality of NAND gates 750-11500 through 750-11510 and a plurality of AND gates 750- 11511 through 750-11514 connected as shown to generate the control strobe enable signals [LOBUI71 00, [IBUF1 100 and [IBUF21 00, reset buffer signal RESETBUF1 00 and write control buffer signal [WRTBUFO1 00. These signals are used to control the operation of the buffer circuits of section 750- 30 7. As seen from Figure 7a, the other write control buffer signal [WRTBLIF '1100 is generated by a buffer delay circuit 750-11515 in response to signal FARDA01 0. The signal [WRTBUFO1 00 is derived from the output of the two input data selector/multiplexer circuit 750-128 which selects either the signal RMIFS1 100 from register 750-127 or signal RIVIII7S131 100 from register 750-129. The selection is made in accordance with the state of signal FARDAOOO produced from the accept line ARDA of data 35 interface 600. The multiplexer circuit 750-128, in accordance with the state of signal FARDAOOO, generates the two sets of signals MIFS21 00, MIFS31 00 and DMIFS21 00, DMIFS3 100 which are applied to the read address inputs of buffer 750-102.

It will be noted that section 750-115 also includes a double precision (F13PFSX) D type flip-flop 750-11517 which is set in response to clocking signal [CLI(T020 to a binary ONE state via a first AND gate input in accordance with the state of the signal PUDP17S '100 applied to the AND gate via amplifier circuit 750-11518 from the DPFS line by SIU 100. The DP17S line when set indicates that two words of data are being sent from SIU 100. Switching occurs when SlUl 00 forces the signal PUARDA1 00 applied thereto via an amplifier circuit 750-11519 from the ARDA line of interface 45 600 to a binary ONE. The ARDA line indicates that the read data requested by cache 750 is on the DFS 45 lines from SlU '100. The output of a FARDA flip-flop (not shown) which delays signal ARDA by one clock period is applied to a second hold AND gate input along with signal F13PFSX1 00. The FDPHX flip- flop 750-11517 remains set for two clock periods. That is, the flip-flop 750-11517 is set in accordance with the number of SIU responses (DPFS signals). In the case of a read single command, the SIU generates two SIU responses, each response for bringing in a pair of words. In each case, this permits 50 the writing of the two words into cache when signal RWIRCACKG 100 is a binary ONE.

The binary ZERO output of flip-flop 750-11517 is inverted by a NAND/AND gate 750-11521 and delayed by a buffer delay circuit 750-11522 before it is applied to AND gate 750-11512. The same binary ZERO output without being inverted is delayed by a buffer delay circuit 750-11523 and applied to circuits which reset the states of bit positions of a transit buffer valid bit register which forms part of transit buffer 750-102.

It will also be noted that the double precision signal FDPF1 10 is combined in an AND gate 750 11524 with a write cache flag signal RWRTCAULG1 00 from transit block buffer flag storage portion of buffer 750-102. The AND gate 750-1152 generates a memory write request signal MEIV1WRTREQ1 00 which is forwarded to section 750-9 for enabling memory data to be written into 60 cache (i.e., controls address switch(s) selection).

As seen from Figure 7a, the initiating request control circuits block 750116 includes an active output port request flip-flop 750-11600. The flip-flop is a clocked D type flip-flop which includes two input AND/OR gating circuits. Flip-flop 750-11600 is set to a binary ONE state in response to clock signal [CLI(T020 when block 750-114 forces a pair of signals ENABSETAOPR1 00 and SETAOPR1 0065 GB 2 114 783 A 40 to binary ONES. When set to a binary ONE, this, in turn, sets the AOPR line of interface 600, signalling the SlUl 00 of a data transfer request. The binary ZERO side of flip-flop 750-11600 is inverted by an inverter circuit 750-11602, delayed by a delay buffer circuit 750-11604 and applied to a hold AND gate. The flip-flop 750-11600 remains set until the clock time that signal FARA020 switches to a 5 binary ZERO indicating that the SIU 100 accepted the cache memory request.

The hold control block 750-117, as shown, includes an inhibit transitbuffer hit FINI-IT13HIT flipflop 750-11700, an AND gate 750-11702 and a plurality of AND/NAND gates 750-11704 through 750-11716. The flip-flop 750-11700 is set to a binary ONE state via a first input AND gate and a NAND gate 750-11701 in response to a T clock signal [CILKT020 when signals INI-ITI31-11T1 00 and T131-11T1 00 are binary ONES. The NAND gate 750-11701 forces signal INHTBH1T1 00 to a binary 10 ONE in the case of a cancel condition (i.e., signal [CANCELC01 2 is a binary ZERO).

The complement output side of flip-flop 750-11700 applies signal FINIITI31-11T000 as one input to AND gate 750-11702. A directory busy signal DIRBUSYOOO from block 750- 526 is applied to the other input of AND gate 750-11702. When the directory is not performing a search (i.e., signal DIRBUSYOOO is a binary ONE) and signal INHTBH1T1 00 is a binary ONE, AND gate 750-11702 forces signal INI-ITBACIVIP000 to a binary ONE. This, in turn, causes the gate 750-11704 to force signal TBH1T1 00 to a binary ONE when the AND gate 750-136 forces a transit block address compare signal TBACIVIP 100 to a binary ONE. At the same time, gate 750- 11704 forces signal T131-11T000 to a binary ZERO.

The AND/NAND gates 750-11708 through 750-11710 generate signals CPSTOPOOO through CPSTOP003 which are forwarded to processor 700 for indicating a hold condition. The other AND/NAND gates 750-11714 through 750-11716 generate signals [HOLD13MEM000 through [HOLDDMEM003 to specify an iinternal hold condition for preventing the other sections of cache 750 from executing the command applied to the command lines by processor 700. Whenever there is a hold command condition (i.e., signal HOLDC1VID000 is a binary ZERO), a miss condition (i.e., signal FRDMISS020 is a binary ZERO), a hold quad condition from block 750-916 (i.e., signal HOLDI-DQUAD000 is a binary ZERO) or a transit block hit condition (Le, signal T131-11T000 is a binary ZERO), the gates 750-11708 through 750-11710 force their respective output signals CPSTOP003 through CIPSTOP000 to binary ZEROS and signals CPSTOP 103 through CPSTOP 100 to binary ONES. This, in turn, causes the processor 700 to halt operation.

Under similar conditions, in addition to a hold search condition (i.e., signal HOLDSEARCHOOO is a binary ZERO) as indicated by AND gate 750-11712 forcing signal [EARILYHOLD000 to a binary ZERO or a hold cache condition (i.e., signal [HOLDCCUOOO is a binary ZERO), the gates 750-11714 through 750-11716 force their respective output signals [HOLI3DIVIEM000 through [HOLDDMEM003 to binary ZEROS and signals rLHOLDDMEM 100 through [HOLDDMEM 103 to binary ONES.

Referring to the Figure, it is seen that the timing circuits of block 750118 include a synchronous D type flip-flop 750-11800 with two AND/OR input circuits. The flip-flop 750-11800 receives a half T clocking signal [C1-KI-IT1 00 via gate 750-11802 and inverter circuit 750-11804. A definer T clock signal DEFTCILK1 10 is applied to one of the data inputs via a pair of delay buffer circuits 750-11806 and 750-11808. Each buffer circuit provides a minimum delay of 5 nanoseconds.

Both the signals [C1-KI-IT1 00 and DEFTC1-K '110 are generated by the common timing source. In response to these signals, the half T flip-flop 750-11800 switches to a binary ONE state upon the trailing edge of the DEFTC1-K '110 signal. It switches to a binary ZERO state upon the occurrence of the next [C1-KI-IT1 00 signal (at the trailing edge).

The signals FHT1 00 and FI-IT000, in addition to signals FHT1 20, FI-ITO 10 and FHT020 derived 45 from the binary ONE and binary ZERO output terminals of flip-flop 750- 11800, are distributed to other circuits of section 750-1 as well as to other sections (i.e., 750-5, 750-9 and 750-114).

The signals FHT1 20, FHT020 and FHT01 0 are distributed via another pair of delay buffer circuits 750-11810 and 750-11812 and a driver circuit 750-11814 respectively.

The T clock signals such as [CLI(T020 and [CLI(T022 generated by the common timing source are distributed in their---raw-form to the various flip-flops of registers. When there is a need to generate a 1/2 T clock signal, the 1/2 T clock signal [C1-KI-IT020 is gated with the 1/2 T definer signal (FI-IT1 00) at the input of the flip-flop or register. The state of signai FHT1 00 is used to define the first and second halves of a T cycle. When signal FHT1 00 is a binary ONE, this defines a time interval corresponding to the first half of a T clock cycle. Conversely, when signal FHT1 00 is a binary ZERO, this defines a time interval corresponding to the second half of a T clock cycle.

For the purpose of the present invention, the data recovery circuits can be considered conventional in design and may, for example, take the form of the circuits described in the referenced patent applications. These circuits generate a data recovery signal for forwarding to processor 700 by ---ANDING"the 1/2 T clock signal FI-IT000 with a signal indicating that data is being strobed into the processor's registers. This causes the data recovery signal to be generated only during the second half of a T clock cycle when such data is being strobed into the processor's registers.

In the case of sections 750-5 and 750-9, the signal FHT1 00 is used to control the switching of other timing and control flip-f lops as explained herein.

ip j 41 GB 2 114 783 A 41 Detailed description of section 750-3

Figure 7b shows in greater detail specific ones of the blocks of section 750-3. Corresponding reference numbers have been used where possible.

Referring to Figure 7b, it is seen that the decoder circuits of block 750303 include a decoder circuit 750-30300 which is enabled for operation by signal ENI3MEMLEV1 00 from the circuits of block 750-920. The signals from non-inverted output terminals of decoder circuit 750-30300 are applied to the input terminals of a first multiplexer circuit 750-30302. The signals at the inverted output terminals are applied to the input terminals of a second multiplexer circuit 750-30304. The multiplexer circuit 750-30302 is always enabled for operation while the multiplexer circuit 750- 30304 is only enabled when signal ENBADR1 100 is forced to a binary ONE by the circuits of block 750-920. It is assumed that the---Wpositions of both multiplexer circuits will always be selected.

Predetermined combinations of the two sets of control signals [ZADR01 100 through [ZADR71 100 and signals [ZADR001 00 through [ZADR701 00 are applied to the control input terminals of each of the eight crossbar address selection switches 750-302a through 750-302h, as shown. It is seen that each crossbar switch includes a number of sections, each section includes three parts indicated by the heavy lines between sections. For simplicity, the number of sections of each switch are shown together. For simplicity, the control portion of each section is shown only once since it Is the same for all the sections which are required to make up the switch.

As seen from the Figure, depending upon the states of the pairs of control signals [ZADR001 00, [ZADR01 100 through [ZADR701 00, [ZADR71 100, the signals from one of the three sources are 20 applied to each set of W, X, Y and Z terminals simultaneously.

Detailed desgription of section 750-5 Figure 7c shows in greater detail specific ones of the blocks of section 750-5 as explained previously. Corresponding reference numbers have been used where possible. 25 Referring to Figure 7c, it is seen that the directory hit/miss control circuits of block 750-512 include an encoder network comprising a plurality of NAND gates 750-51200 through 750-51220 and a plurality of amplifier circuits 750-51224 through 750-51228. The NAND gate circuits are connected to encode the set of signals ZFE '1100 through ZFE71 00 from block 750-506 and the set of signals ZHT1 100 through ZHT71 00 from the blocks 750-546 through 750-552 into the 3-bit code for controlling the operation of switch 750-306.

The signal GSRCH 100 is generated by the circuits of block 750-526. As explained herein, this signal is only forced to a binary ONE during the second half of a T clock cycle. Thus, an output from one of the NAND gates 750-51200 through 750-51208 is generated only during that interval. More specifically, the hit signal specified by the state of the full- empty bit causes one of the signals WDLEV1 000 through ZCDLEV7000 to be forced to a binary ZERO state. This, in turn, conditions NAND gates 750-51216 through 750-51220 to generate the appropriate 3-bit code.

Signal WDICENA131 00 also generated by the circuits of block 750-526 is forced to a binary ONE only during the first half of a T clock cycle. Thus, outputs from NAND gates 750-51210 through 750-51214 are generated only during that interval. That is, the instruction address level signals ZNICLEV01 00 through ZNICLEV21 00 from block 750-910 produce signals 1CL0000 through ICL2000 which, in turn, produce signals ZCD01 00 through ZCD21 00. It will be noted that the signals ZCD01 00 through ZCD2 100 correspond to ZNICLEV01 00 through ZNICLEV21 00.

The signals RDDBLLOOOO through RDDBLL2000 are used to define the second cycle of operation for a read double command. Accordingly, when any one of the signals RD13131-1-0000 through RDDBLL2000 are in a binary ZERO state, this forces a corresponding one of the signals ZCD01 00 45 through ZCD21 00 to a binary ONE.

The signals ZCD01 00 through ZCD21 00 are applied to different inputs of corresponding ones of the amplifier driver circuits 750-51224 through 750-51228. These circuits apply the control signals [ZCD01 00 through [ZCD21 00 to the control terminals of switch 750-306.

A next block shown in greater detail in Figure 7c is block 750-526. As mentioned previously, 50 block 750-526 includes a number of directory control flip-flops. The control state flip-flops shown include the directory assignment '(FDIRASN) control state flip-flop 750- 52600 and a plurality of timing flip-flops of a register 750-52610.

The flip-flop 750-52600 is a clocked D type flip-flop which is set to a binary ONE via first input AND gate in the case of a command request (i.e., signal REQCOMB01 00 is a binary ONE) for a read type command (i.e., RDTYP 100 is a binary ONE) when processor 700 requests data from memory and not cache 750 (i.e., signal BYPCAC1 10 is a binary ONE). In greater detail, in the absence of a hold condition (i.e., signal HOLDOOO applied via an AND gate 750-52602 is a binary ONE), a go transfer (i.e., signal NOG0021 is a binary ONE), no cancel condition (i.e., signal CANCELC01 0 is a binary ONE) and processor 700 has signalled a request (i.e., signal DREQCAC '111 is a binary ONE) an AND gate 60 750-52604 forces signal REQCOMB01 00 to a binary ONE.

An AND gate 750-52606 forces the signal SETONBYP 100 to a binary ONE in the case of read type when decoder circuit 750-528 forces signal RDTYP 100 to a binary ONE when processor 700 42 GB 2 114 783 A 42 forces the bypass cache signal BYPCAC1 10 to a binary ONE. The result is that the MIRASN flip-flop 750-52600 switches to a binary ONE for specifying a directory assignment cycle of operation.

The flip-flop 750-52600 is also set to a binary ONE via a second input AND gate in the case of a command request (i.e., signal REQC0MB0 100 is a binary ONE) when a miss condition is detected for 5 the block requested to be read (i.e., signal SETONMISS1 00 is a binary ONE). The signal SETONMISS1 00 is forced to a binary ONE by an AND gate 750-52608 when signal RDTYP 100 is a binary ONE and signal RAWHITOOO from block 750-512 is a binary ONE. The flip-flop 750-52600 is reset to a binary ZERO state upon the occurrence of clock signal [CLOCK1 12 generated from the common source in the absence of a set output signal from the two input AND gates.

A first flip-f lop (FICENAB) of register 750-52610 is used to define the interval of time within a T 10 clock cycle when instructions or operands are to be fetched from cache 750.

This flip-f lop is switched to a binary ONE state via a first AND gate in response to a clock signal [CLOCKD1 20 when signal FHT1 00 generated by the timing circuits of block 750-112 is a binary ONE. Clock signal [CLOCKD1 20 from the common timing source is applied via an AND gate 75052612 and an inverter circuit 750-52612 and an inverter circuit 750-52514. The FICENAB flipflop resets on the following clock signal when signal FHT1 00 has been switched to a binary ZERO.

The second flip-flop of register 750-52610 is used to define an interval during which operands (not instructions) are being fetched from cache 750 as a consequence of a special condition caused by an IF1 command which did not specify the last word in an instruction block. The FRCIC flip- flop is switched to a binary ONE via a first input AND gate in response to clock signal [CLOCK13 '120 when signal FJAIVIMCLEV000 is a binary ONE. The FRCiC flip-flop resets on the following clock pulse when signal 17JAMMICLEV000 has been switched to a binary ZERO.

As shown, the signal at the binary ZERO output terminal of the FICENAB flip-f lop corresponds to the gate half T clock signal GATEMCHI-M 10 which is distributed to the circuits of block 750-920.

The signal FICENABOOO is combined with signal FRCICOOO and signal RDDBLZCDEOOO within an 25 AND gate 750-52616 to produce signal GSRCH 100. The signal RDDBLZCDEOOO is from decoder circuit. This gate forces signal GSRCH 100 to a binary ONE during the second half of a T clock cycle when operands are being fetched (i.e., signal FICENABOOO is a binary ONE) except in the case of a read double command (i.e., signal RDD131-XDE000 is a binary ONE).

The binary ZERO output of the FICENA flip-flop is combined with signal FRCICOOO within a NAND 30 gate 750-52618. The NAND gate 750-52618 operates to force signal ZCDINCENAB1 00 to a binary ONE during the first half T interval when instructions are being fetched (i.e., signal FICENABOOO is a binary ZERO) or in the case of the type IF 1 command described above (i.e., signal FRCICOOO is a binary ZERO).

The circuits of block 750-526 further include a NAND gate 750-52620 and a plurality of AND 35 gates 750-52622 through 750-52628 connected, as shown. The circuits generate a first enable control signal DIRADDE1 00 for controlling the operation of decoder circuit 750-521. Additionally, they generate a second enable control signal FEDCODE '100 for controlling the operation of a decoder circuit 750-52000 of block 750-520.

In greater detail, during a directory assignment cycle (i.e., signal MIRASN 100 is a binary ONE) in 40 the absence of a transfer no go condition (i.e., signal NOG021 is a binary ONE), AND gate 750 52626 forces signal DIRNOG01 00 to a binary ONE. When a signal FSKIPM000 from the circuits of block 750-916 is a binary ONE, this causes the AND gate 750-52628 to force signal DIRADDE1 00 to a binary ONE which enables decoder circuit 750-521 for operation. When either signal DIRNOG01 00 or FSKIPM000 is forced to a binary ZERO, this causes AND gate 750-52628 to 45 disable decoder circuit 750-521 by forcing signal DIRADDE1 00 to a binary ZERO.

Under the same conditions, the AND gate 750-52624 forces signal FEDCODE1 00 to a binary ONE which enables decoder circuit 750-52000 for operation. The AND gate 750-52630 causes an amplifier circuit 750-52632 to force signal FORCEBY1P000 to a binary ONE when both signals FSKIPRI3000 and FBYPCACOO are binary ONES. The FORCEBYPOOO is applied to the transit block flag section of block 750-102. The signal FBYPCACOOO is generated in a conventional manner in accordance with the signal applied to the line BYPCAC by processor 700. The signal is stored in a flip flop, not shown, whose binary ZERO output corresponds to signal F13MAC000.

The circuits of block 750-520, as shown, include the decoder circuit 75052000 and a pair of multiplexer circuits 750-52002 and 750-52004. It is assumed that normally the signals applied to 55 the -0- input terminals of multiplexer circuits 750-52002 and 750-52004 are selected to be applied as outputs (i.e., the signal applied to the G input is a binary ZERO). Therefore, when the decoder circuit 750-520000 is enabled, the output signals FED01 00 through FED71 00 result in the generation of signals RWFEO 100 through RWFE71 00 in response to clock signal [CLOCKOOO.

The Figure 7c also shows in greater detail register 750-504 as including a clocked four stage 60 register 750-50400 and a plurality of amplifier circuits 750-50402 through 750-50602. The register 750-50400 includes D type flip-flops, the first three of which are connected for storing round robin signals OLDRRO1 00 through OLDRR21 00. The fourth flip-flop is connected to indicate the presence of an alternate hit condition having been detected by the circuits of block 750-562, not shown. That is, it is set to a binary ONE state when signal ALTHIT100 is a binary ONE.

c t t 43 GB 2 114 783 A 43 It will be noted that the flip-flops of register 750-50400 are only enabled in response to clock signal [CLOCK1 12 when signal F131RASNO00 is a binary ONE indicative of no directory assignment cycle being performed (a hit condition).

In the case of a hit condition detected within the half of a block being referenced, signal ALTHITOOO is forced to a binary ZERO. This causes the first three flip-flops of register 750-50400 to be loaded via a first set of input AND gates with the round robin signals RRO1 00 through RR21 00 from block 750-500. When there is a hit condition detected within the other half (alternate) of the block being referenced, the circuits of block 750-512 force signal ALTHIT1 00 to a binary ONE. This causes the three flip-flops to be loaded via a second set of input AND gates with the alternate level signals ALTHITLEV01 00 through ALTHITLEV21 00 generated by the circuits of block 750-512. 10 The binary ONE signals of register 750-50400 are applied as inputs to the amplifier driver circuits 750-50402 through 750-50406 for storage in the transit block buffer 750-102. The same signals are applied to the A operand input terminals of an adder circuit of block 750-508. The adder circuit adds or increments the signals OLDFIR01 00 through OLDRR21 00 by one via the binary ONE applied to the Cl terminal of the adder circuit. The sum signals MTRRO1 00 through NXTRR2100 15 generated at the F output terminals are written into the round robin section of control directory 750500.

Lastly, the signals OLDRRO1 00 through OLDRR21 00 are applied as inputs to another set of amplifier driver circuits 750-50408 through 750-50412 for storage in one of the instruction 20address registers 750-900 and 750-902 of Figure 7e.

Detailed description of section 750-7

Figure 7d shows in greater detail different ones of blocks of section 7507. As seen from Figure 7d, block 750-722 includes a plurality of series connected NAND gates 750- 72230 through 750 72234. The NAND gates 750-72230 and 750-72231 are connected to receive instruction buffer valid and instruction control signals IBUF1V1 00, [ZRIBO1 0 and IBUF2V1 00, [ZR1131 00 from 1 buffers 25 750-715 and 750-717 and block 750-920. The IBUF1V1 00 and IBUF2V1 00 signals indicate the instruction buffer into which information is being loaded. That is, when signal IBUF1V1 00 is a binary ONE, that specifies that 1 buffer 750-715 is loaded. When signal IBUF2V1 00 is a binary ONE, that specifies that 1 buffer 750-717 is loaded with an instruction word.

The control signals [ZR11301 0 and [ZRIB1 00 specify which instruction buffer valid bit is to be 30 examined which corresponds to the instruction buffer being addressed. That is, when signal [M11301 0 is a binary ONE, the IBUFl valid bit is specified by the circuits of block 750-920. When signal [ZRIB1 00 is a binary ONE, that specifies the IBUF2 valid bit. When either signal IBUFl RDYOOO or signal IBUF2RDYOOO is forced to a binary ZERO, NAND gate 750-72232 forces signal TBIBUMY1 00 to a binary ONE indicative of a ready condition.

The circuits of block 750-920 force an enabling signal USET13RDY1 00 to a binary ONE following the switching of the appropriate 1 buffer valid bit. This causes the NAND gate 750-72233 to force the T13RDY000 signal to a binary ZERO. The result is that NAND gate 750-72234 forces the IBUFRDY1 00 to a binary ONE signalling the ready condition.

It will also be noted that NAND gate 750-72234 also forces the IBUFRDY1 00 signal to a binary 40 ONE when an instruction fetch ready signal IFETCHMY000 in forced to a binary ZERO by the circuits of block 750-920. Signal IFETCHMY000 is a binary ONE except when the instructions are being pulled from a block in cache. Lastly, NAND gate 750-72234 forces IBUFRDY1 00 signal to a binary ONE when an instruction buffer compare signal IBUFCIVIPRO00 is forced to a binary ZERO by comparator circuit 750-11435.

Detailed description of section 750-9

Figure 7e shows in greater detail specific ones of the blocks of section 750-9. Corresponding reference numbers have been used where possible.

Referring to Figure 7e, it is seen that the block 750-920 includes a first group of circuits of block 750-92000 which generate the four sets of write control signals WRT001 00 through WRT701 00, WRT01 100 through WRT71 100, WRT021 10 through WRT721 00 and WRT031 00 through WRT731 00. As seen from Figure 7e, these circuits include a pair of multiplexer circuits 750 92002 and 750-92004, a register 750-92006 and four octal decoder circuits 750-92008 through 750-92014, connected as shown.

The multiplexer circuit 750-92002 has signals RHITLEV01 00 through RHITLEV21 00 from block 750-512 applied to the set of 'V' input terminals while signals RTBLEV01 00 through RTBLEV21 00 applied to the set of '1 " input terminals. During the first half of the T cycle when signal FDFN2HT1 00 applied to the control terminal GO/G 1 is a binary ZERO, the signals RHITLEV01 00 and RHITLEV21 00 are applied to the output terminals. They are clocked into the top three flip-flops of register 750-92006 in response to T clock signal [CLKHT02. This enables processor operands to be 60 written into cache 750-300 during the second half of the T clock cycle. During the second half of a T cycle when signal FDFN2HT1 00 is forced to a binary ONE, the signals RTBLEV01 00 through RTBLEV21 00 are clocked into the register 750-92006 in response to the T clock signal [CLKHT02.

44 GB 2 114 783 A 44 This enables memory data to be written into cache 750-300 during the first half of the next cycle.

The second multiplexer circuit 750-92004 has signals ZONE01 00 through ZONE31 00 from switch 750-144 applied to the set of -0- input terminals while signal MEIV1WRTREQ1 00 from block 750-112 is applied to the set of--1 - input terminals. When signal FDFN2HT1 00 is a binary ZERO, the signals ZONE01 00 through ZONE31 00 are applied to the output terminals. They are clocked into the bottom four flip-flops of register 750-9206 in response to T clock signal [CLKHT02. During the first half of a T clock cycle, NAND gate 750-92005 forces signal EN13WRT1 00 to a binary ONE which enables the previously loaded signals to be applied to the output terminals. This enables the processor zone bits to be used in specifying which operand bytes are to be updated when writing processor data into the specified level of cache. When signal FDFN2HT1 00 is forced to a binary ONE, the signal MEIV1WRTREG1 00 is clocked into the register 750- 92006. This causes all the zone bits to be forced to binary ONES for causing all of the bytes of each data word received from memory to be written into the specified level of cache during the first half of the next T clock cycle.

As seen from Figure 7e, different ones of the signals RWRTLEV01 00 through RWRTLEV21 00 are applied to the enable input terminals of octal decoder circuits 750-92008 through 750-92014. The15 signals RWRTLEV01 00 through RWRTLEV21 00 are applied to the input terminals of each of the octal decoder circuits 750-92008 through 750- 92014.

The block 750-920 includes a second group of circuits of block 750-92020. These circuits generate the half T clock signal applied to the circuits of block 750-92000, the enable memory level signal ENABMEMLEV1 00, and enable address signal ENADR1 100 applied to the circuits of block 750-303. They also generate the sets of control signals [ZICO1 0, [ZIC1 10 and [RICA1 00, [RIC131 00 applied to the circuits of instruction address registers 750-900 and 750- 902 in addition to control signals [RIFIA1 00 and [RIRB1 00 applied to the registers 750-308 and 750- 310.

The circuits of block 750-92020 include a pair of half definer flip-flops of a register 750 92022, a group of three control flip-flops of register 750-92024 and a clocked flip-flop 750 92026. The circuits also include a number of AND gates, NAND gates, AND/NAND gates and AND/OR gates 750-92030 through 750-92041.

The series connected AND/NAND gate 750-92030, AND/OR gate 750-92032 and AND gates 750-92034 and 750-92035 in response to a signal FI-DQUAD1 00 from 750-916, a signal FWFIDESCO10 from processor 700 and signals FAUVRIC000 and FACTVRIC100 from register 750- 30 92024 generate control signals [Z1C000, [ZICO1 0 and [ZIC1 10. These signals are used to control the operation of ZIC switch 750-906 and the different sections of registers 750-900 and 750-902 (e.g. level valid bit storage and level bit storage) in addition to registers associated therewith.

The series connected AND gate 750-92036, the AND/NAND gate 750-92037 and NAND gates 750-92038 through 750-92041 operate to generate register strobe signals [RICA1 00 and 35 [RICB 100. These signals control the loading of registers 750-900 and 750- 902. The AND gate 750-92036 forces signal VAI-RDIBUF1 00 to a binary ONE when a hit condition was detected in the case of a read command (i.e., signal FRDMISSOOO is a binary ONE), the transfer was a go (i.e., signal NOG0020 is a binary ONE) and signal CIVIPDATA/ICLEV000 from the comparator circuit of block 750-912 is a binary ONE.

The signal FRDMISSOOO is obtained from the binary ZERO output of the flipflop, not shown, which as mentioned is set in accordance with the Boolean expression:

F13DIVIISS=(RDC1VID. [HOLDDMEil. HrrToic. [CANCELC).

The signals GOODI7TCHAll 00 and GOODFTCH131 00 generated by circuits, not shown, indicate whether the RICA register 750-900 or RICB register 750-902 is being used at that time and its contents are 45 therefore incremented. For example, signal GOODFTCHA100 is generated in accordance with the following Boolean expression:

GOODFTCHA=INSTIF1. FI-DQUAD. FACTVRIC. FDFl\12HT+FDFl\12HT.

FI-DGUAD. FAUVRIC.

Signal GOODFTCH13 is generated in a similar fashion except for the reversal in states of signals 50 FAUVRIC and FAUVRIC.

It is seen that when signal EXECRDIBUF1 00 is forced to a binary ONE when processor 700 forces signal RDIBLIF1 10 to a binary ONE, the NAND gate 750-92039 causes NAND gate 750-92041 to force signal [RICA1 00 to a binary ONE when signal GOODFTCHA1 00 is a binary ONE. The signal EN13STRI3A000 indicates when the RICA register 750-900 is being initially loaded. That is, when signal ENBSTR13A000 is forced to a binary ZERO, it causes NAND gate 750-92041 to force signal [RICA1 00 to a binary ONE. More specifically, signal ENBSTR13A is generated in accordance with the following Boolean expression:

ENBSTR13A=FI-DQUAD. FAUVRIC. FNEWIF1. FDFi\11 HT +FDFi\11 HT. FAUVRIC. FJAIVIZNICLEV. FHOLDIF1 9 GB 2 114 783 A 45 +ONSTIF1 +DCDLDQUAD). FACWRIC. FWN2HT. [CANCI-CMD +FDFN2HT. RTIC. INH2HT. ENAB2HT. wherein ENA132HT=ENABRIC1 +ENABRIC2 and INFIPHT-=[CANC CMD. FLASTINST.

Under either set of conditions, signals [RICA1 00 and [RIC131 00 enable the stroving of their corresponding registers when they are either being initially loaded or following incrementing as when instructions are being fetched or pulled out from cache.

The NAND gate 750-92042, AND/NAND gate 750-92043 and NAND gates 750-92044 through 750-92049 are connected to generate register strobe signals [R1RA1 00 and [RIRB1 00 in a fashion similar to the generation of register strobe signals [RICA1 00 and [RIC131 00.

The NAND gate 750-92046 forces signal [RIFIA1 00 to a binary ONE in the case of a new instruction fetch (i.e., signal NEWINSTOOO is a binary ZERO)or when the processor 700 takes an instruction from R1RA register 750-308 (i.e., signal TAKEINSTOOO is a binary ZERO). The NAND gate 750- 92049 forces signal [RIRB1 00 in the case of a new operand fetch (i.e., signal NEWDATAOOO is a binary ZERO) or when processor 700 takes a data word from RIRB register 750-310 (i.e., signal 15 TAKEDATAOOO is a binary ZERO).

The AND gate 750-92050 and AND/NAND gate 750-92051 generate signal ENBIVIEIVILEV1 00 during the second half of a T clock cycle (i.e., signal FDFN2HT1 01 is a binary ONE) when the circuits of block 750-112 force memory write request signal MEIV1WRITREG1 00 to a binary ONE. The NAND gate 750-92052 generates signal ENBADR1 100 during the second half of a T clock 20 cycle (i.e., signal FDFN 1 HT1 0 1 is a binary ZERO) or when the instruction counter is in use (i.e., signal USEICOOO is a binary ZERO).

As concerns the flip-flop registers, it is seen that the flip-flop of register 750-92026 is switched to a binary ONE state via a first AND gate when AND gate 750-92053 is conditioned to force signal INSTIF1 100 to a binary ONE in response to an IF1 command being decoded by decoder circuit 750- 25 922 (i.e., signal DCD1F1 100 is a binary ONE) which does not require additional descriptors (i.e., signal FFPIMEIS020 from processor 700 is a binary ONE) and AND gate 750-92054 forces signal [CANCELCIVID000 to a binary ONE in response to a no cancel condition (i.e. , signal [CANCELC01 0 is a binary ONE) and a no hold condition (i.e., signal [HOLDDMEM001 is a binary ZERO).

The flip-flop register 750-92026 is reset to a binary ZERO via a second input AND gate which 30 receives signals ENABNEWINSTOOO and NEWIF1 M13K1 00 from a pair of NAND gates 750-92042 and 750-92043 and AND gate 750-92055. The binary ONE output of the flip- flop register 750 92026 is applied to NAND gate 750-92056. NAND gate 750-92056, during the first half of a T clock cycle (i.e., signal FDFN 1 HT1 00 is a binary ONE), switches signal USEICOOO to a binary ZERO when signal FNEWIF1 100 is switched to a binary ONE.

The second flip-flop register 750-92022 includes the pair of timing flipflops which are both set to binary ONES in response to signal GATEHFTCLK1 00 from section 750-5 in response to 1/2 T clock signa! [CLKHT021. The flip-flop of register 750-92022 are reset to binary ZEROS inyesponse to the next 1/2 T clock signal [CLKHT02 1.

The flip-flops of register 750-92024, as mentioned previously, provide various state control 40 signals. The first flip-flop (FRDIBUF) is switched to a binary ONE state when NAND gate 750-92060 forces signal SETWIBUF1 00 to a binary ONE in response to read 1 buffer request from processor 700 (i.e., signal EXECR13IBUFOO0 is a binary ZERO) or an inhibit ready condition (i.e., signal FINHRDY01 0 is a binary ZERO) when AND gate 750-92061 forces signal ENABSETFIDIBUF1 00 to a binary ONE. The signal ENABSET13DIBUF1 00 is forced to a binary ONE in the case of a command which is not a load 45 quad command (i.e., signal FI-DQUAD000 is a binary ONE) or an instruction fetch 1 command (i.e., signal GOODIF1 000 is a binary ONE). The FRDIBUF flip-flop is reset a clock period later in response to T clock signal [CLI(T021 via a second input AND gate.

The second flip-flop (FACTVRIC) of register 750-92024 is set and reset in accordance with the Boolean expressions previously given via the NAND gates 750-92062 and 750- 92064, the AND 50 gate 750-92063 and AND/NAND gate 750-92065. The third flip-flop (FRDDATA) is set to a binary ONE statevia a first input AND gate in response to signal SETFIDIBUF1 00 when the command is a load quad command (i.e., signal FI-DQUAD1 00 is a binary ONE). The FWDATA flip- flop is reset to a binary ZERO state a clock period later via a second input AND gate in response to the T clock signal [C1-KT021.

The next group of circuits included within block 750-920 include the circuits of block 750 92070. As seen from Figure 7e, these circuits include a first plurality of AND gates, AND/NAND gates and NAND gates 750-92071 through 750-92086, connected as shown. These gates generate control signals SETACURLEV1 00, [RICACNTL1 00 and RSTACURLEV2000 which control the setting and resetting of the current level and level valid bit positions of RICA register 750-900 in accordance 60 with the states of signals SETALEV1 VAL1 00, RSTALEV1 VALOOO and SETLEV2VAL1 00. These signals are generated by another plurality of AND gates and NAND gates 750-92087 through 750-92095.

A second plurality of AND gates, AND/NAND gates and NAND gates 750-92100 through 750-92116, in a similar fashion, generates signals SET13CURLEV1 00, RSTBCURLEV200 and 46 GB 2 114 783 A 46 [RICBCNTL100 which set and reset the current level and valid bits for the RICB register 750-902 in accordance with signals SETBLEV1VAL100, RSTBLEMAL000 and SETBILEV2VAL100. These signals are generated by another plurality of AND gates and NAND gates 750-92120 through 750-92125.

A plurality of AND gates 750-92126 through 750-92129, in response to signals SETALEV1 VAL1 00, SETBLEV1 VAL1 00, SETALEV2VAL1 00 and SETBLEV1 VAL1 00, generate control signals [RICALEV1 100 through [RICBI-EV21 00 when signal [CANCELCIVID000 is a binary ONE. These signals are applied to the control input terminals of the level bit storage sections of the RICA and RICB registers 750-900 and 750-902 for controlling the loading of hit level signals from section 750 512.

A further plurality of AND/NAND, AND/OR gates and NAND gates 750-92130 through 750- 10 92137, in response to signals from the level valid bit storage and level storage sections of registers 750-900 and 750-902, generate the use transit buffer ready signal USET13RDY1 00 and the control signals [ZRIBO1 0 and [ZRIB1 00 which are applied to the circuits of block 750-114.

It is also seen that block 750-92070 includes a four D type flip-flop register 750-92140, the pair of AND gates 750-92141 and 750-92142, the pair of AND/NAND gates 750- 92143 and 15 750-92144 and the pair of AND/OR gates 750-92145 and 750-92146, connected as shown.

The flip-flops of register 750-92140 are loaded with the contents of bit positions 8 and 9 of the RICA and RiCB registers 750-900 and 750-902 in response to T clock signal [C1- KI-IT020 under the control of signals [RiCA1 00 and [RIC131 00. That is, the top pair of register flip-flops are clocked when signal [RICA1 00 applied to terminal Cl is forced to a binary ONE while the bottom pair of register flip- 20 flops are clocked when signal [RIC131 00 applied to terminal G2 is forced to a binary ONE. The signals [MC000 and [ZIC1 00 applied to terminals G3 and G4 control independently the generation output signals from the top pair of flip-f lops and bottom pair of flip-flops respectively at the corresponding sets of output terminals.

Pairs of binary ZERO output signals are combined within AND gates 75092141 and 750 92142 to generate address signals ZEXT01 00 and ZEXT1 100, in addition to those signals required for the generation of control signal NEXTI-EVVAL1 00 which is applied to the control input terminals of comparator circuit 7 50-912.

A last group of circuits include a flip-flop register 750-92150 and a plurality of AND gates, an AND/NAND gate, NAND gates and AND/OR gate 750-92151 through 750-92156. These circuits 30 are connected to generate signEfl IFETCHMY000 which is applied to the circuits of section 750-114.

The gates 750-92153 and 750-92154 are connected to generate timing signals DFN2HT101 and DFN2HT1 00 in response to signal FHT01 0 from block 750-112. These signals are forced to binary ONES during the second half of a T clock cycle of operation.

The flip-flop register 750-92150 is set to a binary ONE via a first input AND gate when AND 35 gates 750-92151 and 750-92152 force signals SETINI-IRDY1 00 and CANCELINHRDYOOO to binary ONES. It is reset to a binary ZERO via a second input AND gate when NAND gate 750-92155 force signal RSINI-IRDY000 to a binary ZERO. The binary ZERO output of register 750-92150 is applied to AND/OR gate 750-92156. When signal FINI-IRDY000 is forced to a binary ZERO,k causes gate 750-92156 to force signal IFETCHMY000 to a binary ONE state.

Additionally, Figure 7e shows in greater detail the switch 750-910 and comparator circuits of blocks 750-912 and 750-914. The switch 750-910 is a crossbar switch which operates in the manner previously described. The W outputs select one of the two sets of signals applied to the AO and Al terminals in accordance with the state of signal [Z[Cl 10. The X outputs select one of the two sets of signals applied to the A3 and A4 terminals in accordance with the state of signal [ZIC1 10. The Y and Z outputs select one of the four sets of signals applied to the AO-A4 terminals in accordance with the states of signals [ZIC1 10, [MICLEV1 00 and [ZIC1 10, ZCURLEV1 00.

* The output signals ZNICLEV01 00 through ZNICLEV21 00 from the Y output terminals of circuit 750-910 are applied to the B input terminals of comparator circuit 750- 912 for comparison with the signals RTBLEV01 00 through RTBLEV21 00 from section 750-102. The comparator circuit 50 750-912 is enabled when decoder circuit 750-922 has decoded an lFl command (i.e., signal DECODE1F101 0 is a binary ONE) and signal NEXTI-EVVAL1 00 is a binary ONE. The comparison results in the generation of signals CIVIPDATA/ICLEV1 00 and CIVIPDATA/ICLEV000.

Other comparator circuits of blocks 750-912 and 750-914 operate in a similar manner to generate signals CIVIPCLIRLEV1 00 and CIVIPALTLEV1 00. In greater detail, another section of circuit 55 750-912 compares signals Z1CLEVO 100 through ZICLEV21 00 with signals C7RRO1 00 through C7RR21 00. When there is a true comparison, signal CIVIPCURLEV1 00 is forced to a binary ONE. This section is enabled via a NAND gate 750-91202 when either signal ZLEV1 VALOOO or signal ZLEV2VALOOO is a binary ZERO.

The comparator circuit 750-914 has two sections enabled by pairs of signals ZCURLEV1 00, 60 ZLEV1 VAL1 00 and ZCURLEVOOO, ZLEV2VAL1 00 as shown. The first section compares level 1 signals ZLEV1 0100 through ZLEV1 2100 with round robin signals C7RRO1 00 through C7RR21 00. When there is a true comparison, the output signal at the A=B terminal is forced to a binary ZERO which causes NAND gate 750-91402 to force signal C[VIPALTLEV1 00 to a binary ONE.

7 P 47 GB 2 114 783 A 47 In a similar fashion, the second section compares level 2 signals ZLEV201 00 through ZLEV221 00 with round robin signals C7RRO 100 through C7 RR21 00. When there is a true comparison, the output signal is forced to a binary ZERO which causes NAND gate 750-91402 to force signal CIVIPALTLEV1 00 to a binary ONE.

Description of operation With reference to Figures 1 through 7e and the timing diagram of Figure 8, the operation of the preferred embodiment of the present invention will now be described.

Referring to Figure 8, it is seen that a T clock cycle is divided into first and second halves as illustrated by waveform D. That is, when signal FHT1 00 is a binary ONE, shown as the negative going portion in the Figure, this defines the first half of a T clock cycle. When signal FHT1 00 is a binary ZERO, 10 shown as the positive portion, this defines the second half of a T clock cycle.

During the first half of the T clock cycle, instructions are fetched and memory data is written into cache 750-300 when there is no conflict as explained herein. In both cases, the level to be accessed is already established. That is, for instructions, the level is stored in either the RICA or RICB instruction address register at the time an IF11 or IF2 command received from processor 700 was executed. For memory data, the level is stored in one of the register locations of transit block buffer 750-102 as a result of the circuits of block 750-520 having detected a miss condition which caused cache 750 to fetch the requested data from memory. During the second half of a T clock cycle, either operand data is accessed from cache or processor data is'written into cache in accordance with the results of a directory search.

Accordingly, the arrangement of the preferred embodiment of the present invention enables memory data to.be written into one cache level while a next instruction is fetched from one of the remaining levels during a T clock cycle of operation. This eliminates the need to hold off or delay the accessing of instructions to write memory inform ation/data. When the level into which memory data is being written is the same as the level from which an instruction is being fetched, the accessing of an 25 instruction is delayed until the writing of memory data has been completed.

As described above, an address from processor 700 is loaded into all of the address registers at the start of the second half of the cycle to initiate a possible read or write operation on the second half cycle of the T clock cycle. Therefore, in those instances when the writing of memory data conflicts with an instruction access, an alternate arrangement permits the second half of the T clock cycle to be used 30 to perform a processor read operation and a memory data write oppration.

This last arrangement enables memory data to be written into one cache level while an operand is fetched from one of the remaining levels during a T clock cycle of operation.

However, when the level into which memory data is being written is the same as the level from which a processor operand is being fetched, the accessing of the operand is delayed until the writing of 35 memory data has been completed. A conflict also arises when memory data is being written into one level and the processor is writing operand data into another level.

To illustrate the above operations, it will be assumed by way of example that processor 700 is going to process the sequence of instructions including a load A instruction (LDA), a store A instruction (STA), a load A instruction (LDA), a store A instruction (STA), and a next instruction, as shown in Figure 40 8. The format of these instructions is shown in the cited copending patent applications and in the publication -Series 60 (Level 66)/6000 MACRO Assembler Program (GMAP)" by Honeywell Information Systems Inc., Copyright 1977, Order Number DDOBB, Rev 0. It will be appreciated that the processor 700 executes the four instructions in pipelined fashion which is illustrated in detail in the copending patent application "A Microprogrammed Computer Control Unit Capable of Efficiently Executing a Large Repertoire of Instructions for a High Performance Data Processing Unit", referenced herein.

As indicated herein, processor 700 carries out various operations during 1, C and E cycles of operation in executing instructions. This results in the issuance of cache commands by processor 700 to cache unit 750 as described herein. For ease of explanation, it is assumed that the instructions reside in cache unit 750-300.

It will be appreciated that at some point during instruction processing, processor 700 loads one of the instruction address registers RICA/RICB with address and level information. This usually comes about as a consequence of the processor executing a transfer or branch instruction which results in processor 700 generating an IF1 command followed by an IF2 command. Following the execution of 55 these commands by cache unit 750, the fetching of instructions during the first half of a T clock cycle and operands during the second half T clock cycle proceed as illustrated in Figure 8.

For ease of explanation, it will be assumed that the IF1 command includes an address which specifies the fetching of the first instruction word of a block of instructions in cache which includes the above mentioned sequence of instructions. The operation of cache unit 750 in executing the IF1 and 60 IF2 command now will be described briefly. The IF1 command upon receipt by cache unit 750 is decoded by the decoder circuits 750-922. The decoder circuits 750-922 cause the circuits of block 750-920 to generate signals for loading the alternate instruction address register which is assumed 48 GB 2 114 783 A 48 to be RiCA with signals corresponding to the incremented value of the address included within the IF1 command.

That is, during the first T clock cycle, the address signals from switch 750-530 are incremented by one by circuit 750-912 and loaded into the RICA instruction address register 750-900 in response to 1/2 T clock signal [CLKHT1 00 when signal [RICA1 00 is a binary ONE. The signal [RICA1 00 is forced to a binary ONE by the circuits 750-920 when signal ENBSTR13A000 of Figure 7e is forced to a binary ZERO during the first half of the first T clock cycle.

During the first half of the first T clock cycle, the IF 1 command address is loaded into all of the RADRO-7 registers 750-301 A through 750- 301 n via the ZADRO-7 address selection switches 750-302a through 7 50-302n in response to signal [CLKHT1 00. During the first half of the T clock 10 cycle, signal EN13MEMLEV1 00 is a binary ZERO. Also, signal ENBADR1 100 is a binary ZERO (i.e., the control state FNEWIF 1 flip-f lop 7 50-92026 switches on the T clock in response to signal [CLKT02 1, as explained herein). Therefore, each of the pairs of signals [ZADRO 1100, [ZADROO 100 through [ZADR71 100, [ZADR701 00 are binary ZEROS causing position 0 to be selected as an address source for all eight address registers 750-301 a through 750-301 n.

The IF1 command address is also applied as an input to the directory circuits of block 750-502 via WAD switch 750-530 for a search cycle of operation. Since the instruction block is in cache, the circuits of block 750-512 generate the appropriate hit signals HITTOC71 00 and hit level signals HITLEVC70100-21 00 which are applied to section 750-9. The decoding of the IF1 command causes the hit level signals H ITLEVC70100-21 00 to be loaded into the level 1 bit positions of the RICA instruction address register. Also, the level 1 valid bit and hit/miss bit positions of the RICA register 750-900 are forced to binary ONES (i.e., hit signal HITTOC71 00 switches the hit/miss bit position to a binary ONE). The stored level 1 value is thereafter used to control the operation of the ZCD switch 750-306 during subsequent instruction fetches as explained herein.

The first instruction accessed from the location specified by the IF1 address is transferred as an operand word to processor 700 during the second half of the first T clock cycle via position 1 of the Z131 switch 750-312 during the end of the first T clock cycle. The first instruction is clocked into the RBIR register 704-152 of processor 700 on the T clock in response to signal [CLKT1 00.

The signal FJAWNICLEV000 enables the next instruction to be transferred to processor 700 during the second half of the second T clock cycle. This signal is forced to a binary ZERO by the circuits 30 of block 750-920. The signal FJAWNICLEV000 again causes the level signals ZNICLEVOOO-21 00 obtained from RICA register 750-900 to be applied as inputs to the control input terminals of ZCD switch 750-306 following execution of the IF1 command. That is, referring to Figure 7c, it is seen that signal FJAWNICLEV000 switches signal FRCICOOO to a binary ZERO. This causes NAND gate 750-52618 to force signal WDINCENA131 00 to a binary ONE during the second half of the second T 35 clock cycle. Signal WDINCENA131 00 conditions NAND gates 750-51210 through 750-51214 to generate signals [ZCD01 00 through [ZCD21 00 from signals ZNICLEV01 00 through ZNICLEV21 00.

Also, the IF1 command decoded by decoder circuit 750-922 caused the FNEWIF1 flip-flop 750-92026 to be switched to a binary ONE on the T clock in response to signal [CLKT020. As mentioned previously, it defines the operations during the cycle (second) after the IF 1 command was 40 received. More specifically, during the first half of the second T clock cycle, the NEWIF1 flip-flop 750 92026 causes NAND gate 750-92056 to switch signal USEICOOO to a binary ZERO. The signal USEICOOO conditions NAND gate 750-92052 to force the signal ENBADR1 100 to a binary ONE.

Since there is no memory data transfer taking place at this time, the decoder circuit 750-30300 is not enabled at this time (i.e., signal EN13MEMLEV1 00 is a binary ZERO). Thus, signals MEMLEVOOOO through MEMLEV7000 are binary ONES while signals MEMLEV01 00 through MEMLEV71 00 are binary ZEROS.

The multiplexer circuit 750-30304, in turn, applies the binary ONE signals to its output terminals which results in output signals [ZADR001 00 through [ZADR701 00 being forced to binary ONES while multiplexer circuit 750-30302 forces signals [ZADR01 100 through [ZADR71 100 to binary ZEROS. These pairs of signals condition the address selection switches 750-302a through 750-302n to select as a source of address signals, the RICA instruction address register connected to switch position 1 during the first half of the second T clock cycle.

Accordingly, the RADRO-7 address registers 750-302a through 750-302n are loaded via the ZIC switch 750-906 with the address signals from RICA register 750- 900 in response to the 1/2 T clock signal [CLKHT1 00 during the first half of the second cycle. The RICA register 750-900 is selected since at this time signal [Z1C1 00 is a binary ZERO. That is, signal ENBALT1 00 is a binary ZERO and signal FACTVRIC1 00, from the binary ZERO output of FAUVRIC flip-flop of register 750-92024, is a binary ZERO. These signals condition AND/OR gate 750-92032 to force signal [Z1C1 00 to a binary ZERO. The address contents applied to cache unit 750-300 cause a second word from each level to be read out to ZCD switch 750-306. The level signals ZNICLEV01 00-2100 select the word corresponding to a second instruction at the level specified by the contents of the RICA register 750900 to be applied to the ZIB lines. It is applied to the ZIB lines via position 0 of the ZIB switch 750314.

5 49 GB 2 114 783 A 49 During the first half of the second cycle, the address signals from RICA register 750-900 are again incremented by one by circuit 750-902 and loaded into the RICA register 750-900 via position 1 of ZICIN switch 750- 902 in response to 1/2 T clock signal [CILKI-IT1 00 when strobe signal [RICA1 00 is a binary ONE. Again, signal [RICA1 00 is forced to a binary ONE when signal ENBSTRBAOO is forced to a binary ZERO during the second half of the second T clock cycle. At T clock time, the address of the third instruction resides in the RICA register 750-900. This instruction corresponds to the LDA instruction of Figure 8.

The signal FJAMMICILEV000 when forced to a binary ZERO causes NAND gate 750-92044 to force signal NEWINSTOOO to a binary ZERO during the second half of the second T clock cycle. This causes NAND gate 750-92046 to force signal [R1RA100 to a binary ONE. On the T clock at the end of 10 the second T clock cycle, the second instruction read out from ZCD switch 750-306 is also loaded into the RIRA register 750-308. This enables processor 700 to load the second instruction into its RBIR register in response to T clock signal [CILI(T1 00 at the end of the second T clock cycle when it has completed execution of the previous instruction.

That is, when processor 700 has completed executing the first instruction, it forces the RDIBUF 15 line to a binary ONE. The signal applied to the RDIBUF line by processor 700 causes the circuits of block 750-92020 to switch the FIRDIBUF flip-fiop to register 750-92024 to a binary ONE in response to T clock signal [CLKT020. Hence, signal FR13IBUIF11 00 corresponds to the signal applied to the RDIBUF line delayed by one clock period. Thus, it specifies that a signal on the RDIBUF line was received from processor 700 during the last cycle. This indicates whether the RIRA register 750-308 20 has to be refilled with another instruction during the first half of the third T clock cycle. If processor 700 does not complete the execution of the previous instruction, the RDIBUF line signal will not be generated. When the next instruction to be accessed has already been loaded into the RIRA register 750-308, the register is not refilled during the first half of the next T clock cycle of operation.

The execution of the IF2 command by cache unit 750 is similar to the IF1 command. However, 25 the address contained in the IF2 command is only used for a directory search in the case of a hit as assumed in this example. The result is that the hit level signals HITLEVC70100-21 00 generated by the circuits of block 750-512 are loaded into the level 2 bit positions of the RICA register 750-900.

Also, the valid bit and hit/miss bit positions are forced to binary ONES (i.e., a go condition is assumed).

In this example, it is assumed that processor 700 completed its execution of the previous instruction and forced the RDIBUF line to a binary ONE as illustrated by the first negative portion of waveform E in Figure 8. During the first half of the third T clock cycle, the signal FIRDIBUI71 00 causes the LDA instruction specified by the level signal contents of the RICA register 750-900 to be loaded into the RIRA register 750-308 (waveform K) and the RICA register contents to be incremented by one and reloaded into the RICA register 750-900. The RADRO-7 registers 750-302a through 750-302n as mentioned above, were loaded from the RICA register 750-308 via the ZIC position of ZADRO-7 address selection switches 750-302a through 750-302n on the T clock of the previous cycle.

During the first half of the third cycle, the address signals applied by address RADRO-7 registers 750-302a through 750-302n to cache unit 750-300 cause eight words to be read out from the 40 addressed locations of the eight levels. Also, during the first half of the third cycle, the circuits of block 750-526 of Figure 7c force signal ZCD1CENA131 00 to a binary ONE (i.e., signal FICENABOOO is forced to a binary ZERO). This conditions the circuits of block 750-512 to apply signals ZNICLEV01 00 through ZNICLEV21 00 as control signals [ZCD01 00 through [ZCD21 00 to ZCD switch 750-306.

This causes the first LDA instruction to be selected for loading into RIRA register 750-308 by ZCD 45 switch 750-306 (i.e., see waveform M. Thereafter, the LDA instruction is loaded into the RBIR register of processor 700 on the T clock of the end of the third cycle in response to signal [CLIKT1 00.

Also, on the T clock of the previous cycle (third cycle), the RADRO-7 registers 750-301 a through 750-301 n were loaded from RICA register 750-308 via the ZIC position of ZADRO-7 address selection switches 750-302a through 750-302n (waveform J).

On the 1/2 T clock of the first half of the fourth cycle, the address signals applied by the RADRO 7 registers to the eight cache levels cause eight words including the STA instruction to be read out to ZCD switch 750-306. At that time, the address from RICA register 750-900 is incremented by one and restored. Again, the signals MCLEVO 100-2100 from the level 1 bit positions of RICA register 750-900 select the STA instruction word for loading into RIRA register 750-308 (waveform K). The 55 STA instruction is then loaded into the RBIR register on the T clock of the end of the fourth cycle.

At the end of the fourth cycle, all of the RADRO-7 registers 750-301 a through 750-301 n are loaded with the next instruction address from RICA register 750-900. However, as seen from Figure 8, data words transferred by main memory 800, in response to a previous read quad command, are starting to be received by cache unit 750. The read quad command is assumed to have been issued60 by cache 750 prior to its execution of the IF11 command discussed above as a result of a miss condition (i.e., block requested not in cache). At that time, the block address signals and level signals, in addition to other control signals, are stored in transit block buffer 750-102. That is, write cache flag and read quad flag bit positions of transit block buffer 750-102 are forced to binary ONES. The block address signals correspond to the read quad address applied to the RADO lines 24- 31 by processor 700. The65 - - GB 2 114 783 A 50 level signals TBRRO100-2100 written into transit block buffer 750-102 are obtained from round robin register 750-504 as a consequence of a directoryassignment cycle of operation required because of having detected the miss condition.

When the SIU 100 begins the transfer of data, the circuits of block 750115 of Figure 4 force memory write request signal MEMMTREQ1 00 to a binary ONE. That is, the SIU 100 forces the DPFS line to a binary ONE indicating that the first two words are being transferred (waveform P). The SIU 100 also forces the ARDA line to a binary ONE to indicate that the requested read data is on the DFS lines.

Also, the states of the ARDA and DPFS lines are clocked into the FARDA and MPFS flip-flops of block 750-115. The presence of signals on these two flip-flops together with the write cache flag signal being a binary ONE result in the circuits of block 750-115 forcing signal MEMMTREQ1 00 to a binary ONE. At the same time, the SIU applies signals to the MIFS lines, bits 2 and 3 condition the transit block buffer 750-102 to read out the address and level signals for writing the pair of data words into cache storage unit 750-300. Also, the contents of the control bit positions including the write cache flag bit are read out.

The MEMMTREO, signal when a binary ONE operates to enable decoder circuit 750-30300 of Figure 7b. Upon decoding the level signals TBLEV01 00-2100 read out from buffer 750-102, decoder circuit 750-30300 forces one of the eight signals MEMLEV01 00 through MEMLEV71 00 to a binary ONE. At the same time, the complement signal of one of the eight signals is forced to a binary ZERO (i.e., one of the signals MEIVILEV0000 through MEMLEV7000). The result is that the appropriate one of the address selection ZADRO-7 switches 750-302a through 750-302n is conditioned to 20 select position 2 rather than position 1 (waveform R). It is only the address selection switch specified by the TB level signals that selects position 2. The remaining address selection switches for the other seven levels select position 1. As explained herein, this assumes no conflict between the instruction and memory data levels.

Therefore, as seen from Figure 8 (waveform R), the transit block address on the T clock is loaded into one of the RADRO-7 registers while the instruction register address from RIRA register 750 900 is loaded into the remaining RADR registers (waveform J). This permits the writing of the first memory data word loaded into the RDFS13 register 750-712 on the T clock to be written into cache unit 750-300 at the specified level on the 1/2 T clock concurrent with accessing an instruction word from the remaining sevel levels. The appropriate instruction word is selected as an output from ZCD 30 switch 750-306 under control of level 1 signals ZNICLEV01 00-2100 from RICA register 750 900. Since the RDIBUF line on the last T clock was a binary ONE, the LDA instruction word from ZCD switch 750-306 is loaded into RIRA register 750-308 on the 1/2 T clock (waveform M. On the next T clock, the second LDA instruction is loaded into the RBIR register of processor 700 (waveform F).

Since there are seven levels available from which instructions can be accessed concurrent with 35 writing memory data, the conflicts are reduced significantly. However, when a conflict is detected by the comparator circuits of blocks 750-914 and 750-916, this causes the circuits of block 750 920 to hold up instruction accessing. Since processor 700 will not be pulling instructions from cache 750 on every T clock, this has little effect, if any, on processor operation.

When there is a conflict, signal MPDATA/ICLEV1 00 switches to a binary ONE. This is shown by 40 the dotted portion of waveform V of Figure 8. In greater detail, it is seen from Figure 7d that the memory write request signal MEMMTREQ1 00 when forced to a binary ONE, one of the sections of the comparator circuits of blocks 750-912 and 750-914 forces signal MPDATA/ICLEV1 00 to a binary ONE and signal CIVIPDATA/ICLEV000 to a binary ZERO when the transit block buffer level signals RTBLEV01 00-2100 are identical to the instruction level 1 signals ZNICLEV01 00-2100.

The signal CIVIPDATA/ICLEV1 00 switches the FINI-IRDY flip-flop 750-92150 to a binary ONE on a T clock during the second half of the fourth cycle when processor 700 forces the RDIBUF line to a binary ONE. The flip-flop 750-92150 when a binary ONE conditions AND/OR gate 750-92156 to switch signal IFETCHMY000 to a binary ONE. The result is that the circuits of block 750-114 force the IBUFRDY line to a binary ZERO. This is indicated by the dotted portion of waveform W in Figure 8.

The signals CIVIPDATA/ICLEV000 and FINI-IRDY000 inhibit the circuits of block 750-920 from incrementing the address contents of RICA register 750-900 and strobing RIRA register 750-308 (i.e., inhibits generation of signals [RICA1 00, [R1RA1 00 and setting of FRDIBUF flip-flop).

The above conflict results in delaying the accessing of instructions until the first 1/2 T clock after the four words of memory data have been written into cache unit 750-300. This is illustrated by the 55 dotted portions of the waveforms H, 1 and K in Figure 8. Thus, the second LDA instruction will not be loaded into the processor's RBIR register until 3 T clock cycles later.

The remaining three words of memory data are written into cache unit 750300 in the manner previously described. Of course, where there is no conflict, each of the three words will be written into cache unit 750-300 concurrently with the pulling of instruction words from cache unit 750-300 60 (waveforms R, S and J, K of Figure 8). That is, as long as the write cache flag control bit read out from transit block buffer 750-102 is a binary ONE, the data word is clocked from the RDFS register 750 702 into the RDFS[3 register 750-712 on a next T clock signal and written into cache unit 750-300 on the following 1/2 T clock. These operations are repeated twice for each pair of read quad data words received from S1U100.

4 a z R 51 GB 2 114 783 A 51 Also, during a first T clock cycle (fourth cycle which corresponds to an 1 cycle) processor 700 begins executing the LDA instruction as explained herein. This involves the formation of an address which is included in a read single command forwarded to cache 750 by processor section 704-4 of Figure 3e. The command is coded to specify a memory read quad operation for fetching a 4 word block from memory 800. In greater detail, the generated address loaded into the RADO register 704-46 5 serves as the command address. Additionally, command bits 1-4 and zone bits 5-8 are generated by the circuits 704-118 of Figure 5c and switch 704-40. The zone bits 5-8 are set to binary ONES, since they are not used for read commands. Command bits 1-4 are forced to a command code of 0 111 by the decoder circuits of block 704-118 (i.e., quad operation). The circuits of block 704 108 generate the cache command signals coded to specify a read single type command which are 10 applied to the DMEM lines. The decoder 704-120 forces the DREXAC line to a binary ONE. As seen from Figure 8, during the next T clock cycle 5, which corresponds to a C cycle, processor 700 signals cache 750 of the cache request by forcing the DREQCAC line to a binary ONE (i.e., waveform G).

The address contained within the read command is applied via MAD switch 750-530 as an input to ZADRO-7 switches 750-301 a through 750-301 n in addition to the directory circuits of 15 blocks 750-500 and 750-502. As seen from Figure 7c, during the first half of the fifth cycle, AND/NAND gate 750-92051 and NAND gate 750-92052 force signals ENBIVIEMLEV1 00 and ENBADR1 100 is binary ZEROS. The result is that the circuits of block 750303 cause the pairs of control signals [ZADR001 00, [ZADR01 100, through [ZADR701 00, [ZADR71 100 to be binary ZEROS.

Accordingly, the ZADRO-7 switches 750-302a through 750-302n select MAD switch 750-532 20 as an address source.

As seen from Figure 8, the read command address is loaded into the RADRO7 registers 750 301 a through 750-301 n for application to all levels on a 1/2 T clock in response to signal [CLKHT1 00 (i.e., waveform H). When a hit condition is detected by the circuits of block 750-512, this causes the operand address word at the specified level to be read out from ZCD switch 750-306 25 during the second half of the T clock cycle as illustrated in Figure 8 (i. e., waveform 1).

in greater detail, with reference to Figure 7c, it is seen that the circuits of block 750-526 force signal GSRC1 1100 to a binary ONE during the second half of a T clock cycle. The hit signals ZHT1 100 through ZHT71 00 from circuits 750-546 through 750-552 are used to control the operation of ZCD switch 750-306 in accordance with the results of the search operation just performed. In the case of a hit condition, when one of the signals ZHT1 100 through ZHT71 00 is forced to a binary ONE and the hit detected level is used to generate signals [ZCD01 00 through [ZCD21 00. This results in the operand address word from the level at which the hit occurred to be applied to the M1 lines via position 1 of Z131 switch 750-312. As seen from Figure 8, the comparison of bits 10-23 of the read command address, the encoding of the hit level signals when there is a hit and the enabling of the ZCD 35 switch 750-526 requres a full T clock cycle of operation.

The operand word applied to the M1 lines is loaded into the processor's RDI data register 704 164 of Figure 3c in response to T clock signal [CILM 00 (waveform 1 of Figure 8).

When a hit condition is not detected, the output signals applied to the M1 lines are still loaded into RDI data register 704-164, but the processor 700 is prevented from further processing or held 40 via the CPSTOP line. When the requested information is obtained from memory by cache unit 750, the contents of RDI data register 704-164 are replaced at which time the DATARECOV line is forced to a binary ONE and processor 700 is permitted to continue processing (i.e., the CPSTOPOOO line is forced to a binary ONE).

While it is to be seen that the read command address from processor 700 was loaded into the 45 RADR register 750-301 on the 1/2 T clock in response to signal [CLKHT1 00, other addresses also are loaded into the RADR register 750-301 during the other 1/2 T clock times, but they are not meaningful. Hence, they are not shown in Figure 8.

It will be noted from Figure 8 that processor 700 prior to generating the read command forces the RDIBUF line to a binary ONE a second time during the third cycle. This signals cache unit 750 that 50 the processor 700 has taken the first LDA instruction on the previous T clock. Hence, during the first half T of the fourth cycle, cache unit 750 refills the RIRA register 750- 308 with the next instruction.

This corresponds to the STA instruction in Figure 8.

In greater detail, it is seen from Figure 7c that the circuits of block 750-526 force signal ZCD1CENA131 00 to a binary ONE. This conditions the circuits of block 750- 512 to apply level signals 55 ZNICLEV01 00 through ZNICLEV21 00 from RICA instruction register 750-900 as control signals [ZCD01 00 through [ZCD21 00 to ZCD switch 750-306. This causes the STA instruction at the location specified by the address contents of RADR register 750-301 loaded on the previous T clock (waveform J) to be selected for loading into RIRA register 750-308 by ZCD switch 750-360 (i.e., waveform K). Thereafter, the LDA instruction is loaded into the RBIR register of processor 700 on the T 60 clock in response to signal [CLKT1 00 (i.e., waveform L).

The LDA instruction remains in the RBIR register only for one clock period. Therefore, the STA instruction is loaded into the RBI R register on the T clock as discussed above.

Figure 8 illustrates the operation of an alternative embodiment of the present invention. In this embodiment, instructions are always fetched during the first half of a T clock cycle. The writing of 65 52 GB 2 114 783 A 52 memory data occurs concurrently with the accessing of instructions when there is no conflict between levels.

However, in the case of a conflict detected during the first half of the T clock cycle, memory data is written during the second half of the T clock cycle. The writing of memory data proceeds concurrently with the processor's accessing of operands when the levels are not the same. In the case where a processor read command specifies accessing an operand at the same level into which the memory data is written, the accessing of the operand is delayed by at least one T clock until no conflict is present. Of course, a processor write command will cause a conflict since the writing of data can only proceed through the ZCDIN switch 750-304.

It will be appreciated that the alternate embodiment, requires additional circuits for storing the hit 10 level signals, for detecting the conflict and for controlling the hold logic circuits of block 750-116 and the operation of the data recovery circuits as explained herein.

The waveforms H and T illustrate the case where a memory data address is loaded into a specified one of the RADRO-7 registers 750-301 a through 750-301 n while the processor read command address is loaded into seven of address registers 750-301 a through 750-301 n. That is, 15 the memory write request signal MEMMTREQ1 00 is forced to a binary ONE during the second half of the fifth T clock cycle, causes one of the ZADRO-7 address selection switches 750-302a through 750-302n specified by level signals RTBLEV01 00-2100 to switch from position 0 to position 2. This, in turn, loads one of the RADRO-7 registers with the address from transit block buffer 750- 102. The remaining seven registers are loaded with the read command address from MAD switch 750-530.

On the T clock at the time when the operand output from cache 750 applied to the M1 lines via Z131 switch 750-312 is loaded into the processor's RDI register (wavefrom 1), a comparison is made between the hit level and level into which memory data is being written. The comparison is made by comparison circuits such as those of blocks 750-912 and 750-914 of Figure 7d. Anytime the comparison circuits detect that the hit level signals resulting from the search cycle of operation (i.e., signals ZCD01 00ZCD21 00) are identical to the level signals RTBLEV01 00-2100, they force output compare signal CIVIP13ATA/OPERLEV to a binary ONE (waveform X). This conditions the hold circuits of block 750-116 to force the CPSTOPOOO line to a binary ZERO (waveform Y). The true comparison, in effect, causes the cache circuits to simulate a miss condition until the conflict of writing 30 memory data and operand accesses no longer is present.

As seen from waveforms H and 1 of Figure 8, the detection of a conflict delays the accessing of the operand until the writing of memory data has been completed. At that time, the operand is accessed from cache unit 750-300 and strobed into RDI register of processor 700 by the data recovery circuits. At that time, processor 700 is released (i.e., the CPSTOPOOO line is forced to a binary 35 ONE).

It will be appreciated that when the memory write request signal MEMWRTREG1 00 is forced to a binary ONE during the first half of a T clock cycle, the level signals RTBLEVO 100-2100 from transit block buffer 750-102 are saved in a register for writing memory data during the second half of a T clock cycle.

Now, the description of Figure 8 will be completed with reference to the first embodiment. That is, the STA instruction causes the processor 700 to generate a second cache request to cache unit 750. In greater detail, the STA instruction requires two processor cycles for completion. During the first cycle, processor 700 carries out operations similar to those required for the LDA instruction which results in generating the address. This address is included in the write single command which processor 700 forwards to cache unit 750 and the end of the first cache cycle. At that time, processor 700 forces the DREQCAC line to a binary ONE (waveform M).

As seen from Figure 8, the write command address applied to the ZADOB/RADO lines is loaded into RADR register 750-301 from position 1 of ZADR switch 750-302. During the first half of the sixth cycle, when there is no memory data transfer, the circuits of block 750-92000 of Figure 7d force signals ENBIVIEIVILEV1 00 and ENABADR1 100 to binary ZEROS. This causes the circuits of block 750-303 to force the sets of signals [ZADR001 00, [ZADR01 100 through [ZADR701 00, [ZADR71 100 to binary ZEROS. Accordingly, ZADRO-7 switches 750-302a through 750-302n connect the address output of MAD switch 750-530 as the address input to RADRO-7 registers 750-301 a through 750-301 n. While the command write address is clocked into RADRO-7 registers on the 1/2 T clock in response to signal [CLKHT1 00 and applied to all of the levels, nothing happens at this time, since the directory search must be performed for the write command (i.e., no write signals are generated). The write command address is saved in the RDAD register 750-532 for writing the processor data word during the next T clock cycle.

The write command address is also applied to directories 750-500 and 750502 for carrying 60 out a search cycle of operation. As mentioned, the search operation requires a full T clock cycle. As seen from Figure 8, the write command address saved in the RDAD register 750-532 is applied via position 1 of MAD switch 750-530 to the ZADRO-7 switches 750-302 during the first half of the seventh clock cycle. Again, ZADRO-7 switches 750-302 connect the address output of MAD switch 750-530 as the address input to RADRO-7 registers 750-301 a through 750-301 n. The 65 4 C W 53 GB 2 114 783 A 53 write command address is again clocked into address registers 750-301 a through 750-301 n on the 1/2 T clock in response to signal [CILKI-IT1 00.

Referring to Figure 7e, it is seen that during the second half of the seventh T clock cycle, the multiplexer circuit 750-92002 applies the hit level signals RHITLEV01 00 through RHITLEV21 00 from the circuits of block 750-512 as inputs to register 750-92006. These signals are clocked into 5 register 750-92006, in response to 1/2 T clock signal [C1-KI-IT02 1, and applied to the inputs of decoder circuits 750-92008 through 750-92014. At the same time, the zone signals ZONE01 00 through ZONE31 00 from switch 750-144 obtained from processor 700 are also loaded into register 750-92006, during the second half of the cycle.

During the second cycle of the STA instruction, processor 700 transfers the data word via the 10 ZADO lines and the RADO register to cache unit 750. At this time, the circuits of block 750-526 condition ZCDIN switch 750-304 to apply the processor data word via position 1 as an input to all of the levels of cache storage unit 750-300. The decoder circuits of block 750-920000 force one of the write signals of one of the sets of write signals (e.g. signal W13TO0 100) for writing the data word into the appropriate zone (waveform 0).

As seen from Figure 8, during the third cycle, processor 700 again forces the RDIBUF line to a binary ONE indicating that the STA instruction was loaded into the RBIR register. During the first half of the fifth cycle, the RDIBUF flip-flop of register 750-92024 set by the RDIBUF signal causes the second LDA instruction, stored at the location specified by the contents of RADR register 750-301, to be loaded into RIRA register 750-308 (waveform K). That is, the RDIBUF flip-flop causes signal 20 TAKEINSTOOO to be forced to a binary ZERO, which forces signal [R1RA1 00 to a binary ONE.

The RADRO-7 registers 750-301 a through 750-301 n are loaded with an address from RIC-A instruction register 750-900, during the second half of the fourth cycle via ZIC switch 750-906 and position 1 of ZADR switch 750-302 (waveform J). This address is applied to the address inputs of all levels of cache storage unit 750-300. Also, during the first half of the fifth cycle, the address contents of the RICA register 750-900 are incremented by one and loaded back into the register 750-900.

The read out of the appropriate instruction from ZCD switch 750-306 proceeds under the control of the level signals ZNICLEV01 00-2100 from switch 750-910 which are used to generate signals ZCD01 00-2 100.

While the RIRA register 750-308 is loaded with the second LDA instruction, it is seen from 30 Figure 8 that it is not transferred to the RBIR register until the sixth cycle (waveform F). The reason is that the STA instruction, as mentioned previously, requires two cycles.

Following the completion of the 1 cycle execution of the STA instruction, processor 700 forces the RDIBUF line to a binary ONE (waveform E). As seen from Figure 8, the second LDA instruction, following its loading into the RBIR register, results in processor 700 forwarding a second read 35 command to cache 750, as signalled by the forcing of the DREXAC line to a binary ONE (waveform G). In the manner previously described, the read command address from processor 700 is loaded into RADRO-7 registers 750-301 a through 750-301 n, during the first half of the eighth cycle, in response to signal [CLKHT1 00 (waveform H). During the second half of the cycle, the operand address word, from the level at which the hit condition occurred, is loaded into the processor RDI register via 40 the M1 lines.

Because the RDIBUF line was forced to a binary ONE during the sixth cycle, this again causes a new instruction corresponding to the second STA instruction to be loaded into RIRA register 750 308, during the first half of the seventh cycle (waveform K). The STA instruction is loaded into the processor RBIR register on the T clock, during the second half of the seventh cycle (waveform L).

In the manner previously described, the processor 700 generates a second write command which is forwarded to cache unit 750, during the ninth cycles, and signalled by forcing the DREQCAC line to a binary ONE (waveform M). The write command address is loaded into the RADRO-7 registers 750 301 a through 750-301 n from the RADO lines and RDAD register 750-532 on the 1/2 T clock, in response to signals [CLKHT1 00 (waveform N). During the second half of the tenth cycle, the processor 50 data word is written into cache unit 750-300. Also, the next instruction is loaded into RIRA register 750-308, during the first half of the eighth cycle (waveform K).

From the foregoing, it is seen how the arrangement of the preferred embodiment enables a plurality of operations to take place simultaneously, and how the arrangement of the preferred embodiment minimizes the interference among the different types of operations required to be performed by a cache system. Accordingly, this results in improved systems performance in terms of efficiency and hit ratio.

Also, it is seen how the arrangement of the preferred embodiment enables instructions to be accessed from cache storage unit 750-300 during the first half of a T clock cycle and the writing or read out of processor operands into and from cache storage unit 750-300 during the second half Of 60 the same T clock cycle.

It will be appreciated that in a system which has a high hit ratio such as the preferred embodiment, considerably more instructions are accessed from cache than memory data being written into cache. Hence, the split cycle arrangement minimizes interference between such instruction and processor operand accesses.

54 GB 2 114 783 A Also, the arrangement prevents interference between the writing of memory data and processor operand accesses. As mentioned, during the first portion of each T clock cycle, when there is data to be written into cache storage unit 750-300, the circuits of block 750-115 force the memory write request signal to a binary ONE. This results from the MIFS steering signals returned by main memory 800. Bits 2 and 3 are used to select the address contents of one of the transit block buffer locations for 5 read out into the RADR register 750-301.

Referring to Figure 7e, it is seen that signal MEMMTREQ1 00 from 750-115 causes AND/NAND gate 750-9205 to force signal EN13MEMLEV1 00 to a binary ONE and signal EN13MEMLEV000 to a binary ZERO. This causes AND gates 750-30302 and AND gate 750-30304 to force control signals [ZADR01 100 and [ZADR001 00 to a binary ONE and a binary ZERO, respectively. The result is that the ZADR switch 750-302 selects position 2 (ZTBA) instead of position 1. Accordingly, the transit block buffer is connected as the address source for the RADR register 7 50 301.

On the T clock signal, the transit block buffer address is loaded into the RADR register. On the 1/2 T clock following that T clock, the memory data signals which are loaded into RDHB register 750- 15 712 are written into cache storage unit 750-300 via WDIN switch 750-304 at the address read out from buffer 750-102.

As seen from Figure 7e, the signal MEMMTREQ1 00 forces the bottom three flip-flops of register 750-92006 to binary ONES. This enables all of the decoder circuits 750- 92008 through 750 92014 for operation. Accordingly, each of these circuits decodes the level signals RTBLEV01 00 through RTBLEV21 00 and forces one of its outputs to a binary ONE. This causes all four bytes of the data word to be written into cache unit 750-300. It will be appreciated that the remaining words of the data block are written into cache unit 750-300 in the same manner during the first half of successive T clock cycles of operation.

It will be noted that in those instances where memory data is being received preventing instruction accesses, the circuits of block 750-920 prevent the IBUFRDY line from indicating a ready condition. That is, the signal MEMWRTREQ1 00 causes the inhibit instruction ready FINHRDY flip-flop 750-92150 to be forced to a binary ONE. This causes AND/OR gate 750-92156 to force signal IFETCHRDYOOO to a binary ONE. The result is that signal IBUFRDY1 00, generated by the circuits of block 750-115, is forced to a binary ZERO indicating a non-ready condition.

Claims (1)

1. Claims

   1. A cache unit for use with a data processing unit for providing fast access to information fetched from a main store coupled to said cache unit in response to commands received from said data processing unit, said cache unit having a cycle of operation and comprising a buffer store including a plurality of addressable word locations for storing said information, address switch selection means having a number of inputs for receiving a corresponding number of addresses from a corresponding number of address sources and an output, address register means coupled to said output and to said buffer store, said address register means for storing the address specifying the word location to be accessed during the cache cycle of operation, control circuit means coupled to said address switch selection means, said control circuit means generating and supplying coded control signals to said 40 address switch selection means for identifying which address source is connected to supply said address to said address register means, and timing means for generating timing signals for defining a number of intervals of said cache cycle of operation, said timing means being coupled to said control means, said control means being conditioned by said timing means during one of said intervals to enable said address selection means to select an address for loading into said address register means from one of said address sources and said control means being conditioned during another one of said intervals to enable said address switch selection means to select an address for loading into said address register means from another one of said address sources for enabling the accessing of the information stored in the locations specified by both address sources during the same cache cycle without interference between said accesses.

   2. A cache unit according to Claim 1 wherein said information includes data and instructions and said buffer store word locations are organized into a plurality of levels, and wherein said timing means generates first and second timing signals for defining first and second intervals corresponding to said number of intervals.

   3. A cache unit according to Claim 2 wherein said levels are organized vertically for accessing 55 information on a word basis.

   4. A system according to any of Claims 1 to 3 wherein said timing means includes a clocked bistable element having a clock input terminal, a gate input terminal and at least one output terminal, first input means for receiving a first series of clock pulses for defining a time interval which is one-half the duration of said cache cycle, said first input means being connected to said clock input terminal, 60 and second input means for receiving a definer clock pulse signal, said second input means being connected to said gate input terminal, said bistable element being conditioned by said clock pulses and said definer clock pulse signal to produce at said output terminal, a bistate signal whose first and second states define said first and second intervals of said cache cycle.

   4 A i 56 GB 2 114 783 A 56 first and second memory write enabling signals designated as ENBIVIEIVILEV and ENBIVIEIVILEV respectively in accordance with the expressions:

   ENBMEMLEV=MEMWRTREQ. FIDN2HT and ENBIVIEIVILEV=MEMWIRTREQ. IFIDN2HT wherein signal MEMMTREO. indicates that said requested information is to be written into said buffer 5 store and signal M2HT defines said second interval, and said first and second gating means generates first and second coded control signals [ZADRID and (ZADR respectively in accordance with the expressions:

   ZADRO=ENABIVIEMILEV. ENBADR and [ZADRO=ENABMEMLEV-ENBADR wherein signal ENBADR is a binary ONE during said second interval, for selecting an address from said instruction address register, said buffer and said input circuit means for loading into said address register means when signals [ZADRO, ZADRO have the values 00, 01 and 10 respectively.

   14. A cache unit according to Claim 12 or Claim 13 wherein said control means further includes fourth gating means for generating an output signal for indicating when a predetermined type of command from said data processing unit was decoded during said first interval, said fourth gating means being coupled to said first and second gating means, said fourth gating means being operative in response to said predetermined type of command to force signal ENBADR to a binary ONE enabling said address switch selection means to select an address from said instruction address register means for loading into said address register means during said first interval for accessing an instruction from 20 said levels of said buffer store during said second interval.

   15. A cache unit according to Claim 14 wherein said predetermined type of command includes a command code specifying an operation for loading the address of a next block of instructions into said instruction address register means for enabling said data processing unit to access further instructions from said buffer store during subsequent cache cycles.

   16. A cache unit according to any of Claims 2 to 15 wherein each of said commands includes a command code and an address and wherein each level of said buffer store contains a number of blocks of said word locations, each level and each block being defined by a level address and a block address respectively and said cache unit further including a directory having a plurality of locations corresponding in number to the number of levels in said buffer store and being addressable by said 30 level addresses, each location of said directory storing block addresses of blocks of words within the associated level stored in said buffer store, said directory responsive to said level address corresponding to a low order portion of said command address to read out said block addresses corresponding to a high order portion of said command address, comparison means coupled to said directory for comparing said block addresses read out from said directory with the high order portion of 35 said command address and generating hit detection signals indicative of whether or not the information being accessed is stored in said buffer store, and directory level control means coupled to said split cycle timing means to said comparison means and to said buffer store, said directory level control means in response to said hit detection signals being operative to generate a set of hit level signals during said second interval of a next cache cycle for enabling the transfer of a requested operand word to said data processing unit specified by each command having a command code specifying a read type operation in accordance with the results of a directory search operation performed during the previous cache cycle without interfering with transferring instruction words requested by said data processing unit.

   17. A cache unit according to Claim 16 wherein said cache unit further includes output multiposition switch means including a number of sets of input terminals corresponding to the number of levels, a plurality of output terminals and a set of control input terminals, and a number of conductor means, each coupling a different one of said number of sets of input terminals to the output of said buffer store for receiving signals read out from a different one of said levels of said buffer store and said control input terminals being connected to receive said set of hit level signals, said multiposition switch 50 means being conditioned by said set of hit level signals to apply to said output terminals said signals from one of said levels designated by said level signals as the operand word to be transferred to said data processing unit during said second interval of said next cache cycle.

   18. A cache unit according to Claim 16 or Claim 17 wherein said cache unit further includes input switch means including at least one set of input terminals coupled to receive information to be written 55 into said buffer store during said cache cycle and a set of output terminals coupled to apply said information to each of said levels of said buffer store, and write control circuit means comprising decoder circuit means including first input means for receiving said set of hit level signals and second input means for receiving write control signals specifying those portions of said information applied from said input switch means to be written into said buffer store, said decoder circuit means being 60 1 GB 2 114 783 A 5. A cache unit according to Claim 2 or any claim appendant thereto wherein said control circuit means includes first gating means coupled to receive said first timing signal from said timing means, said gating means being operative to generate an output signal for enabling the loading of address information into said address register means during said first interval for accessing information from said levels of said buffer store during said second interval of said cache cycle, second gating means coupled to receive said second timing signal from said timing means, said second gating means being operative to generate an output signal for enabling the loading of address information into said address register means during said second interval for enabling access to information stored in said levels of said buffer store during said first interval of said cache cycle, and said address switch selection means having control inputs connected to said first and second gating means, said address switch selection 10 means being conditioned by said coded signals for enabling said address switch selection means to load said address register means with said addresses from said address sources during said first and second intervals of said same cache cycle of operation.

   6. A cache unit according to Claim 5 wherein said one of said address sources includes an instruction address register coupled to said one of said inputs of said address switch selection means, 15 said instruction address register including a number of bit positions, a group of said bit positions storing an address specifying a next word location within said levels of said buffer store from which an instruction word is to be accessed during said first interval of said cache cycle.

   7. A cache unit according to Claim 6 wherein each of said commands includes a command code and an address and one of said address sources connected to another one of said inputs of the address 20 switch selection means includes an input circuit means coupled to said processing unit for receiving said address of each said command, said input circuit means being connected to said another one of said inputs of said address switch selection means and said input circuit means being operative to apply said command address specifying a word location within each of said levels of said buffer store from which an operand word is to be fetched or into which an operand word is to be written during said 25 second interval of said cache cycle.

   8. A cache unit according to Claim 7 wherein said address sources connected to said another one of said inputs of the address switch selection means comprises a buffer for storing at least one address derived from a command which has a command cycle specifying a read type operation, said address specifying the word location within said buffer store into which the information requested from said. 30 main store by said command is to be written, and means coupled to said buffer and to said address switch selection means, said means for applying said address to a further one of said inputs of said address switch selection means for loading into said address register means enabling the writing of said information into said buffer store during said first interval of said cache cycle.

   9. A cache unit according to Claim 8 wherein said buffer is arranged to store a set of level signals 35 specifying which one of said levels in which said requested information is to be written and said cache unit further including input switch means including at least one set of input terminals coupled to receive information to be written into said buffer store during said cache cycle and a set of output terminals coupled to apply said information to each of said levels of said buffer store, and write control circuit means comprising decoder means for receiving said set of level signals from said buffer, said 40 decoder circuit being enabled in response to said set of level signals to generate a set of write control signals for writing said information into the location and level of said buffer store specified by said buffer during said first interval.

   10. A cache unit according to Claim 9 wherein said unit further includes an input data register coupled to receive data words from a main store transferred in response to one of said commands having a command code specifying a read type operation previously stored in said buffer, said input data register being coupled to said one set of input terminals of said input switch means for enabling said data words to be applied to said levels of said buffer store during said first intervals of said cache cycle for writing into the designated level.

   11. A cache unit according to any of Claims 8 to 10 wherein said control means further includes 50 third gating means for generating memory write enable signals enabling said requested information to be written into said buffer store during said first interval, said third gating means being connected to condition said first and second gating means for generating said coded control signals to cause said address switch selection means to switch from a first position to a second position for selecting said address from said buffer in place of said address from said instruction address register for loading into 55 said address register means.

   12. A cache unit according to Claim 11 wherein said unit further includes instruction ready control circuit means for generating an output signal to said data processing unit for signalling when instructions are ready to be accessed from said buffer store, and inhibit control means coupled to said third gating means and to said instruction ready control means, said inhibit control means being conditioned by said third gating means to inhibit said instruction ready control circuit means for generating said output signal when said requested information is being written into said buffer store during said first interval.

   13. A cache unit according to Claim 11 or Claim 12 wherein said third gating means generates 57 GB 2 114 783 A 57 operative in response to said set of hit level signals to generate a set of write control signals for writing said information into the designated one of said levels of said buffer store during said intervals.

   19. A cache unit according to Claim 18 wherein each of said commands whose command code specify a write operation comprises a number of data words to be written into said main store, and wherein said input switch means includes another set of input terminals, said cache unit further including input conductor means coupled to said another set of input terminals for enabling said number of data words to be applied to all of said levels of said buffer store during said second interval of said cache cycle for writing therein when said hit detection signals indicate that the block of information words specified by said command resides in said buffer store.

   New claims or amendments to claims filed on 20.12.82 Superseded claims New or amended claims:- 1. A cache unit for use with a data processing unit for providing fast access to information fetched from a main store coupled to said cache unit in response to commands received from said data processing unit, said cache unit having a cycle of operation and comprising a buffer store including a 15 plurality of addressable word locations for storing said information, address switch selection means having a number of inputs for receiving a corresponding number of addresses from a corresponding number of address sources and an output, address register means coupled to said output and to said buffer store, said address register means storing the address specifying the word location in the buffer store to be accessed during the cache cycle of operation, control circuit means coupled to said address 20 switch selection means, said control circuit means generating and supplying coded control signals to said address switch selection means for identifying which address source is connected to supply said address to said address register means, and timing means for generating timing signals for defining a number of intervals within said cache cycle of operation, said timing means being coupled to said control circuit means, said control circuit means being conditioned by said timing means during one Of 25 said intervals to enable said address selection means to select an address for loading into said address register means from one of said address sources and said control circuit means being conditioned during another one of said intervals to enable said address switch selection means to selectan address for loading into said address register means from another one of said address sources for enabling the accessing of the information stored in the locations specified by both address sources during the same 30 cache cycle without interference between said accesses.

   2. A cache unit according to Claim 1 wherein said information includes data and instructions and said buffer store word locations are organized into a plurality of levels, and wherein said timing means generates first and second timing signals for defining first and second intervals corresponding to said number of intervals.

   3. A cache unit according to Claim 2 wherein said levels are organized vertically for accessing informbtion on a word basis.

   4. A cache unit according to any of Claims 1 to 3 wherein said timing means includes a clocked bistable element having a clock input terminal, a gate input terminal and at least one output terminal, first input means for receiving a first series of clock pulses for defining a time interval which is one-half 40 the duration of said cache cycle, said first input means being connected to said clock input terminal, and second input means for receiving a definer clock pulse signal, said second input means being connected to said gate input terminal, said bistable element being conditioned by said clock pulses and said definer clock pulse signal to produce at said output terminal, a bistate signaf whose first and second states define said first and second intervals of said cache cycle. from which an instruction word is to be accessed during said first rnterval of said cache cycle.

   7. A cache unit according to Claim 6 wherein each of said commands includes a command code and anaddress and one of said address sources connected to another one of said inputs of the address switch selection means includes an input circuit means coupled to said processing unit for receiving said address of each said command, said input circuit means being connected to said another one of 50 said inputs of said address switch selection means and said input circuit means being operative to apply said address specifying a word location within each of said levels of said buffer store from which an operand word is to be fetched or into which an operand word is to be written during said second interval of said cache cycle.

   8. A cache unit according to Claim 7 wherein said address sources connected to said another one 55 of said finputs of the address switch selection means comprises a buffer for storing at least one address derived from a command which has a command cycle specifying a read type operation, said address specifying the word location within said buffer store into which the information requested from said main store by said command is to be written, and means coupled between said buffer and said address switch selection means which applies said address to a further one of said inputs of said address 60 switch selection means for loading into said address register means enabling the writing of said information into said buffer store during said first interval of said cache cycle.

   58 GB 2 114 783 A 58 9. A cache unit according to Claim 8 wherein said buffer is arranged to store a set of level signals specifying one of said levels into which said requested information is to be written and said cache unit further including input switch means including at least one set of input terminals coupled to receive information to be written into said buffer store during said cache cycle and a set of output terminals coupled to apply said information to each of said levels of said buffer store, and write control circuit means comprising decoder means for receiving said set of level signals from said buffer, said decoder circuit being enabled in response to said set of level signals to generate a set of write control signals for writing said information into the location and level of said buffer store specified by said buffer during said first interval.

   10. A cache unit according to Claim 9 wherein said unit further includes an input data register 10 coupled to receive data words from a main store transferred in response to one of said commands having a command code specifying a read type operation previously stored in said buffer, said input data register being coupled to said one set of input terminals of said input switch means for enabling said data words to be applied to said levels of said buffer store during said first intervals of said cache cycle for writing into the designated level.

   11. A cache unit according to any of Claims 8 to 10 wherein said control means further includes third gating means for generating memory write enable signals enabling said requested information to be written into said buffer store during said first interval, said third gating means being connected to condition said first and second gating means for generating said coded control signals to cause said address switch selection means to switch from a first position to a second position for selecting said 20 address from said buffer in place of said address from said instruction address register for loading into said address register means.

   12. A cache unit according to Claim 11 wherein said unit further includes instruction ready control circuit means for generating an output signal to said data processing unit for signalling when instructions are ready to be accessed from said buffer store, and inhibit control means coupled to said third gating means and to said instruction ready control circuit means, said inhibit control means being conditioned by said third gating means to inhibit said instruction ready control circuit means from generating said output signal when said requested information is being written into said buffer store during said first interval.

   13. A cache unit according to Claim 11 or Claim 12 wherein said third gating means generates 30 first and second memory write enabling signals designated as ENBIMEMILIEV and ENBIVIEIVILEV respectively i accordance with the expr ssions: ENBMEMLEV=MEMWRTREQ - FDN2HT and ENBMEMLEV=MEMWRTREQ. MN2HT wherein signal MEMWRTREQ indicates that said requested information is to be written into said buffer store and signal FIDIN2HT defines said second interval, and said first and second gating means generates first and second coded control signals [ZADRO and [Z-ADRO respectively in accordance during subsequent cache cycles.

   16. A cache unit according to any of Claims 2 to 15 wherein each of said commands includes a command code and an address and wherein each level of said buffer store contains a number of blocks of said word locations, each level and each block being defined by a level address and a block address respectively and said cache unit further including a directory having a plurality of locations cormsponding in number to the number of levels in said buffer store and being addressable by said level addresses, each location of said directory storing block addresses of blocks of words within the associated level stored in said buffer store, said directory responsive to said level address corresponding to a low order portion of said command address to read out said block addresses corresponding to a high order portion of said command address, comparison means coupled to said.directory for comparing said block addresses read out from said directory with the high order portion of said command address and generating hit detection signals indicative of whether or not the information being accessed is stored in said buffer store, and directory level control means coupled to said timing means to said comparison means and to said buffer store, said directory level control means in response to said hit detection signals being operative to generate a set of hit level signals during said second interval of a next cache cycle for enabling the transfer of a requested operand word to said data processing unit specified by each command having a command code specifying a read type operation in accordance with Printed for Her Majesty's Stationery Office by the Courier Press, Leamington Spa, 1983. Published by the Pathrit Office, 25 Southampton Buildings, London, WC2A lAY, from which copies may be obtained -0 i 1 -l o ' Y,