CA1141040A - Data processing apparatus - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

A cache system includes a storage unit organized into a plurality of levels, each including a number of multiword blocks and a corresponding number of address selection switches and address registers. Each address selection switch has a plurality of different positions connected to receive address signals from a plurality of address sources. A decoder circuit generates output signals for controlling the operation of the address selection switches.
In response to previously defined level signals, the decoder circuit conditions a specified one of the number of switches to switch from a first position to a second position. An address specifying the location into which memory data is to be written is clocked into one address register while the address specifying the location from which an instruction is to be fetched is clocked into the remaining address registers. A comparator circuit compares signals indicating the level into which memory data is to be written with signals indicating the level from which a next instruction is to be fetched. The comparator circuit generates signals which cause the delay of instruction access when there is a conflict between writing memory data and accessing instructions.

Description

~4~

~, The present invention relates to data processing systems and more particularly to cache memory systems.
It is well known to provide hierarchal memory organizations in which a large slow s~eed main memory operates in conjunction with a small high speed bu~er storage unit or cache. In such arrangements, the central processing unit ~CPU) can access operand data and!or instructions at a rate which more closely approximates the machine. During normal operation, when the CPU provides the address of the information to be accessed, control circuits per~orm a search of a directory which stores associative addresses for specifying which blocks o~ informatlon reside in cache (i.e., define hit condition). When it determines that the information resides in cache, the information is accessed and transferred - 15 to the CPU. When the requested information is not in cache, the control circuits request the information from main memory and upon its receipt write -the information into cache at which time it may be accessed. ~ ` -Examples of such systems are disclosed in co pending patent applications o~ Charles ~. Ryan and in U.5. Patent No. 3,588,829. In the system disclosed in the Ryan applications, the cache includes four levels which were addressed by the same set o~ address signals for accessing of four words of a block of instruction or data. _7;
~

Sinee memory data must be proeessed on a real time basis, the writing o~ memory data normall~ inter~eres with such accessing of instructions. To overcome such interference, prior art arrange~ents hold up proeessor operations until the memory data is written into cache. This has been found to limit the overall aceess rate o~ the CPU resulting in a deerease in CPU periormanee.
Aeeordingly, it is a primary object of the present invention to provide a cache arrangement whieh provides a central processing unit with rapid access to in~ormation.
It has been reeognized that the limiting factor for the rate at whieh caehe aecesses take place is the time required to per~orm a directory search. In general, an entire caehe eyele of operation is required to determine whether the requested in~ormation is in cache (i.e., make a directory access and compare associative addresses).
In the case of a hit condition indicating the in~ormation to be fetched or updated is in cache, further access is required for completing the processor operation of either aceessing operand data or wri-ting data into the cache.
Since the caehe memory data must be processed on a real time basis and instruetion accesses must be made from cache, the writing of memory data and instruction accesses normally inter~ere wlth sueh operatlons. To overcome such interference, prior art arrangements hold up processor operations until the :

memory data is written into cache or instructions are accessed.
This has been found to limit the overall access rate of the CPU
resulting in a decrease in CPU performance.
Accordingly, it is a more specific object of the present invention to provide a cache arrangement which eliminates the interference between the different types of operations required to be performed.
According to the present invention, there is provided a cache unit for use with a data processing unit for providing fast access to information fetched from a main store coupled to said cache unit in response to commands received from said data processing unit, said cache unit comprising: a buffer store including a plurality of addressable word locations for storing said information address switch selection means having a number of inputs for receiving a corresponding number of addresses from a corresponding number of address sources and an output; address register means coupled to said output and to said buffer store, said address register means for storing the address specifying the word location to be accessed during a cache cycle of operation;
control circuit means coupled to said address switch selection means for generating coded control signals identifying which address source is connected to supply said address to said address register means; and, timing means for generating timing signals for defining a number of intervals of said cache cycle of operation, said timing means being coupled to said control means, said control means being conditioned by said timing means during one of said inter~als to enable said address selection means to select an address for loading into said address register means from one of said address sources and said control means being con-ditioned during another one of said intervals to enable said address switch selection means to select an address for loading into said address register means from another one of said address sources for enabling the accessing of said information specified by both address sources during the same cache cycle without inter-ference.
The invention further provides a cache unit for use with a data processing unit for providing fast access to instructions and data fetched from a main store coupled to said cache unit in response to commands received from said data processing unit, said cache unit comprising: a buffer store including a plurality of addressable word locations organized into a plurality of levels for storing said data and instructions; multiposition address switch selection means having a number of sets of input terminals for receiving a corresponding number of sets of address signals from a corresponding number of address sources, a plurality of output terminals and a plurality of control input terminals; an address register coupled to said plurality of output terminals and to said buffer store, said address register for storing the address specifying the word location within said levels to be accessed during a cache cycle of operation; control circuit means coupled to said plurality of control input terminals of said multiposition address switch selection means, said control means generating coded control signals identi~ying which address source is connected to supply said addr~ss to said output terminals; and, ,~ - 5-.3~) split cycle timing means for generating timing signals for de-fining first and second intervals of said cache cycle of operation, said timing means being coupled to said control means, said control means being conditioned by said timing means during said first interval to enable said address selecti.on means to select an address for loading into said address register applied to a first one of said sets of input terminals by a first one of said address sources and said control means being conditioned during said second interval to enable said address switch selection means to select an address for loading into said address register applied to a second one of said sets of input terminals applied by a second one of said address sources for enabling the performance of different types of operations without interference involving the accessing of data and instructions specified by said first and second address sources during the same cache cycle.
In accordance with the present ~nvention,.there is further provided a cache system for us~ with a data processing unit for providing fast access to instructions and data fetched from a main store coupled to said cache unit by a number of address sources in response to commands received from said data processing unit, said cache system comprising: a cache store including a plurality of addressable word locations organized into a plurality of levels for storing said data and instructions, said levels being arranged vertically for accessing information on a word basis; a multiposition address switch having a number of s.ets of inPut ter~inals for receiVing a corresponding number of sets of address signals from s~id number of address sources, a plurality of output terminals and a plurality of ~ontrol input terminals; an address register coupled to said plurality of output terminals and to said cache store, said address register for storing the address specifying the location within said levels whose contents are to be accessed during a cache cycle of operation;
control circuit means coupled to said multiposition address switch input control terminals for generating coded control signals identifying which one of said number of address sources is con-nected to supply said address to said output terminals; and, split cycle timing means for generating timing signals for defining first and second halves of said cache cycle of operation, said timing means being coupled to said control means, said control means being conditioned by said timing means during said first half to enable said address switch to select an address for loading into said address register applied to a first one of said sets of input terminals by a first one of said address sources for enabling access of data during said second half of said cache cycle and said control means being conditioned during said second half to enable said address switch to select an address for loading into said address register applied to a second one of said sets of input terminals by a second one of said address sources for enabling the accessing of instructions during said first half of said cache cycle without interference.

- 6a -~r 1~ 0 In a preferred embodiment, the cache arrangement includes a high speed storage unit or cache which is organized into a plurality o~ levels. Each level includes a number o~
multiword blocks and has associated therewith a corresponding number of address selection switches and address registers.
Each address switch has a number of different positions connected to recei~e address signals from a plurality of address sources and selectively applies the address signals to the address register associated therewith. In response thereto, a decoder circuit is connected to generate output signals for controlling ~he operation of all of the address selection switches. In response to ~reviously established level signals coded to define a level to be written into during a cache cycle of operation, the dec~der circuit conditions a specified one of the number of switches to switch from a first position to a second position while the remaining address sw~tches remain selecting the first position.
During a cache cycle o~ operation, an address specifying the cache location into which memory data is to be written is clocked into one address register via the second position of one address selection switch. ~n address specifying the cache location from which a next instruction is to be ~etched is clocked into the remaining address registers via the first position of the other address selection switches.
The instruction address is clocked into the remaining address registers when no conflict between levels has been detected. That is, the cache arrangement includes a comparator circuit for comparing signals indicating the level into which memory data is to be written with signals indicating the level from which a next instruction is to be fetched. When there is a conflict, the comparator circuit generates signals which delay instruction access.
The arrangement of the preferred embodiment of the present invention enables memory data to be written into one cache level while a next instruction is fetched from one of the remaining levels during a cache cycle of oper~tion.
Thus, this eliminates the need to hold off or delay the accessing of instructions to write memory data. The result is increased performance.
Of course, this assumes a small number of conflicts in levels. It will be appreciated that as the number of levels is increased, there will be a corresponding decrease in the probability of conflicts. In the preferred embodiment, eight levels were selected. However, it will be appreciated that the invention is not in anyway limited to such number.
A cache cycle of operation is split into first and second halves. During the first half of the cache cycle, instruction accesses and memory data write operations are executed while CPU read and write oPerations are executed during the second ha]f Or the cache cycle.

~ 9 In such a split cycle arrangement, when applying the teachings of the present invention, the address of the cache location into which memory data is -to be written is clocked into one address register at the beginning of the cache cycle. The instruction address is clocked into the - other address registers at the same time as long as there is no con~lict detected. Memory data is then written into cache while the next instruction is loaded into an output register during the first half of the same cache cycle.
No~mally, an address from the CPU is loaded into all of the address registers at the beginning of the second half cycle to initiate a possible read or write operation at the end of the second half cycle. Therefore, in those instances when an instruction access conflicts with the writing of memory data, the second half of the cache cycle can be used to perform a CPU read operation and a memory data write operation simultaneously. Similar to the above, at the beginning of the second half of the cycle, the write memory data address is loaded into one of the address registers.
The CPU address is loaded into the remaining address registers.
During the second half O r the cycle J the requested data is read out to the CPU while the memory data is written into cache. This arrangement also results in increased CPU
performance.
Thus, in the first instance, the teachings of the present ~ 3~(~

invention permits the writing of memory information/data to be executed concurrently with the accessing of instructions provided the level into which memory data is to be written is different from the level from which instructions will be accessed. In the second instance, the writing of memory information/data to be executed concurrently with the accessing of operands provided the level into which memory data i5 to be written is different ~rom the level from which operands will be accessed.
A directory is organized into a plurality of levels for st~ring address information for accessing the blocks stored within the levels of cache. Timing circuits generate timing signals for defining first and second intervals of a cache cycle.
The control circuits which are connected to the timing circuits generate output signals for controlling the operation of the address selection s~itch. In operation, during the second interval oi' a cache cycle, the control circuits, in response to timing signals from the timing circuits, generate signals for loading the address from one address source into the address register. This enables either the accessing of instructions from one of the levels of cache or the writing of memory information data during the first interval of the following cache cycle.
Also, during the ~irst interval, the address selectlon switch selects an address ~rom another address source which is clocked into the address reg;ster. This enables processor operations such as the accessing of operand data or the writing of CPU/processor data to be performed during the second interval of the same cache cycle.
It wlll be appreciated that for efficient processing, the information requested to be accessed, resides in cache.
This results in a bigh hit ratio wherein the majority of cache accesses normally will be for instructions. Therefore, it is important that the accessing of instructions not interfere with the accessing of operand data. Accordingly, when a request for an instruction is received, it can be accessed and transferred to the processor during the first interval o~ the same cycle that an operand requested by the processor is accessed and kransferred. This eliminates any interference or conflicts arising from having to access instructions and also transfer operands. More importantly, such conflicts are eliminated without decreasing processor performance, This is particularly desirable in cache organizations wherein accesses proceed on a single word basis rather than on a block basis.
Additionally, it is desirable to be able to write memory data transferred on a real time basis. Accordingly, when memory data is received, it can be immediately written into cache durin~ the ~irst interval of the same cycle that an operand requested by the processor is accessed and transferred to the processor. This eliminates any interfersnce or conflicts arising from having to write memory data and also transfer processor operands.
In the case of accessing instructions, the source of addresses is an instruction address register. When there is no need to write memory data, the control circuits select as the source of addresses the instruction register whose contents specify the address of the next instruction to be fetched from cache. When memory information/data is to be written, the source of addresses is a buffer. In such cases, the control circuits select as the source of addresses, the buffer whose contents specify the address in cache where the requested memory information is to be stored.
The source of addresses for processor operations is a register containing an address received from the processor.
During a previous cache cycle, the directory is searched to determine whether the information specified by the same address resides in cache. The results of the directory search are processed during the second half of the next cache cycle as described above utili7.ing the stored processor address.
By controlling the address switch to select different sources of addresses during the eirst and second intervals of a cache cycle, the cache arrangement of the present invention eliminates the kinds of inter~erene~ ~rom the number of competing sources/
activities described above.

o Arrangements according to the invention will now be described by way of example and with reference to the accompanying drawings, in which:-Figure 1 illustrates in block form a system employing5 the principles o-f the present invention.
Figure 2 shows in block diagram form the host processor 700 and the cache unit 750 of Figure 1.
Figures 3a through 3e show in greater detail, certain ones of blocks of Figure 2.
Figure 4 shows in block diagram form the cache unit 750 of Figure 2.
Figure 5 shows in greater detail, the cache processor interface 604.
Figure 6a illustrates the format of the control store control unit of Figure 1.
Figure 6b illustrates the format o~ the microinstruction words o-f the execution control store of Figures 2 and 3.
Figures 7a through 7e show in greater detail, different ones of the sections of cache unit 750.
Figure 8 is a timing diagram used in explaining the operation of a pre~erred embodiment of the present invention.

.... , . . ~ . .. , .. ,_ _ , _ _, . . . _._ .. .. .~ .. , .. , _. _ .. . ... . . . .

. ~
'4 As se~n from ~lgur~ 1, the system which lncorpor~tes the principles of the pYe~ent invantlon includes at lea6t X input/output proces~or (IOP~) 200, a syatem interace unit ~SIV) 100, a high-~peed multiplexer (HSMX) 300, a low-speed multiplexer (L~MX) 400, a host proce~or-700, a cache m~mory 750, at least one m~mory module corre0pondlng to a local memory module 500, and at l~a~f one memory module corre~ponding to a memory module ~00.
~iffersnt one~ of th~e modules connect to one o~ a ~umber of poxts o the ~ystam in~erface unit 100 through a plurali~y of lines of differen~ types of intsrface~
600 through 60~o Mbre.~pecifically, the input~output 15 proce~aor 200, the cach~ me~ory 750, and the high-~p~d :multiplex*r 300 connect to port~ G, E and A, respectively, whlle the l~w-apee~ multiplexe~ 400, local memory module : 500, and main m~mory modul~ 800 connect to porta J, L~O
and RMO, re~pecti~ely. Th~ ho~t pxoce~sor 700 connecta to the ~ache m~mory 750~ -~ efore de~cri~inq in de~ail the proce~sor 700 andcache unit 750, constructed in accordance with principles of the pre~ent in~snt~on, sa~h of ~he lnterface~ S00 through fi04 dlscus~ed previou~ly will ~ be de3cribed.
The data ~nter~ace 600 ~h~e~ 1B one of the lnt~r-~ace~ which provide~ ~or exchang~ of informa~ion be-tween an active module and sy~tem ~nterf~ce unit 100.
~xchange i~ acco~pli~hed by controlling the logical states of variou~ ~ignal l~ne~ in accordance with pre-establi~hed rules impl~mented through a ~equence of .

~ignal~ termed a "di~log".
The interf3ce 601 1~ a programmable lnterace which provld~s for tran~fer of command lnformatlon from an actlv2 module a~d a designated module. The tran~fer 5 i8 accompllshed by controlling the logic of state~ of the variou~ signal lines in accordance with pre-e~tabli~hed rules implemented through a sequence of ~ignal~ termed a "dialog" .
A further int~rface i~ the interrupt interface 602 which provides or interrupt proce3~ing by the input/
output proces~or 200. Th~t iB, the interface en~ble~ the - trans~er of int~rrupt information by an active module to he SIU 100 to ~he input/ou~put proce~30r 200 ~or pro ces~ing. Simil~r to th~ other ln~erface~, the transfer of ln~errupt requ~t~ i~ accompli~hed by controll~ng the logical s~at~ o the varlou~ signal lines in accord~nce wl~h pre-e~tab$i~h~d rule~ implemented through z ~s~uence - of ~ignala termRd a ~di~log".
A nex~ ~e~ of int~rface llne3 utilized by certain one~ of the mQdulee of Fiqure 1 corresponds to the 1D~a1 memory interf~ce 603. This interf~c~ provide~ for exJ
changing informatlon between loc~l memory 500 and the module~ of the syste~. ~he exchange i~ accompl~ hed by controlling l~gical state~ of the YariOu~ 3ignal inter-face line~ in ac~ordance with pre-establi~hed rules implemen~ed through a dlalog ~equence of ~ignals.
Memory and programm2ble interface com~ands are tr~nsferred out of the 8ame phy~ical data lin~s of the interface. The int~r~ace does not include a -~¢t of lines for proc~asing interrupt requests and ~herefore the module~ connected to the loc~l memory by the SIU 100 ~annot directly cauRe a memory interrupt.

For a mor~ detailed de~cription of the elements of Ei~ur~ 1 and each o th~ lnterf~ces 600 through 603, rsf~r-~nce may be made to ~. S. Patent No. 4j006,466.
~he last interfac~ 604 i~ an lnternal interface between the cache unit 750 and central processor 700 which correspondfi to the cache/CPU interface llne~ of Figure 5. This inter~ace pxovides ~or exchanging informa-tion and control ~ig~ls b~tween the proces30r 700 and the cach~ unit 750. Tha exchange is ~ccomplished by controlling the log~c~l 3~ates of the various 3ignal interface lin~s~ The cache~CPU interface includes a plural~ty of da~a-to proce 80r line ~ZDI 0-35, P0-P3), a plurality o~ ZAC and write data lines (ZADO 0-23, ~ADO
24-35, P0-P3), a procQ~sor reque~t ~ignal line (DREQ-CAC), 15 a plurality o~ cache comMand line~ (DMEM 0-3), a hold ca~h~ llne (HO~D-C-CU)~ a cancel l$ne (C~NCEL-C), a flush lino (CA~-FLUSH), a read ~e~e~ e (~D-EV~U), a read instruction bufer line (RD-IBUP), a read double (FRD-DE~L~), a~ odd line ~FODD), a plurality of irlstructiosl l~ne~ ~ZI~0-35, P0-P3), a control llne (DSZ~, a r~d I-buff~r d~ta line (RD-IBUF/Z~
plurallty of zone bit lines (DZD 0-3~, a bypaB8 cache line (BYP-CAC), a wri~e ~ignal llne (W~T SGN~ ~ an instruction buffer empty line (IBUF-EMPTY), ~5 an instructiorl bu~far re~dy line (IBUF-RDY), an instruction bu~f~r Pull line ~IBUF-FULL~, a ~P ~top line (CP-STOP~, a CP control line (DA~A-RECOV), a des-c~ ;~ ~0~
a~ll ~ontrol line ~FPIM-EIS), a transfer no-yo line (NO-GO) and a plurality of word addr~s~ lines (ZP~ROUT0-1).
3~ In3truction~, cache command~ a~d data are forwarded to ~che cache unit 750 vi~ different ones of the~e lines.
Additionally, the operat~on of the processor 700 is enabled or disabl~d by ce;rtain ones of these line~ a~ .

explained herein. ~he descrip~ion of the CPU/cache interfaGe lines are given in greater detail herein.

CPU/CACHE INTERFACE LINES
De~ignation Descrlption ~ .
5 DREQ-CAC This line extend~ from proce~or 700 . to cache unit 750~ When the DNEQ-C~C
line i~ set to a binary.ONE, a ZAC
command i~ transferred tc c~che 750.
In the ca~e of a write ZAC command, ~rite data word~ are tran~fsrr~d in the one or two cycl~ following ~he ~AC command and data word~ are ~ent from the proc~980x 700 through ~he Gache 750 wlthou~ modi1cation, to th3 SIU 100~
~MEM O ,1,2 ,3 The~e lines extend from the proc~s~or 700 to cache 750. Th~e lines are cod~d to deslgnat~ the comm4nd that the cache 750 i~ to exe~ute. The : 20 coding i8 as follows:
~V~-OD~~ ~e g~ No action i~ t~ken and no cach~ requ~st i8 gen~rated.
DM~K- 001 Dl reC~ ~he direct command enabl~s th~ procesaor 700 to per-2S form a direct transfer of a~ opera~d ~al~e wi~hout a~tion on the part of : the cache 750. Hence, no cache r~que~t is gener~ted by this type of co _ ~nd.

.
.

CPU~CA~ INTERFAC~ LINES (Cont'd) DeBigna. ion D~cription .
DMEM 0010 - Address Wraparound Command (ADD-WRAP~ The addre~s wrap-~ ~ ~ v ~. c~ :
~,~' 5 ! ~r~und command i~ executed to return the command given to cache 750 by pro-cessor 700. 0~ the same cycle, the command i3 give~ to processor 700 via the ZDI line~ 0-35.
DM~0100 - Load In~truction Buffer In~truction Fetch 1 5L~-IBUF-IFl). The :~ lo~d instruction buffex command i~
us~d'ko load the addres~ of the . nsxt block of inqtructions i~to the altern~t~ in~ruction regi~ter RIC~/
RICB.
Ther~ are three pos~ible sequences o operation for thi~ command.
1. In the ¢a~e of a cache hit when the cache 750 i8 no~ be~ng by- ~ -pa6sed, the block address and level ~tored in the cache 750 are loaded in o the alternate in~truc-~ion register. A cache acce~3 is made to fetch the de~ired instruc-: tion which i8 tran ferred ~o pro-ce~or 700 via the ~DI lines 0-3g on the ~ub~equent T clock pul~e.
: ~hc alternate instruction regi~ter now become~ the current in-~ruc-tion regi~ter.
.

~c\

CPV/CACHE_INTERFAOE LINES (Cont'd) Desiynation Descriptlon

2. In the ca~e of ~ cAch~ mls~ when the cache 750.1s not being bypa~sed, the block address and the level designated by the round robin cir-cuits are load~d lnto the alt~rnate instruction regis~er. The processor is turned off or he~d on the subjse-quent T clock pulse to determ~ne whather the generation of th~ IFl command iA in response to a trdns-fer inAtruction. If it i~ and the tran~fer i8 a N0-~0, the curr~nt instructlon reg~ster is u~ed to acc~ss the next instruction and the proce~or 700 i8 turned on. If the IF1 command is cau~ed by a tr~n~ fer instruction which 1~ a . 20 G0, then cache 750 aend~ a memozy request to SIU 100 for the desir~d bl~ck of in~tructions and a.
directory as~ig~ment i~ made for the missing block. The instructlons re-ceived from memory are fir~t written :~ into the in~truction buffer and then : ints cache. The reque~ted in~truc-tlon ls transferxed t~ proce~sor 700 via the ZDI lines and the pro-ce~sor 700 i turn~d on or relea~ed . ~
~ , 5~ (Csnt'd) De~gn~tlon De~crlp~ion ,, A , _ _ , ____ _ on the ~ubsequent T clock pul3e.
- Th~ remalning instruction~ of the S block are transferred to proce~sor-700 from the ins~ruction buffer vi~ the ZIB line~.
. 3, ~hen the cache i8 t.o be bypa~ed . ................... . , and there i8 a hit, the ~ull-empty bit for th~ block i~ r~et. All L other operation~ are the 5ame a3 in ~he c~che mi~s ~ase, except that no direc~ory a~ign~nt i~
: made and the block i8 not written lS into cache.
DME~-0101 - Load In~truction ~uff~r .
: : In~t~uctlon Fetch 2 ~D-IBUF-IF2) The lo~d in~truct1on bu~fer co~mand i~ u~d ` to load ~he le~el of the second block .~ 20 of in~truction~ into the current in-~truction regi~ter~ me procesaor 70~
~: i8 no. turn~ off in the case of a mi~3 condltion. There are al80 three : ~ pos~ible sequences of operation ~or : 25 th~ command.
1. In the case of a cache hit condi-tion ~d no bypas~, the l~vel of the ~econd~block of instruction~
i~ loaded into the cur~0nt instru~-tion ragi~ter.
' , ~ [Cont'd) Designati~n De~cr1ption 2. In tha caae of a cache miss condition and no bypass, when the IFl command wa~ found to be the re~ult of a tran~fsr ln-struction N0-G0 condition, the IFl operation i3 c~ncelled, . .
In the case of other than a N0-G0 condition, a directory :~: aas~gnment i8 m~d~ ~o~
the second block of instructions and th~ level obtainad from the : . round robin circuits ~re wri~ten lS into th~ curr2n~ in~truc~ion re~
ter. Cache 750 ~end8 a m~mon reque~t to memory for the blo~k and when the instruct~ons are re-ceived ~hey are fir6~ wrltten into ~he in~truction buffer and later into cache 750. When the in3truction~ are need~d, they are read out from th~ ln~tru~tion bu~fer and tr~nsferred to pro-ceasor 700 vla the ZIB line~ 0-35.

3. In the case of a bypa~s, wh~n there i~ ~ hit condition, the full-empty bit for that block iR reBet~
All o~her operation~ are the 8~e ~3 in the case of a cæ~he mi8~ ex-cept ~hat there is no direotory ' , 41~o .~ E9~ ( Cont 7 d) D~signation Dascrlpt~ on assigr~nt and the block i8 not written into cache 750.
U~ ~ 01 L O - Lo ~-1 Q:~d The load quad command is used to load the blocJc addres~ for data (not instrUction~) m into the alternate inBtructiOn rsgiB
": .
,i.~ t2r. It is similar to ~he IF2 except that the` addr~s~ and level (row~d robin circUit~ provide level when a cache nLLss condition) ara written ~ to- the alternate instruction regis-,i ter~ ~hen th~ data ~ not in cach~
~5 15 - 750 and processor 700 requ4~st3 it, -~ be~ore it i~ received from me}nory, ~ the proce5sor 700 iB held or s~oppad `. until the da~a i3 received.
d ~ D~ Th2 pre read comma~d is used to 102d cache -~ 750 with data which the proce~sor 700 - expects to use in . he near future.
The thr~oe possibl~ sequences of opera-tion are aB foll~w~:
~5 1. For a caclle hit and no bypa~s, ~hé pre-xead ~ cor~ rnand~ lS-- execu~ed as a no-op.
2. For a cac:he miss and no ~ypass, the cache 750 generates a memory reques~ for the block and a :~ .

"

~: `
CPU/CACHE INTERFACE LINES (Cont'd) ~e~ignation ~e~cription dlrectory asslgnnwnt i~ ma~e for the missing block. When the data is received from memory, it i8 written into cache. The proce~or 700 i8 not held for this condltion.
3. For a cache bypa~s, the pre-read command i~ treated as a no-op.
~
The read ~ngle command ~ uaed o trans ~er a single data word to pro-ce~s4r 700. There are four pos~ibl~
~equence~ of operation for t:}li8 csJ~ nd.
1. In the ca~e nf a cache hit and no bypa~s, 1;h2 addreR~ed word i~
r~ad from cache 750 and tr~n~-~err~d to proceqsor 700 on ~he next T clock pulse vi~ the æDI
line -~ O- 35, 2. In the ca3e of a caehe mi~ ~nd o bypa~s, the proces~or 70~ is stopped and mi~sing blo~c is assign~d in t,he d~ rectory. Cach~
750 transfer~ the memory request to mairl m~mory. Th~3 data word ~re written into cache as they are recelved. When the requested da~a word i~ received5 prs:ce~ 3r 700 is tur312d on upon the o ~p :: CPU/CAC~É INTER~'~OE LINES (Cont'd-) ~ignatlon D~crlptlon occurrence of the sub~equent T
clock pulse.
3. In the cas~ of a cache hit and bypas~, the full-empty bit of the addxessed block is reset and the proce3~0r 700 is turned off or held.
The cache 750 transfers the re- , quest for one word to memory and the processor 700 i~ turned on upon the ~ubsequent T clock pulse :~ f~llowing receipt of the requested data word. The data word i8 not ~ written in~o cache 750.

4~ For a cache miss and bypa~ the ~me opera~ions take pl~ce ~8 in the cache hit and bypa~ case with the ~xception that tha full-empty bit of the addre~ed block , is not chanqed.

The.read clear command i~ u d ~o tran~fer a data word from ms~ory ~nto pr~ce~or 700 and al~o clear it out.
There are two possible sequence~ of op~ratio~ for ~his command.
1. For a cache hit, the full-empty bit for ~hat block i8 reset and proce~or 700 i8 turned off~ The ~ ~' .
.

~s ~PU/~U~ INtr~rAc~ LIN~5 (Cont'd) , ~eslgn~tion Uescription .
cache 750 makes a memory request for one data word. The memor~,r clears the location. When the word is received, the cache 750 transfer~ the word to processor 700 and turn~ on the Pros~essor 700 on the next T cloc~ pulse. The word i8 not written into cache 750.
- 2. For a cache miss, th~ same opera-tion~ ake place as in th~ cache hit with the exception of no .
change in full-empty bits s:~f tlle addre~s~d block~ -The road double command i~ u~ed to : tran~ar two d~ta words to proceasor . ~00. There ar~ two t~pes of re~d 20 doubla commands which diffar in the ordsr in which the data word~ are : . glvsn to proce~sor 700. When llne DSZl i~ a binary ZERO, the order i9 odd word and even word. When line DSZl is a bianry ONE, the order i~
even word and then odd word, There are four po~ le sequences of opera-tion ~x thi~ conuna~d.

2~

~ (Cont'dl L~slgnation De~crlptlon -l. For a cache hit and no byp~s~, the first word is transferred to pro-cessor 700 on the subsequent T
clock pulse via the ZDI lines 0-35.
On the next T clock pulse, the second data word is transferred to processor 700 via the Z~I lines 0-35.
2. For a cache miss and no bypas~, the processor 700 is turned off and ~irectory a~ig~ment i~ made for . ~he block containing the addre~sed word pair. ~he cache 750 tran~f3rs the m~mory reque~t to SIU lO0 ~or the block. As the data words are recelved they are writtan : into cache. When the requested : 20 word pair i8 available, the first : word is tran~ferrad to processor 700 and it i8 turn0d on or r~-lea~ed on the subs~que~t ~ clock pul~e. The cache 750 tran~fbrs the ~econd word to processor 700 on the next T clock pulse.
3. For a cache hit and bypa~, the full-empty bit of the addressed block is reset and processor 700 is turned off. The cache 750 tran~fers the reque~t to memory .

(Cont'd~
De~iynation Descrip~ion for the two data words. A~
~oon as the two word~ are available, : 5 . the processor 700 is turned on and the first data word is tran~-ferred to it on the sub~equent T clock pul~e. The processor 700 ~ recsives the ~econd data word on : 10 the next T clock pul~e. The data words are not written into c~che.
4. ~or a cache miss and bypass, th~
same operatlons take place as in the case o~ the cache hit and by-~: 15 pa58, except that there i8 no change in full-empty bits.
DMæM~1011 - Read Remot~ (RD--RMT) to . circumvent normal cache read actions.
When the command i8 received, pro-ce~ or 700 i8 turned off and the re-- qu93t iS transferred to the mai~
memory. ~hen the re~uested word - pair has been fetched frvm memory, the fir~t word is given ~o processor 700 a~d it ig turned on the Yubse-quent T clock pul~e. Tha second data word i5 transferred to processor 700 on the next ~ c}ock pul8e. The order ~n which the ~ata word~ are trans- -~rred i~ ~ven word and then odd word.

"
"

~g CPU/C~CIIE IN~ER~AC~ LINES (Cont' d~
L~eAignation Descrlption No change~ are made within cache 750.
DMEM=llO0 - Write _lnqle (WRT-SNG) -The write single command is used to write data into memory. There are ~wo possible sequence~ of operation for thi~ command.
1. For a cach~ hit, the cache 750 transfers the request to memory.
~hen it i~ accepted ~he data word ~ ~s transf2rred to memory~ The :~ data word is alsQ written into cache 750.
2. ~or a cache mis~, the same opera-tions tak~ place as the cache hit except that no change i8 made to ~he Gache 750.
~
~he write double command i~ used to write two data words into memory.
:Thi~ command i~ carried out ln h : manner ~imilar to the wxite ingle command except that two words are tran~fer~ed/written rather than one word.
DME~sllll - Write Remote ~WRT-RMT) The write remote command ~s u~ed to circumvent normal cache write actions in that when the addre~s~d words are . in cache 750, they are not updated.
.
: .

53Y~Ç~ ~5~ LLLL (Co~t'd~
De~ignation Descrlption The cache 750 transfers the reque~t to memory and when accepted, the . two data words are transferred to memory.
HOLD-C-CU Thi-~ line extends from proces~or 700 . to cache 750. When set to a binary ONE, ~hi~ control signal pecifie~
that the cache 750 i~ to assume a HOLD state for r~quests or data ~rans fers .
CANCEL-C This line extend~ fxom processor 700 to c~che 750. When set to a binary ONE, this control signal indicates : that the cache 750 should abort any proc~sor command which i8 currently bsing sxecuted.
CAC-FLVSH This line extend~ from prOCessOr 700 to cache 750. When ~et to a binary ONE, it ~taxts a flush of the cache : 750 ~i~e., the cache 750 is forced . to look empty by re~etting all of the full-empty bitsl.
RD-EVEN ~his line extend3 from proce3~0r 700 to cache 750. ~en the ~ache make3 a double word rsquest to th~ SIU, the ~v~n word 1~ saved in a special regi~ter ~EVN). When RD EVEN line i~ set to a binary ONE, the contents ` ~ .30 . CPU/CAC~IE INTERFA~E LIN~S (Con~'d) De~lgna~ion Uescription ..:
of the REVN reglster ~ gated onto the ZDI lines via the Z~IN sw$tch.

5 ZADO 0-23, The e 40 unidirectional lines extend RADO 24-35, from proces~or 700 to cache 750. The PO-P3 line~ are used to trans~er ZAC command~
and write data word~ to cache 750.
When the DREQ CAC line iB forced to a binary ONE, æAC command and in the case of a write type of command, the write data words are tran~err~d dur-ing t~e one or two cycle~ follow~ng : ~ ~ the ~C command. The commands en-cod2d onto ~h~ DMæM lines may sr may not be the same a~ the ZAC command.
~D-IBVF Thls lin~ extend-Q from the proces~or tOO
to cache 750. When set to a binary ONE, the line ind~cate~ that proces~or 700 i8 ~aking the in~truction from the in~truction regl~t~r ~IRA. In most case6, it is u~d t~ start the fetching : of the next in~tructlon to be loaded into ~IRA.
25 DZD 0-3 The~e four lines extend from proces~or - 700 to cach~ 750. ~hese line~ tran~-for odd word ~one bit signal~ for write double commands.
. BYP-CAC This line extends from proce~sor 700 to c whe 750. ~hen ~et to a bin~ry .
.

~3\
~' C.3 ru/c~cHE INT~FAC~ LIN~;S (Contld) D~iy~atlo~ e~er~utlon ONE, this line caus~s the cache 750 to reque~t data woxds from main memory for read type lnstr~ctions. When a cache hit occurs, the bloc~ containing the requested data i~ removed from cache 750 - by res~tting the full-empty bit associ-ated ~herewith. For write single or double command~, the data i9 written i~-to cache 750 when a cache hit occur~.
;~ WRT-SGN Thi~ line extend~ from the cache 750 to p~oces30r 70U. It i~ u~ed to ~ig- -~al the proces~or 700 during write : 15 ~ommand3 that the cache 750 has co~-pl~ted the tran~fer o~ ZAC commdnds and ~ata word to the SIU 100.
FPIM-EIS This line extend~ from proce~sor 700 to ca~he 750. When forced to a bin-ary O~E, it si~nal~ cache 750 that pxoce~sor 700 i8 1ssuing an IFl command - for additional ~IS descriptorc.
~SZl Thi~ exte~ds from the processor 750 to cache 750. The state of thi~
line s~ecifias to cache 750 the order i~ whach words are to be sent to the proce~sor 700 when a read do~ble command is performed.
NO-GO ~hi~ line extend~ from proce~.~or 700 to cach~ 750. When forced to a binary O~E, lt indic~te~ that processor 700 executed a tran~f~r .

-L~
-2~
~ , ~; O~C~ rli~Ac- LIIIIIS (Con'c'd~
De~ignation Description ~ , .
lnetructlon ~hich i~ a NO-GO.
Thl~ signals cache 750 that it S ~hould cancel the IFl conunand it received when it was a mi~s and . lgnore the IF2 colTunand which i8 currently applied to the DMEM lin~.
RD-I3UF/ZDI This line extend~ from proce~sor - 10 700 to cache 750. It c~uses the cache 750 to access the data word at the addr~ss contained in the ~: alter2~at~ instruction register and put thi~ data on the ZDI line~. For a~l outstanding LDQUAD co~n~nd, the cache 750 holds proce~or 700 when line RD-I~UF/ZDI i~ orc~d to a binary ONE.
FR~D~L Thi~ lin~ extends from proce~or 700 to caohe 750. This ~ign~ls ca~he 750 in advance ~hat the processor - 700 i~ reque~tirlg that a read do~le oper~tion be performed.
FODD This line exta~d~ from processor 700 to cache 750. ~his line i~ used in con~unction with the FRD-DBLE line to ignal the order of the word~
bsing requested. When thi~ line i~ a birlary ONE, thi~ indicates that the ord~r is odd followed by even.

CPUJCACII~ IT~;RFJ~CI:: LINE~; ((,'on~ ' d) ve~ignatlon DoHcr1pti on Z~I 0-35 ~he~e 40 unldirectlonal llne~
Po~ Pl, P2, P3 extend from cache 750 to prQces~or 700.
They apply data from th~ cache 750 to the processor 700.
ZIB O 35 The~e 40 unidirectional lines extend PO, Pl~ P2~ P3 from cache 750 to processor 700.
They apply in~tructions to the pro-cesso~ 700.
I ~UE'-EMP~Y This line extendR from cache 750 to : ~ proc~sor 700. When set to a binary ~: ON~, this line lndica~es that cache ~ .
. 750 ha~ tran~ferred the last ~n~truc-tion fro~ th~ current in~truction block.
I BUF-RDY Thi~ line exkends from c~che 750 to - proces~or 700. When set to a binary ONE, the line indicat~s that there i~ at ~e&~ one instruction in tAe .
current in~truction block in cache 750. The line is set to a bina~y ~RO to indicate a non-ready condition a3 follows:
1. Whenever the in~tru~tion ~ddr B~
switches from the la~ instruction of an IFl block in cacha to the first instxuction of an IP2 block not in cache and not in the IsuF2 buffer.

.

o~
CPU/CAC~ T~RFACE LINES (Cont'd) De~igna~ion De6crip~ion 2. Whenever instructions are being fetched from the IBUFl or IBUF2 buffer and the next instruction to ~e fetched 18 in a two word pair which ha~ not been received from memory.
I ~U~-FULL Thi~ lin~ extends from cache 750 to processor 700. Thi~ line indicates : that there are at least four in~truc-: tionq in the current instruction block or it has at least one instruc-tion and an outGtanding IF2 request.
15 CP ~TOP Thl~ line extends from cache 750 to processor 700. When f~rced to a binar~ ONE st~te, the line signal6 that the proce~or 700 is held or required to wait or halt lts operation.
In the case of a xead miss condition due to a proc0sYor command, processor 700 is held on the subsequent T clock cycle pul~e. ~hen released, the DATA ~ECOV line iq forced to a binary 2~ ONE to restrobe the affected proca~sor regi~ter(s). When the RDIBUF/ZDI
line i~ forced to- a binary ONE before the data is received from memory, processor 700 is held prior to the subsequent T clock pul~e. When re-lea~ed, the xeques~ed data is made v 3~i ~/CACHE INT~:RFAC~E LINES (Cont ' d) De~ignatiorl Dcsc:riptl on ~v~lla~le to procc~sor 700 on the ZDI lines and i8 used on the ~ubse-. 5 quent T clock pul~e.
DA~A-RECOV This line extends from the cache 750 to proce~or 750. It is used to re-strobe proce~sor registers followin~
the stopping of the processor 700 in re8ponse to the detection of a cache mis6 condition or read bypa~ condi-tion. At the end of the cycle in which the DREQ CAC line is forced to a binaxy ON~, the mi98 condition i8 detected but processor 700 cannot be ~- stopped until after the 6ubsequent T clock pulse. Therefore, bad data~
. in~tructions are strobed into the pro-cessor regi~ters from the ZDI/ZIB
line When the requested data/
instructionC become available, the DATA RECOV line i9 forcsd to a binary ONE to restrobe the registers -: - which were 3trobed during the last c~che reque~t.
ZPTR-OU~ 0-1 These two line~ extend from cache 750 to processor 700. The~e lines are coded to specify the two lea~t signLficant bits of the address of the instruction contained in the ~: ~IRA instruction reqister or the I
. buffor.

:~ :

GeneraL Dascri~tion o Proces~or 700 - Fig. 2 ~ ferring to Figure 2, it is saen that the ho6t processor 700 include~ an execution control unit 701, a control unit 704, an execution unit 714, a character unit 720, an auxiliary arithmetic and control unit ~ ~h i~P (AACU) 722,~ multiply-divide unit 728, which are inter-connected as shown. Additionall~, the control unit 704 has a number of intarconnections to the cache unit 750 as shown.
The execution contxDl unit 701 includ~s an execu-tion control store addre~s preparation and branch unit 701-1, and an execution control store 701-2. The ~tore 701-2 and u~it 7.01-1 are int0rconnacted via bu~es 701~3 and 701-6 a~ shown.
5'he control unit 704 includes a control logic unit 704-1, a control ~tore 704-2, an addres~ preparation unit 704-3, data and addre~ output circui~q 704-4,~an XAQ register section 704-5 wh~ch i~t~rconnect as shown.
A~ ~e~n from Figure 2, the SIU interface 600 provides a num~er of input lines to the cache unit 750.
The lines of this interface have been deacribe~ in de-tail previously. ~Towever, in connection with the operation of cache unit 750, certain orles oE the3e line~ are specially coded a~ follQws.
1. MITS 0-3 for Read~ are coded a~ follow~:
bit~ 0-1 3 00;
bits 2-3 ~ Tran~it block buffer addres~ containlnc the ZAC command for current r~ad operation.
For Write Operation b~t 0-3 - Odd word zone 2. MIFS line~ ~re coded a~ follows:
bit O = O;
bit 1 - O even word p~irs (words 0,1);

3~ O
~31 bit 1 = 1 odd word pairs (word~ 2,3~;
~: b~ts 2-3 = Tran~it block buffer addre~ con-talning the ZAC command for the data being received.
~s concerns the interface llnes DFS 00-35, P0-P3, these lines convey read data to cache unit 750. The lines DTS 00-35, P0-P3 are used to transfer data'from cache 750 to th~ SIU 100.
The control unit 704 provides the necesYary control for performing address preparation operations, inQtruc-tion fetching/execution operations and the sequential control for various cycles of operation and/or machine states. The control i8 g~nerated by logic circuits of block 704-l and by the execution control unit 701 for : : 15 : the variou~ portions of ~he control unit 704.
: ThQ XAQ reglstQr ~ection 704-5 lncludes a number of pro~ram visibla registers such a~ index reg~ster3, an aacumulator register, and quotient register. Other ; progxam visible registers, such as the instruction counter and addre~ registers, are included within the address preparation unit 704-3.
As seen from Figure 2, 'che qection 704-5 receives ignals from unit 704-3 repre~ent~tive of the contentY
: : o~ the lnstruction counter via lines RIC 00-17. Al~o, line~ Z~ESA 00-35 apply outpu~ signal~ from the executlon unit 714 corre~ponding to the result~ of operations per-: ~ formed upon various operand~. ~he ~ection 704 5 also receives an output signal from the auxiliary arithmetic and control unit via llnes ~A~U0-8 The section 704-5 provides signals representative of the content~ of one of tho registers included within the section a~ an input to the address preparation unit 704-3. The addr~ss preparation unit 704-3 forwards ~- .

. ...

3~

the information through a switch to the exPcution unit 714 via the lines ZDO 0-35. Similarly, the contents of certain one~ of the regi~ter~ contained within section 704-5 can be tran~ferr~d to the execution unit 714 via the line~ ZEB 00-35. Lastly, the contents of selected one~ of the3e regi~ters can be transferred from section 704-5 to the multiply/divide unit 728 via the lines ZAQ Oû-3S.
The a~dres~ prepara~ion unit 704-3 generates v o-~ o~ ~.
addres~es from the contents of ~ regi~ters contained thersin and applies the re.qultant logical ~ effectivs and/or ab~olute addre~e~ for di~ributlon to other units along the lines ASF~ 00-35. The addre~ preparation uulit 704-3 raceives the re~ults of operations performed on a pair of operands by the execution unit 714 via the lines ZRESB 00-35. The unit 704-3 r~ceive~ sign~ls repre~n~ative of the contents o~ a pair of base pointer r~gi~t~rs from the con~rol logic unlt 701 ViB
: ~ the lin~q R~ASA and RBASB0-1. Output8 from the multlply/
~t! 20 divide unit 728 are applied to the address ~ ~
unit 704 3. La~tly, th~ contents of a secondary in~truc-tion regiBter ( ~IR) ~re applied a~ input to the url$t - 704-13 via the li~ R8IR 00-35.
The d~ta and addre~6 output circuit~ 704-4 generate the cachs memory addr~fi ~ignals which it applies to 'che cache urlit 750 via the line~ RAD0/ZAD0 00-35. These - addre~ signals corre~polld to the ~ignals applied to on~ ~
:~: of the s~ts o input lin~ ZDI Oû-35, ASFA 00-35 2nd ZRESB 00-35 selected by ~witches included within the circuits of bloclc 704-4. These circuitR will be further discussed hereir~ in qreater detail.

. . . ~, . , , _ ,, , 4~
,~

l~he control logic unit 704-1 provides data paths which have an intexface with various wnlt~ in-cluded within the cache unit 7S0. As described in ~reater detail herein, the lines ZI~ 00-35 provide 5 an interface with an instruction buffer lncluded within the cache 750. The lines ZDI 00-35 are u~ed to tr~nqfer data ~ignals from the cache 750 to the con-trol logic unit 704-1. The ZPTROUT lines are used to transfer address information from cache 75~ to unit 10 704 1. Other signal~ are ap~lied via the other data c ~ e.~-- C~
and control lines of the ~eche-e~-interface 604.
These line~ includ~ the CP-STOP line shown separately : in Figure 2.
seen from ~igure 2, the control logic unit 704-1 : 15 provide~ a number of groups o~ output 8ignal8. These output ~lgnals include the content~ of certain registers, . as for example, a b~si~ instruction register (RBIR) whose contents are applied as a~ input to ~ontrol 3tsre 704~2 via the line~ NBIR 18-27. The control lcgic unit 20 704-1 receives certaln control signals read out from control store 704-2 via the lines CCSD0 13-31.
. The control logic unit 704-1 also lncludes a secondary insgruction regi~ter (RSIR) which i8 loaded in parallel with the ba~ic instruction register at the ! 25 start of proces~ing an in~truction. The contents of the - secondary instructio~ r~gi~ter RSIR 00-35, a~ proviously : mention~d, are applied as input~ to the addr~s prepara-C tion unit 704-3. Additionally, a por~ion of the con-te~t~ of the secondary instruction register-~e~
30 applied as. ~ ~to the auxiliary ~rithmetic control unit 722 via the lines ~SI~ 1-9 and 24-35.
~ .

o ~o The control store 704-2 as explAined herein pro-vides for an initial decoding of program instruction : op-codes and therefor~ i8 arranged to include ~ number of storage locations ~1024), one for each po~sible instruction op-code.
As mentioned, si~nals appli~d to lines RBIR 18-27 are applied as inputs to control store 704-2. These signals select one of the possible 1024 storage loca-tiOnB. The contents of the selected storage location 10 are applied to the lines CCSD0 13-~1 and to CCSD0 00-12 as shown in Figure 2. The signals supplied to lines CCSD0 00-12 correspond to address signals which are u~ed to address She execution control unit 701 as ex-- ~ plained herei~.
The remaining section~ of proces~or 700 will now ~e briefly described. The execution unit 714 provides for instruction ~xecutlon wherein unit 714 performs arithmetic and/or ~hift operations upon operands ~elected from-the various inputs. The re~ults of such oper~tions.
are applied to sel~cted outputs. The execution unit 714 receive~ data from a data input bus which corre~-ponds to lines RDI 00-35 which have as their ~ource the control logic unit 704-1. The content~ of the accumula-tor and quotient regi~ters included within eection 704-5 - 25 are applied to the execution unit 714 via the lines : Z~B 00-35 as m~ntioned previously. The signals applied : : . to the input bus lines ZDO 00-35 from the address prepara-tion unit 704-3 ar~ applied via 6witches included within the execu~ion unit 714 a~ output signals to the lines 3û ZRESA 00-35 and ZRESB 00-35, as shown in Figure 2.
Additonally, executior~ unit 714 receives a set of scratch o ~1 ._,,~9:

~: pad addre~6 iynals ~rom the auxiliary arithmetic and control unit 722 applied via the llne~ 2RSPA 00-06.
Additionally, the unit 72Z al90 provides shift informa-tion to the unit 714 via the lines Z~SC 00-35.
The character unit 720 is used to execute character : type instructions which require such operations as translation and editing of data fields. As explained herein, these types of instructLcns are referred to 10 as extended instruction set (EIS) instructions. Such instructions which the character unit 720 executes include the move, ssan,~compare type instructions. Signals repre~entative of operands are applied via lines 2~ESA
00-35. Informatlon a~.~o the type of character position within ~ word and the number of bits is applied to the charact~r unit 720 via the input lines ZDB
0~-~7.
Information repre~entative of the results of certain data operations is applied to the unit 722 via the lines ZOC 00-08. Such information includes expon-ent data and data in hexadecimal form. The character unit 720 applie~ output operand data and co~trol informa-~ion to th~ u~it 722 and the unit 728 via the lines ~CHU 00-35.
~ne auxiliary arithmetic and control unit 722 per-forms aritnmetic operations upon control information such as exponents used in ~loating point operations, calculates operand leng~h~ and pointer~ and generates count informa-tion. The resul~ of these operations are applied to execution unit 714 via the lines ZRSPA 00-06 and lines Z~SC 00-06 as mention~d previou~ly. Information signal~
corre~ponding to characters such as ~-bit characters,

6-bit characters, decimal data converted from i~put h~xadecimal data, quotient information and sign informa-_._ . , .

o 4~

~ion are applied to ~ection 704-5 via the lines RAAU
00-08.
A~ seen from Figure 2, the un~t 722 receiv¢s a numbcr o f input~ . Char~cter polnter lnfo~matton i~ ;
~pplied via the lines ASFA 33-36. EIS numerlc scale factor information and alphanumerlc field length lnfor-mation are applied to the unit 722 via the line~ RSIR
24~350 Other signals relating to fetchin~ of specific instructions are applied via the lines RSI~ 01-09.
~xponent signals for floating point data are applied to the unit 722 via th~ lines ZOC 00-08 while floating : point exponent data ~ignals from unit 704-1 are applied via the lines RDI 00-08. Shift count information 9ig-- nals for certain instr~ction~ ~e.g. binary shift in~tructions) are applied to the unit via the line~
RDI 11-17. As Goncerns th~ input 3ignals applied to the 1ines RCHU 00-35, lines 24W35 apply ~ignals corres-ponding to the length of EIS in~truction fields while 18-23 apply addre~ modification ~ignals to the unit 722.
The last unit i9 the multiply/divide unit 728 which provides for high-speed execution of multiply and divide instructions. This unit may be consid~red conventional in design and may take the form of the multiply unit described in U.S. Pat~nt ~o. 4,041,292 which is asqig~ed to the ~ame a~ignee as named herein.
The unit 728 as s~en from Figura 2 receives multiplier dividend and divi~or input s~gnal~ via the line~ RCHU 00-35. The multiplicand input signals from register sec-tion 704-5 are applied via the line~ ZAQ 00-35. The result~ of the calculations performed by the unit 728 o 4~

~re applied a~ output s1gnals to the llnes ZMD 00-35.
- A~ mentloned ~roviou~ly, the cnche unlt 750 tr~n~-fers and receiv~ d~ta and control slgnal~ to and from the SIU lO0 via the data lnterface line 600. The : 5 cache unit 750 transfer~ and receive6 data and control siynal~ to and from the processor 700 via the lines of interface 604. Lastly, the cache unlt 750 receives addres~ and data signals from the circuits 704-4 via the lines RAD0/Z~D0 00-35.

~ .
.

v ~ 4 r etailed De~criptlon o the Proces-qor 700 Certain ones of he sections which comprlse the processor 700 illu~trated in Fiqure 2 will now b~ di3-cu~sad in greater detail with rsspect to Figures 3a through 3e.
Referring to E'igures 3a and 3b, it is ssen that the proc~ssor include~ two control stores: (1) the eontrol unit control store (CCS) 704-200 which forms part of the control unit 70~; and (2) the exeeution control store (~CS) 701-3 whieh 18 includ~d wlthin the e~ecutlon eontrol unit 701.
Tlle eaehe oriented proeessor 700 of the px~ferred embodiment of the pre~nt inventicm includes ~ three C stage p~peline. Thi~ mean~ that the processor 700 re-quires at lea~t ~hree proce~or eycle~ to eomplete th~
proe~ssing of a giv~n program in~truetion and ean i3sue a new instruetion ~t the beginning of eaeh eyele.
Hen~e, a number of program in~truct1Ons may be in 80me stage of proeessing at any given instant of time.
In the preferred ~mbodiment~-f~ the proees~or 700 inelude~ the following 3tage~: an instruetion eyele ~I) wher~in instruetion lnt~rpretation, op-eode deeoding - and address preparation take plaee; a caehe eyele (C) wherein acce~ to the eache unit 750 i~ made ensuring high performance operat$on; ~nd, an ex~eut1On cycle (E) wherein in~truction execution take~ plaee und~r miero~
program control.
As eoncern~ control, during the I cyel~, the op eode of the instr w tion applied via lines RBIR 18-27 is u~ed to aecess a location within control store 704-2. Dur-ing a C cyele, the aece~sed con ents from control store 704-2 are applied to line~ CCS D0 00-12 and in turn u~ed to access one of the storage locatisns of the execution control store 701-2. During the C cycle, the micxoinstru~tlons of the microprogram used to execute the instruction ~re read Ollt from the execution control store 701-2 into a 144-bit output regi~ter 701-4. The signals d~ignated M~MD0 00-143 are di~tributed to the various functional units of processor 700. Durlnq an E
- cycle, the processor execute~ the operation p¢cified by the microinstruction.
Referring specifically to Figur~ 2, it is seen tlla~ the control stoxe 704-2 includes a control unit control store (CCS~ 704-200 which is addre~sed by the op-cod~ signals applied to the lines RBIR 18-27. The C'CS 704-200, a~ m~ntioned previously, includes 1024 ~torage loc~tions, the cont~nts of which are read out in~o an output register 704-202 during an I cycle of operation. Figure 6~ show~ schematically the fonmat of the words stored within the control BtOre 704-200.
~ferri~g to Flgure 6a, it is aeen that each con-trol unit control ~tore word include~ five fields. The first field i8 a 13-bit field which contain~ an ECS
s~arting addre&~ location for the instruction having an op-code applied ~o lines RBIR 18~27. The next field is a three bit field (CCS0) which provides for the cQntrol of certai~ operations. Ths bit inte~pretations o~
this field depend upon its des~ination and whether it is decoded by s~ecific ?ogic circuits or decod~d under microprogr~m control. The next field i5 a 4-hit field 30 which provide~ for certain register control operatior~s.
The next field i3 a 6-bit sequence control field which is coded to ~pecify a ~equence of operations to ~ ., .

4b ~ , ~e perEormed under hardwired lo~ic circult control well ~ tJI~ typ~ of c~che o~eration. In the present e~ample, thl~ fleld 13 cod~d as 758. The la~t fleld i8 a 6-bit indicator field which 18 not pertlnent to an understanding of the present invention.
As ~een from Figure 3a, signals corre~ponding to the CCSA field of a control unit control store wor~ are applied via a path 704-204 as an input to the execution generation circui~s 701-7. Signal~ corresponding to the CCSR Eield ar~ applied as an input to the execution unit 714 via path 704-206. Additionally, the same signals - ~ are applied a~ ~n input to the address preparation unlt ~- 704-3 v~a another path 704-208.
Signal~ rapre0entative of the sequence control field 15 apply as an input to the ~equence control logic cirauits 704-~ via Path 704-210. AB explained herein, these circui ~ decod~ the ~equence control field and generate signal~ ~or conditioning the cache unit 750 to perform J the operation desiqnated.
A~ mention~d previously, the execution address g~neration circui~ 701-1 receive an input address which corresponds to field CCSA from tke control store 704-2.
A~ seen from Figure 3b, these circuits lnclude an ~ nput addre~s regi~ er 701-10 who~e output iB connected to 25 one posltion of ~ four position ~witch 701-12 de~ign~ted ZECSA. The outpu'c of the ~witch serve~ as an addre~
~ource for the control ~'core 701-2. ~he first position of the switch 701-12 is connecked to receive sn addres~
from the MICA regist~r 701-14. The contents of reqis-30 ter 701-14 are updated at the end of each cycle to point to the loc~tion within kh~ ECS control store following the ~Ll ~ location whose contents were read out during that cycle.
: l~he second po~ition elects the addre~s produced rom the ZCSBRA branch address selector ~witch 701-18.
~'he third po~ition 6elect8 the address of the first micro-instruction in each microprogram provided by the ~CS
control store which 1~ loaded into the REXA reglster

7~1-10. When the CCS output i~ not available at the termination of a microprogram, ~ predetermined address toctal addres~ 14) i~ automatically s21ected.
The fir~t po~ition of branch ~witch 701-18 receive~
signals corresponding to a branch address read out from : store 701-2 lnto ragister 701-4 which is in turn for-warded to a return control regi~ter 701 20. The second, third and fourth positions of ~witch 701-18 receive~
15 signal~ from RSCR register 701-20, an MIC register 701-15 and the content~ of a number of vector branch registers 701-36. The MIC register 701-15 stores an addres~ which points to the microinstructlon word follow-ing th~ microin~truction word being executed. This 20 addr~s corr~sponds to'addre~ from switch 701-12 incre-m~nted by one by an increment circuit 701-12.
The vector ~ranch regl~ters include a 4-bit vector branch registex 0 (RY80), a 2-bit vector branch reg~ster 1 ~RVBl) and:a 2-bit vector branch regi~ter 2 (~VB23.
2S These registers are loaded during a cycle-of operatlon with addre~s value~ derived from sig~als stored in a - number of dif~exent indicator flip-flops a~d regi~tex~
applied as inputs to the number of groups of input multiplexer selector circuits 701-32 and 701~34. The 30 outputs of the circuit~ 701-32 and 701-34 are applisd as input~ to two po~ition ~elector circuits 701-30.

., . _ ,. _ ,, _ _ _ . . _ -- . . . .

~l~h~e circuit~ in turn generate the output ~lgnal~
ZV~R0, ZY~Rl and ZV~2 which ~re ~tored in ~he regls-t~r 701-36.
The ~witch 701-36 provide~ an address based upon the testing of varlou~ hardware lndicator signals, state flip-flop signals s~lected via an INDGRP field.
The branch decision i8 determined ~y masking (ANDINGj the qelected indicator set with the INDMSKU and INDMSKL
field~ of a microin~tructlon word. If a vector branch i~ selected, INDMSKU is treated as 4 ZERO bits. The "OR" of the 8 bit~ ls compared to the state d~flnQd by ~he TYPG and GO microln~truc~ion fields. The hardware ~ignal~ are appli~d via a number of data ~slec~or cir-cuit~ 7û1-28 only one of which is shown whooe OUtp~lt~
are in turn applled a~ input~ to a further flv~ po3ition multiplexer seleotor circult 701-26. Th~ output of the multiplexer circult 701-26 fe~d~ a comparissn cir-cuit which "ands" the indicator ~ignals with the maak 8ignal 8 to produce the re~ul'clny ~ignal~ MSXCE~R0-7 .
The ~ignal~ MSXC~R0-7 are applied ~o anoSher com-pari~on circuit which Nand~" the signals with the condition branch test ~$gnal~ TYP(:G0 to set s:~r xeset a branch deci~ion flip-~lop 701-22 which produces a signal R13DG0 whose ~tate indi~ate~ whether branching i~ to 'cake place. The output ~ignal RBDG0 i~ applied as a control input to the fix~t two posit~ on~ of switch 701-12. When the branch test condltion i~ not met (i . e ., ~ignal RBDG0 ~ 0), then the incremented addxess from the MICA register 701-14 i~ ~el~cted.
In some instanc~, a~ ~een herein, it i q not possible to test the state of an indicatc~r on th~ cycle .

o followi.ng its formation. For this rea~on, history register~ ~R0-~IR7, not ~hown, are provlded for regist~
- storage of the Group 2 indicators. The states of sucn stor~d indicator~ are ~elected and tested in a mannsr S ~imilar to that of the other indicatorq (i.e., mask fields).
Addltionally, the unit 701-1 includes a number of indicator circuit~, certain ones of the~e are used to control the operation of certain portlons of the pro-ce~sor 700 when the strinq~ ~eing processed by cer-tain typ~s of instruct~ons hav~ been exhaus~ed. These : indicator circuits are included in block 701-42 and are set and reset under the control of a field wi hin the microi~qtruc~ion w~rd o Figure 6a ~i.e., IND6 field). The hi~s of this ~ield read out from th~ ECS
output regi~ter 701-4 are applied to an RMI registe2 701-38 for decodlng by a decod~r 701-40. Ba~ed upon the ~tate of ~tatu~ indic~tor signal~ received from the various proce~or units (e.g. 71~, 720, 722, etc.), ~0 thc ~ppropriate one~ o the aux~llary flip-flop~ are swltched to binary ONE ~tates. The output~ of the~a flip-flop~ are applie via tha dlffexent po~itlons of a 4 po~ltion swltch 701-44 to the GP3 po~ition of switch 701~26 for testing. The same outputs are applied to a ~Qcond po~ition o~ a ZIR ~witch 701-43 for storage via the ZDO ~witch 704-340. ~he 2IR ~witch 701-43 al80 : receives indicator si~nal~ from an indicator regi~t~r ~IR) 701-41. Thi~ register iB load~d via tha ~DI
li~es 10-30 and 32 in response to certain instructions.
~he indicator status ~ignal~ for exampla include the output~ of different addsr circuit~ ~AL, AXP) of o ~o ~h~ wlit 720. ~hes~ signals will ~e~ d~fferent ones of a number of exhau~t flag flip-flops deslgnated FE11, 7~ FE12, FE13, FElE, FE2E, FE2 and FE3. The FElE and FE2E flip-flop~ are set during any FPOA cycle of any instruction. ~he~e flip-flops in turn cause the FEll, FE12 and FE13 flip-flops to be set when the~output~ f~om ~he AL or AXP adder circuit~ of unit 720' The setting and re~etting of the~e indicator~ will be de~crib~d herein in further detail ~n connection with the descriptlo~
of operation. However, the exhaust flag flip-flop~
~ertinent to th~ exa~ple given herein are ~et and xeset in accordance with the following Boolean qxpressions.
SET : F~lE o FPOA + IND6FLD field.
RESET : FElE = IND6F~D field.
SET : FE2E ~ FPOA + IND6FLD field.
~ESET : FE2E - IND6FLD field.
SET : ~Ell 3 IND6FLD fiQld.FElE (ALES + AXPES +
DESCl-APO-430) + IND6FLD field-FElE-DESCl-(AP0-5-O~APZN~LZN) ~ IND6FLD field.
~SET ; FEll = FPOA + II~D6FLD 1~1d.
: SET : FE12 = IND6FLD fi~ld-FElE-(ALES + A~PES + FE13).
R~SET : FE12 - FPOA * IND6FLD field.
SET : FE13 = IND6FLD field~FElE-ALES + IND6P~D field.
R~S~T : FE13 - FPOA + IND6FLD field.
SET : FE2 = IND6~LD field~FE2~-ALES + IND6FLD field-FE2E-D~SC2~(APO-4sO ~ APO-5~0 + APZN +
ALZ~ + (IND6FLD field) FE2~ . DESC2 IND6FLD.
RESET: FE2 = FPOA ~ IND6FLD field.

10~

S~T : ~3 = IND6F~D fiold-D~SC3~(AP0-4=0 + AP0-5 +
APZN t ALZN1 + IND6FLD field~DESC3 +
IND6PLD.
R~SET : FE3 = FPOA + IND6FLD field.
Wherein IND6FLD indicates a particular code;
ALES 8 AL30 or AL-C;
AXPES=AXP=0 or A ~
APZN c AP0-7 S 0; and, A~ZN = AL0~ 0.

: .

: :

~ ~ ' ' ' .
, .

- ~5 ~

~ rhe ZCSBR~ ~witch 701-18 i~ normally enabl~d when thc branch decision flip-flop RBD waB ~t to a blnAry ON~
in the previous cycle. Th~ fir~t po~ltlon selects a 13-bit branch addre~s from the current microin~tructlon -.
~= c---~
~ applied via the-~&~ ragister 701-20. The branch address r~ enable~ any one of the locations of the ECS control store to be addres~ed directly. The second positlon selects the concatenation o~ ~he 6 low order address bits from the current microin~tructio~ applied via MIC
register 701-15 and the 7 upper bits of the branch address from the current mlcroinstruction applied via the RsrR
regi~ter 701-20. ~hi~ permit~ branches withi~ a 64-word pa~e de~ined by the contents of the MIC regl3ter 701-15 (current location + 1). -The thlrd position ~elacts the concatenation of 4 low ord3r bits from thc RVBO vector branch regi~ter, 6 bits fro~ the br~nch field of the current mlcroin3truc-tion stored in RCSR regl~ter and the 3 upp~r bits of the addres~ stored in the MIC regist¢r. This permits 16-way branches. The fourth pO9~ tion selecta the con-catenation of the 2 low order Z~ROS with 4 bits from the vector bra~h regis~er RVBO with the 4 most signifi-cant bit~ of the branch addr~s~ ~ield of the curr~nt microinstruction and the 3 upper bit of the current addres~ stored in ~he MIC register. Thi~ permits lG-way branches with 3 control ~tore locations between each adjacent pair o~ de~tination addr~ss~s.
~ he ~if~h po8ition ~el~cts the concatenation of 2 low order ZEROS with 2 bit6 from vector branch regi~ter RVBl, with the 6 bit3 of the branch addreYs of the curr~nt microinstruction and the upper 3 bit~ ~rom the .~
- 4?~
~ , , MXC register. Thi~ pQrmits branches with 4 possible destinations with 3 control ~tors locatlon~ between each adjac~nt pair of destinatlon addresses.
The sixth position ~elect~ the concatenation of 2 low order ZEROS with 2 bita from vector branch regis-ter RVB2 wlth the 6 bits of the branch addres3 of the cuxrent microin3truction and the upper 3 bits from the MIC register. This p~rmits 4-way branches with 3 con-.
trol store locations b~tween each ad~acent pair of destination addres~es.
The output o~ swltch 701-12 addresses a speci~ic location within contr31 store 701 2 which causes the read out of a microinatruction word having a format : illu6trated in Figure 6~ Re.ferring to that Figurej it 15 i s seen that thi~ microinstruction word is coded to in-clude a number oP different field~ whlch are u~ed to con-~rol ~lle various ~unctional uni~ within processor 700.
Only those fi~lds whlch are relat~d to thc present exampl~ will be described hereln.

4~4~) : ~ Blts 0-1 Reserved for Future U~e.
~it 2 EUFMT Defines whlch form~t the EU
i~ to operate with. EU~T-O .
specifies a first micro-inBtruction fo~mat while EUFMT-l specifies an ~lter-nate microinstruction format.
Bit~ 3-5 T~L TR Low Write Control.
Write control of EV temporary regi~-ters TR0-TR3.
: OXX No change :~ ~ 100 Write TR0 :
101 Write TRl 110 W~ite TR2 :~ 15 111 Write TR3 Bits 6-8 ~RH T~ Hlgh Write Control.
Wr~te control of EU temporary regis-ter~ TR4-TR7.
OXX No change 100 Write TR4 10I Write TR5 110 Wri te TR6 111 Write TR7 25 ~its 9 12 ZVPA ZOPA Switch Control.
Selects the output o~ ZOPA ~wi~ch.
0) 0000 TR0 ~ 1~ 0001 TRl : 2) 0010 TR2 3~ 0011 TR3 4) 0100 TR4 5) 0101 TR5 .

~ , 6~ 0110 q'RG
7) 01ll l'R7

8-113 10XX RDI
12) 1100 ZEB
13) 1101 ZEB
14) 1110 ZÆB
15) 1111 0 (disable) Bits 13-16 ZOPB ZOPB Switch Control.
Selects the output of ZOPB switch.
10 ~its 17-18 ZRESA ZRESA Switch ~ontrol.
S~lects the output of ZRESA ~witch.

01 Shift~r ln Scratchpad~RDI swltch . 11 ZDO
~its 19-20 ZRESB ZRESH Switch Control.
Selec~s the output of ZRESB switch.

01 Shifter 10 Scratchpad/~DI switch ~it 21 ~SPB Scratchpad Buffer Strobe - Control.
Strobes RSPB with ~ESB data.
0 ~o strobe 1 Strobe RSPB
~it 22 RSP Scratchpad Write Contro.
0 Read scratchpad - 1 Wri~e cratchpad ~ , , . - . ........ ..... . .. .

o Bit 23 ZSPDI ScrAtchpad/nDI ~wltch Control.
Select~ the output of the Scratchpad/
~DI Bwitch.
0 Scratchpad output Bits 24-25 ZSHFOP Shifter Operand Switch Con-trol.
Selects the left operand to the Shifter.
00 ZOPA output 01 EIS ou~put 1~ 0 . 11 Select 0 or -1 depending on bit.
. 0 o~ right operand to Shifter.
15 Bit~ 24-27 ALU ALU Fu~ctio~ Co~trol.
; Selects the operation applled to the two input~ ~A and B) to the ALU.
~its 24-29 N/a : Bits 26-31 RFU P~es~rved ~or Future Use.
20 ~its 30-31 Z~LU ALU Switch Control.
Selects the output of ZALU ~witch.
~its 32-33 NXTD Next Descriptor Control.
- Strobes RBASB and RDESC register~.

R~ESC 00 01 ~ASB 0l RBASB A1t ~DESC 10 ll No strobes (default) Bits 32-35 CCM Control constant field referenced by the CONTF
fi~ld.

4~
s~
.~ ', ait~ 34-35 I~PIPE I~UF/Pipellne Control.
Select~ the readlng of IBUF or the ~lp~line oper~tlon.
00 No op~ratlon 01 Read I~UF/ZDI (Alt) Type 1 Re~tart ~elease or 11 Type 4 Re~tart Wait ~it~ 36-37 FMTD
Selects the loading of various CU
registers and indicates the ~nter-pret~tion to be given to the MEMADR
:~ fiald for small CU control.
00 No operation : ~ lS . 10 RADO ZRESI~

~it~ 38-40 MEMADR Cache Control.
5elects ~ache op~ration~. ThC com-plete interpretation for 'chi~ control is a unctlon of the FMTD corltrol.
- 000 No opera'cion 001 Read Sgl 010 Load Qua~
011 Preread 100 Write Sgl 101 write Dbl 110 R~ad Sgl Trans ~for FMTD 11 only) 111 Write Sgl Word ( for FMTD = 11 only) ~g Bi ~ 41. ZONE Zone Control .
Indicates zone or no zone for 3mall CU control.
0 No zone 1 Zone Bit~; 42-44 TYPA Type ~ Flag.
Indicates the type A overlayed fields being used .
000 Type A~0 fi~ld~
o '~ .
100 Type A-4 fields lS Bits 44-46 PIPE Pipeline Control Sel~cts the type of restar'c to be initiated .
000 No ~peration 001 Type 1 Restart and Release 010 Type 2 Re~tart ; 011 ~ype 3 Restart 100 Type 4 Re~tart 10} Type 5 Release 110 Type 6 Re~tart Bitz 44-47 AUXREG Auxiliary Register Wrlte Control Selects an auxiliary regi~ter or ro-i~bination~ ts~ be ~txobed wY ~ data ~el~cted by the AUXIN control field.
0) 0000 No strobe 1) 0001 ~
2) 0010 F~29 : - -, -s9 -~

3) 001l R29, RRDXA, F~, RID
4 ) 0100 RRDXB
5) 0101 RTYP
6 ) 0110 RBASA
7) Olli RBASA, RTYP
8) 1000 R~ASB

9) 1001 RDESC

10 ~ RBASA, R2 9, RRDXA
~ s 45-46 TYPB Type B Fla~.
. Indicate~ the Type B overlayad fi~ld~
be irlg u~ed .
00 Type B = 0 fields ~: 15

11 Type B ~ 3 field~
~it 47 RSC RSC Strobe Cont:rol.
Strobe~ the RSC register. ~Shift Count) ~it 47 RSPA RSPA Strobe Control.
Strobe~ the RSPA r~gister.
~its 47-48 N/A
~i t 4 7 R~AU RAAU Strobe Cozltrol .
Strobes RA~U regi~t~r.
~it~ 48-49 ~ ZLX ZLX Switch Co~trol.
S~lects the output of the ~LX ewitch.
Bits 48-49 ZSPA ZSPA Switch CoJ~trol .
Sele~:ts the QUtpUt o the ZSPA
~witch.

o : " ~

~it.5 48-50 AUXIN Auxiliary Regi~ter Input Contr~l.
Selects data to be Atrobed into auxiliary register(s).
5 Bit 49 ZADSP ZADSP Switch Control.
Selects the ou put of ZADSP ~witch.
~it6 50-52 ZSC ZSC Switch Control.
Select~ the output of ZSC swi~ch.
Bit~ 50-52 ZRgPA ZRSPA Switch Control~
10 Selects the output of ZRSPA switch.
~i.f 5 ~0-52 ZAAU Z~AU Switch Control.
Bit 51 ~SI~ RSI~ ~gister Strobe.
Strobes ~he RSI~ re~lster as a fun~tion of th~ AUXIN field.
15 Bit 53 ~DW RlDW, R2DW Regi~ter Stro~e.
Strob~s the Rl~W or R2DW regi~ter a a function of the RDESC regi~ter.
~ita 53-54 ZLNA ZLNA Switch Control.
~ Sel~ct~ output of ZLNA ~witch.
20 Bits 54-57 CONTF Mi~c~llaneouæ ~lip-rlop Control.
Select~ on~ of four groups of ~ontrol ~llp-flops to be set or re3et by t~e control constant field tCC~). The flip flop~ include those of block3 704-104 and 704-110.
Bits 55-56 ZLNB ~LNB Switch Control.
Selec s the output of ZLNB ~wit~h.
Bits 55-56 ZSPA(2~ ~ype A~2 ZSPA Switch, ~SPA
Register Control.
Select~ ZSPA ~witch output and ~trob~
R~PA regi~ter.

o 6t ~ .
Bit~; 57-58 ~PC ZPC Switch Control.
Selects ~che output of æPC ~witch.
Bits 59-62 ZXP ZXP Switch, RXP ~e~ister Bank Control.
S Selects ZXP switch output and the RXP
register into which it will be written .
Bits S~-63 ZLN (l) ZLN Sw~tch, RLN Register (Type Bank Control.
A=l ) Select~ ZI,N ~witch output and the RLN
reg~ster into which it will be written.
Bi~ 59-60 Z,PA ZPA Switch Con~rol.
S~lects the ou~pu~ of ZPA switch.
. ~0 ~ R~O
.

~0 11 = RP3 ~its ~1-62 ZPB ZP~ Switch Control.
Selects the output of ZPB 0witcho ~0 =RP~ ' .
~5 . ~

11 = RP3 ~ ~ .
.. . . . .

b:2 rdil 5 63-64 ZXPL ZXPL Swltch Control.
ype A-O ) Select~ the output of ZXPL ~witch.

, lU Bit: 63 ~LN(2) ZLN Switch, RLN Register ~ype Bank Con trol .
` .AY;! ) ~: : Selects ZE.I~ swi~ch output ~nd the ~L~
regi:~ter into which it will be written.
13its 63-66 ~D~N RDI In Control.
: 5elects the d~'ca to be ~trobed into ~he RDI - regi3t~er and sel~c~s one of tha modification controi f ~eld8 ~3, TAG) ~ f ~n in~truction word . PcDI
strobe may al80 b~ controll~d-by the MISC~EG field.
E~it 64 ZXPLtl) 2XPI, Switch Control.
(q'ype~ A~l) :~ ~ Selec~ the output of ZXPL ~witch~
2 5 lii t s 6 4 - 6 8 Z RPAC Z RPA Swi tch, Z RPC Swi tch, ~Type RE'O-3 Regi~ter Bank Control.
: Aa2 J
Selec'cs ZRPC and ZRPA ~witch outputs - an~l: the ~PO~3 register into which th~3 ZRPA output will be written.

~ ~ .
, , __ ~3 F~ , 1~it;~ 65-6~ ZXPR zxrR Swltch Control.
t Type 1~
';olocts the output ~f ZXPR ~wltch.
~it~ 65-66 ZXP(l) ZXP Switch, RXP Reqlster (Type ~ank Control.
A~l) Selects ZXP ~witch output and the RXP
r~gl~ter into which it will be written.
l~its ~7-6S ZPD ZPD Switch Control.
(Type A=O) Selec~s the ou~put of ZPD switch.
it 67 ZRPAC(4~ ZRPA Swit h, Z~PC Switch, (~ype RPO-3 Reyi~ter ~ank Co~trol.
A-4) Select~ CP4 from ZRPA switch and strobe~ the RPl register.
~it 67 TYPD Type D Flag.
` ~ype D Flag whi~h ind~cates D ovsr-layed fields.
~0 ~it 68 ZRPD(4) ~P~ Switch, RP4-7 Regi~ter (Type ~ank Control.
A=4) Select~ O from Z~PB ~witch and strob~s the RP4 regl~ter.
25 Bits 68-71 MEM Cach~ Memory Control.
5~1ects the cache oper~tion in con-junction with the SZ control.
O) 0000 No op~ration .

15) 1111 Write Remote Bits 68-70 I~UF I~UY Read Control. ';
Selects the de~tination of IBUF data wh~n re~dlng IBUE'.
BitB 69-73 AXP ZXP~ Switch, ZXPB Switch, (Type . AXP Adder, ZAXP Switch, RE
A~0) Register Control.
~: Select~ ZXPA and ZXP~ switch outputs, the AXP adder function applied to them, and the ZAXP ~witch output. Also strobes the RE reg~ster.
~it~ 69-73 ~Pa ~RP~ Switch, RP4-7 R~gis~er lType Bank Control.
A=l) Sele~t~ Z~P~ ~witch output and the RP4-7 regi~ter into which it will be written.
: ; ~itB 69-71 ZRPAC-3 ZRPA Switch, Z~PC Switch, ~ (Type RP0-3 Regi~ter Bank Control.
A83) -~ 20 Select~ ZRPC and ZRPA ~witch outputs ~nd the RPO-3 r~gister into which the ZRPA out~ut will ~e written.
- Bits 72-74 ZRPB~3) ZRPB Switch, RP4-7 Register (Type B~nk Contxol.
A-3) Select~ ZRPB switch ou~put and ~he ~P4-7 regi ter into which it will b~
wrltten.
~its 72-73 SZ Size/Zone Cache Control~
C~ntrol~ cache operations in conjun~tion with the ME~ control field.
, ~s J
Bi~s 74-78 ZRP3(3) ZRPB Switch, ~P4-7 ~egister (Type Bank Control.
A~0) S~lect~ ZRP swltch output and the RP4-7 register into which it will be written.
~its 74-78 AL ZALA Switch, ZALB Switch, ~L
(Typ~ Add~r Control.
A~l) Selects ZAL~ and Z~LB swltch output~
and the AL adder function applied to them.
Bit 74 TYPE Type E Flag.
Type E flag which indicates the type E overlayed fi~lds.
15 ~it~ 75-77 ZXP(3) ZXP Switch, RXP R~gi~t~r Bank ~Type Control~
AJ3) Select~ ZXP ~witch ou~put ~nd the RXP
register into which it will b~ written.
20 ~its 75-78 MISCREG MiHc~llsn~ous R0gi~t~r Con-~rol.
Selects various operations on ~
cellaneous regi~er~ ~e.g. RBI~, RDI, RLEN ~ ~PP) .
25 Bit~ 75-78 ZDO ZDO Switch Control.
Sel~cts the output of the ZDO switch.
~it 78 ZIæN ZIZN Swi ch CoAtrol.
Selects the output of ZIZN switch.

_6~

Bit~ 79-83 AP ZAPA Switch, ZAPB Switch, AP Adder Control.
Select~ ZAPA and ZAPB ~wltch output and the ~P adder function applied to them.
~it~ 79-81 ZLN(3) ZLN Switch, RLN Regi~ter tTYp9 ~ank Control.
A~3) Select~ ZLN switch output and the RLN
register into which it will be written.
Bits 79-~3 ZLN(4) ~ Switch, RLN ~egister Bank (Type Control.
- A~4) Selects Z~N outpu~ and the ~LN ~gis-ter into which it will be writt~n.
~it~ 80-81 ~AAU ~AAU/RE R~gi~ter Strobe.
Sel~cts the data to be ~tro~ed lnto th~ R~AU and RE reg~ters by con~
trolling 6everal switche~ and adders in the unit 722.
` Bit~ B2-B3 AP (3) 2APA Switch, ZAPB Switch, (Type AP~Adder Control.
A~3) ~ S~lects Z~PA and ZAPB switch output~ --~ j 25 and the AP adder function applied to ~hem.
Bit 84 ZRSC ZRSC Switch Cvntrol.
~ype A=0~
Select~ the output of ZRSC Switch.
30 Bits 85-8~ N/A

r3~

~it 86 RLEN ~LEN Strobe Control.
~Typ~ A=3) RLEN ~trobe~ are al~o controlled by hardware or by the MISCREG fleld.
5 Bit 87 FMT Format Flag.
Indicates he type of format.
Bits 88-89 TYPF
Indicates the type of overlayed fields.
00 = Scratchpad Addre~
01 = Character Uni~ Control 10 - Mul iply/Divide Contrsl 11 - N~A
Bit 90 RFU ~eserved for Future Use.
~it~ 90-93 CHROP Character Unit Op Code.
Select~ main operation to be per-: form~d by Character Unit and the ~nterpretation to be giYe~ to the CHSUBOP f~eld.
O) OOOO No operatio~
1~ 0001 ~oad Data 2) 0010 MOP Execute 3) 0011 Compare Sinyle - 4) 0100 Compare Double 5) 0101 Load Re9l~ter 6) 0110 Update CN
7) 0111 Untefined 8) lQ00 Se~ RC~ Operatio~ A
9~ 1001 Se~ RTFl 10) 1010 Se~ R~F2 11) 1011 Set RTF3

12) 1100 Set RCNl ~6 ~ ' , .

13) 1101 Set RCN2

14) 1110 Set Edit ~lag~

15) 1111 CH Vnit Clear ~it 90 RCH RCH Reg~ster Strobe.
Strobes the OPl RCH register.
Bit 90 RFU Reserved for Future Use.
Bits 91-97 SPA Scratchpad Addres~.
Co~tains the addre~s that may be uséd to address the EU scratchpadO
Bitg 91-93 N/A

.
.

~9 :, ~ i Bit8 94-97 C~SU~OP Char~cter Unit Sub-Op Coda.
, Select~ the detailed functlon of the Char~ter Unit or it may conta~n ~ con--~tant. The intsrpretation of thia field is a function of the CHROP
control a~ shown below.
CHROP = 0000 No Operation CHSu~OPo_3 : XXXX No interpretation C~UBOPo_l ~Suboperation) 00 OPl Load by CNl and TFl :~ 01 OPl Load in Reverse by CNl and TFl OP2 Load by CN2 and TF2 and Test Character 11 Load Sign CHSuBOP2-3 ~F~ll ContrOl) ; lX Fill charact~r loaded to ZCU
Xl E'ill character loadad ~o :, ZCY
' CHSu~cPo-l (Suboperation) 00 MOP et by CN2 01 MOP Ex~cut~
Undefined : 11 Undefined CHuBop2-3 ~ 30 XX No interpretation .~ .

~its 94-97 C~ISUBOP (continued) CIIROP = 0101 I.oad Reg~ster Operatlon --Ci~SU~OPo_l (Selecta ou~put of ~C~) Cl~suBop2-3 (SelectR outpu~ of ZOC
. sw~tch) CHROP = 1011 Set_RTF3 Operation CHSU~OPo 1 (Selects data to be ln~pected for 00, indicat-ing a 9-bit character.) CHSU~OP2-3 (Constant Field) CHROP = 1110 Set Edit Flag~ Operation ~- CHSUBOPo_3 (Constant s~lecting flag~
: to be set) :~ lXXX Set ES (End suppression) XlXX Set SN (3ign) XXlX Set Z ~zero) XXXl Set BZ (Blank When ZeroI.
Bits 94-97 RFU Re~erved for Future U~e.
Bits 97-97 N/A :
20 Bit 9~ TYPC ~ TYPE G E'$AG.
dicates the type sf overlayed field~.
0~= BRADRU field - 1 - IND6 fi~ld : Bit 99 GO State of Conditional Branch T~t.
:~ Bits 99-106 BRADRU Branch Address Upper.
: Bits 99-106 IND6FLD Indicator Control.
Selects an indicator.

.

3~V

~ , , Bits 9g-106 Bit 99 z 0 sp~clfie~ a rhange indica-tors instructlon.
~it 99 = 1 specifie~ a se~/rs~e lndl~
cators instruction (set or reset indicated by X bit 0 or l respectively~
its 100 104 105=1 1O6G1 _ .

.
llOOX Exhaust 1 ~3xhaust 2 llOlX Exhaust 3 N/A
lllOXExhaust 1 ~xhau~ 2 ~ffO Eff.
Bits 107-112 BRADRL~RANCH ADDRESS LOWEn.
Contains lower portion of an ECS addre~
u-~ed for br~nching.
Bit 113 EXIT ~lection of Exit Switch Con-.
~0 trol.
Selection of Exit indicatas end of microprogram.
BitB 114-116 ZCSBRA ZCSBRA Switch Co~trol.
Defi~es the po~ltion to bs selected in ~ Control Store ~rancA Address Switch.
Bits 117-118 N/A
~it 119-123 INDGRP Conditional Br~nch Indicator Group Co~trol.
The ~irs~ two ~its (119-120)~ele~t the "group~ of microprogram indicators.
The last three blt~ ~121 123)~ele~t ~ 3~0 ,. . .. .

. ~ ~ the "~et" of indicators within each " group'~Y~
it 1~4 TYPH 'rype H field.
Indlcate~ the type H overlayed flelds.
0 = INDMSKU
1 = VCTR field Bit~ 125-12~ INDMSKU Conditional Branch Indicator Mask Upper.
Contains the upper 4 blts of the indi-cator maqk in type H = 0 field.
~its 125-129 VCTR Vector Sele~t.
Selects the branching ve~tors to be strob~d in o the RVB0, RVBl and ~VB2 r~gisters. The st ~ignificant bit (125) deteYmines which of two groups 0 or 1, 2 or 3 and 4 or 5 will be strobed into the RVB0, RYBl and ~V~
register~ respectlvely. The remalning 3 b$t~ select the vector within each group.
Bits 129-132 INDMSKL Condltional Branch Indic~tor Maqk Lower.
Contains the lawer 4 bits of the ind~cator mask.
Bits 133-135 N/A
~its 136-139 CNSTU Con~tant Upper.
Contain~ the upper 4 b$ts of the con-~tant field.
~its 140-143 CNSTL Con~tant Lower.
Contains the lower 4 bit~ of the con-stant field.

~ Control Lo~ic Unit 104-l , , , _ This uni~ lnclude~ the so(luence decod~ loglc cir-cults 704-l00 as m~ntlon~d who~e output~ ~eed a plural- -ity of I cycle control ~tate fllp-flops of ~lock 704-l02. These flip~flop~ in r~-qponse to ~ignals from the circuits 704-l00 as well as microinstruction signals from reyister 701-4 (DMEMR038-40 which corresponds to the mem address field MæMADR of Figure 6b) ~enerate the various required I cycle control state~ required for the execution of program instructions. It i8 as3umed that block 704-102 aI80 in~ludes gate circuits which -7 ' g~era~e regi~ter hold signals (HOLDE00)whi~h are d~-tributed throughout the proc2~0r 700.
A~ seen from Figure 3c, the I cycle control state 15 flip-flop~ r~ceive control input signal3 via control lines including a line CPSTOP00 from cache unit 750.
A~ explained herein, the state of the CPSTOP00 line det~rm~nes wheth~r proce~sor operation continues in that when the line i~ forced to a binary ZERO, the hold or enabling ~ignals for the I cycle control state fllp-flops and other storage registers are al80 forced to Z~ROS~ The hold signal~ corre~ponding to ~lgnals [HOLDI00 and lHOLDE00 operate to hold or freeze the state of the processor 700. Since no incrementing of the co~trol ~torQ ~ddress can tak~, the ECS control store reads out the same microinstruction word. The signals lHOLDI and lHOL~E are ~et in accordance with the ollowing Boolean expre~sion~: [HOLDI = CACHE HOLD
+ TERMB (DRE~-IF-DIR) f HOLD RæL wherein the ~tate of ignal CACHE ~OLD corresponds to the state of ~ignal CPSTOP, the state~ of signals TERMB (D~EQ-IF-DIR) are binary ONES during control ~tate ~POA when the cache 34(3 ~4 70~
~ , conunand ~pecifies an I fetch or dlract operation and - the ~ignal HOLD ~EI. is a binary ONE until switched to a binary ZER~ by the generation of a microprogram r~leas~
signal; and LHOLD E 3 [HOLD I.
S As 6een from Figure 3c, signals corre~ponding to the I cycle control ~tates are applied as inputs to a plurality of control flip-flops of block 704-104, de-coder circuits of block 704-106, a number of control logic clrcuit~ o ~lock 704-108 and to a plurallty of control flag indicator flip-flopa of block 704-110.
It i~ o se~n that the var~ous indlcator flip-flops of block 70~-110 al80 receive microinstruction input 8ig-nals via lines MæMD054-57 from ex~¢ution control un~t `! ./ 701-4.
-- 15 A~ seen from Figure 3c, signals generated by the hardware control logic circu~ts 704-108 fall into ona of thre~ groups as a function of the unit~ whose opera-tion~ are being controlled. That i~, the groups are : instructlon buffer oontrol, hardw~r~ control and hard ware me~ory control.
~ n each ca3e, each group of signals a~ ored to-gether wlth equivalant signal6 gen~rated by other sources and then decoded. The oth8r ~ources corre~pond to fields withln the two different format~ of the microinstruction word o~ Fi~urs 6a which are loaded into ~CSR xegister 70~112 from ~he ECS outpu~ regi~er 701~
: One field corre~ponds to bits 32 83 of one format ~large CU) and anothar field (shoxt CU) corre~ponds to bit~ 32-41 of anoth~r ~ormat. These fields are de-. csded by ~ decoder 704-114 into the get~ of bit~ indi-; cated and c~mbined within th~ decoder~ 704-116, 704-124, 704 126 and 704-128 ~s shown. Further decoding is ~5 ~ ' ', :: done by the circuits of blocks 704-118, 704-135 and 704- -1~0. Tlle results of decoding such fields are eithe~
distributed throu~hout proces~or 700 or are ~ ored ln an RMEM register 704-130, an RSZ fllp-flop 704-132, an S FREQDIR flip-flop 704-136 and an FREQCAC flip-flop 704-134.
Additional decoding of the large and ahort CU
~ields and ~ignal~ from the I c~cle state circults of C.oc~e ~
.~,^i~ block 704-112 i6 done via ~eao~ 704-106 and 704-107~ The decoder 704-106 generates control signal~ for lo~ding different ones of the register~ and for enabling various mult~plexer/selector switches within the pro-ce~or 700. The decoder 704-107 operate~ to generate signals for setting and r~et~ing a pair (R~ASB) of ba~e po~nter 8 flip-flops 704-144. Other combination~
of the~e ~ignal~ are u~ed to 8et and reset th~ des-criptor nunb~r flip-flops of bloc~cs 704-140 ~nd 704-1J.2.
A8 ~een from Fig~sre 3c, the d¢coder 704-116 re-ceives a control signAl lEXH00 generated by the decoder ~0 s~ircuits of block 704-117. These circuit~ receive : signal~ from the RDESC regi~ter ~04-140 and ~ignal~ from -the exhaust flip-flops of block 701-1~ In accord~nce with the state~ of the8e signal~, the circuit~ force signal [~XH000 to a binary ZERO to i~hibit the genera-tion of a cache memory command upon the occurrence of an exha~st conditionO The signal l~XH000 i~ gansrated in accordance with the following Boolean expression:
[EXH000 = DESCO FEll + DESCl-FE2 ~ DESC2-FE3.
The flip-flop FNUM i~ normally set in re~ponse to the CCS-OP field of the m.icroinYtruction word. When 6et to ~ binary ON~, thi~ indicates that the descriptor LV
lb ~ , , being processed i3 a numeric type.
The di~erent flip-flops of bloc~ 704-104 will now be di~cussed in greater detail. In greater detail, the flip-flop FC~AR provldes certaln changes in the contro, 5 of addresq generation. When the FCHAR flip-flop is set to a binary ON~ during the proce~sing of a load type instruction specifying character mod~fication, then the contents of the RDI registar ~ not changed under hard-Ware-G~. This allow~ the ~DI xegister to be l~aded with data under ~icroprogram control prior to starting the pipeline. Also, if the FCHAR flip-flop i~ ~et to a bi~ary ONE during a store typ~ lnstruction specifying character modification, then the execution addres~ for this instruction is modified under hardware control to point to a unique addr~s6 of th~ micrsin~t~uction Be~uence in ~he E:CS co~trol s~ore that i8 to proces~
this type of in~truction.
The flip-flop ~T-FOUR provid~s additlo~al control on the re~dout of the addres~ r~gister ~ZARo 19) of block 704-304. Flip-flop ~AD~-WD provides additional control for the ZDO switch 704-340. When this flip-flop i~ ~et to a binary ONE, th~n the ZAR po~ition of the Z~O
s~itch is forced to select a word address. Th~ ~lip-: flop FADR-~ provide~ additional control for the ZDO
multiplexer sw~tch. When set to a ONE, then the ZAR
po~ition of ~he ZDO swi~ch is forced ~o select a byte address. The flip-1Op FNUM is normally set in respons~
to the CCS-OP field of the microinstruction word. ~hen ~et to a binary ~NE, this indicates tha~ tha descr~ptor being pro~essed is a numeric type. The flip-flop YIG-LEN
provides additional control over the loading of r~ ters withi~ the unit 7~2 (Iength registers~ and over memory , ~1 operations. When set to a bin~ry ONE, the ~XP and ~LN
registers within unit 722 are not loaded from the RSIR
regi~ter 704-154 during certain processox control stat~ .
FPOP.
The FI~H-ADR flip-flop inhibits the operation of the address preparation unit 704-3. When set to a binary OI~E, an addre~s cycle (FPOA/PPO~) conqists of adding the contents of a temporary effective address register ~EA-T
~ ZERO. The regis~er REA-T will have bee~ loaded with th~ ad~ress prior to doing a FPOA/FPOP cy~le. The FABS
fl$p-flop enables the generation of absolute addresses.
When set to a binary ONE, a 24-b~t absolute addr~ss i8 us~. A~ concerns the flag or indicator flip-flops of block 704-110, flip-fl~p l'ID when set to a binary ONE
provide~ an indication that indirect addre~s modification during an instruction is required on the descriptor loaded into he RSIR register.
The FRL flip-flop when set ~o a binary ONE indic~tes that the length i~ specified in a re~istsr associated with the instruction loaded into various instruction registers. The three flip-flops FINDA, FINDB and FINDC
provide indication~ used in processing memory type instruc-tions. Flip-flop FINDA is set to a bin.~ry O~E when length is qpecified in a re~ister or when flip-~lop 25 FAFI is set to a ONE. Flip-flop FINDB is ~et to a binary ONE when the descriptor does not include nine bit characters. The fIip-flop FIN~C is set to a binary ONE
whe~ the descriptor does include ~ix bit characters.
The FAFI flip-flop is set to a binary ONE wh~n the processor circui~ detect that indicator bit 30 of IR
register 701-41 was set to a binary ONE during the execu-tion of an EIS instruction i~dicative of a mid i~struction . . _ _ _-- , int~rrupt (reyuired to adju~t pointer and length value~ -, because of interrupt). The FTRGP, TTNGO and FTRF-TST
flip-flops are 6et to binary ONES in conjunct~on with transfer type in~tructiona. More specifically, the FTRGP flip-flop provides a microprogram indication of being set to a binary ONE when the proceqsor clrcuits detect the read out of a transfer type of instruction during the execution of an execute double (XED) or re-peat (RPTS) inqtruction. The FTNGO flip-flop provid2s a microprogram i~dication of being set to a binary ONE
when the conditlon of transfer signalled by the ~xecu-:: tion control unit 701 was transfer NO GO (i.e., transfer ~ did not take place). The output of thi~ flip-flop i~
: applied to the NO GO l~ne of int~xface 604. The FTRF-~ST flip-flop of ~his group indicates when s~t to a binary ONE that the previous in~truction executed by proces~or 700 was a tran~er t~pe instruction and that the curret I cycle 1~ to be executed conditioned upon the pre~ance of a transfer GO ~TRGO) ~gnal from con-trol unit 701.
Addi~ionally, the circuit~ of block 704-110 include a n~er of flip-flop~ used in performing indirect addres~iny op~rations under hardwired control for other than EIS instruction~. The~e include FIR, FIR~, PIRL
and FRI flip-flops which are witched to b~nary ONES
as functions of ths different types of indir~ct addres~
modific~tion~ required to be performed. For example, the FRI flip-flop ~ignals 3 regi6t~r then indirect addr~ss modification and i~ ~witched ko a binary ON~ whe~ a register indirect (R~ indicator i~ a ~inary ONE. ~he FIR flip-flop ls ~wit~hed to a binary ONE when an in-direct ~hen regi~ter (IR) indicator iq a binary ONE.

~hls 11p-flop ~lgnal~ the beglnnlng of an indlr~ct ~hen r~lst~r addresa modlflca~lon. The FIRL fllp flop i~
~wl ch~d to a l~ln~ry ON~ when an lndirect th~ tally : in~irect ~IT-I) indlcator i~ ~ blnary ONE. Thls flip-S flop signals a la~t indirect oper~tion. Another flip-flop ~SX2 provids~ an ~ndlcatlon used in processing tran~fer and ~et index inqtruc~ion~ whlle a STR-CPR flip-flop is used during the processing of ~tore inatruGtio~s.
A~ seen from Figure Ic, the output~ from ~he control flag flip-~lop~ of block 704-110 are applied ~ input~
to the branch i~dicator circuits of block ~01-l. Also, output signal~ from th~ control flag fllp-flops ara al~o applied a3 input~ ~o th~ I cycle flip-flop~ o~ ~lock 704-102.

4~3 ,~
~ , , egister Section 704-150 As ~een Prom Flgur~ 3c, the contrcl logic unit 704-l further includes a regi~ter sec~ion 704-150. Thi~ ~ec-tion contains the ba~lc in~truction reglster (R~IR) 704-152, the secondary instruction register ~RSIR) 704-154, a base pointer A register (RBASA) 704-156 used for selecting one of the address registers RAR0 through RAR7 of block 704-3~4, a read index regi~ter A (RRDXA) 704-158 us~d for ~election of index registers included within sertion 704-5 ~ot shown) and for selection o~ output~
from the ZDO multiplexer switch 704-3~0, a read index A
ave ~RRDXAS) register 704-159, and a de~criptor type regi~ter (~TYP) 704-160 indicating the type of data characters baing pointed to by the de3criptor value : 15 (e.g. 9 bit, 6-bit, 4-blt). The ~ection 704-150 ~urther include~ a 1-bit instruction/EIS de~rlptor register designated R29 of block 704-162. The ~tat~ of this blt in con~unction with the content~ of the ~AS-A regist~r 704-158 are used to select the particular address regls-: 20 ter u~ed for address preparation. When register R29 ~f block 704-162 i~ ~et to a binary ZERO, thi~ indicate~ .
:that none of the address registers of block ~04-304 are u6ed during addre~s preparation7 The last reglsters of ~ection 704-150 include the data in register (RDI) of block 704-16~ and a read index rsg~ster B (RRDXB~ poln~--~ ing to regi~ter~ u d by execution unit 714.
As ~een from Figur0 3c, the RBIR rsgi~ter 704-152 : i~ loaded via a two po~ition switch 740-170 connected to receive signal~ .rom the ~ource~ indicated ~i.e., ~
switch ZIB-B 704-172 and lines ZDI 0- 5). The ~SIR
: regi~ter 704-154 ~imilarly receive~ ~ignal~ from the 4/~
, ~1 ~DI line~ and ~witch 704-172. The ~ASA registsr 704-156 r~celves ~31gnals from the ZDI lln~ 0-2 in additlon to a further 9witch ZB~S~ of block 704-174. The RnDXA
regis'cer and RTYP register receive signals from the ZDI
lines ~s well as ~~ eeh 704-176 and 704-178 a~ shown.
~; A190, the RRDXA register receives 3ignal~ from ths RRDXAS
regist~r 704-159.
The ~witch 704-172 is a two position switch which receiv~s input~ from the switch~s ZIB and ZRESB from the cache unit 750 and execution u~it 714 respectiv~ly. The switch 704-174 is a three input switch which receives two inputs from the execution ~ 714 and the output of the ZIB switch of cache ~it 750.
Switch 70~-176 1~ ~ four ir~put switch which re~eiYe~
'cwo of its input~ from the execu'cion unit 714 and a ~ingle input from cache unit 750. The firPt pos~tion of the ZRDXA switch 7a4-176 se1ects the output of a ZRDXM
9witch 704~185. One position of ~h~s switch provide6 a tag field v~lue from bit posit1On~ 5-8, 14-17, and - 20 32-35 of the RBtR register 704-152 and bit po8ition~
32-35 of the RSIR register 704-154 ~e1ected from 2IDD .
switch 704-180 and a two position ~MF 8witch 740-176.
The ~econd po~ition of ~witch 704-185 provides a : ~ con~tant value from the output of the ECS output regis-ter 704-1 (CCM fleld 32-34). Th~ signal3 from the line~
ZIDD 27-35 are app1ied as inputs to control flag flip-~- flops of block 704-110~ The swltch 704-178 receives an input Pr~m the contro1 store 704-2, an input from cache unit 75û and an input from ex~cution uni~ 71 The data input xegister 704-164 receive~ a ~erie~
of input signal6 from a ZIDD switch 704-180 which connects in series to a ZDIA ~witch 704-181 who~e output provides one input of a further switch 704-182 which directly load~ into th~ RDI reqi~ter 704-164. The ZDIA -~witch 704-181 ~rovide~ ~ furthor input to a three input ~witch 704-1~3 which receives the other input~
indicated from cache unit 750 and execution unit 714.
The ZIDD ~witch 704-1~0 receives an effective addre~s via ~witch 704-186 from the address preparation unit 704-3 a3 well a~ inputs from the RBIR regi~ter 704-152, the RSIR register 704-154 and a two po3ition ZMF
switch 704-187. The positions 1~ through 35 of thë REA
po~ition of ~witch 704-180 are d¢rived from the ZDIA
switch 704-181 as shown. The ZDIA switch 704-181 re-ceive~ signals from the ZDI line~ 0-35, a constant value gsneratéd from the inputs to a firRt ~witch po3ition in additlon to si~nals from ~he output of the ZIDD
~witch 704-80 and the ZRESB switch in execution unit 714.
The switch 704-182 receives the output of the ZDIA
switch and 3i~nal~ from the ZDI line~ 0-35. The RRDXB
register 704-1~9 is loaded by a three po~ition switch ~0 704-188. The switch receiYe~ via a fir~t poslt~on signals ~rom a RREG r~gister included in the eXQCUtion `
unit, a constant v~lue ~rom control store 701-2 vla a ~ second posi ion a~d signals from the ZIDD swit~h via a - third position.
The s2ctio~ 704-150 further includes a two po~i~ion switch 704-185 and a Rcratchpad pointer register 704-186 whose output i8 used by the AAt~U 722 to form addresses for acces~ to the scratchpad mems:~ry of the E;U 714. q'he ~irst ~witch position prt)~ride~ a ~onstant value and i8 selected under hardware control (FPOA~).
~hQ seco~d ~witch po~ition applies a~ an output the contents of the ~A5A register 704-156. This position .

~ ., 1`f3~
,,.. ~,, - iB select~d under bo$h h~rdware and microprogram con-trol (l.e., FP~A-R~9 or MISC~E~ field).
lt wlll be ~ppr~ci~ted that the requlred ~imlng ~lgnal3 for operatlng aect~on 704 ~ well a~ other 3ec-tion3 of processor 700 and cache unit 750 are provided -by centr~lly located clock circui~s. For example, in the preferred embodiment of Figure 1, the clock cir-cuits are located within ~he inpuf/output processor system. Such clock circuits can be considered as con-ventional in de~ign and can comprise a crystal con-trol.l~d oscillator and coun~er circuits. The timing or clocking signal~ from ~uch clock circuits are di~- .
: tributed in a conventional manner to th~ varlou~ por-~: tion~ of the ~ystem of ~i~ure 1 for ~ynchronized opera-tion. From ~uch timing signal~, circuits within pro-e980r 700 derlv~ addisional clocklnq signals as re-qulr~d. ~hi~ will be d2scri~ed in grcater detail with respeot to the cache uni~ 750 of Figure 4.

Q
Address Pre~aratlon Unit 704-1 .~ ~he ~ddre~ preparatlon unit 704-3 include~ a num-~er of regi~ter~ and adders. Th~ regi~texs include a number of base registers (i.e., TBA5E0 through TBASEB) S of block 704-300 u~ed for s~oring descriptor values of an inst~uctlont a pair of temporary e fectlve address registers (T~AO, T~Al) and a pair of instru~tion counters (IC~, ICBB) includ~d within block 704-302 used for addresslng the inBtruction buffer and eight addre~s 10 registers (RAR0 through RAR7) of 7Q4-304 used durlng a~dres~ preparation operations. The unit 704-3 ~180 i~clud~s a~ instruction counter 704-310.
~he adder3 includ~ adder 704-312 used to update in~truction counter 3~4-310 via switche~ 704-311 and 15 704-314 and a pair o adder~ 704-320 and 704-322. The adder 704-322 i~ u~ed to generate ~n effective ~ddre~s value which is ~tored in a register 704-342 applied a~
an input of the control unit 704-1. The eff~ctlve addre~ i8 generated from a number of ~ources whlch 20 include ZY ~wi ch 704-326 whose ou~put i9 appl~ed vla a number of AND gates of block 704-327, s~lect~d ~ddres~
register~ o~ block 704-304 or selected tempor~ry 2ddr~ss regi~tars TEA0 and TEAl of block 704-302 applled via another switch 704-32~ or the ~ndex ~ddr~ss slgnal~
?S ZX0-20 from unit 704-S. Additionally, adder 704-322 is used to update the content~ of the in~ru~tion counter of the cache instruction buf f~r.
: As ~een f rom Figure 3d, th~ output~ from ~dder 704-322 aro also applied as an input to th~ adder 704-30 320. The adder 704-320 i~ u~ed to co~b~ne base value stor~ ln any one o f ~he temporary base regi~ters TBASE0 through TBASEB with the addre~ signals ACSOS0-19 from ~s --e3;--adder 704-322. The re~ultin~ ~its are applied as ~n input to a furth~r a*dsr network 704-320 ~hich ~ener~te~
a lo~ical addre~s which is applled to the llna~ ASF~0 36 via an adder 704-321~ This adder ~ums the operand in- -i puts together with the carry input~ from blocks 704-300 and 704~320. The effective addres~ is used to obtain an absolute address when the ~y~tem is operated in a paged mode. Since this operatio~ i~ not pertinent to thc present invention, it will not be discussed further herein. For further information regarding suGh addre~s dev~lopment, reference may be made to U. S. Pa~ent No.
3,976,978.
The temporary base registers of blosk 704-300 ar~ .
loaded via a sw$tch 704-332. The switch receives a~ in- :
put from the execution unlt 714 ~nd the output from bloc~ 704-300. The ~xecution unit 714 applles further input~ to the regi~ter~ of block 704-302 Yia a swit~h 704-334 as wall as to ~he addre~s registers of ~lock 704-304. An output multiplexer ~ZD0) ~witch 704-340 enables the 8elect~0n of the variouB regi~ters wlthin : the addre~ prepar~tion unit 704-3 and unit 704-5 for transfer of their con~ent~ ~o the execut~on unit 714 via lines ZDO 0-35. Al~o, the ~DO swltch 704-340 ensble~
the co~tents of varlous one~ of the regi~tars and con-: 25 trol flip-flops of unlt 704-1 to be read out via a fourth po~itio~ (ZD0-A~. The fifth position enables the ~tate~ o~ ~arious indicator~ wi hin the control ~tore circuits of block 701-1 to be selected for examinatlon.

~ .

o Vata,/Addres~ OutPut S~ction 704-4 Flgure ~e 'rhe section 704-4 lncludes the registers ~nd ~wltch~s U~Q~ for transferrlng commands and data to the cache 750. Such transfer operations normally requlre at least two cycle~, one for ~ending an addre~s and another for sending the data. Bits 5-8 of a command word are derived from the output of a four po~itlon switch 704-40.
5his switch receives a flrst constant value via a first po6ition, She contents of a RZN register 704-42 via a second po~ition, a second constant value via a third po3ition and a third constant value via a fourth po~itio~.
~its 1-4 of a command are applied by ~he c~rcuit of block 704-1 to an OR ~ate circuit 704-44 together w~th 15 bits 5-8. The O~ gate 704-~4 al80 receive~ via a ~ADO
~witch 704-46 bi~s 1-8 of an RADO regi~ter 704-48.
The RADO register 704-48 i9 an addre~s and data ou~
register which receives via ~ irst pOB~ tlon of a ~ADO~ ~witch 704-48 ~ logical 5virtual) ad~re~s ~rom 20 addres~ preparation unit 704-3 via the lines A5~0-35 an~
data output ~ignal~ from the EU 714 via llnes ZPESB0-35.
The positions o~ the ~ADOB switch 704-48 ~ u~d~r the - ~ control o`f ~ e FM~D fi~ld for small CU format and the RAVO field in the case of large CU format.
As seen from the Figurs, either the ZZ~1-8 blts or the ZADO bit6 1-8 are applied a~ outputs to the RADO/
~ADO lines as a function of the state of control ~ignal L~ADO-ZADO. Bits O and I are always binary ONES whila bits 10-35 are furnished by the RADO registQr 704-4fi.
For additional infoxmation regarding the remaining sectio~ of proces~or 700 a~ well as the 3sction~ of ~igures 3a through 3e, reference may be made to the copendinq applications refere~oed in the introductory portion of this application.

CAC~; UNIT 750 - FIGVRE 4 .. .. .
neral De~criptlon lrhe cache unit 750 18 divided lnto flve primary nections: a trarl~lt bu~fer and command queue section 750-l~ a cache nection 750-3, a dlrectory and hlt con-trol section 750-5, an in~ruction buffer ~actlon 750-7 -and an instruction counter ~ectlon 750-9.

. The trana~t bll~fer ~nd comman~l qusue d0~tl~n 750-l in-0 clud88 a8 ~or el~ment~ a four word write command buf~r 750-lO0 a3~d a four word tran~lt block bu~fer read co~and buffer 750-102 whlch are addres~sd vla a palr of cowlt~r clrcui'cs 750-lO~ ~d 75û-106 i21 ~ddltion to ~ coram~nd queu~ 750-107 wlth associated in ~nd out nddr~ ps~nt~r and compar~ circuits o~ block~ 750-lOB through 750-llû.
Th~ write bu~fer 7500100 provid~ stor~ge for two wrlte ~ingle or O-~G wxlt~ double co~d whlle the tr~n~lt blo-~
750-102 provide~ storage for up o four read type co~d~.
The tran~1t b1OCk bUf8r 750-102 ~1BO storee lnformatlon a~ociat~d w~th ~uch ~ad co~ nds us~d ln controll$ng th~ wrltlng of fnemor~f d~ a word~ lnto as~lgned ~re~
(i.~., lev~ of c~che ~ectlon 750-3~ The four regi~ter~
allow up to ~our memory rea~ to be in progre~s a~ any g~en tlm~. .
Sect~ orl 7501-l al80 includes ~ control sect~on ~50-112 . Th~ ction includes aets of dif er~nt control c$rcuit~ such as the command decoder ~d control c~ rcuit~
of blocks 75û-113 ~nd 750-114 j the lnterf2ce contxol cir-CUit8 of blocks 750-115 and 750~ and hold control circuits o~ block 750-117.

The circuits, of blocks 750~113 and 750-114 decode the signals applied to the PMEM lines representative of commands transferred by processor 700 via the RADO/ZADO lines of interface 60~ and generate the control signals for making entries in the command ~ueue 75Q-107, incrementing and setting values into the in pointer and out pointer circuits of blocks 750-108 and 750-109.
Also~ the circuits generate control signalS for storing commands into either write buffer 750-100 or transit block ~uffer 75Q-102.
The interface control circuits of blocks 750-115 and 750-11~
generate signals for controlling the transfer of data signals received from SIU 100 into section 750-7 and for commands including the transfer of such commands to the SIU respectivelyO The hold circuits of block 750-117 which receive signals from decoder circuit 750-113 generate control signals for holding the execution of commands in appropriate situations ~e.g. directory section busy) and controlling the loading of data into section 750-7.
As seen from Figure 2~ the transfer of write command control words proceed from buffer 750-100 via the third position of four position ~ZDTS3 s~itch 750-118, a data register 750-11~ and the first position of two position switch 750-1200 The write data words are transferred from buffer 750-lOO to SIU 100 via a write data register 750-121 and the second position of switch 750~120. The RWRT position of switch 750-120 is selected for one ~write single command) or two (write double command) clock intervals following receipt of a signal from SIU 100 via the ARA line made in response to a signal placed on line AOPR by cache 750 for transfer of the write command.

4~) ,, ~ ~

' ReAd co~nd~ are 'crAns~rr~d ~rom the read co~nd porklon of tr~n~lt bloc~ bu~er 750-102 to ~IU 100 V~A the ~ourth po~ltlon (zT~C) of thn ZDT8 l~wltch 750-118, ragl~tar 750-119 And the fir~t poeltion o~ ~wltch The mul~$port identifier llnes ~ receive zone bit signal~ via a RMITS regi~t0r 750-124 asld a two ps~ition switch 750~1~5 for the second dat~ wo~d ln the ca~e o~ a wr~ double conun~ . A~ ~een from ~he Flg U~ d swi~cs:h recelvss ~lgnal~ from co~nd queuo 750-iO7 ~nd pxoc~s~or 700. 'Th~t is, wh~n caah~ 750 iBllUe~l a r~ad co~nand, ~ran~lt ~lock nu~ber ~l~nals ~rom quoue 750-107 a~e lo~d3~ into blt positlon~ 2 ~nd 3.o~
RM~TS r~ ter 750-1241.
Tho tr~n~lt b~ock ~u3nber ~lgnal~ ~re return~d by SIU 100 on th~ EW~ lin~ with ~he r~d dat~ ~ord.
~he~ ~ign~10 ~r~ loaded into an RMIFS regi-~er 750-127 via ~ multiposltion ~wltch 750-126. Thoroa~!lor, Sh~
- contents of blt ~O~Iit~On8 2 an~ 3 are appllsd vi~ the f~ rst po~ltlon of ~ two po~ition ~wlt h 750-128 to ~
pair of addre~s lnput tonnln~l~ of translt bl~ buffer 750-102. A ~oco~ad a~ reg~st~r 750-129'provid~ por-ary ~torage of the tr~slt block nu~bar ~ign~ls for - ~ultiword tran~f~r~ (i.2., ~uad rea~ comman~O
The outpu~ aig~al3 from switch 750-128 ~re al80 appli~d to the ~onltrol l~put ter~ninal~ of ~ ~our po~ltion ZqBA ~wltch 750-130 for ~electlalg th~ ~ppropr~ 2d~r~
~lgn31~ to bo applioa to cache s~tlon 750-3 ~r storage of khe d~lta words. ~he addrsss content~ oP thQ trzm~lt blo¢k buffer 750-102 ~xe Al~o ~pplled to or~e sat of ~n put terminale of ~ pr~dete~n~d one of ~ group of compare ~r clrcuit~ 750-132 through 750-135 ~or comparl- -son w~th th~ ~ddres~ portion of ~ ncxt comm~nd appll~d ~_ ._ . .

to a sesond 3et of input texminal3 of the co~p ~ ~r circuit~ via the RADO/ZADO line~. Th~ result of the compari~on~ generated by a N~ND gat~ 750-136 la ~ppliad ~J ~o the hold control circuits of block 750-117~
As ~een from Fiqure 4, the zone bit signal~ of the ZAC comm~nd applied to the ZADOB lines 5-8, in the ca~e of ,~ write single command,or for the even word of a write double command, ar~ loaded into a RZONE regi~ter 750-140 when the write command i~ l~aded into write command da~a buffer 750-100. The output of RZO~E re~i~ter 750-140 i appli~d to the first po61tion of a two position ZONE
switch 750-144. The zone bit signal~ 7~2æ~ applied to the lines DZD0-3 by proce~sor 700 for the odd word of a write double comman~ are loaded into a ~DZD reglster 750-142. The ouSput of RDZD reglst~r 750-142 is applied to the ~econd po~ition of ZONE switch 750-144. Tha out- -put signals ZONE0-3 are applied to the circuits of ~ection 750-9 ~or controlling the writing of proces~or d~ta into cache 750-300 as explained herain.

.. ..

4~) Cache Sec~ion 750-3 The ~ectio~ 750-3 includ~s a cnche ~tore 750-300 having 8192 ~8K) 36-bit word loca~ions orgAnized into 128 a~ts of eight, eight word blocks. ~he unit 750-300 is con~tructed Prom bipolar random acc~s memory chips, conventional in design.
The cache storage unit 750-300 i~ addresAed by a 10-bit address RADR 24-33 applied via any one of a ~umber o~ ~ X 4 cro~sbar ~witche~ ~e.g. 750-302a), conventional in desiqn and the addres~ regi~ters assoclated therewith.
R3 ~een from th~ Fiyure, the crossbar switch r~eivea addr~ss ~lgn~ls rom ~ev~ral 80urc~8 wh~cll include sec tion 750-5, ZTBA ~witch 750-130 and ~ectlon 750-7. Ths ~: : addres~ ~ignals appearing at the output of the cros~bar switch ar~ t~mporarily ~tored in the as~ociated addres~
:~ regl~ter and applied ~o the addre~ input te~minals of cache ~torage unit 750-300.
During a write cycle of operation, the four ~ets sf writ~ control sig~al8 ~WRT00100-WRT70100 through WRT03100-73100; ~en~rat~d by ~ection 750-9, are applisd ~ to the cache-storage unit 750-300 and are u~ed to apply : or gate clocking ~ign~16 to the write strobe input termin-al~ of the memoxy chips. Thi3 enable~ from o~e to four byte~ of either a proce~sor 700 d~ta word from the ZADO/RADO lines or a ~emory data word from section 750-7 to be writt~n ~nto the addre~ed o~e of eight levels of cach~ 3torage unit 750-300. For proces~or data, the write slgnal~ ar~ gen~rated by decoding ~ignal~ ZONE0-3 from switch 750~144. For memory data word~, all of th~
zone signals are forced t~ ~inary ONES.

qz The appropriat~ leve1 i~ establi~hed ~y the s~ate~
of sign~l3 ~TBLEV0100-2100 from tran~it bloc~ buffer 750-10~ wh~n wr~ting m2mory data and by the hlt 18vel detected by directory circuits of block 750-512 wh~n wr~ting proce3~0r data. These signal~ are decoded by a decoder circuit 750-303 when enabled by a signal ENBMEMLEV100 from section 750-9.
During a rearl cycle of operation, the 36-bit word of each of the eight block~ (level~) i3 a~plled as ~n 10 ln~ut to a 1 of 8 ZCD switch 750-30h. The ~electlon of the ~ppropriate word is e~ta~1ished by the Bt4te~ of a xet of hit level 8~gnal8 ZCD010-210 gener~ted by 8eCtiQn 750-5. The~ ~ignals are applied to the control input terminals of ZC~ ~witch 750-306.
As seen from the Figure, the ~electad word i~ appl~ed to ~ pair of ~egi~ter3 750-308 and 750-310, a 1 of 8 ZD~ -switch 750-312 and a 1 of 4 ZI~ 3witch 750-314. The RIRA and RIRB reglsters 750-308 and 750-310 apply the~r content~ to different positions of th~ ZIB ~nd ZDI
20 6witche~ 750-312 and 750-314. The ZIB switch 750-31~
lect~ instruction~ which are applled to the instruction ~,' bus (ZIB3 of processor 700 while the ZDI sw1tch 750-312 l. C~ ~ O V\ S
selects data or ~por~nds which are ~pplled to the d~t~
in bus (ZDI) of proces~or 700.
In additlon to applying ~n~truction word signals read out from cache 750-300, the ZI~ switch 750-314 al90 : a~plie~ instruction word signals received from ~ection 750-7 to proce~sor 700. The ZDI ~wi\tch 750-312 al~o applies data slgnal~ rec~i~ed from the ZCDIN ~witch 7sa-30 304 and 3ect~0n 750-7 to processor 700. Th~ states of the control slgnals [ZI~010 110 and [ZDI010-210 applisd q~

Q to the control input terminals of ~wltche~ 750-314 ~nd 750-312 aelect the sources of instruct~ons and data words ~o be tran~rrod to proce~sor 700 by such ~wit~hes.
The control ~lgnal~ ~re generated by the circuits of 5 ~ection 750-9.
In greater det~il, the fZIB010-110 signals are coded to select position ~2 of switch 750-314 for a fir~t instruction tr~nsfer in respon~e to the detection of a directory~hi~ for an I fetch 1 co~mand or a directory 10 hit for an I f~tch 2 command ~ollowing an I fetch 1 co~mand to the la~t word in a ~lock. The control 8ig-nals are coded to ~elect the ~I~A position #1 for ~ub~e-quQnt in~truction tran6fers following a directory hit - g~nera~ed in re~ponse to an I fet~h 1 or I fetch 2 command.
Wh~re t~ I fetch 1 or I fetch 2 command results in a directory mis~ J the [ZIB010~110 signal~ are coded to select po~ition ~3 of ZI~ switch 750-314 for tran~fer of in~truction words received from sectiGn 750-7.
As concern~ the ZDI swit~h 759-312, the ZCD po~ition #1 is select2d in rosponse to the detection of directory hits and ~ignals applied to the ~DIBUF/ZDI lin~ in re-~pon~e to a directory h~t generated for a LDQUAD com~and.
Me~ory data word~ are transferred to processor 700 vla 25 the ZVIN position #3 of the switch 750-312 followlng a directory miss. Following holdln~ proce~sor 700 for - an in~ruction fetch from main memory, the signals lZDI010~210 ar~ coded to se1eGt the ZDIN position of switch 750-312 for tran~fex of the first instruction 30 upon it~ receipt by 6ection 750-7. The remaining in-stxuctions ar~ transPerred via ZIB switch '1S0-314.

. . . . . . .. __ q4 , -,, ~he ZCDIN po~ition #2 of ~wltch 750-312 i6 u~ed -. ~or diagnostic purpo~es to trAnsfer ~iqnals from the Z~D0-~RAD0 llne~. The re~inlng posltions of ZDI
switch 750 312 ~re u~ed for digplay purposs~ (i.e. r 5 positions P~IRB, ZRIB and RIRA). Al~o, poHition RIRB
i~ ~elected to tran~fer data word6 to processor 700 in the case o~ a LDQUAD con~nand when there is a directory ihlt 3~0 ,- ` ~. , , ~ ' , Di~ectorY and ~lt Control Sectlon 750-5 ~ hla ~ectlon lnclude~ an elght level control directory 750-500 and elght level ~et a3soclative addres~ dlrectory 750-502. The ~irectory 750-502 ~8 12B locations, 5 each location contalning a 14-~it as~ociativ~ address for each l~vel. A four position ZDAD 3witch 750-~30 provid~s the random access memory (RAM) addres~es for , addres~lng directories 750-500 and 750-502 in addition to cache storage unit 750-300.
.~i 10 Dur~ ng a direntory ~earch cycle of operation, switch 750-530 under the co~trol of s~gnals S~ZDADC0100-1100 - ganerated by circuit~ within a block 750-526 ~elect~ RADO
po~ltion 0 . Thl~ applies the 14-blt ~ddress siqnals of ZA~ con~nd fro~ line~ RADO 24-33 from procofi~or 700 to 15 the ou~ut.4erminal~ of the ZDAD ~wltch 750-530. Ths~e Elignals are applied to th~ ~ddre~ lnput t~rmln~l~ of directories 750-500 and 750-502. During ~e s~arch cyol9, the contents o~ elght block/level ~ddres~ are rend out and applied a~ one ~nput of each of a group of e~ght ~: 20 comparator circu~t~ 750-536 through 750-543O Each co~para-to~ circult co~par~ lts ~lock/l~vol ~dd~eas with bit~
10-23 of the ZAC co~and to deter~lne ~ hit or mis~ con-dition. The results ~enerated by the c~rcu~t~ 750-536 throuyh 750-543 are appli~d to corre~pondln~ inpu~s of a 25 group of AND g2te3 750-545 through 750-55~. ~ach co~pAra-tor Gircu~t i8 made up of ~our ssetion~, the rQ~ul 8 of - whiah ar~ combln~d ~n one of th~ AN~ gate~ 750-545 throuyh : 750-$52. The final r~ult h~t signal~ Z~0100 through : ZHT7100 are applIed a~ lnputs to hit/miss network circuits 30 of block 750-512 a~ explained h~rein.
The ZAC addre~ ~lgn~ are al00 sav~d in an RDAD
regl~tsr 750-532 whon no ~ condltion t~ detected 'lb ,, (i . e., signal lHOLD-DMEM fxom 750-112 is a blnary ZERO) .
During the directory ass$gnment cycle following the searc:h cycle which detec~d a mls~ condition, signals SELZDADC01û0-100 select RDAD po~itlon 1 of ZDAD ~witch 750-530. Also, a RDRIN register 7S0-534 is loaded with thc 14-bit a~socia~ive address signals Erom the ZADO-B
lines 10 23 whe~ the directory search cycle ia completed for writing into the directory 750-502.
The con~rol directory 750-500 also includes 128 location~, each having a predetermined number of bit position~ for ~toring control i~formation. Such informa-tion includes the ~ull-empty (F~E) bits for the eight levels and a round ro~in (RR) count bits in addition to parity check bits (not shown~O ~
The full-empty bit~ indicate whether the particular directory addresse~ have any significance (i.e., are validJ. For a c~che hit to occur, the F/E bit must be set to a ~inary ON~. A binary ZERO indicates the pre-sence of an empty block or portion thereof. The round robin bit~ provide a count which indicates which block was replaced la~t. This count when read out vla one of th¢ two set~ of ~ND gate6 of block 750-504 into a regis-- ter 750-50~ i8 normally incremented by one by an incre-: ~ent adder circuit 750-508. The re~ulting s~gnals NXTRR0-RR2 are written into directory 750-500 to identify .
the next ~lock to ~e replaced.
As ~een from the Figur~, the F/~ bit contents of the location are read o~ via the positions of a two position ZEER selector ~witch 750-50~ and appli~d as inputs to ths directc ry hit/mi~ ~nd hit control cir-cuits of block 750-512. The ZF2R switch 750-506 ~elects 9-'1 ' which half of a group of ~/E blts are to be u~ed by th~
circuit~ of block 750-512 for a hit/miaa lndicatlon and which h~lf of the group of F/E blt~ are to be us~d by ~uch clrcuit~ for an alternate hit determlnatlon. An address bit signal ZDAD31 controls the selection of switch posltions.
The circuits of block 750-510 include a multi-section multiplexer circuit which yenerate3 the output signals FEDA~0100 and FEDATllO0 as a function of the hit and miss data pattexn. Accordingly, these signal~ are ~et in re~pon~e to the ALTHIT signal from the circuits of block 750-512. A pair of d~coder circuits 750-520 and 750-521 operate to decode th~ level information signal~
ZLEiV0100-~100 for generating appropriate sets of write e~able strobe ~ignals R/WFE:010-21û and R/~LV010-710 for control dlrec~ory 750-S00 and addres~ dlrectory 750-502.
Thus, level (ZLEV) 3witch 750-522 operate~ to control the level at which P/E bit~ are set or re~et and the level in the addres~ directory 750-502 at whlch new addre~es are written ~ff`a directory a~ignm~nt cycle of o~eration.
A~ seen from the Figure, the first po3itlon D~
ZL~V ~witch 750-522 when ~elected, applies to it~ output terminalq signals OLDR~010-210 from directory 750-500.
The second po~ition of swi~ch 750-522 when ~elected applies to i~s output terminals signals ~LEVR0-R2 from a level regi~er 750-524. The level register 750-524 i~
u~ed to ~ave the last ~et of hit level ~iqnal~ ganerated ~ 3~
1'6 by the hit/mi~s level network circuit~ of block -~
750-512. Thia permit~ the hit level value to distri-bute to other ~ect$ons o~ cache 750 for sub~equent u~e (i.e., ~lgnals RHIT~V0-2).
The third po~ition of switch 750-522 when selec ed applies to ita output terminals, slgnals LEVR0-R2 generated by the circuits of block 750-512. The ~witch 7S0-522 i6 controlled by ~ignals from control flip-flops included within block 750-526 (i.e., signals FBYPCAC and DIR~USY). Ag seen from khe Figure, the complements of the level signal~ stored in register 750-524 correspo~ding to si~nals RHITLEV010-210 are applied via a group of AND
gates to control circuits within section 750-9.
: During the ~earch cycle of operatio~, the hit/mlss level network circuits detect which level, if any, con-tains an ~ddr2s3 which matche~ the ZAC address. In the case of a match, ~t f~rce~ signal RAWHIT100 to a binary O~E and generate~ ther~from the ~et~ of hit 1eYÇ1 signals ZCD010-210 and HITLEVC7010-7210 throu~h ~n encoding cir-cuit. The signal~ are generated in accordancQ with thestates of the F/E bit signals ZF~010-710. That i~, for~
a cacha hit to occur at a given 1 vel, the F/E bit must be a binary ONE. A~ m~ntioned aboYe, a binaxy ZERO indi-cate~ the presence of an emp~y bloc~ level. Each encoder circuit includ~ AND~OR gating circuit~, conv~n~ional in design which generate ~he level aignal~ in accordance wi~h the Boslean expxe~sion L i = e~0 l~E o ZHTj~ZFE;.
Addi~ionally, the signal~ ZCD010-210 o may be generated from the level signals Z~ICLEV000-2100 provided by sec-30 tion 750-9 during in3truction f~tches.

q~

The b1OCk 750-512 a1~O inC1Ude~ an a1ternate hi~ -netWOr~ WhiCh Can a1SO be U~ed ~n the aS8~gnmQnt Of an eight word block by generating an ~lternate hit 3ignal ALTHIT100 and a ~et of signals A~T~ITLEV0100-2100 for loading into regiater 750-504 in place of the round robin as~ignm~nt signals C7RR0100-2100. For the purpose of the ~resent invention, such arrangements can be considered conventional in design. Reference may be made to U. S.
Pa~ent No. 3,820.078 listed in the introductory portion of thi~ ~ppllcation.
A~ ~een ~rom the Figure, the clrcuits of block 750-512 Yenera e Other hit 8igna1~ HITTOTB100, ~ITTOC7100 and HITTOIC100. The8e Signa15 are deriVed ~rOm ~igna1 RAW~ITl00 in aCCOrdanC~ With he fO11OWing BOO1~an eXPre~iOnS:
1. HITTOC7100 ~ ~WHIT100-BYPCAC000.
2. HIT~OIC100 S HITTOC7100.
3. ~ITTOT~100 ~ RAWHITl00-~YPCAC000~PR~RDl00-BYPCACl00.
The circuits of block 750-512 reCeiVe the c~che 20 bYPa~8 Bigna1~ BYPCAC000 and BYPCAC100 frOm b1OCk 750-526.
AB mentloned, this block includes a number of control ~tate fiip-flop~ which generat~ signal0 fvr ~equonclng the section 750-5 thro~h various required operation~ for : the proce~sing of the variou~ type~ of command~.
25 Additionally, block 750-512 includes lsglc circuit~
for generating required Gontrol slgnals during such operation~. For the purpose o f the present invention, these circuit~ m~y ~e lmælemented in ~ conventional manner. Therefore, in order to ~impli~y th~ descrip~ion herein, only a ~rief de~cription and the Boolean expr~-~ions will be given for certain control ~tate flip-flops and control logic clrcuit~ as reyll~red for ~n under~tnnd-ing of the operation of the pre~ent invention.

4~
... .
IC~
~6-.~ , , ~ ~ 5~L g ~ ~ ~
, The FJAMl flip-flop is ~et in respon~e to a hit condition a~ the end of a directory search cycle for a r~ad double command. The flip-flop hold~ the lower addres~ bits in register(~) 750-32 enablin~ the acce~sing of the second word from cache storage unit 750-300 in the case of a r~ad double command. Also, the flip-flop is set ln re~ponse ~o a write single command to cau~e the ~election of the RD~D po~ition of th~ zDAn switch 750-530 for providing or causing th~ same addr~s3 to be appl~cd to cache storage unit 750-500 for one more clock interval or cycle. In th~ ab~ence of a hold cond~tion (~ignal ` [HOLDDMEM~l), the FJAMl flip-flop remains ~t ~or one cycle in accordance wikh the following ~oolean expre~sion:
SE~FJAMl~REQco~B-~wHIT-~yF~E.~RDDBL+wRTsNG)+
nZ~lR~E~q~F~AM2+HOLDDMEM-FJAMl.
The FJ~M2 flip-flop i~ ~et in re~pon~e to a hit condition at the end of a dlrectory search cycle for a write double conanand. Th~ ~etting of the F3~M2 fllp-flop causes the ~etting of the FJAMl ~lip-flop at the end of.
the next clock interval. The control ~tate of the ~J~M2 flip-flop og0thor with the FJAMl flip-flop cause~ the selection of the RDAD PO~itiOn of ZDA~ switch 750-530 for provlding the proper addre~ for wrltlng data ~5 into cach~ ~toraqe unit 750-300.
Thc FJAM2 flip-flop al~o remain~ 69t for one cy~le in accoxdance with the following Boolean expre~ion:
: SET-P~M2~REQCO~O-RAWH IT ~F~ W~TDBL+HOLDDMEM-FJAM2.

-IC>I ' A flip-flop NRMPTCl directly ~Dntrol~ the ZDAD
~witch 750-530 and ~8 ~et in accordance with the states of signals gen~rated by the other control ~tate flip-flop~. ;
The NRMPTCl 1ip-flop normally remains set for o~le cycle in accordance with the following Boolean expression:
SET=NRMPTCl' ~WRTl)13L Rk;QCOMBO RAW~IT ~) FJAM2~SE~FJAMl~R~QCOMBo ~RDTYPE-~YPCAC+RDTYP~RAWHIT)~ h1r~ +
H~L-D) The FDIRASN flip-flop specifies a direc~ory asslgn-ment cycle of operation wherein'associatlve addre6s entry i8 wr~tten into address directory 750-500 in the case of mi~s condition~ or ca~he bypass operations for read type command3.
: The FDIRASN flip-flop is 9et for one cycle in accordance with the following Boolean expre~slon:
SET~l~D~RASN~R~QCOMBO-RDTYP~BYPCAC~ )o ~0 Th~ FICENA~ flip-flop enables the loading of the instruction regLster and i~ set ~or one cycle in re3ponfie to a 1/2 T clock pulse in accordance with the following ~oolean exprss~ion.
SET - FHTl~O.
The FRCIC flip-flop is set for one cycle in ra~ponse to a 1/2 T clock pulse in accordance w~th the following ~oolean expre~sion.
SET ~ FJAMZNIC~EV.

, __ _ .. ...

~oz r CONTROL LOGIC ~I~,NALS

1. Th0 ~THIT slgna~ indic~e0 th~ presenc~ of ~- 9. c- -~ O
-p8~ hlt condition.
AL.T~IT~ALTLE3VO+ALTLEVl+ . . . ALTI,EV7 .

2. The signals ALTHITLEV9, ALTHITLEVl and ALT~ITLEV2 provide a thr~ bit code which ~pecifies the l~vel at which a-~*~ hit cond~tion occurred. The sig-nals are coded ~8 ~ollows:
a. ALTHITL~V0-ALTLEV4~ALTLEV5~AL~L~V6+ALTL~V7.
: 19 b. AL~IT~EVl-AL~EV2~ALTL~V3~ALTLEY~ALTLEV7.
c. ~LTHI~EV2~ALTL~Vl+ALTLEV3~ALTLEY5+ALT~Y7.

3. ~he ~lgnal~ ~TL~V0 through ALTLEV7 indica~e which one o~ th~ ~ight lev~ls,if any, ha~ do~ct~d a ~ hit condltion.
a. ALT~EV0~Z~T0-~

: - .
b. A~'rJiE3V7=Z~lT7 ~iF7, .
4, ~he DIRADDE ~ignal i8 an enablinq siqnal for de-coder 750-521 which allow~ the generat~on of wrlte strobe signals applied to addr~s directory ~50-500.
~IRADDE~ FDr~AsN.

5. ~he DIRBUSY signal indicates when the directorie~
: 750-500 aAd 750-502 ar~ busy.
DI~USY~FLSH~FJA~2+~JA~ DIRASN.

.

3~(~

~ .
6. ~he FEDCODE ~ignal i~ an ena~ling ~ignAl for decoder 750-520 which~allow~ ~he generation of write strobe ~ignals applied to control directory 750-500.
FEDCODE-E~DIRASN-NO~

5 7. The E~RCEBYP signal ena~le~ a cache bypas~ operation to take place.
FORCEBYP=FSKIPRR+FBYPCAC .

~. The GS~CH signal indicate~ wh~n a search cycle of : operatlon i~ to take place.
GSRC~DD~iI.ZCDg - ~~

9. Th8 signal8 HI~LEVC7~, ~ITLEVC71 and HITLEVC72~provid2 a 3-bi .csde which ~pecifie~ the 18v91 a~ h h~t condition bas occurred.
a. HITLEVC70-~ITLEV4+~ITL~V5+~ITLEV6+HITLEV7.
b. }lI~LEVC71~HITL~V2~HITLEV3~HITLEV6+~I~L~V7.
c. HITLEVC72~HITLEVl~HITLEV3~liITLEV5~ITLEV7.

~;: 10. ~he siqnal 11ITLEv0 through HITLEV7 indicat~ whi~h one of the eight level~, if any, has detec~ed a h~t condition.
a. HITLEV0~ZFE0-ZHT0.:
.

b. HITIAEV7= ZFE7 ZHT7 .

,. . .

'~4 r 11. The RAWHIT signal indicates the det¢c lon of a hit condition .
; RAW}~IT~IITLEV0~ . . .+HITLEV7 .
:
12. The BITTOC7 and HITTOIC signals each indicates the detection of a hit condition to certain circuits within ~ection 750-9.
~1 ITTOC:7~=H IT~roI C= RAWII I T ~ BYPCA~ .

13. The ilITTOT~ signal indicates the detection of a hit condition or a pre-read collunand when in the bypass mode to the tran~it block buf fer ci rcuit~ .
l~ITTorr~3-RAwl~IT ~+PRERD BYPCAC .
: .
:-~ 14. The LDRAD ~ignal en~ble~ the loading of the RDAD
regi~ter 750-532.
LDRDAD~ii~.

15 15. . The LDRDRIN 6ignal enables the loading of ~DRIN
register 750-534.
- LD~DRIN~sFD~RASN.
~ .

16. The signal I~DD~LZCD~ is used to enable the %CD
switch 750-3~6 in the case of a read double comm~nd.
IIDDBLZCDE~FICE~NAB- ~FDIRASN~FJAMl~FJ~M2) .

17. The REQCOMBO signal indicates the presence of a cache reque6t.
REQCOM~O~N~S- ~iOLDDMEM 1 ~iZI~- DREQCAC .

' ~ ., . . _ _ . . .

', 1-`'`` 11~1040

18. Th~ ZCD0, ZCDl and ZCD2 ~ign~l~ are us~d to control J~ ~he operation of th~ ZCD ~witch 750-306.
a. Z~D~-ZCDL4+ZCDL5+ZCDL6+ZC~L7+ZNICLEV0-ZCDICEN~B+RDD~LLO.
¦ 5 b. ZCDl~ZCDL2+ZCDL3+ZCDL6+ZCD17+ZNICLEVl ZCDICENA~+RDDBLLl.
c. ZCD2~ZCDLl+ZCDL3+ZCDL5+ZCDL7+ZNICLEVZ-ZC~ICE~AB~RDDBLL2 wher~in ~he ~r~ ZCDLi is 2CD~EUi,

19. The Z~EDATWTl ~ignal i8 a d~ta write strobe ~iqnal used ~or wr~ting F/E blt signals FEDA~OlO0 and FEDATllO0 ~nto directory 750-500.
ZPE~A~WTl~FDIRASN-ZDAD3l.

?. Th~ F~DATOlO0 8ignal corresponds to the ~lrs full/
lS empty bit.
PEDATOlOO~BYPCACOOO+FALT~I~lO0.

21. The ~ED~llO0 ~ignal corre~pond~ to the second full/e~pty bit.
F~DATllOO~FALTHITlOO~FBYPCAC000.
~:

20 22. The SEL~DADCl signal controls the operation of the ZDAI~ switch 750~530.
' ' Sl~:LZDADCl~NRl!~PrCl .

23. Th~ RWAR signal i~ a round robin writ~ ~ignal used for wrlting the RR blt signAls b~ck ~nto directory -~ 25 750 500.
- RWRR ~ FDI~ASN-N~ ~ .

1~2~
~ ' .
It wlll be ~een from the Fiqure ~hat the dlff~r~nt . decoded command ~ignal~ are generated by a deco~or cir- -~
- cuit 150-528 in response to the ~lgnals applled to t~e DMEM lines 0-3 by proce~sor 700. The decoder 750-528 is enabled by a signal from the DREQCAC line. ~he decoded command signals (¢.g. WRTDB~, WRTSNG, PRERD, ~DTYPE) together with other control signals such a~ [~O~DDMEM, FSKIPRR00 ~nd tho~e from the line3 [CANCELC and ~YPCAC
are appli~d a~ inputs to th0 circuits of block 750-526. . -.
:

.
~` ' .

' - ' .

.

~ 3~ ---103~
~ .
Instru~tion ~uffer Section 750-7 .~_ Thi~ ~ection receives meniory da~a and in~tructlon~
from the DFS line~ which are transferred to processor 700 via the ~ I switch 750-312 and ZIB switch 750-314 respectlvely. The memory ~ignals are loaded into an RDFS ragister 7S0-702 via one po~ltion of a two po-~ition switch 750-700.
Memory data fetched as a result of a mi~s oondition .~ upon receipt'applied to the ZDI switch 750-312 via the `~ 10 nDFs po~ltion #0 of a 1 of 4 pofiition (ZDIN) ~witch 750-708. In the ca~e of a load quad command, memoxy data is loaded in~o the 4 loc~tion (LQBUF) buffer 750-706 when the [I~QBUF signal 18 orced to a binary logical ONE. The write/read address ~iqnal6 [WRTBUF010-llO/[RD~U~OlO-llO from section 750-112 control the writ-~: ing and reading of data into and from the location6 of :: bu~far 750-706.
The memory d~t~ stored in the LQ~UF buf~er 750-706 is then ~ransferred to th¢ ZDI via the RLQBUF pos~tion #2 of the ZDIN switch 750-708.
In the case of a read double command, tha even word of the pair is tran~ferred into a REVN registex 750-710. ~hereafter, the even word 1~ tran~ferred to the ZDI Awitch 750-312 via po~ition #1 of ZD~N awltah 750-?08 for execution of a read double odd command reque3t or upon receipt of a RD~LVEN slgnal from proc~ssor 700.

~ f~

~ ,, As seen from the Figur~, each memory data word i~
also loaded into th~ RDFS~ register 750-71~ and there-a~ter written into c~che ~torage unit 750-300 vla the ZCDII~ switch 750-304 at the l~vel ~pecified by the con-tents of the RADR register 750-32.
In the case of in~truction tran~fer_, each instruc- - -~ion received from memory i9 loaded into one of the 4 storage locations of a 3pecified one ~I~UFl/IBUF2) of a pair of instruction buffers 750-715 and 750-717. The I~UFl and IBUF2 buffers 750-715 and 750-717 are uqed to buffer up to two Pour word block-q that can be acces~ed from memory in response to I fetch 1 or I fetch 2 commands for which a mis~ condition has been detected.
The in~truction~ are written into the location of o~e of the I~UFl and I~UF2 buffer3 750-71~ ~nd 75~-717 specified ~y signals lWRTBUFO100-llOG und~r ~he coAtr of write ~trob~ signal0 [I~UFl~[~UF2. Raad control signal~ lRD~UFO100-1100 enable th~ read out of such ln-~truction~ for tran~for to proce3~0r 700 whenev~r the IBUFl or IBUF2 locatio~ ~pecified by the signals lZEXTO100-1100 ~ontain8 an ln8truction. The instruction is txansferred to proaessor 700 via positions 1 or 2 of a two position switch 750-7~0 and the ZRIB ~witch poqition of the ZIB ~w~ ch 750-314.
2j The IBUFl and IBUF2 buffer~ 750 715 and 750-717 apply output v lid slqnals IaUFlV100 a~d IBUF2V100 o : I~UFREADY circuit~ of block 750-722. ~hese circuits force I~U~R~Y line to a binary ONE ind~cating that there ~8 at least one instruction in the I buffer being addr33~ed ~current in6truction ~losk)~ As ~een from the F~gure, the I~UF~EADY c~rcuit~ receive input ignal~ le . g.
USE~BRDY, IPETCHRDY) from co~trol circuits within ~ection 750-g.

\ool In~tructlon Counter Sect~on 750-9 .
Thi~ ~ction ~tores cache address ~ignal~ (24-33) for ~: lndicatln~ the next in~tructlon to ~e acaqssed, ln on~
of two lnstru~tion ad~re~s regl~ter~ ~ICA/RICB) 750-900 5 and 750-902. The cache ~ddre~s signal~ 24-33 are loaded into the inHtruction register RICA~RIC~ not being used wh~n an I~TCHl command i~ received from proces~or 700.
The cache addre~ tr~nsferred via the RADO po31tion of ZDAD 8wltch 750-530 and a ZDA~ position #0 of a 4 10 position ZICIN 3witeh 750-904.
Each time proce3~0r 700 acce~ses an instruction, the contents of the in~truction xegi6ter RICA/RICB
read out via one po3~tion of a two position ZIC switch ` 750-906 ~ increm~3n'ced ~y one via 2m increment circuit 15 750-908 . ~he increme~ted contents are returned t~ the instruction reglst~r ~IC~ IC:B vi~ the I~NIC posltion #1 of ~ICIN switch 750-904.
As seen from the Figure, each instructlon register ~tore~ two level field~ for fetching flrst and ~e~ond blocks of in~tructions in re3pon~e to IFETCHl and IF~TCH2 commands. The two pa~ra.of level f~ld ~ignal~
are applied to ths different 3witch po8ition3 of a 4 position cro9~bar ~witch 750-910. The selected level ~ignal~ ZNICLEV0100-2100 appli~d a3 inputs to block 750-512 are used to control the operatlon of ZCD switch750-306 for acce~ing the instructions specif~ed by the in truction regi~ter ~IC~RICB. The level field ~ignal3 corre~pond to ~ignal~ LEVC70100-2100 which ~re generated by the circuit of blo~ 750-512. These 5ig~1s are loaded into on~ of the instruction reg~ 8ter8 followinq a directory ~3i~nment cycle of oPeration.

~ , ', In addition to the level field ~ignals, the RICA
and RIC~ instruct$on addres3 reglsters store other sig-nals used for var~ous control purpo~es which will be di cu3~ed herein to the extent necessary.
The incom~ng cache address signals from the 2DAD
switch 750-530 ~ incremented by one vla another incre-ment circuit 750-912~ The ~ncrem~nted address slgnals~
are loaded into the RICA/RICB lnstruction register via the INC po3ition ~3 of ZICIN switch 750-904. The least ~igni~icant two blt~ 32-33 of th~ cache address provide ~he IBUFl or IBUF2 addre~s ti.z., ~ignal~ ZEXT0100-1100) to r~ad out in~truction bloc~s accessed from memor~.
It will b~ no~ed th~t tha pair o~ lev~l f~sld slg- .
nal~ LEVl ~nd LEV2 ~rom other ou~put3 of sw~tch 750-910 are applled a~ lnputs to a pair of comparator circuits 750-912 and 750~ . The circuit~ 750-912 and 750-914 comp~re th~ level signal~ LEVl and ~EV2~ of th9 current lnstruction bloc~ from swl~ch 750-910 wi~h the ~nput l~vel ~lgnal~ C7RR0100-2100 cor~e~pondin~ to th~ round robin count for the next av~lnblo ~lock. Also, ~he : co~parator circ~it 750-912 receiv~e ~8 input~ mamory level slgnals R~BLEV0100-2100 ~nd ln~t ~ct~on level ~ig-nal~ ZNICLEV0100~-2100 Erom ~witch 750-910 for compfirisoh in addition to level signal~ ZIC0100-~100 for compariso~
25 with signal~ C7RR01~0-2100~ Thc cache addr~s signale are incremented py ~ by an increm~nt circuit 75C-91~ ~nd ap~lied as an input to khe ro~d robin ~kip control cir-CUltB of bloak 750-916. Th~ circuits receive a~ ~nother ~air o~ inputs the lnput cach~ ~ddr~s sign~l~ 24-30 ~rom 30 ZDAD ~witch 750~530 and the c~che address ~lgnals o~ th~
current in~tructlon block ~rom ZIC switch 750-906 for campari~on by o~rcult~ lnclud~d ~h~reln.

The results of the pairs: of cache addres,s signals and level signal comparison are combined within other c~,rcuits, within the round robin skip control circuits of block 750-916. The circuits of block 750-916, in response to decoded signals from a decoder circuit 750 922, generate output control signals which avoid addressing con1icts. For a further discussion of the operation of such circuits, reference may be made to the copending application o Marion ~. Porter, et al titled "Cache Unit Information Replace-~ent Apparatus" referenced in the int~oduction o-f this application.
The output control signals frQm block 750-916 are applied as inputs to the circuits of IC control block 750 9200 Additionally; the control circuits~of block 750-920 receive the results of the decoding of command signals applied to the DME~ lines by the decoder circui~ 750-922 when it is enabled b~ a signal from the DREQCAC lineO These decoded signals together ~ith the other signals from sections 750-1 and 750-5 are applied to block 750-920. The control circuits of block 75Q-~2~ generate address and control signals for sequencing section 750-9 through the required cycles of operation for processing certain types of commands ~eOgO IFETCHls IFETCH2 and LDQUAD
commands).
The block 750-920 includes a number of control state flip-flops and logic circuits for generating the required control signals. For the same reasons mentioned in connection with section 750-5, only a brief description and the Boolean expressions will be given for certain state flip-flops and control circuits.

CONTI~OL STAT~ PLIP-FLO~S
FA~CURLEVl flip-flop deflnea the current level for the RICA/RICB instruction r~gister. Thi~ flip-flop is 3~t and re~et in re~ponse to a T c:lock ti~ng 5 signal in accordance with the Pollowing Boolean ex-pressions. The ~et condltion overrides the re~et condit~on. When FA/FBCURI,EV is a binary ZERO, i~
3elects level 1 and when a binary ONE, 1~ ~elec~ level-2.
10 SET - DEcoDEIFl-F~ HoLDDMEM~ r~ANc~I,c-ZDAD08-ZDADO9-11IT-FACTVRIC100/000 + ZEXTO-ZEXTl-RDIaUF-IIOLDEXECRDIBUF-FA/~CU~LEVOOO~ -C~D~EIS-FACTVRIC100/000-~3 W ~ ~XTO-ZEXTl~FLDQUAD-RDIBUF-~b~b~8~ n~F
FACTVR~ClOOJOOO~N~
R~SET~ DECODEI~ FFraer~-tHO~DD~EM- ~ -FACTVRIClOO~OOG + DECODE~DQUAD- ~ -~ANC~C~F~TVRIC100/000 + ZEXTO-Z~XTl-~ a~SFr~r~ ~A/P~MPh~V100 -FACTVPsIC0U0~100 RDIBUF~ii~o~æi.
The FAcT~rRIc f l ip- f lop 0peri f ie ~ the currently active in~truction xeg~ter RICA/RICB. When th~ flip-flop i~ set to a bin~ry ONE, it ~p~cifies the RICA
regiater aJId when a binary ZERO, lt sp~cifles the ~CB
2~ register. It is set and reset in re~pon~e to a T clc~ck timing pul~e ~i~nal in accordance with the following ~oolean eXpre~uion~.

ll3 ~-- , ~ , , pAcq~RIc ~ FAC~VRIC TGLACTVRIC
wherein ~GLACTV~IC ~ DECODEIFl fii~pOEM. lCAMCEL~-P~PIt9EIS + ENEWIFl NOGO.
FACTVRIC ~ ~Acl~vnIc T~LAC~V~c whereln 5 TG~ACTVP~IC ~ (DECODEIE~l +[HOLDDMEM + [CANCELC +
FFPIMEIS) (ENEWIE'r + NO~O) .
The FCP~lWRTREQ ~lip- ~lop de fines the time during which proces~or data i~ to be written into cache. It i8 set and re~et in reaponse to a T clock ~iming pulse 10 in accordance with 'clhe following Boolearl expres~ion~.
SET o~ (DECODEWRTS~3GI, ~ DECODEWRTD~L) HI~'- tHOLDDMEM
.~.
RESETC FWRT~ OL~H~cPUW~r~X~
The FD~SS flip-~iop defins~ a r~3ad double type 5 mi83 condition and i~ u~ed to selQct the ZDIN po~ition of ZDI awitch 750-312 ~uring the cycle followlng data recovery. It i~ ~et and re~set in response to a T clock tim~ny pulse in accordance: ~ith the following E~oolean - exprea~ions.
20 SET = (DECOD~:RDDHL + DECODERDRMT)~ [HOLDDMEM
I CANC~3~C MISS .
RESET~ FRDMISS .
l'he FEV}~NODD flip-flop specifi0~ which word of the two word pair6 proce~sor 700 is waiting for when a r~3ad single type mis~ conditisn occur~. The flip~flop al~o define~ the order that the d~ta word~ are to bs returned to proce~ or 700 in the case of a read doubla type mi~s co~dition .
~ urther, the flip-~lop i~ used during a read double 30 hit condition to acce~ the ~e~ond data w~rd. It ~ 8 set and re~Qt in respo2ls~ to a T clock timlng pul 3e in as~cordance with the following Boolean expreasion3.

~14 ~lla ~ , ~ , , S~T - (DECODERDSNGL ~ DEC:ODE~Fl.FFPIl~EIS) ~ -~ ANC3E~ ZDADO9 + DECODERDDBI.
`~ ~- 7~- DSZl .
l)ECOl~EJ'~DSNCL ~ DECODEI~
~ ZDAD~9 + DEcoDERDD~ HoLDDM~M-~CA~e3~- DSZl ~ DECODERDRMT-~
lCA~C'l~-~C.
Th~ FFPI~:IS f~ip-flop specifie8 th~t th~ la8t proce~or ~tate w~8 an FPIMEIS ~tate which means that 10 the I~l co~and on the DMEM line~ i9 a requ~t for additional ~IS descriptor~. Thi~ 1ip-flop i~ ~et and - reset in re~pon~ to a T clock pulse in accordanc~ wi~h the follswiny ~o~lean expres~ions.
Sl~T - FPIltEIS .
15 ~SE'l'= D~CODEIPl.~.l~.
The FHOLDIE'l ~lip-flop de~lnes when proc2ssor 700 i~ being held becau~e of an IFl mlss condltion ~o that when the in~truction ~8 received from memory, the current is~struction reg~ter RICA/RICB ca~s b~ updat~d by 20 the FDATAR~5COV flip-~lop. The flip-flop ~ 8 set and re-set in response to a T clock pulae in ac:cordance with the following: E3Oolean expre~ion~.
SET ~ Dl~CODE:IFl- IFPIMEIS ~ C~LC-~I8S .
RESET- FNEWIFl NIOGO + Fl)ATARE:t:OV.
~5: l'he FI~i~lRDY ~lip-flop is used to inh~bit the ~ign~l-- ~ ing of an I~UFRDY eondition 'co proc~s~sr 70G when a con~lict oc~urs b0~we~n the instruction ~IC31 lev~l and ~: sne3nory ds~a l~v~l at the t~m~ proce~or 700 took th~
in3truction loaded into RI~A~R~R~ from cache. It iB ~e 30 in response to a T alock pulse arld is re~et un~ondition-- ally on the next T clos~k pu13~ when no ~t conditlon i~
~: pre~ent. It i~ ~et i~ accord~nce with the following ~oolean expxe~iQn.

' ... . . .......

SET = SETIRTERMREADIBUFO ~IOLDDMEMNOGO
~Yherein SETIRTERM = CMPDATAICLEV + MEMWRTRE~-(ZEXTOZEXT1IF2~CANCELCMD ~
DECODEIF1.FFPIMEIS ~ FINHRDY)O
RESET = SET.
~he FJAMZNICLEV flip-flop is used to force the level signals ZNICLEVO00--2100 of the next instruction to be applied to the control input terminals of ZCD switch 750-306 (i.eJ, signals ZCD010-210) following an IF1 command which did not specify the last word in the block. The flip-flop is set in response to a T clock pulse in ac-cordance with the following Boolean expression. It is reset on the occurrence of the next T clock pulse.
SET = DECODEIFl.FFPIMEIS.HIT~ OLDD~E~o¦CANCELC -- -~CANCELC (ZDAD08ZDADO9)O
The FNEWIF1 flip~flop defines the cycle after an IFl command is received from processor 700. It is set for one cycle in response to a T clock pulse in accord-ance with the following Boolean expressionO
2Q SF.T = DECODEIF1-FFPIMEIS- ~OLDDMEM-tCANCELC.
The FRDIBUF flip-flop is used to specify that a signal on the RDIBUF line was received from processor 700 during the last cycle of operation. It is set in accordance with the following Boolean expressionO It is reset during the next cycle in the absence of a set condition.
SET = RDIBUF~HOLDEXECRDIBUF.NOGOO

,~

11~

The P~D~ISS flip-flop i~ u~ed to c~use ths holding of proce~sor 70D upon detecting a mi88 condition for any read type com~and. It i8 set and re~et in re~ponse to a T elock pul~e ~ A accordance with the following 5 soolean expresaiona.
S~ll ~ tDECODERDSNGL + ~DECODEIFl~ + DECODERDRMT
DECODE~I.R + DECODEP<D~
~ CAN~EL~ MI SS .
R~:SETz FDRTARECOV ~ WI Fl NOGO .
~he ~RDREQ 1ip-flop define~ when the ~econd word ~etched in re~pon~e to a RDDB~ command for a hit condi-tion iY to ~e read out fr~m cache. It i~ 8et and reset in re~pon e to a T clock pul~ in accordance with the following soolean expr.e~siona.
15 SET = D~COD~R~DBL:-~lIT-nT~ q~5-~~ESET~ ~3ÇiSÆ~.
The F~ATARECOV flip-flop inhibits the inerementing o the in-~txuction regi3ter RICA~RICB when the IFl command i~ to the last word in the blocX and the IF2 cs)mma~d i8 20 cancelled. It i~ set ~d re~et in re~ponse to a T clock pulse in accordance with the follswlng ~oolean sxpre~sions:
SE~ = DATARECOV~ ASTINST- lHOI.~DMEM. lCANCELC ~ D~l~RECOV
~ FLASTINS~ ~ ~CANCELC ~ DATARECOV .
~.
25 RESET- ~HOLDDMEM- FDAT~RECOV.

~11 CON'rROL LOGIC SIGN~S
1. The FA/FBL~;VlVAL signal i~ used to ~efine the state of a ~ix~ valld bi~ po~i~ion of the RICA/RICB in-Rtruction register. It i8 ~et and reset on a T
cloclc pul~e in acs-ordance with the following Boolean expxes~ions. The re~et condltlon overrides the set condition .
a . FA/FBLEVlVALSET ~ DECODEIFl ~
lCANOELC FACTVRIC100/000 ~ DECODE:IFl FP'PIMEIS ~- ~i~l~-OE~- FACTVRIC000/100 + DE:CODELDQUAO
lii~ ~ PACTVRIC100/
`~ 00,0.
b. FA/FBLE:V;rV~ ;ET - DECODEIFl FFPIMEIS ~-1CANCELC~HIT- ZDADOB ~ ZDADO9 FAC~ IC100/000 ~ UZ:XTO~ ZEXTl-~- DE:CODX~)U~D ~DQV~D -RDIEIU~. ~. FAC~C000/
- ~,90FA/~CMP~V00~~5 + Z2~XT0 2 0 ZEXTl ~ FL~2U~D RDIBUE' ~
FACl~RICl00/000 ~.
wherein RICA ~S F~iC~C = l and ~ICa 3 ~CqVRIS~
2. rrhe ~A/F~L~V2VAL. signal i~ u~ed to dofln~ th~ ~tat~
of a ~econd valid blt positlon of the RICA/RICB ln-2S struction register. It 1~ set and x~s~t on a T clock pul~e in acc~xda~e with th~ following l3Ool~san - ~xpre~ion~.
a. ~A/FBL~:Y2V~ET ~ D~3co~EIF2.
FAGTVRIC:000/100.1~ ~ DECODEIF1 F~P I~æI S .7~h- ~.
FAC~VRIC:000/100 EISIF2 .

4~

, b. FA/~I~LEV2VALRESET - DECODEIFl~
[CANCEI.t:- FAcTvRIclooJooo +
DECODELDQUAD-1H~LDDhEM-~CANCELC
~FACTVRIC100/000 + ZEXT0-ZEXT1-DECODEI~ ECODELDQUAD.F~QUAD-. FA/F~CURIEV-~ACTVRIC000/100 RDIBUF-HOLD~XECRDIBVF~NOGO.
Wherein RICA - FAC~VR~ ~ 1 and RICB ~ FACTVRIC = 1.
3. The [ZIB0 and [ZI~1 8ign~18 CO~trO1 the ZIB 8WitCh fOr tran~er8 Of 1n8trUetiO~ frOm CaChe 750 tO
prOce8~0r:700 Via the ZIB 1ineS.
a. [ZIB0 S IFETCHRDY-FN~WIF1.
: b. [ZIBl = IP~EE~.
~. Th~ [ZDI0, 1ZDI1 and [ZDI2 signals control the ZDI
lS switch.for tran~fers of instruo~ions and data fro~l cache ~50 to proce~or 700 .ria the ZDI line~. Control ~ignal [ZDIO, whlch s:orre~ponds to the most slgnificant bit of the thr~e bit code, can be assigned to be a binary 2J3RO unles~ position~ 4 t~rough 7 are b~ing u~ed for di play purpo~es.
a. lZDIl ~ DATARECOV + FD~IPlISS + RDI!:VEN.
b. 12~I2 ~ 7~- (HITq~IC + FRDREQ) .
- 5 . The [ZICIN0 ~nd [ZIC:INl sl~al8 control the ZICIN
~witch fvr loading addre 8 signals into the RICA and RICB instruction addre3s registers 750-900 ~nd 7~0-902 .
a. tZICIN0 ~ ALTCMD100-FDFN2MT~
~. [ ZICINl ~ PD~ T ~ WIFl t ~DFN~IT.

a~o 6. Tha ignal~ ENAl~lCl ~nd ENABRIC2 are used to enal~le the loaclill-3 ~IC~ and RICB registers.
A~KICl ~ WIFl E'J~MZNICLEy --FD~TARk~OV + FlIOLDIFl DATAR~COV .
b. ENP~B}UC2 =~ FIN~fRDY SE~ R~. DEN2HT
wherein ~Y - DFN2T- [MEMWRT~EQ
~ZEXTOoZS~EXTl-EXECIF2-~ +
~ UEDOI~1 ~ PS~OI~ +
~;~7~
- 7. The ~ignal DATARECOV defines the time that new data has been loaded irats:> the processor ' ~ rag~ ~ter~ ~ . g . RDI or R~IR) and when t:he processor is released. This 8~ g-nal i8 genar~teâ by a f11p-1Op o~ s~ct~on 750-1 which i8 get to a binary OP~E in xesponse to a T clock pul~e uporl detecting 2In ident~cal comparl son between the addre~ ~ignala spec~ying ~he word request~d to be acc~s~d by procesaor 700 ~nd signals indicating the ~ord being transf~rred lto ca~:he unit 75û. The compari~on indicat~ that signals DATA, MIFS2, MIFS3, MIFSl and DATAODD are :Ldentical to signal3 FEiT, F~rûLDTBO, F~iOLD~Bl, RADR32 and DOUBLEODO r~sp~ti~rely wherein signal FHOLDTB0 - FRDMISS-LDTBV~LID-~i FTE~PTR0:
r~ignal FHOL~TBl 3 FRDMISS-LDTBVALII) m~ FT13PTRl;
l DOUBLEOD~ FEVE~aoDD - FDPFS; arld sign~l DA~A = FARDA ~ FDPFS.

DETAILEC~ DESC:RIPTION OF SECTION 750-1 Figure 7a shows in greater detall dlfferent onea of the block~ of ~ection 750-1. It wlll be no ed that for the purpose~ of facilit~t~ng under~tandlng of the pre~ent inv0nt~ on, the ~ame reference numbers have ~een u~ed to th~ extent po~sible for corre~pondlng elements ~n Figure 4. In many case~, a ~$ngle block d~picted in Figure 4 includes several grouplngs of circuits for con~rolling the oper~tlon thereof and/or for genera~ing as~ocia~ed control siqnal~. Therefore, som~ block.q with appropr~ ate r~f~rence numbers are in-clu~led a~ part of th~ diff~rent blocks of ~c~lon 750-1.
I~eferring to the P'igure, it 1~ ~een that c~rtaln por~ion of block 750-102 ~re ~hown in great~r detail.
The tran~lt block buffer 750-102 i~ shown a3 includlng a fir~t group of clrcu~ for lceaplng tr~ck of da'ca wor~s rec:eived ~rom msmory in respon~e to a re~sl quad ltype command. Thes~ circuit~ includ~ a ~lux~l~ ty of clockad pair count flip-r~lop~ whlch co~prl0e a four-bit po31tlon regi~ter 750-10200, a multiplexer clrcuit 750-102û2, a plu~ality c>f NAND ~ate~ 750-10204 through 750-10210 ~nd a decod~r circuit 750-10212. It will Ibe. not~d that ~here i~ A p~ir coun1; flip-flop for ~ach tran~it buf far locatlon .
Addi~cionallyt the first group of circults inc:ludes ~ plu~ality of clock~d tran~it blof~k valid flip-flops whla:h ~ompri e a four-blt posi~ion regi~ter 750-10~14, The binary ONE outpu~cs of each of the flip-~lop~ are coIInected ~o a corresE~ ding >ne of the four pair count ~O f 1 ip- flc:~ps a 8 shot~
In respon~e to a r~ad quad con~{land, a flrst pair of words i~ ~ent to cache 753. Thi~ i~ followed by a gap and then the second pair is sent to cache 750. The pair count flip-flop as-sociated with the transit block bufer location being referenced as specified b~ the states of signals: MIFS2110 and MIFS3110 is switched to a binar~ ONE via a first AND gate in resp~nse to T clock signal ~CLKT022 when signal DATAODD100 is forced to a binary ONE by the circuits of block 750-114.
Signal RESETTBV100 is initially a binary ZERO and decoder circuit 750-10212 operates to force one of the fi.rst four output signals SETPC0100 through SETPC3100 in accordance uith the states of the MIFS2110 and ~IFS3110 from- switch 750 128.
The pair count flip-flop i~ held in a binary ONE state via the other input AND gate by a transi~ bloc~ valid signal associated therewith being forced to a binary ONE. The app~priate one of the transit block valid hit flip.flops designated by decoder circuit 750-10601 ~.e., signals INOlC~
through IN3100) is set to a binary O~E via a first AND gate. When switching takes place, increment signal INCTBIN100 is forced to a binary ONE state in response to T clock signal ~CL~r022O
The multiplexer circuit 7S0~102Q2 in accordance with the stat~s ~ the signals DMIFS2100 and DMIFS3100 from switch 750-12~ selects the approp-riate binary ONE out o the four pair count flip-flops to be applied to NAND gate 750-10204. This causes NAND gate 750-10204 to force signal LASTODD100 to a binary ZEROo This results in NAND gate 750-10206 forcing signal LASTDTAODD000 to a binary ONE~ -When the next pair of data uords are received, this causes NAND
gate 750-10206 to foree signal LASTDTAO~D000 to a binary ZERO. This, in turn, causes NAND gate 750-10210 ~ 12Z
~ , tO OrC~ r~t 81~na1 RESETTBVllOO tO O b1n~rY ONE.
Th~ deCOder C1rCU1~ 750-10212 1~ COndit;Oned ~Y 81~7n~1 SET~VlOO tO ~OrOe One Of the ~our output termlnal~ -4 thrOU~h 7 tO ~ b1n~XY ONE. ~hi~, 1n tUrn, r~3~t8 the a~rOPr13te One Of the tr~nB1t b1OCk Va11d b1t f11P-f 10P9 Via th~ Other AND gate . A~ soon ~g the TB Va11d f1iP-f10P reeat8, ~t re~et~ the P~ir COUnt f11P-f1P
a~80Ci~ted th~r~W1th Via it8 O~r A~iD g~te. It Wi11 be aPPXeCiated that ~UCh 8WitChing OCCUr~ ~n re8POn3e tO
T C10Ck 81~a1 1CL~T~22.
As seen from Flgure 7a, the f1r8t group of circul~s oP 13lock 750-102 ~urthex include~ ~ plur~lity of g~te~ 750-10216 through 750~10222, ~nch o whlc~h 1 aonnected ~o rec~ive a dl f f0rent ~ne of th~ bin~Y
ONh~ ou. puta from register 750-10214. ~he bin~ry ONF~
ola~Rut~ ~TI3V0100 ~hxou~h FT~V310û ~r~ also conn~ta~ to th~ Gontrol input t~rmln~l~ o~ the trans1t blook ~Odr~
co~par~tor clrcuita 750-132 throu~h 750-136.
~ h of ~he NAN~ ga~ea 750 10~16 through 750 10222 20 alsc)-a~ conne~s:t~d to recelve ~ di~ferer,t on~ o~ th0 ~ignal~ IN0100 th~ough IN3100 from de~odor clrcult 750-1û601. Th2 output~ f~om 'che~ g~t~ ar~ ~ppll~fl to ~n ~ND qate 750-10224. The ~lgnal~ V~ID000 through VALID3000 are u~ed to indicat~ when ~ tr~n~ t bloc:k r~
25 t~r lc~ on i~ ~vallAble for writlng. That i~, ~hon a selected translt blo~k v~lid blt fl~p-flop i8 ln a ro~t e, A~D g~te 75Q-10224 malntains ~lgn~l YAI,~DIN000 ln a binary ONE at~te.
~he VAI,IDINû00 slg7lal condltion~ ~ ~urther AND~
N~D yate 750-1022b 'co orce ~ control ~$gn~1 lRq~B109 ~o ~ ~in~y ONE durlng ~chc ~e~:ond hal of ~ ~y~l~ o~
opera~iotl (i.e., slynal FHT020 iB 2~ blnary ONE) ln the CR!~e 0~ a read con~and ~i.e., slgnal DR~QR~D100 la a binary ONE) at She time a directory assignment i8 not being made ~ o ~ signal FLDTB~r~LIDooo i8 a binary ONE~.
~ 3een ~rom Flgure 7a, control signal ~RTB100 i~
applied via a driver circuit 750-1022B to a decoder cir-cuit 7~0-10230. The cont.rol signal [RT~110 causes the decoder circuit 750-10230 to force an appropriate one of the output signals [RTB0100 through tRTB3100 designated by the ~tates of ~ignals FT~PTR0100 and FTBP~R1100 applied Yia a pair of driver circuits 750-10232 and 750-10234 to a binary ON~ ~tate. This in turn causes bit position~ 24 31 of one of the transit block re~ister location~ to be loaded w~th addrès~ signals applied via the RADO lines ~4-~1. The comp~ement si~nal [RTB00n i-~
applied a3 an input to ~lock 750-101 for controlling the loadin~ o~ com~and queue 750-107.
A second group of ~ircuit~ of block 750-102 sho~n in greater detail lnclud~s the tra~sit block buffer flag : ~torage ~ection 750-10238 of buffer 750-102. This sect~on as well a~ the ~ec~ion of buff~r 750-102, not shown, i constructed from a 4 X 4 simultaneou~ dual read/write m~mory. ~he memory is a 16-bi~ memory organi~ed as 4 word~ of 4 bits each, only thre~ bits of which are shown. Words may be independently read from any two locations at the ~ame time a~ information i~ being 25 wr~tten into any loc~tion. The signal~ FTBPTR0100 and FTBPTR1100 are appl~ed to th~ wrLte addres~ t~r~lnals while ~h~ read addre~ses ar~ enabled by the VCC si~nal applied to the Gl and G2 tenmi~al~. Tlle Y b~t locations are s~lected ln accordance w~th the ~tAte8 of read address ~ignal~ MIPS3l00 and MIYS2l00 from switch 750-128. The Z bit locations aro seleGted in accordanca wlth the 3tates r ~ 39LV
~24, , of signal~ DMI~3100 and DMIF2100 from sw~.tch 150-12~.
Since theu~ location~ are not pertinent th~y wlll not b~ dLscu~d further herein.
l'he memory may be consldered conventlon~l ln design, 5 for example, it may tak~ the form of the clrcults die-closed in U. S. Patent No. 4 ,070,657 which iY as~igned to the same as~i~nee a~ named herein. Upon th2 recelpt of memory data, the fl~g bit contents of th~ t~ansit ~loc~ loc~tion ~pecified by ~ignal~ MI~S2100 and MI~S3100 ~0 ar~ applied to the Y output terminal~. Thase ~i~nal~ are in turn applied to block~ 750-102, 750-115 and 750-117, a~ shown. During the dlrectory assignment cycle for cache read mi~, the flag b~t posl~ions of the tran~$t block location specifiea by signals FTBPTR0100 an~
15 ~'T~PTRllO0 are loaded with the stgnals FO~CBBYP000, FRDOUAD100 and FLDQUAD100 generated by the circuits of blocks 750-5 a~d 750-114.

:
:~

/2~
, It i~ also seen from Figure 7a that block 750-102 furth~r include~ a gro~p of in~tructlon fstch flag clr-: cuit~ which are aasociated with the operatlon of transit block bu~fer 750-102. The~ clrcuit~ i~clude two se~s of input AND gates 750-10240 through 750-10243 and 750-10250 through 750-10253, a pair o multiplexer ~elector circuits 750-10255 and 750-10256, an IFl and IF2 flag stora~e register 750-10258 and an output multlplexer clrcuit 750-1026G arranged a~ ~hown.
~rhe binary ONE output~ of the indivldual lFl and IE~2 flip-flop~ are connected to corresponding ones of the sets of AND gates 750~10240 through 750-10243 and 750-10250 through 750-10253. ~hese AND gates al~o rec~ive input signal~ from the cixcuits of block 750-106 yenerated in r~spon~e ~o the in pointer ~i~nal-~ FT~PTROOOO
and E'TBPTR1000 us~d for addrss~ing the diffarent register location~ within ~he buf~r 750-102 as mentioned pre-Vi OU5 ly .
Th~ multiplex~r circuit 750-10255 i~ connected to receive a~ a control input, signal ~IFlA~SIGN100 from FIE~lASSIGN fllp-flop 750-11418. Ths multipl~xer c~r-circuit 750-10256 is connected to receive ~8 a control inEJut 6ignal FIF2ASSIGN100 from FIF2ASSIGN flip-flop .
750~141U. This enable~ the setting and~or re~etting of ~5 the IFl and IF2 flip-1Ops of register 750-10258 in raspon~e to the ignal~ FIFlASSI(;N100 and FIF2ASSI~N100.
'I~he ~witching occurs in response to T eloc:k ~ign~l (CL~CT022 during the loading of a transit block register location when a contro.l ~ignal LDTBVALID100 is switched to ~ binary ONE via ar~ AND gat~ 750-11428.
It will be noted 'chat register 750-10258 coTItains an I~l and IF2 flag bit position for ~ach tran~it block regi~ter location. . That 1~, the regi6ter include~

12b ~lip-flops ~IF10, FIP20 through FIF13, FIF23 for tran it block register locat~on~ 0 through 3 respe~ively. Each of ~he bin~ry ONE outputs fro~ the IFl and IF2 flag flip-flop~ are also applled to the different input terminal3 S of ~he output multiplexgr circui~ 750-10260. The circuit 750-11450 contain~ two ~ections. Thi~ permlts DMI~S2100 and DI~IFS3100 si~nRls applied to the control termin~ls of the multiplexer circult 750-10260 from block 750-128 to ~lect a~ output~input signals from both an IFl and lG IF2 flag flip-flop. The selected pair of ignal~, in turn, provide flag slgnals ZIFlFLG100 and ZIF2FLG100 which : ` are applled to block 750-115. The~e ~ignals ~re used to control the writinq of memory information into the IBUPl ~: and I~UF2 buffers 750-715 and 750-717. Addltionally, the complements of the output~ from multlplexer clrcu~t ~50-10260 which correspond to ~ignal8 ZIFLFLGooo And ZIF2FLG000 are applied to a pair of input terminal~ of a multl~ection comparator circuit 750-110/750-11435.
It will b~ noted tha~ the last ~ection o~ each of multiple~er circuits 750-10255 and 750-10256 are connected in serie~ ~or gen~ratlng the enable transit block.
buffer ready ~lgnal ENABTBRDYlQ0 appli~d to bloc~ 750-114. As shown, tAe "0" input termlnal of the l~st ection of mul~iplexer circui~ 750-10255 connec~ to a vsltage 2S VCC ~repr~sentative of a binary ON~) while the "1" lnput t~rminal connects to ground (repre~entative of a b~naxy ZERO). The output term~l o~ the last section of multi-plexer circuit 750-10~55 connects to the "0" lnput ter-mlnal o~ the la~t sectlon of multiplexer circuit 750-3Q 10256 whil~ he ~1" input terminal connect~ to ground.
The mu1t~plexer circuits 750-102$5 and 750-10256 operate ~3--to ore~ eiyn~l ~NA~T~RDYl00 to a bln~ry ONE only after the completlon of an 1n~truction fetch as~lgnm~nt cycle when both siqnals FIFlASSI~100 and FIF2~5SIGN100 ar~
binary Z~OS. Therefore, the "On input terminala are S selected a3 outputs by the multiplexer ci rcuit~ 750-10255 and 750-10256 which result3 in signal ENABTB~DYl00 being ~orced to a binary ONE. This presents the inadvertent generation of the I~UFRDYl00 signal a~ explained herein.

As seen from Figure 7a, the circuits of the transit buffer in pointer block 750-106 includes a clocked two-bit position register 750-10600 and a decoder circuit 750-10601. The register 750-10600 has associated there-~ith a NAND/AND gate 750-10602 and a two input AND/OR
gate 750-10604 connected in a counter arrangement. That is, the NAND gate 750 10602 in response to load signal FLDTB~ALIDlll from block 750-114 and signal NOGO020 forces an increment signal INCTBIN100 to a binary ONE.
This causes the address value stored in register 750-10600 to be incremented b~ oneO The increment signal INCTBIN100 is applied to the circuits of block 750-1020 The most significant high order bit position of register 750-10600 is set to a binary ONE via the gate 750-10604 in response to either signals FTBPTR0100 and FTBPTR1000 or signals FTBPTR1100 and FTBPTR000 being forced to binary ONESo The complemented binary ONE out put signals of the register bit positions corresponding to signals FTBPTR0000 and FTBPTR1000 are decoded by decoder circuit 750-106010 The circuit 750-1061 in response to the FTBPTR0000 and FTBPTR1000 signals farces one of the four pairs of output terminals to a binary ONE.

2 ~

The command control circuit block 750-114 includes an inotruction fetch 2 search (FIF2SEARCH) synchronous D type flip-flop 750-11400. The flip-flop 750-11400 is set to a binary ONE ~tate in response to T clock siqnal [CLXT020 when a two input AND/OR gate 750-11402 and an Ai~D ~ate 750-11404 force a set signal S~TIF2SEARCH-100 to a binary ONE. This o~curs when either an IFl command which is a hit or an IF2 command is received from processor 700 during an IFl a~slgnment cycle.
In the case of an IFl command, this preoumes that there i9 no hold condition (i.e., signal lHOLDDMEM000 from block 750-117 i8 a binary ONE) snd that a directory 4earch generated a hit (i.e., signal HITTOTB100 i8 a binary ONE) indicating ~hat the requested instruction block res~des in cache store 750-300. For an IF2 command, it i8 aosum~d that there has been A directory so~ignm~nt cycle following a directory search in which there was a miss made in re~ponoe to the IFl command ~i.e., signal FIFlASSI~1100 is a binsry ONE).
In either of the ~ituation~ msntloned, the gate 750-11402 forces the signal SETIF2TIME100 to a binary ONE. When the instruction fetch command wao caused by a transfer or branch instruction, which is not a NOGO
(l.e., ~iqnal NOGO030 is a binary ONE) indlcating that it should process tho IF2 command currently being applied to the command lines (i.e., indicated by signal DREQCAC112 being forced to a binsry ONE), AND gate 750-11404 forces signal SETIP2S~ARC~100 to a binary ONE.
This ~wltche~ flip-flop 750-11400 to a binary ONE when sign~l lCANOEL012 ~o a binary O~E.
A~ seen from Figure 7a, the binary ZERO
outpu~ from flip-flop 750-11400 is applied a~ an input to the hold circui ts of block 750-1}7. The siqn~l ~3o .~ , FIF2SEARCH900 is delay~d by a buffer circuit 750-11406 and applied to one $npu~ of an input N~ND gate 750-11408 of an in~truction fetsh 2 asRlgnment (IFI~2ASSIGN) flip-~lop 7~0-11410.
The signal FIF2SEARCH010 together with the ~ignal EI~IF2000 (indicate~ a non-EIS type ins~ruction) cau3es the NAND gate 750-11408 to switch FIF2ASSIGN fllp-flop 750-11410 to a binary ONE in re~ponse to a gating aignal SETB~ALID100 ~nd T clock signal [C~XT020. ~he state of this flop-~lop as the others i8 gated as an output when sign~l FLDTBVALIDlll is a binary ONE.
It will ~e noted ~Aat 61gnal FL~VALIDlll i8 ~witched to a binary ONE via an ~ND gate 750-11412, a clooked flip-~lop 750~ and a d~lay ~uffer circuit 750-il416 15 in the case of a ~i88 condition ~i.e., signal HIT~TB010 i~ a binary ONEI gen~rated in re~ponse to a directory ~earch made for ~ rsad type command (~.g. IF2). Thi~
~88ume8 that ther~ i8 no hold condltion (i.e., slgnal lHOLD~MEM000 $~ a binary ONE), that ln the ca~e of an I~2 command lt wa~ not due to a tr~n~fer NOGO (i.e., signal NOGO020 i~ a binary ONE) and ~h~t there i~ no ~anc~l ' oondition (i.e., ~ignal ~CANCELC010 i~ a binary ONE) ~or - a read ~ype operation decod~d by the clrcult~ of block 750-113 in respon~e to the r~ad com~and applied to the cormmand line~ ~i.e., ~lgnal D~EQ~EAD100 i~ a binary ONE
wherein DREQ~EAD100 ~ READ100-DREnCAC112)~
Under imilar condition~, an in~truction etch 1 a~slgnment (FIFlAS~IGN1 flip-flop 750-11418 is ~wi~ched to a ~inary ONE vla an input ~ND gate 750-11420 in 3~ r~pon~ to an IFl OOmmd~d (i.e~, when ~ign~l IF1100 i~ 8 blnary ONE) in whlch there wa~ a ml~s detected (i.e., ~ignal SETTBVALID10~ bin~ry ONE). The load ~ransit buffer valid ~Ilp-flop 750-11414 remain~ set untll signal S~TLD~VALID100 ~witches to a binary ZER~.

~ l3~
~ ~
rt will be noted that the binary ZER~ output ~ i gna 1 FL~T~YAI.Il)û 09 1~ applied to cl rcul t~ lnclud~d a~
part of block 750-102.
~he other pair of fllp-flop3 sre 750-11422 and 750-11424J8~t in re~poa~se to ~ignal SETLDT~AI.I~100 ln the case of a mi~s conditlon. The load quad fllp-flop 750-11424 i~ se~ to a blnary O~JE ~tate when the colrunand ~pplied to the DMEM comonand line~ i~ decoded as belng a LDQUA~ command (i . e ., 8i gnal LDQUAD100 from decod~r la 750-113 is a binary 0:7E) and that the ZAC command applied to the ZADO~ lines i9 coded as re~quiring a read quad opexati~n (e. g. ~1, IF2, LD~UAD, PRERD and RDSNGLE
collunand~ ~pecified by signal ZAWE~04100 being set to a binary ONE~ .
~he RDQUAl) ~Ellp-flop 750-11422 is ~et to a binary ONE via an AND g~te 750-11426 when 4 ~ignal CQIN1100 from ~he circulta ~ncluded wlthin conunand queue bloc~c 750-107 iB a binary ONE indic~tiv0 of a dou~le preci~isn command (i.e., sisnal ZAD0~02100 i~ a bin~ry ONE).
2n As aeen from lFigur~ 7a, block 750-114 furthex in-- clude~ a comparator circuit 750-114 35 . ~hi~ circult may b~ con~ldar~d converltional in desiqn ~nd, for example, ¦~ may take the form of the circuit~ di~clo~ed ~n U.S.
Pat~nt No. 3,955,177.
~h~ comparator ~lrcuit 750-11435 i8 ~nabl~d by signals USETBRDY100 and DATA100. The ~ignal USE:~8PDY100 n(licate~ tlhat the cache is waiting for in~tructic)n~
from memory to be loaded into the I~UPl or IBUFZ bufers.
The ~ignal D~T~100 1~ forS~ed to a binary ONE by a N~D
gat~ t5û-114~6 tnd~aating receipt of informatlon ~ro3n memory. The cosnpaxa'cor circuit include~ two 6~ctions.
on~ sectlorl ~ompares the command queue input polnter .. .

signalR and outpu. pointer signals from blocks 750-10~ -and 750-109 re~pactlvely~ This ~ection ~orce~ ~ign~l~
CQC~Pl00 and C~BMP000 t~ a bln~ry ONE and bln~y Z~ O
r~pectivaly when the pointo~ la ~re oqual. Tho sectlon corre~ponds to block 750-ll0 ln Flgure 4.
Th~ other ~ection compares input ~ermin211~ Al, A2 and ~ 2, the control signalR [ZRIB100, lZRI~O10 applied to input terminals Al, A2 to the states of the I fetch 1 and I fetch 2 1ag signal~ ZIFlFLG000, ZIF2FLG000 applied ~co t~rm$nal~ Bl, B2. When ~qual, this indicate~ that th~ information being received fxom memory at this tirQe is either in re~ponse to an I etch 1 or I
~etsh 2 eommand. ~t wlll be noted that control signal [Z~IB100 control3 ZRIB switch 750-720.
Th~ inpu terminals A4, A8 compare ~ignals ZEX~0l00, ZEX'l`1100 ag~l~st sig3~al8 MIFS1100 and DATAt:~DDl00 appll~d to the ~4, BB terminals. This lndicates whether the information being ~ddra~ed within the instructlon buffer ~qual~ tha information ~ing received~ More apeclfically, signals ZEXT0100 and ZE~T1100 ~re generat~d ~y tbe cir-CUit8 of block 750-920 from the l~a~t two ~ignlfic~n~ bit addre~R o th~ in~truction stored in the RI~A regi~t~r.
Thus, thay ~pacify the word location being ~ddre~s~d within th~ I buffer. Slgnal MI~S1100 i~ coded to 3-pecify ~5 whether the firqt or ~econd half of the block i8 being recelved. Signal DA~AODD100 spQcifies wh~ther the first or second word of the ~irst two word pairs i8 being re-ceived~ The ~ignal DATAODD100 i~ g~nerated by an ~ND
gate 750-11437, 3V ~tly, the comparator circuit 750-11435 compareA
a ~ignal EN~BTBRDY100 applied to ~erminal A16 fro~
block 750-lQ2 with the voltag~ VCC repre~entative of a bin~ry ON~ appli~d to terminal ~16. In the pre~snce of ,~

a true compari~on between the two s~ts of all 5iX 8ig-nals, the circuit 750-11435 force~ its output to a binary ONE. Thi~ r~sults in the complement output terminal forciny ~ignal IBUFCMæR000 to a binary ZERO, Thls cau8e8 block 750-722 to ~orce ~he IBUFRDY100 signal to a binary ONE as explai~ed herein Additionally, ~ection 750-114 includes an AND
~ate 750-11417. During the fir~t half of a cache cycl~
(i.e., signal FHT120 from delay circuit 750-11810 iB a ~inary ONE) when ~he FLDTBV~ID flip-flop 750-11414 is a b.inary ONE, the AND g~te 750-11417 forces control slgnal (RTB5-8100 to a ~inary ON~. This Yi~nal i8 applied a~ a : clock strobe input to ~he le~el storage sectlon of transit block buffer 750-102. Thi~ ~ection is constructed `~ 15 from a 4 X 4 3imultaneous dual read/wrlte 16-bit memory organized as four words each 4 bit~ in length similar to the memory device of block 750-10238 ~nd ~he memory d~-: vic~s u~ed in constructin~ the 36-bit read command buffer section of block 750-102 as well as the write command/data buffer 750-100.

1:

, r ,. . ~ _ r ~ 4 ~
1~
~ , Figure 7a shows that the data r~ception and control ~loc~ 750-115 include~ a plurality of NAND gates 7~0-11500 through 750-11510 and a plurallty of AND gate~ 750-11511 through 750-11514 connected as shown to generate the control strobe enable signals [LQBUF100, [IBUF1100 and - [I~UF2100, reset buffer signal RESET~UF100 and write con--trol buffer qi~nal [~RTBUF0100. These signais are used to control the operation of the buffer circuits of s~ction 750-7. A~ ~e~n fxom Figure 7a, the other write control buffer signal [WRTBUF1100 is generated by a buffer delay circuit 750 11515 in re3ponse to signal FARDA010.
rl~he signal 1WRTBUFO100 i~ derived from the output of the two input data selector/multiplexer circuit 750-128 ~hich s~l~ct~ e~ther the ~gnal RMIFS1100 from reg~ster 750-127 or slgnal ~MIFSB1100 from register 750-129. The selaction i5 made in accoxdanc~ with the state of signal FARDA000 produced from the accept lin~ ARDA of data ~nterface 600.
Th~ multiplexPr circuit 750 128, in accordance with the state o~ signal ~ARDAOOO, generate~ the two sets of signals MIFS2100, MIF53100 ~nd DMIFS2100, DMlFS3100 which are applied to th~ read address lnputs of ~uffer 750~102.
It will be not~d that ~ection 750-115 also includes a doubl~ pr~cision ~F~PFSX) D type flip-flop 750-11517 which i~ set in reApon~ to clockin~ signal lCLKT020 to ~5 a binary ONE state via a fir~t AND gate input in accord-ance with ~he ~tat~ of the ~ignal PTXDPFS100 appli~d to the AND gaté via amplifler circuit 750-1151B from the ~PFS line by SIU 100. The DP~S llne wh~n 8et indica~eg ~hat two words of data are being s2~nt from SIU 100.
Switching occurs when SIU100 forces the signal PTXARDA100 ap~lied thereto via an amplifier c:ircuit 750-11519 rom ~,~ i.3S

the ARDA line ~f interface 600 to a binary ~1 The AR~A line indicates tha the rPad data reque~ted by cache . 750 is on the DFS line~ from SIU100. ~he output of a ,~ ~F~RDA flip-flop Snot shown) which delay~ ~ignal P~r~DA
;~ 5 by one clock period is applied to a second hold AND
yate input along with signal FDPFSX100. The FDPFSX flip-;~ flop 750-11517 remain~ set for two clock periods. That , the flip-flop 750-11517 is 3e ir ~ccordance with tbe number o SIU ré~po~e~ (DP~S siqnals). In the ca~e of .. ; 10 a read 3ingle co~mand, the SIU generates two SIU re~pons~3, ~ each re~ponse for bringing ln a yair of word3. In each i~S ca~e; thi3 permits the wxiting of the two word~ into -; caehe when ~ignal ~WRCACFLG100 i~ a binary O~E.
The binary ZER~ ou~put of flip-flop 750-11517 i8 lnvert~d by a NAND/AND gate 750-11521 and delayed by a :~ buffer.d~lay circuit 750-1152~ before it i~ applled to AND gate 750-11512. The ~ame ~inary ZERO outpu without being inverted is delayed by a buf~er delay circuit 750--11523 and applied to circuit~ which re~et the sta~e~ of bit positions of a tran~it buffer valid bit register . which forms part of transit buffer 750-102.
. It will also be noted that the double precision signal FDPFllO i8 combi~Pd in an AND g~t~ 750 11524 with a write cache flag signal ~WRTC~FLG100 from tran~it block bufer flag storage portion of buffer 750~102. The AN~ gate 7~0~1152 generate~ a mPmory write requeRt ~ignal MEMWRTREQ100 which is forwarded to ~ec~on 75~9 '~or anabling memo~y d~ta to be written in~o cache (~.e., con-~' trol~ a-~dress ~witch~ ) s~lection~.

~y l.3~

A~ s~en from Figure 7a, the initiating reque~t con-trol clrcuit~ block 750-116 include~ ~n ac~lve output ~ort request flip~lop 750-11630. q'h~ fllp-flop 18 a : clocked D typ~ fllp-flop which include~ two lnput ANDJOR
~ating circuits. Flip flop 750-11600 1~ aet to a bLnary ONE ~tate in re~ponse to clock slynal lCLKT0~0 when block 750-114 forces a pair of signals ENA~SETAOPR100 and SETAOPR100 to blnary ON~S. When ~et to a blnary O~, thi~, in turn, 3et8 ~he AOPR line of intsrface 600, signalling the SIU100 of a data tran3fer request. The binary ZERO side of flip-flop 75~-11600 1~ invsrted by an inverter c~rcuit 750-11602, dela~ed by a delay buffer : circuit 750-11604 and applied to a hold AND gate. The flip-flop 750-11600 rem~ins s~t until the clock time that ~ignal FA~A023 ~w~tches to a binary ZERO ~ndicat~ng ; that the SIU100 acc~pted the cache memory reque~t.

~ : , )3~
11 ~, ', The hol~ control block 750-117, a~ shown, includ~
an inhlbit tr~nsit bufer hit FINH~ HI~ fllp-1Op 750- .
11700, an AND g~te 750-11702 and ~ plurality of AND/NAND
ga'ces 750-11704 through 750-11716. The flip-flop 750-5 11700 i~ set ~o a binary O~IE stat~ via a first input AND gate and a NAND gate 750-11701 in xe~ponse to a T
clo,ck sign~l 1CLKTO20 when ~ignals INHTBHIT100 and TBHI~100 ~', arei binary ONE5. The NAND g~te 750-11701 f~orce8 slgnal . ~ INHT~HIT100 to a binary ONE in the case of a can~el lû condition (i.e., signal [CANCELC012 iB a binary ZERO~.
:: ~ Th~ complement output sids of flip-flop 750-11700 appli~ slgnal FINHT~HIT000 a~ on~ input to AND gate 750-11702. A direc~ory bu~y ~i~nal DIRBUSY000 from block 750~52C i~ applied to the oth~r input of AND g~te 750 : 15 11702. Wh2n th~ directory i~ not performirlg a search e., slgnal DIRBUSY000 iY a bin~ry ONE) and signal INHTBHIT100 is a binary ONE, AND gate 750-11702 forc~s . ~ ~ ~iqnal I~H~EUCMP000 'co a binary ONE. This, in turn, ~: cau~es the gate 750-11704 to fc~rce ignal TBHIT100 to 20 a bin~ry ONE when the A~aD gate 750-136 fs~rce~ a tran~it : ~ block addr~s3 compare ~ignal TBACMP100 to a binary ONE.
At the 3~me 'ciml3 t gate 75Q-11704 force~ signal T~HIT000 to a hinar~ ZERO.
The AND/NP~7D gate 750-11708 through 750-1l710 : ~ 25 ger~erate ~ignals CPS~OP000 through CPSTOP003 whlch ar~
forwarded to proces30r 7ao for indicatin~ a hold condi-: ~ tion. The other AND/NAND gate~ 750-11714 through 750--~ ~ 11716 genarate si~nal8 (HOLDDMEM000 through [HOIDDM~M003 to specify an interaal Aold condition for preven~ng 39 the oth~r section~ of cache 750 from executing th~ command applied ~o thQ colwnand llnes by proce~or 70Q. ~ene~er ' ,~

;

g~

there i8 a hold command condition (i.e., aignal ~OL~CMD000 ~ a ~inary ZERO~, a mls~ condition (i.~., signal E~M~SS020 i8 ~ binary ZERO), a hold quad condltlon Prom block 750-916 (i.e., slgnal ~OLD~DQU~D000 i8 a blnary ZE~O~ or a txan~it block hit condltion ($.e., signal T~HIT000 is a binary ZERO), the gatea 750-11708 through 750-11710 force their r~spectiv~ output signals CPSTOP003 through CPSTOP000 t~ binary ZEROS and signals CPSTOP103 through CPSTOP100 to binary ONES. Thi~, in turn, cause~
the pxoce~or 700 to halt operation.
Under similar condition~, in addition to a hold search condition (i.e., signal ~OLDSE~RC~000 i~ a binary ZERO) a~ ind:Lcated ~y AND g~te 750-11712 forcing aignal lEA~YHOLD000 to a binary ZERO or a hold cache cond~t~on 15 (i.e., signal lHOLDCCUOOO i8 a binary ZERO), the gate~
750-11714 through 750-11716 force the~r respect~ ve output siynal IHOLDDMEM000 through IHOI.DDMEM003 to ~inary ZEROS
asld signal~ [HOLDVMEM100 thr~ugh [HOLDDMEM103 to b~ nary OI~S .

., _, , `, 139 - Referring ~o the Figure, it is seen that the timing - circuits of bloc~ 750~ include a synchronou~ D type flip-~lop 750-L1800 with two AND/OR input circults. Th~
fli~-10p 750-11300 rsc~lves a half T clocking ~ignal [C~KHT130 via gate 750-11802 and inverter circuit 750-11804. A definer T clock ~ignal DEFTCLX110 i~ applied to one of the data i~puts via a pair of delay buffer circuit~
750-11806 and 750-11808. Each buffer circuit providss a minimum delay c~ S ~ano~econd~.
~oth the signals [CLKHT100 and D~FTCL~llO are ge~rated by the common timing ~ource. In response to ~hese signals, the hal~ T flip-flop 750-11800 0wi~ches to a binary ONE ~ate ~pon th~ traLling ~9~ of tha DEFTCL~llO
signal. It switches to a binary ZERO state upon the .
occurrence of the next lC~HT100 s~gnal ~at the trailing edge).
The signal~ FHT100 an~ ~H~OOO, in additlon to signals FHT120, PHTO10 and FHT020 derived from th~ binsry ONE ~nd binary ZERO output terminals o~ flip-flop 750- -~, 20 118007ar~ di3tributed to other clrcuits of aection 750-1 ~as well as to other ssction~ (i.e.9 750-5, 750-9 and 750 114). The ~ign~l~ FHT120, FHT020 and FHTO10 are di~tributed via another pair of delay buffer circuit~
750-11810 and 7~0-11812 and a driver circuit 750-11814 r~p~ctiv~ly.
The ~ clock signals such as lC~XT020 and [CLKT022 g~nerated by the common tlming 30urce are distributed in their ~ra~n form to th~ variou~ flip-flop~ o registers.
When ~her~ i~ a ~e~d to generste a 1~2 T clock ~ign~l, the 1/2 T clock signal lCLKHT020 1~ gated with ~he 1/2 T

- ~4 definer ~ignal (F~T100~ at the i.npu~ of the ~llp-flop or regi~ter. The ~tat¢ o~ signal FHT100 is u~ed to de-fine the flrst and ~econd halves of a T cycle. Whon ~ignal FHT100 is a binary ONE, thls define~ a time 5 interval corresponding to the flrst half of a ~ clock cycle. Conver~ely, when ~ignal F~100 i9 a binary Z~RO, thi~ define~ ~ time interval corresponding to th~ 0econd hal f o a T clock cycle .
~'or the purpo~e of the present invention, the data 10 recovery circuits can be con~id2red conventional in design and may, fQr example, take the form of tha cir-cuit~ de~cribed in ~ha referenced pat~nt application~.
: The~e circuit~ gen~rate a data recovery ~ignal forforwarding to proce~sor 700 by "AN~ING" ~le 1/2 T
clock ~ignal F~T000 w$th a ~ignal indicating that data is being ~trobed into the processor5s reqisters. Thi3 cau~e~ the data recovery signal ~o be generated only durir.g the ~econd half of a T clock e:ycle when ~uch data 18 belng ~trob2d int~ the processor'~ register~.
In the case of ~ection~ 750-5 and ?50-9, the slgnal FHTlOC is used to control the switching o~ other ti~ng and control flip-flop~ a~ explai~ed herein.

~ 41~

D~:TAILED DES~I~IPTION Ol; SECTION 750- 3 ~____ __ ___ . _____ ura 7b ~hows ln gr~tcr det~ p~al~lc onc~
v ~he block~ of ~ectlon 750-3. Corr~pondlng r3for- . -`: ence nu~ber~ have bean u~ed where poaslble.
S ~eferring to ~ig~re 7b, it ls ~een that the decoder circuit~ of block 750-303 include a decoder circuit 750-30300 which is enabled for operation by signal ENBMEMLEV100 from th~ circuit8 of block 750-920. The 1gnal~ from non-inverted output terminal6 of decod~r . 10 circuit 750-30300 ~re appliQd to the input termlnals of a fir~t ~ultiplex~r circuit 750-30302. The ~lgnal~
at ~he inv~rted output terminals are appli~d to the ~nput termlnals of a second mul~lplexer circult 750-30304.
The mul~iplexe~ circuit 750-30302 ia alw~y~ ~na~led or ~ 15 operation wh1le ~he multiplexer circuit 750-30304 18 :: ~ only enabled when slgnal ENBADR1100 i8 fOrCG~ to a binary . ~: ON~ by the cixcuits o~ block 750-920. It i~ a~sum~d :~ that the "0~ po~i~ion~ of both multiplexer circui~
will alway~ b~ sel~cted.
-~ 20 Predet~rmi~ed co~bination~ of the ~wo ~ets of con-trol signals 1ZADRO1100 through [ZADR71100 and 8ignal~
[ZADR00l00 through [Z~D~70100 are applied to the control input terminals of each of the el~h~ cro~0bar add~es~
selectlon ~witches 750-302a through 750-302h, a~ ~hown.
~: 25 ~ een that ~ach cro~bar 3witch lncludes a nu~b~r of ~ectior3s, each section include~ three p~rt~ indlcated by the heavy line~ betwee~ ections. For slmpllclty, th~ nwr~¢r o ~ection~ of each switch are showA togethar.
Por s~mplicity, the control portlon or' each s~ction 1~
shown only o~lce sincQ 1~ i~ th~ same for all ~he sectlons whi ~h are required to make up the ~wltoh .

' .,' - 13~
.~ .
A0 se~n from tlle Figure, depending upon the ~ta~e3 of the ~lr~ of control signals [ZADR00100, IZADROllOO
through [ZAD~70100, 1zADR7lloo, the ~ gnals from one of ~Ae three ~ource~ are applied to each set o~ W, X, Y and 5 Z te~minals simult~neou~ly.

, ~
, -~` D~TAI~D DESCRIPTION _F SECTION 750-5 , . .
: Plgure 7c show~ in greater det~il speclfic ones of the b1Ocks of ~ection 750-5 aY explained pr~viously.
Corresponding reference numbers have be~n u3ed where S pos~ibla.
Referring to Figure 7c, it i8 seen that the directory hit/miss control cir¢uits of block 750-512 include an encod~r n~twork eompri~ing a plurality of NAND gates 750-51200 through 750-51220 and a plurality of ampllf~er cir-cuits 750-51224 through 750-51228. The NAND gate cir-GUit~ are con~acted to encode the set of signals ZF~1100 through ZF~7100 from block 750-506 and ~he se~ of ~ignal~
ZHT1100 through ZHT7100 from the block~ 750-545 through 750-552 into the 3-bit ~ode for co~trolllng the op~ration of swit~h 750-306.
Tll~ ~ignal GS~CH100 ls g~nerated by the circuits o block 750-526~ A~ explained herein, this sign~l i8 only forced to ~ bi~ry ONE during the second half of a T clock cycle. Thus 9 an output from one of the NAND
gates 7$0-51200 through 750~5120~ enerat~d only durlng that interval. More spec~ fically, the hit signal.
syecified by the state of the full-empty bit cau~e3 one of the signal~ ZCDLEV1000 through æCDLEV7000 to be ~orcad to a bin~ry ZE~O state. This, in turn, condition~ NAND
~ates 750-51216 through 750-51220 to genera~e ~he appro-priate 3-bit code.
Signal ZCDICENAB100 also ge~erated by th~ ~ircuit~
of ~lock 750-526 i~ forced to a blnary ONE only durlng the first half of a T clock cycla. Thus, outputs from NAND gates 750-51210 through 750-51214 are generated only during that interval. That is, the instru~tion ~ddress level ~ignal~ ZNICLEV0100 through ZNICLEV2100 from block 750-~10 produce ~ignal~ ICL0000 ~hrough ICL2000.

f' which, in turn, produce ~ignals ZCDO100 through ZCD2100.
It will be not~d that the sign~l~ ZCDO100 throu~h ZCD2100 correspond to ZNICL2VO100 through ZNICLEY2100.
The ~ignal~ RDD~LI,OOOO through RDDBL~2000 are used . 5 to define the second cycle of op~ratlon for a read double command. Accordingly, when any one of the slgnal~
RDD~LLOOOO through RDD~LL2000-~e ln a blnary ZERO ~tate, thi~ force~ a corresponding one of the signals ZCDO100 through ZCD2100 to a binary ONE.
The signal~ ZCDOldO through ZCD2100 are applied to different inputs of corre~ponding on~s of the ~mplifier driver circuits 75~-51224 through 750-51228. These - circuits apply the control ~ignals ~ZCDO100 through [ZCD2100 to the ~ontrol tersinals of ~witch 750-306.

.

~: A n~xt block ~hown in greater detail in Figuro 7c i8 block 7S0-526. A~ ment~oned prevlously, block 750-5'~6 lnclude~ a number of dircctory c~ntrol ~llp-flops.
l'he control ~tate fllp-1Op~ ~hown lnclude the dlrectory as6ignment ~FDI~ASN) control ~tate flip-flop 750-52600 and a plurality o~ timing flip-flops of a register ?50-52610.
~he flip-flop 750-52600 i~ a clocked D type flip- -flop which i~ set to a ~lnary O~IE via first input AND
gate in the ca~e o a ~ommand reque~t ~i.e., sign~l R~QCOMB0100 i~ a binary ON~) for a read type oommand i.e., RDTYP100 i~ a blnary ONE) when proce~sor 700 - requests data from memory and not ca~he 750 (i.e., ~iqnal BYPCAC110 1~ a b~nary O~E). In greater detail, in the ab~ence of a hold condition ~i.e., ~ignal HOLD000 ~pplied v$a an ~ND g~t~ 750-52602 1~ ~ binary ONE)~ a 9O transfer ~i.e., ~ignal NOGO021 i~ a binary ONE), no cancel condition (i.e., signal CANCELC010 i8 a b~nary O~E) and proce sor 700 ha~ signalled a reque~t (i.e., signal D~QCAClll i6 a ~inary ONE~ ~n~ AND gate 750-52604 force~ s~gnal ~EQCOMB0100 to a blnary ONE.
~ n AND ga e 750-52606 forces the sign~l SETONBYP100 to a binary~O~E ~in the oase of read type whe~ de~oder circuit 750 528 ~o~c2s signal RDTYP100 to a binary ONE
when procéssor 700 ~orce~ the bypass ~a~he ~ignal BY~CAC110 to a b~nary ~N~. The result i~ that th~
YDIRASN flip-~lop 750-52600 switch~s to a binary ONE
for ~p~cifying a dir~ctory assignment cycle of operatlon.
The 1ip-flop 750-S2600 is also ~et to a binary ONE via a ~econd~iAput AND gate in the case of a command reque~t ~i.e., ~ig~al ~EQCOM~0100 ~s a binary O~E) when a m~Qs condition i8 detected for the block 3~
14b requa~ted to be read (i.e., ~ignal SETONMISS100 1B a blnary ONE). ~he slsJnal SETONMIS5100 1~ forced to a b~n-nry ONI~ by an ~ND g~ts 750-52608 when ~i~nal RDTYP100 i8 a binary ~NE and ~lgn~l RAWHI~000 from block 750-512 i~
i5 a ~inary ON~, Th~ flip-flop 750-52600 is reset to a binary ZERO state upon the occurrence of clock signal [CLOCK112 generated from the comm4n source ln the absence of a set output signal from the two ~nput AN~ qates.
A first flip-flop (~ICENAB) o~ rqgi~er 750-52610 10 i~ used to define the interval of time with~n a T clock cycle when instruction~ or operands are to.be fetched from cache 750.
~ hi~ flip-flop i~ ~witched to a binary ONE ~tate via a first AND gate in re~ponYe to a clock ~ignal [CLOCKD120 when ~lgnal FHT100 g~nerated by the tl~ing circuit~ o block 750-112 i6 a bin~ry ONE. Clock signal [CL~CKD120 from the common timing source i3 appll~d via an AND g~te 750-52612 a~d an invert~r circuit 759-52612 and an invertsr circuit 750-S2514. The FICENAB flip flop reset-~ o~ the foll~wing clock signal when qlgnal FHT-100 has been switched to a binary ZERO.
The 3econd flip-flop of register ~50-52610 i~ used to define an int~rval during which operands (not instruc-tion8) are being fetched from c~che 750 a~ a con~equence of a special condition cau~ed by an IFl command whlch did not speciy the la6t word in an instruction block.
Tne ~'RCIC flip-flop i~ ~witched to ~ binary ONE via a first input AND gate in respon~e to cloc~ signal lCLOCX-D120 when sig~al ~JAM~NICLEV000 i~ a biAary ONE. The FRCIC flip-flop reset~ on the following cloc~ pulse when ~iqnal FJAMZNICLEV000 ha~ been switched to a blnary ZERO.

, ~_~

3~0 , . .
1//. ~
}4~
.~ , A~ ~hown, 'che 3ignal at the binary ZERO outpu~ ter-minal of 'che FIC~NA~ fl~p-flop correaponds to the gate half T clo~k sigz~al GATEHF~C~LX110 whlch i~ dist,ributad to the circuit~ of block 7S0-920.
S The 6ignal FICENAB000 i~ combined with signal FRCIC000 ~nd slgnal RDDDLZCDE900 wi hin an AND ~ate 750-52616 to produce signal GSRCH100. ~he ~ignal RDDBLZCDE000 i8 from decoder circuit . Th~ s gate force6 signal GSP~CH100 to a binary ONE dur~rlg the ~econd h~lf of a T ~::lock cycle when op~rand~ are belng fetched (i.e., ~ign~l FI5:ENA13000 is a L inary ONE) ~xcept in the c:a~e of a read double co~nand ~ ., sign~l RDD~L3CD~000 i8 a binary ONE).
The blnary ZERO output of the FICENA flip~flop i8 combined with ~i~nal FRCIC000 wlthin a N~ND g3te 750-52618. The NAND gate 750-526113 operates to force ~ign~l ZCDINCE~ 100 to a binary ONE durlng the first half T
in~erval when lnstruction~ are l~elng fatched (i.e~ ~ signal FICENAB000 ls ~ ~nary ~ERO) or ln the c:ase of the ~ype IFl con~nand d~scribed above (i . e ., ign~l FRCIC000 i8 a - 20 binary Z13RO).
The circuits of block 750-526 further include a N~ND gate 750-52620 ~d a plurallty of l~D q~ . e3 750-52622 through 750-52628 connected, a~ ~hown. The clrcuits yenerate a fir~t enab}o control ~ignal DIRADD15100 for controlling the operatlon of decoder circuit 750-521.
Add~ tlonally, they gener~te a ~econd enable control 0ig-nal FEDCODE100 for controlling the operatlon of a decoder circuit 750-52000 of bloc~c 750-520.
In greater detall, durlny a directory asgiynment cycle (i.e., signal PDIRA5N100 is a binary ONE) in the ab~ence of a tran ~er no go condi~ion (i.e., ~ignal NOGO21 i~ a binary ONE~, AND gate 75û-52626 forces signal 1~

DIRNO~O100 to a binary ONE. Wh~n a signal FSKIPRR000 fro~l the circu~ of block 750-916 1~ a blnary ONE, thi3 cau~es the AND gate 750-52628 to force si~nal DIRADDE100 to a binary ONE wh~ch enable~ decoder circuit 750-521 S for operation. When oither signal DI~NO~100 or FSRIP~R000 is forced to ~ binary-ZERO, thi~ ceuees AND gate 750-526~8 to dl~able decoder clrcuit 750-521 by forclng nlgnal DIRADDEl00 to a blna~y ZERO.
Under the 8ame condition~, the AND gate 750-52624 force~ ~ignal FEDCODE100 to a binary ONF, which enables decoder circuit 750-S2000 for operation. The AND gate -~ 750 52630 causes an amplifler ~ircuit 750-52632 to force : signal FORCEBYP000 to a binary ONE when both aignAl~
~SKIPRR000 and FBYPCAC00'are binary ONES. The FOROE ~YP000 15 iB applied to the transit block flag section of block 750-102. The sign~l F~YPCAC000 i8 generated in a conventional manner in accord~nce with th~ ~ignal applied to the line ~YPCAC by proces~or 700. The signal i8 stored in a fllp-flop, not shown, who3~ binary ZERO output corre~pond~ to : 20 signal F~YPCAC000.
: ~ The c~rcuits of block 750-520, a~ show~, include ths d~coder circuit 750-52000 and a pair of multipl~xer - circuits 750-52002 and 750-52004~ It is a~6umed that nor~ally the ~ignal~ applied to the "0~ input terminuls o~ mul~iplexer circuits 750-520~2 and 750~52004 are ~el~cted to ~e applied ~ output~ (l.e., he si~n~l applied to the G input i~ a binary ZE~O~. Therefore, when the d~cvder circuit 750-520000 i~ enabled, the output ~ignal~ F~D0100 through FED7100 rasult ln the generation of signal~ ~WFEO100 through ~WFE7100 in re~pon~e to clock sig~al [CLOCX000.

~q The ~'lgu~e 7c al~o 0how~ ln greater detall regl~ter 750-504 ~ lnclu~lng ~ clocked foux ~tag~ ro~ist~r 750-S0400 and ~ plurality oP amplifier circult~ 750-50402 through 750-50602. The register 750-50400 includes D type S flip-flops, the fir~t ~hree of which are connected for ~toring round robin ~ignals OLDRR0100 through O~D M2100.
The fourth flip-flop is connected to indlcate the pre-3ence of an alternate hit condition having ~ean detected by th~ circuits of block 750-562, not shown. ~hat 18, it i~ s~t to a blnary ONE state when signal ALTHITl00 i~
a binary ONE.
I~ will be noted that the flip-flops of regLster 750-50400 are only enabled in response to clock signal tcLocKll2 when sig~al F~IRASN000 is a bianry ONE indicative of no dir~ctory aHsign~ent cycle being performed (a hlt condi~ion~.
In the case of a hit condition det~cted within the half of a block being r~ferenced, sig~al ALTHIT000 1~
forced to a binary ZERO. This cau~e~ the fir3t three flip-flop~ o~ regi8t9r 750-50400 to be loaded via a fir~t set of input AND gates with the round robin Bignal3 RR0l00 thxough ~R2100 from block 750-500. Whsn thera i8 a hit condition detected within the other half (alter-nate) of the block being referenced, the circuits of bloc~ 750-512 force Glgnal ALTHITl00 to a binary OM~.
This cause~ the ~hree flip-flops to be loaded via a ~econd ~et of input AND gate5 with the alternate level ~lgnals ~LT~ITL~V0100 through ALTHITLEY2100 gen~rated by the circult~ of ~lock 750~512.
The bi~ary ONE ~gn~ls of regi3ter 750-50400 are applied a~ lnput~ to th~ amplifier drlver circuits 750~50402 throu~h 750-50406 for storage in the transit block buffer 750-102. l'he same signals are applied to the A operand input terminals of an adder clrcult of block 750-50~. The adder circuit adds or increments the sig-nals OLDRR0100 through OLDRR2100 by one via the binary GI~E applied to the Cl terminal of the adder circuit.
The sum signals NXTRR0100 through NXTRR2100 generated at the F output terminal~ are written into the round robin section of control directory 750-500.
La3tly, the siqnal~ OLDRR0100 throlloh ~L~ 2100 are applied as inputs to another set of amplifier driver circuits 750~50408 through 750-50412 for storage in one of the instruction ad~ress registers 750-900 and 7S0-g02 of Figure 7e.

DE;TAILED DESCRIPTION OF SECTION 750-7 Flgure 7d ~how~ ln greater ~etail dlfferent on~ of : block~ of ~ection 750-7. A~ ~een ~rom Flgur~ 7d, bloc~
750-722 includes a plurality of ~erie~ conne~ted NAND
gates 750-72230 through 750-72234. The NAND yates 750-72230 and 750-72231 are connected to receiYe inetructlon buffer valld and instruction control slgnals IBVFlV100, lZRIB010 and IsUF2V100, ~Z~I~100 from I buffers 750-715 an~ 750-717 and bloc~ 750-920. The IBUFlV100 and 1~UF~Vl00 signala in~icate the instruction buffer into which information i8 being loaded. That i~, when signal I~UFlV100 iB a binary ON~, that ~pecifie~ that I buffer - 750-715 is io~ded. When signal IBUF2V100 i~ a binary ONE, that ~pecifles that I buffer 750-717 i~ loaded wlth an instruction word.
The control signal~ [Z~IB010 ~n~ lZRI~l00 ~peclfy which instruction bu~f~r valid bit i~ to be examlned which corresponds to the instructlon buffer belng a~dr~ d. That i~, wh~n signal [ZRIB010 i~ a blnary ON~, the IBUEl valid bit i~ 3pec~fied by the circuit~ of block 750-920. When ~ignal ~ZRIB100 i~ a binary ONE, : that ~pecifie~ the IBUF2 val~d bit. When either ~ignal I~UFlRDY000 or ~ignal I~UF2RDY000 i~ forced to a binary ZE~, NAND gate 750-72232 forces ~ignal TBIBUFRDY100 to a binary ONE indicative of a ready cond~tio~.
The circuit~ of block 750~920 force an enabling ~ig-: ~ nal US~TB~DY100 to a b~nary ONE following th~ ~witchlng of ~le appropriat~ I buffer valid bi~. Thi~ cau3e~ the NAND gate 750-72233 ts foxce the T~aDY000 signal to a binary Z~RO. The result is that NAND gate 150~72234 forces tha I~UFRDY100 to a binary ONE signalling the ready condition.

o ls ~

It will al30 be nsted that NAND ~ate 750-72234 al~o force~ the IBUFRDY100 ~ign~l to a binary ONE wh2n an inatruction f~tch ready ~l~nal IFETCI~DYOOO 1 forcsd to a binary zEno by the circults of block 750-920. Signal IFETCHRDYOOO is a binary ONE except whenthe instructions are being pulled from a block ln c~che.
La~tly, NAND gate 750-72234 forces IBUFRDY100 signal to a binary ONE when an instruction buffer compare ~ignal IBUFCMPROOO i~ forced to a binary O~JE by compara~or cir-cuit 750-11435~

DETAII~D D~SCRIPTIO,~I OF sEc~rIot~J 750-9 ~_ _ __ ___ Figur 7e .~howa in greater detail speclfic one~ of th~ ~locks of sectlon 750-9. Correapond~ng reference number3 havz been u~ed where pos~lblo.
Referring to Flgure 7e, it i~ ~een that the block 750-920 includes a first group of circuitc of block 750-92000 which generate the four sets of write control signals WP~T00100 through WP.T70100, WRT01100 through WRT71100, WRT02110 through WRT72100 and WRT03100 through W~T73100. As seen from Figure 7e, these circu~ts include a pair of multiplexer clrcuits 750-92002 and 750-92004, a register 750-9200~ and four octal deco~er circuits 750-92008 through 750-92014, connected as shown.
The multiplexer circu~t 750-92002 has signals : 15 nHITL~voloo through RHITLEV2100 from block 750-512 : applled to the set of l-o" input terminals while si~nals Rq'BLEVO100 through RTBLEV2100 applied to the set of ~1"
input ter~inal~. During the first half of a T cycle when ~ignal FDPN2HTl00 applied to the control terminal G0/Gl is a binary ZERO, th~ al~ RHITLEV0100 and RHITLEV2100 are ap~lied to the output termin~ls. They ~re ~locked into the top three fl1p-flop~ of register 750-92006 ln response to T clock ~ignal l:CLl(HT02. Thif3 enable~ pro-cessor operand~ to be written lnto cache 750~300 durlng ~5 the second half of the T clocJc cycle, Durlng the ~econd half of a r cycl~ when sign;~l FDEN2NT100 is forced to a binary ONE, the 6ignal~ R~rBLEV0100 through RTBLEV2100 are clocked into the r~gister 7$0-92006 in response to the T alock signal tCLi~HT02. This enables memory data to be writtçsn into s:aahe 750-300 during the fixst half of the nex'c cycle.
The ~econd multiplexer çircuit 750-92004 has signal~
ZONE0100 through ~ONE3100 from switch 750-144 applied to the ~et of "0" input tsrmi~als while signal ME~RTREQ100 3~
,.,, lS~

from block 750-112 is applied 'co the set of "1" input termln31~. When ~lgnal FDF~2HT100 1~ a blnary ZER-), the signals ZON1~0100 'chrough ZON~3100 are applied ts~ the output terminal~. ~h~y are clocked into the bottom 5 ~ flip-flops of register 750-920~ in re6ponse to T
clock signal [CLKHT02. During the fir~t hal~ of a T
clock cycle, NAND gate 750-92005 forces ~ignal ENBWRT100 ~ to a binary ONF which enables the previously loaded sig--nal~ to be applied to the output t~rminal~. Thi0 en~bles the processor zone bits to be u~ed in specifying which operand byte~ are to be updated when writing proces~or data into the specified level of cache. When signal FDFN2~1T100 1~ forced to a binary ONE, the ~ignal MEMWRTRE~100 1~ clock~d lnto the regi~ter 750~92006.
Thi~ cau~es all the ~on~ bit6 to be forced to binary ONES for causing all of the ~ytes of ~ach datA word received fro~ memory to be writtan into the ~peclf~ed lev~31 of c~che durin~ the first half of the nex~ ~ cloc5c cy~le.
As seen from Figure 7e, dif fareJlt ones of the ~ignals ~W~TLEV0100 through RWP.TLEV2100 are ~pplied to the enable input termlnals of octal decoder circuit~ 750-92008 through 750-92014. The ~ignals ~WRTL~V0100 through ~WRTLEV2100 are applied to the lnput terminals of each of the octal dacoder c~rcuit~ 750-92008 throuyh 750-9~014.

l5 ~
~ , , ~ he block 750-920 includes a second group of circuits of block 750-92020. These circu~ta qenerate the half T clock sLgnal applied to the circuit~ of block 750-92000, the enable memory level ~ignal ENABMEMLEV100, and enable address signal ENADR1100 applied to ~he circuit~ of block 750-303. They also generate-the sets of control signals [ZIC010, [ZIC110 and [RICA100, [P.I~B100 a~plied to the circuits of instruction address registers 750-900 and 750-902 in addition to control signals [RIRA100 and [~IRB10~ Applied ~o the re~iater~ 750-308 an~ 750-31~ .
The circuits of block 750-92020 include a palr o~ half definer flip-flops of a regi~ter 750~92022, a group of .
three control flip-flops of register 750-92024 and a clocked flip-flop 750-92026. The circuits also include a number of AND gate~, NAND gates, AND/NAND ~ates and AND/OR ~e~e 750-92030 ~hrough 750~92041.
The serie~ connected ~D/2~AND gate 750-92030, ~ND/
OR gat~ 750-92032 and AND gates 750-92034 and 750-92035 in re~ponse to a signal FLDQUAD100 ~rom 750-916, a si~nal FWFID~SC010 from prscessor 700 and 31gnals FAC~VRIC000 and FACTVRIC100 from register 750-9~024 generate control signal~ lZIC000, [ZIC010 and [2IC110. These ~ignals are u~ed to control the operation of ZIC switch 750-906 and the different sections of registers 750-900 and 750-902 (e.g. level valid bit storage and level bit storage) in addition to regi~ters associated therewith.
The series connec~ed ~ND gate 750-92036, the ~ND/
NANV gate 750-92037 and N~D gate~ 750-9203B through 750-92041 op~rate ~o ge~erate register strobe ~ignals , `~ . ,~, , I ~ , , lRICA100 and ~IC~100, These signal~ control the loading ~: of r~iaters 750-900 4nd 75Q-902. The ~ND q~te 750-g2036 forco~ ~lgnal VAL~ U~'100 to ~ bln~ry ONE wh~n n hlt condition was detected in the case of a read com~and (i.e., signal F~DMISS000 i8 a binary O~lE), the transfer was a go (i.e., signal NO~020 iq a binary ONE) and ~ig-nal CMPDATA/ICLEY000 from the comparator circuit of block 750-912 i8 a binary ONE.
: The signal FRDMISS000 is o~tained from the binary . 10 ZE~ output of the flip-flop, not shown, which a~ mentioned . is set in accordance with the Boolean expression:
. FRDMUSS = ~RDCMDor~OL~ M-~ OIC~ CELCl.
!~: The signal~ GOODFTCHA100 and GOODFTCHB100 genera~ed by -cir~uits, not shown, :lndic:ate wh~ther the RICA regi~ter 750-goo or. RICB r~gister 750-902 is b~ing used at that tim~ and $t~ contents are ~here fore increm~nt~d . For example, slgnal GOODFTCHA100 i8 generated in accordance : ~ ~ith the followislg Boolean expre~sion:
~OODF~CHA ~ I~UAD-~TV~-FDEN2HT I Fl)~N2HT-~: 2 0 FLDQUALI- FAClVRIC .
:: Signal GOODPTCHI~ i~ generated in a similar fa3hion except ror the revar~al in 8tate8 of ~ignal~ FACIYRIC and ~: ~ ~A~
seen that when signal EXECRDIBU~100 i5 forced o a ~ina~y ONE when processor 700 forces signal RDIBVF110 to a binary ONE, the NAND gate 750-92039 causes :~ NAND gate 750-9Z041 to force signal lRICA100 to a binary ONE when signal GOODPTC~A100 i8 a bln~ry ONE. The : signal ~NBST~BA000 indicate~ when the RICA reqlst~r 7$0-900 is being initially 1Oaded. That is, when signal ENBSTRBA000 is forced to ~ binary ZERO, lt c~us~s NAND
gate 750-92041 to force siynal ~RICA10û to a blnary ONE.
M~re specifically, sign~l EN~STRBA i~ generated in ,:

ll /~-~

. ~ accordance with the following Boole~n expre~sion:
ENBSTR~3A = FLDQUAD^FACIVRICFNEWIFl.FD~71HT
F~ENlHT-FAClVRIC.FJAMZNICLEV~E~OLDIFl + (INSTIFl + DCDLDQVAD) .F~CTVRIC-FDE~12HT. tCANCLCMD
~ FDFi~2~{T [ ZIC INH 2~T ENAB2~T .
wherein ENAs2E~T - ENAsRIcl ~ ENAsRIC2 and INH2HT = [CANCLCMD-FLX~TINST.
Under either set of conditions, signals [RICA100 and : ~RICB100 enabl~ the strobing of their corresponding registers when they are either beinq initially loa~ed or following incrementing as when instructions are being . fetched or pulled out from cache.
The N~ND yat~ 750-92042, AND~NAND gate 750-92043 and NANi~ gates 750-92û44 through 750-92049 are connected to ge~erate register strobe signals [RIRA100 and [RIRB100 in a fashion 3imilar to the genexation of regi~ter : ~ strobe ~ignals [RICA100 and [~ICB100.
. : The NAND gate 750-92046 forces signal l~.IRA100 to a binary O~E in the case of a new instruction fe'cch (i.e., 20 signal NEWINST000 is a binary ZERO) or when the processor 700 taKes ar~ struction from P~IRA register 750-308 `~. (i.e., signal TAKBINST000 i~ a bin~ry ZERO). The N~ND
gate 750-92049 forces signal ~RIRB100 in thQ case of a , ~ new operand fetch ti.e., slgnal ~EWDATA000 i8 a binary i 25 ~ERO) or when proces~or 700 takes:a data word fxom RIRB
I register 750-310 ti~., signal T~KEDATA000 i~ a bin~ry ZERO)~
The ~ND gate 750-92ûS0 and ~ND/NAND gate 750-92051 generate sig~al ENB~EMLEV100 durin~ the second half of a-T clock cycle ~i.e--., signal FDFN2HT101 is a binary ONE) when the circu1tfi ot block 750-112 force meQory write ,~
~-request ~ignal MEMWRTREQ100 to a bi~ary ONE. The N~JD
te 750-92052 qenerate~ ~lgn~l ENBAD~llOO during he ~ocond half of ~ T clock cycle (l.e., ~lgnal FDF~l~lTlOl 13 a blnary ZERO~ or when the inBtructiOn countQr l~ ln use (i.e., ~ignal USEICOOO i~ a bin~ry ZERo).
As concern~ the flip-flop register6, lt 18 seen that the flip-flop of register 750-92026 i8 ~witch~d to a binary ONE atate via a first AND gate when ~D gate 750-92053 i~ conditio~ed to ~orce signal INSTIFllOO to a ¦ 10 binary ONE in response to an IFl command being decoded by 1 decoder circui~ 750-922 (i.e., signal DCDIFllOO is a ! binary ONE) which does not requ~re additional descriptor~
~i.e., signal FFPIMEIS020 from proces~or 700 ~a a binary - ON~) ~nd AND ga~e 750-92054 fsrces algnal [CANCE~CMDOOO
: 15 to a binary ONE in respon~e to a no cancel co~dition ~i.e., ~ign~l lCAN OE LCOlO is a binary ONE) and a no hold condition ~i.e., slgnal ~HO~DDMEMOQl i~ a b~nary z~RO).
. ~he flip-flop regi~ter 750-92026 i8 re~et to ~ bin~ry Z~R~ via a second input ~ND gate which receives signalR
ENA~NLWINSTOOO and NEWIFlFDBKlOO rom a pa~r of NAND
gates 750-92042 and 750-92043 and AND gate 750-g2055.
The binary ONE output of ~he ~lip-flop regi~ter ~50-9202 iY appli~d to NAN~ gate 750-92056~ NAND ~ate 750-92056, during tha fir~t half of a T clock oycle (i.e., signal ~FNll~T100 is a binary ONE), ~witche~ ~ignal USEICOOO ~o a binary Z~O wh~n signal FNEWIFllOO i8 ~witch~d ~o a binary ON~.
~ The second fllp-flop regi~ter 750-92022 include~ ~he : 30 pair of timing flip-flops whiGh are both set to binary ONES in r~spon~e to 3ign~1 G~TEHFTCLX100 from ~ection - ~
l5 ~
~ , , 750-5 in respon~e to l/2 T clock ~i~nAl ~CLXHT021. The fll~-flop~ of re~ter 750-92022 ~re ~e~t to }~lnary ZEROS ln r~spons~ to the next 1/2 T clock ~lgn~l lCL~T021.
The flip-flops of register ~750-92024, as mentioned prevlously, provide variou~ ~tate control signals. The fir~t flip-flop (FR~IBUF) i~ ~witched to a binary ONE
~tate when NAND gate 750-92060 force~ signal SETRDIBUFl00 to a binary ONE in re~pon3e to read I buffer r~que~t from pro~essor 700 (i.e., siynal EXECRDIBUF~00 is a binary ZE~O) or a~ inhiblt ready condition ~i.e., signal FINHRDY010 is a binary ZERO~ when AND gate 750-92061 forcas signal EM~BSET~DI~U~100 to a binary ~NE. Th~
- signal ENABSETRDI~UF100 1~ for~ed to a blnary ONB ln : 15 the ca~e of a ~ommand whlch i8 not a load quad com~and (iOe., signal FLDQUAD000 i~ a binary ONE) or an i.nstruc-tion fetch 1 co~mand (i.e., slgnal GOODIF1000 i8 a binary ON~)o The FRDIBVF ~l$p-flop i9 re8~t a clock period later i~ r3~pon~e to T clock ~lgnal [CLKT021 vla a second . 20 input AND gste.
- $he second ~lip-flop (FACTVRIC) of register 750-9~024 - i8 ~et and re-aet in accordance with the ~oolean expre~ions prev~ously given via the NAND gates 750-92062 and 750-92064, the AND gate ~50-92063 and AND~NAND gate 750-92065, The third flip-flop (P'.RDDATA) is ~et to a binary ONE state ~vla ~ first lnput A~ gate ln re~ponse to signal SE~RDIBUF100 when the comrnand ls a load quad command (i.e., signal FLDQUADl00 iB a binary ONE~. The FRDDATA flip- lop i~ reset to a binary ZERO state a ~0 clock period later via a second inpu~ AN~ gata in re~ponse to the T clock ~lgnal (CLKT021.

l60 . ~he next group o~ circuits included within block 750-920 include the circuits of block 750-92070. As ~een from Figu~e 7e, th~s~ c~rcui~s include a first f plurality of AND gates, AND/~AND gates and NAND gates 750-92071 through 750-92086,connected as shown. These ~ates generate control signals SETACURLEV100, [ RICACNTL100 and ~STACURLEV2000 which control the setting and resetting of the current lev~l and level valid bit positions of RICA register 750-900 in accordanc~ with the states of Yignals SE~ALEVlVAL100, RST~LEVlVAL000 and SETLEV2VAL100.
The~# qignals are generated by another plurality of ~D
gat~s and NAND gates 750-92087 through 7$0-92095.
A 3econd plurality of AND gates, AND/NAND gates and NAND gatas 7~0~9210Q through 750-92116, in a similax fashio~, generate~ signals SETBCURLEV100 ~ RSTBCURLEV200 and [RICBCNTL100 which set and reset the current level and valid bits for the RICB register 750~902 in accordance with signals SET13LEVlVAI,100, RSTBLEVlVAI.000 and SETBLEV2-G VAI.100. These signals are generated' a~other pll~rality of AND gates and N~ND gate~ 750-92120 through 750-92125.
A plurality o~ ~D ga~es 750-92126 through 750-92129, in respo~se to signals SETALEVlVALl90, SET~LEVlVAL--100, S~TALEV2VAL100 and SETBLEVlVAL100, generate contrsl signals ~RICALEVllO0 through ~RICBLEV2100 when signal 25 [C~NC~LCMD000 i8 a binary ONE. These signal~ are applied to the control input tenninals of the level bit storage ~ections of the RICA and RICB registers 750-990 and 750-902 for controlling ~he lo~ding of hit level signals fro~
section 750-512.
A further plurality of ~D/NAND, AND/OR gates and NAND gates 750-92130 throuyh 750-92137,in response to /6~

~ignals from the level valid ~it 3torage and level s'coraqe ections of rsgisters 750-900 and 75û-902, g~nerate ~he u e transit buffer ready ~ianal USET13~Y100 and the control ~ignals [ZRI8010 a~d ~Z~IB100 which are S applied to the circuit~ of block 750-114.
It is al~o ~een that block 750-92070 include~ a four D type flip-flvp regi~ter 750-92140, the pair of ~ID gates 750-9214:l and 750-92142, the pair of AND/NAND
gate~ 750-92143 and 750-92144 and the pair of I~ND/OR
ga~ 750-92145 a d 7~0-9~146, connected as ~hown. The flip-flops of ~ 750 92140 are loaded with the con-tents of bit position~ 8 ~nd 9 of the RICA and P.ICB
register 750-9û0 and 750-902 in re~ponse to T clock sig~
nal [CI.KHT020 lmder the control of signals 1RICA100- and lRIC13lOOo That i~, the top pair of register flip-flops are clocked when signal [RICA100 applied to terminal C1 is fors~ed to a bin~ry O~E whlle the bottom pair of - register flip-flop~ are cloclced whezl ~iqnal ¦RICB100 applied to terminal G2 i~ forced to a binary ONE. ~he - 20 signals ~ZIC000 and lZIC100 applied tu terminals t~3 and : G4 control independe~tly the generation output signals from the top pair of flip-f lops and bottom pair of flip-flops re~pectively at the corresponding set~ of output terminals~
Pairs o~ binary ZE~O output ~iynals are combined within A~D gat~ 750-92141 and 750-92142 ~o gener~te address ~ignals Z~XT0100 and ZEXTllOO, in addition to tho~s :~iign~15 requir~d for the generation of control si~nal NE:XTLEWAL100 which is applied to the control 3~ input termlrlal-~ of comp~rator circuit 750-912, /bZ
~ ' .
A la~t group of circuits include a flip-flop regi3ter 750~92150 and a plurality of ~ND gates, an AND/N~ID gate, NAND gat~s and AND~OR g*g~ 750-92151 through 750-92156.
.~ These circuit~ are connected to gener~te signal IFETCHRDY-000 which is applied to the circuit~ of sectlon 750-114.
The gates 7S0-92153 and 750-92154 are connected to gPnerate timing ~ignals D~N2HT101 and DFN2HT100 in re- -~pon e to signal F~T010 ~rom block 750-112. These ~ignals are forced to binary ONES during the second half of a T s~lock cycle of operation.
The flip-flop regi~ter 750-92150 i8 set to a binary ONE ria a ~ir~ ~npu~ AN~ ga~e when ~ND gate~ 750-92151 and 750-92152 fos~c~ signals SETINHRDY100 and C~ICE;LINHRDY-000 to b~nary ON~3S. It is re~et to a binary ZE~O via ~,O~cc ~, a ~econd ~nput AND gate when ~ND gate 750-92155 ~e~e-signal RSINHRDY000 to a binary ZERO. The binary ZERO
output of re~i~ter 750-92150 i8 applied to AND/OR gate 750-92156. Wh¢n signal FINHRDY000 is forced to a binary ZERO, it cau~es gate 750-92156 to force ~ignal IFETC~iRDY-000 to a binary ONE state.

Ib3 ~-- , , Addition~lly, Figure 7e show~ ln greater d~tall the ~wltçh 750-910 and comp~r~'cor clrcuits of block~ 7~0-912 and 750-914. ~he 3wl~ch 750-910 i8 a cro~ r Elwitch which operat~ ln the~ manner prevlou~ly descrlbod. The S W outputs Qelect on~ of th~ two ~ot~ of 8iynal8 applied to the A0 ~nd A1 terminal in accordance with the state of ~lgnal ~ZICllO. The X outputs ~elect ona of the two ~elt~ of ~igno.l~ ~pplied to the A3 ~nd A4 termlnals ln ~ccordan¢~ wl~h the ~t~ta of slgnnl [ZICllO. The Y
~nd Z outputs ~olect one of the four ~ats of ~lgn~13 ~ppl~d to the A0-~4 'c~rmlnal~ ln ~ccord~nce wlth ~he ~tate~ of si~nal~ lZICllO, lZNICLEV100 and [Z~CllO, ZCU
The oultput ~lgnals ~NICLEV0100 ~hrough ZNICLEV2100 1~ from tile Y output to~n~nal~ of ~ir~:uit 750-910 ~re applled to the ~ lnput ~c~inalæ of compar~tor circuit 7~0-912 for compar~on wl'ch the Elgn~l~ RTB~V01û0 - throl~gh RT~L~5V2100 ~rom sectlon 750-102. Th~ compar~tor circuit 750-912 i~ enAbl~d whHn d~coder circult 750-922 2û h~3 decoded an IFl co~ nd ~1.e., si~nal DECODEIF1010 - iR a b~ ry ONE) ~nd ~lqn~l NEXTLEWAL100 1~ ~ bln~Pry ~, Th~ comparl~Qn ro~ult~ in ~hs g~neration o~ 81g~1al8 C~fP~TA~ICLEV100 ar cl CMPDATA/ICI.EV000~ -Ot~lar c~mp~r~tvr clr~ult~ og block~ 750 912 an~
:Z5 750~914 operate ln ~ 81mllar mann~r o ~en~rAt~ sign~
C~ U~I~Y100 ~d C~PALT~EV100. ~n gre~ter ~ ail, ~no~her ~ectlon of clrcuit 750~912 ~30mparUB Ellgnal8 ~ICLEV0100 throuyh ZICI,E:V2100 w~th si~nals 7~0100 through C7~R2100. When ther~ tru~ comp~rl~on, ~ign~l CMPCU~E:Y100 ~ orced tc> a blnary ONE. ~hls sec~io~ i~ en~ d ~1~ a NAND gat~ 750~ 02 when ~lther ~ign~l Z~:VlVAL000 or ~ig~al Z~:V2~ALG00 is a binary ZERO.

~3 The ~ompdrator circuiS 750-914 has two 3ections - enabled by p~ir~ of ~lgn~l~ ZCURLEV100, ~VlV~100 ~nd ZCURL~VOOO, ZI~Y2VAl.10~ hown. ~he fir~t ~ction comp~rt3~ lev~l 1 01gn~1~ Z~:V10100 through Z~Vl~lnn wlth round ro~ln ~ig-lals C711P~0100 through C7R~2100.
When there 1~ ~ txue Gc)mparlson, the output 8 ~ gnal at the A~ termlnal i8 forced to ~ binary ZERO which cauaes NAND
gate 750-91402 to force signal CMPAI.TLEV100 to a binsry ON~ .
. 10 ~n a ~imilar fa~hlon, the second ssction compsre~ -level 2 signals ZhEV20100 through ~L~V22100 with round robin signal~ C7RE~0100 through C7RR2100. When there 18 a true compari~on, the s:~utput signal is forced to a binary ZEP~ which caus~ NAND gate 750-91402 to force lS signal CMPALTLEV100 to a binary ONE.

' l~5 0 DESCRIPTION OE' OPERATION
With reference to Figures 1 through 7e and h~
timing diagram of Figure 8, the operation of the preferred embodiment of the present i~vention will now 5 be de~cribed.
Referring to Figure 8, it is seen that a T clock cycle is divided into first and second halves as illustrated by waveform D. That is, when si~nal FHT100 is a binary ONE, ~hown as the negative going 10 portion in the Figure, this defines the first half of a T clock cycle. When ~ignal FHT100 is a binary Z~RO, shown as the positive portion, ~his define~ the second half of a T clock cycle.
During the first half o~ the T clock cycle, in-15 struçtions are fetched and m~mory data iB written into cache 750-300 when there is no conflict as explained herein. In both cases, the level to be accessed i3 already establi~hed. ~hat i~, for in~tructions, the level is ~tored in either the RICA or RIC~ instruction 20 address regi~ter at the time an I~l or IF2 command received from processor 700 was executed. For memory data, the level i8 stored in one of the regi~ter loca-t,ions of tran~ block buffer 750-102 as a re~ult of the circuit~ of block 750-520 having detected a mi~3 25 condition which caused cache 750 to fetch he re~
quested data from memory. During the second half of a T
clock cycle, el~h~r operand data is accessed from cache or proces~or da~a i~ written into cache in ar-~cGrd~nca wi~h the re~ult3 of a directory searchu .,;.; ~ccordingly, the arrangement of the preferred em~odiment o the presant invention en~les memory dat~ to be written into one cache level while a next ~ ~ o instruction is fetched rom one of the remaining l~vel~
during a T ~lock cycle of operation. This eliminatss the need to hold off or delay the acce.qsing of in~t~uc~ -tion~ to write memory information/data. When the level . 5 into which memory data is being written is the same as the level from which an instruction is being fetched, the acces~ing of an instruction is delayed un-til the writing of memory data has been completed.
A9 described above, an addres~ from processor 700 . 10 is loaded into all o~ the addres~ registerY at the start of the second half of the cycle to initlate a possible read or write operation on the ~econd half cycl~ o~ the T clock cycle. Therefore, in those in~tance~ when th~ wrlting of memory data confl~cts with an instructlon acc~s, an alternate arrang~ment permits . the ~econd hal~ o~ the T clock cycle to be used to per- :-form a procesqor read operation and a memory ~ata wrlte - -: operation.
This la~t arrangement ena~le~ memory data to ~e i 20 written into one cache level while an operand is fetched from one o~ the remaining lsvels during a T clock. !:
cycle ~f operation. -.- However, when the level into which memory data is bein~ written i8 the same as the level from which a processor operand 1~ being fetched, the acce~ing of the operand i~ delayed until the writing of memory data has been completed. ~ conflict also arise~ when memory ~-data is being written into one l~Yel and the proGessor is writing opexand data into another lsvel.
: 30 ~o lllustrate the abo~e op~rations, it will be ass~med ~y way of example that processor 700 is going Q --~
to process the ~equence of in~tructions including a load A instruction (LDA), a ~tore A in~tructlon (STA), a load A ln~truction /sLDA)~ a store A in~truction (STA), and a - -~
next instruction, as shown in Figure 8. ~he format of 5 these lnstructions is shown in the cited copending ~;
patent applicatlons and in the publicat~on "Series 60 (Level 66)/6000 MACRO A~sembler Program ~GMAP)" by -~.
I~oneywell Information Systems Inc., Copyrlght 1977, Order l~umber DDOBB, Rev. 0. It will be appreciated that the --~
10 proces~or 700 executes the four instructions in pipelined fashlon which is illu3trated in detail in the copending -~
pat~nt application "A Microprogrammed Computer Control ~ :
Unit Capa~le of Eflciently Executing a Large Repsrtoire -.
of In~tructions for a High Performance Data Proces~ing i5 Unit", referenced herein. --~
As indlcated hereln, processor 7oo carri~s out ~: various operations during I, C and E cycles of operation i~
in axecuting inSstructions. This results in the i8 uance of cache commands by proces~or 700 to cache unit 750 20 as de~cribed herein. For ease of axplanation~ it i8 .` -a~sumed that thB instructions re~ide in cache unit 750~
300O .
It will be appr~clated that ~t som~ point during instruction proce~slng, pxocessor 700 loads one of the -~
25 instruction addre~s registers RICA~RICB with addres~
~nd level in~ormation~ Thi~ u3ually cc~ about a~ a con~ t.
3equellce o the proceff~or exe~:uting a tran~fer or ?~i branch in~truction which re~ultq in proces~or 700 generat- -~
ing an IFl conunand followed by an IF2 conDnand. Follow~
3~i ing ~he execution of these conanands by cache unit 750, --¦
~h~ f~tching of instruction~ during the first half of a T clock cycle and csperands during the ~econd hal f T `~
~::loc5c cycle proce~d as lllust~ated in Flgure 3.

`~`

-lG4--~;~For ease of explanation, it will be assumed that the IFl command include~ an address which specifies the fetching of the first instruction word of a block of instructions in cache which includes the above mentioned : 5 sequence of instructions. The operation of cache unit 750 in executlng the IFl and IF2 command now will be described briefly. The IFl command upon receipt by cache unit 750 i~ decoded by the decoder circuits 750- -922. The decoder circuits 750-922 cause th~ circuits of block 750-920 to generate sionals for loading the alternate instruction address reglster which i8 as~umed o be RICA with signalQ corr~spondlng to the incremented value of the address included within the IFl command.
That i5, during the first ~ clock cycle, the addres~
signals from switch 750-530 are incremented by one by circuit 750-912 and loaded in~o the RICA instruction address regi~ter 750-900 in response to 1/2 T clock signal lCLKH~100 when signal [RICA100 is a binary ONE.
The signal lRICA100 i8 forced to a binary O~E by the circuits 750-920 when signal ENBSTRBA000 of Fiqure 7e is forced to a binary ZERO during the first half of the first T clock cycl~.
nuring the first half of the first T clock cycle, the IFl command addres~ is loaded lrlto all of the RADR0-7 registers 750-301A through 750-301n via the ZADR0-7 address selection switches 750-302a through 750-302n in respons0 to signal [CLXHT100. During the first half of the T clocX cycl~, signal ENBMEMLE:V100 is a binary ZERO.
Also, siy~al ENBADR1100 is a binary ZERO (i.e., the control ~tate ENEWIFl flip-flop 750-9~026 switches on thc T clock in respon~e to signal [CLKT021, as explained herein). Therefore, each of the pair~ o~ ~ignal8 [ZADR01100, [Z~DR00100 through [ZAD~71l00~ [ZADR70100 are binary ZEROS causing position 0 to be sel~cted as an address source for all ei~ht address registers 750-301a through 750~301n.
The IFl command addxess is also applied as an inpu~ ~o the directory circuits of block 750-502 via ZDAD switch 750-530 for a ~earch cycle of operation.
Sinc~ the instruction block i~ in cache, the circuits of block 750-512 generate the appropriate hit signalR
HITTOC7100 and hit level ~ignals HITLEVC70100-2100 : which are applied to ~ection 7S0-9. Ths de~oding of the IFl command cause~ the hit level signals NITL~VC70100-2100 to be loaded into the level 1 bit positions of the RICA in~truction addr~s register. Al~o, the level 1 valid bit and hit~ml~ bit positions of the RICA regis-tar 750-900 are forced to binary ONES ~i.e., hit ~ignal HITTOC7100 switche~ the hit~mi~R bit p~sition to a bin-ary ONE~. The stored level 1 value is thereafter used to control the operation of the ZCD switch 750-306 during subsequent instruction fetches as sxplained h~rein, The first in~truction acce~sed from the location ~pecified by the IFl addre3s is tran~ferred as an operand word to proce~sor 700 during the s~cond half of the first T clock cycle via position 1 of the ZDI switch 750-312 during the end of the f~x~t T çlock cy¢le7 The fixst in~truction i3 clocked into the ~BIR register 7~4-152 of proce~sor 705 on the T clock in re~ponse to ~ignal tCLKTl00.
The sig~al FJ~MZNICLEV000 enab~es the next in~truc-tion to be tran~erred to processor 700 during the Q~
l7~

second l~alf o~ the ~econd T clock cycle. This 31gnal i8 forced to a ~inary Z~RO by the ci.rcuit~ oF bl~ck 750-920. l~he signal FJAMZNICLEV000 agaln cause~ th~ level sign~ls ZNICLEV000-2100 obtained from RICA register 750-900 to be ~pplied as inputs to the control lnput termin-als of ZCD ~witch 750-306 following execution of the IFl command. That i5, referrin~ to Figure 7c, it i9 ~een that ~ignal FJA~IZNICLEV000 6witches ~$gnal FRCIC000 to-a ~inary ZE~O. Thi~ cau~Qs NAND gate 750-52618 to force signal ZCDIN OEN~B100 to a binary ONE during the ~econd half of the ~c~nd T clock cycle. Signal ZCDINCENAB100 conditions N~ND gate8 750-51210 ~hrou~h 750-51214 to generate ~ignals ~ZCD0100 through [~CD2100 rom signais ZNICLEVQ190 through 2NICL~V2100.
Al~o, ~he IFl command decoded by decoder circuit 750-922 caused the FNEWI~1 flip-flop 750-9202~ to be ~witched to a binary ONE on the T clock in response ~o signal [C~T020, A8 mentioned previou~ly, ~t d~fines the operations during the cycle ~econd) after the IFl 2Q command was received. More 3pecifically, during the fir~t hal~ of the 3econd T clock cycle, the NEWIFl flip-' flop 750-92026 cau~es NAND gat~ 750-92056 to swit¢h - - s.ignal U8EIC000 to a binary ZERO. The ~ignal USEIC000 condition~ NAN~ gate 750-92052 to force the signal ENB~DR1100 to a binary ONE. Since there i8 no m~mory ~ata transfer taking place at thi~ time9 1:he decoder 5i2'Cllit 750 -~0 00 1B not enabled at this time (i~e., Yignal EN~EMLEV1~0 is a b~nary ZER~. Thus, ~ignals ME~L~V000~ thrQugh ME~IEV7000 are b~nary ONES whlle ~.~gnAl~ M~$EV0100 through MæMLxv7loo are binary Z~R~S.

, The multiplex~r circuit 750-30304, in turn, appll~3 the ~inary ONE signals to its output te~minal~ which re-sults in outpu~ signals lZADROO100 through tZADR70100 being forced to binary ONES while mul~iplexer circuit 7sn-3030~ ~orces signal~ [ZADR01100 through [ZADR71100 to binary ZEROS. The~e pairs of siynals condition the adclress selectlon switches 750-302a through 750-302n to ~elect a~ a source of address signals, the RICA instruc-tion addre6s register connected to switch position 1 13 during the flrst half of 'che second T clock cycle.
Accordinyly, the RADR0-7 addres~ registers 750-302a through 750-302n are loaded via the ZIC switch 750-906 with the addr~s~ signals from RICA register 750-900 is~ re~ponse to th~ l/2 ~ clock sigr~al [CLRHTlOI~ during -1 5 the first half of the ~econa cycle. The RICA register 750-900 i~ selected since at ~his time signal [ZIC100 is a bin~ry ZERO. That i~, signal E~BALT100 is a binaxy Z~RO and signal FACTVRIC100, from the binary ZERO output of FACTVRIC flip-~lop of regi$ter 750~92024, is a b~nary - ~0 ZE~O. Th~se signa1s condition ANV/O~ gate 750-92032 to force signal ~ZIC100 to a binary ZERO. The address contents applied to cache unit 750-300 cause a second wor~ from each level to be read out to ZCD switch 750-306.
~h~ lev~l signals ZNICLEV0100-2100 select the word corre~-2~ pond~ng to a ~e ond instruct~on at the level ~perified by the content~ of the RICA r~gister 750-900 to be applied ~ the ZIB line~. It is applied to the 2IB line~ via posltion V of the ZI~ ~witch 750-314.
~ur~ng thP fir~i~ half o~ ~he second cycle, the addre~s signals from RICA xegister 750-900 are again incremen~ed by olle by circuit 750-902 and loaded into 1~2 ~r the RICA r~st~r 750-900 via ~08ition 1 of ~ICIN swltch 750^90~ in response to 1/2 T clock ~lg~al lCLXHT100 wh~n - strobe sig~al ~RICA100 i8 a blnary OME. Again, si~nal [RICA100 is Por~ed to a bi~ary ONE when signal ENBST~3A00 is forced to a binary ZERO during ths second half of the second T clock cycle. At T clock time, the address of the third instruction resides in the RICA reqister 750- :
900. This instruction correspond~ to the LDA instruction of Figure B.
The slgnal FJAMZNICLEV000 when forced to a binary ~RO causes NAND gate 750-92044 to force ~ignal NEWINST000 to a binary ZERO during the second half o~
the second T clock cycle. This causes NAND gate 750-9~046 to force signal [RIRA100 to a binary ONEo On the ~ lock ~t the end of the second T clock cycle, thP second instruc~ion read ou~ from ZCD swi~ch 750-306 is also loadzd into the RIRA register 750-~08. This enables proces~or 700 to load the second instruction into its RBIR reglster in reRponse to T clock signal [CLKT100 at thz end of the second T clock cycle when it has completed execution of the previous in truction.
That is~ when processor 100 has completed executing th~ irst instruction, it forces the RDI~UF line to a ~inary ONE. The ~ignal applied to the RDI~VF line by 2 r proc2ssor 700 causes the circuits of block 750-92020 to : swit h the FRDIBUF flip-flop of register 750-92024 to a binary ONE in response to T clock slgnal ~CLKT020. Hence, ~i~nal FRDIBUF100 cD~respond~ to the signal applied to the kDI~VF line delayed by one clock period. Thus, it :s~ specifies ~hat a signal on the RDIBUF line was received from prooessor 700 during the last cycle. This indicates ,.,; . -, . . . , ~ .. ~ . . .. . ..... .. .

l7~
; 9 ~ -wheth~r the RIRA register 750-308 has to be refllled with another instruction during the fir~t half of the third T clock cycls~ If proces60r 700 doe~ not complete the execution of the previous instruc~ion, the RDIBUF llne signal will not be ~enerated. When the next instruction to be accessed has already been loaded into the RIRA
register 750-303; the register is not refilled during the fir~t half of the next T cloc~ cycle of operation.
The execution of the IF2 command by cache unit 750 i., ~imilar to the IFl command. However, the address contained in the IF2 command i8 only u~ed for a directory se~rch in the ca~e of a hit as assumed in thi3 example.
Th~ result is that the hit lev~l signals EIITLEVC70100-2100 gs~rated by the circui s of block 750-512 are lS loaded lnto the level ~ bit positions of th~ RICA regis-ter 750-900. Al~o, the valid bit and h~t/~iss bit po~itions ar~ forced to binary ONES (i.e., a go condi-tion is a~sum~d).
In this example, it is a~umed that processor 700 completed it~ execution of the previous instruction and forc~d the R~IBUF line to a binary ONE as illustrated by the first ~egakive pGrtiOn of waveform E in Fi~ure 8.
~uring ~he first half o the third T clock cycle, the signal FRDIBUF100 causes the LDA instruction speclfied 25 by the level signal contents of the RICA register 750-900 to ~e loacled into tha RIRA register 750-308 (wave-fonn K) and the RICA r~glster contents to he incremented by one and rel~aded lnto the RICA reg~ster 750-900. ~he ~DR0~7 reglster~ 750-302a through 750-302n as mentioned 3~ ~ove, wer~ loaded from the RICA register 7S0-308 via th~ ZIC positlon of ZADR0-7 address selection swltche~

l74 ~ , 750-302a through 750-302n on the T clock of the previous -cycle.
During the f~rst half of the third cvcle, the addres~
signals applied by address RADR0-7 registers 750-302a S through 750-302n to cache unit 750-300 cause eight words to b~ read out from th~ addressed locations of the eight levels. Al~o, durin~ th~ fir~t half of the third cycle, the circuit~ of block 750-526 of Figure 7c force signal ZCDIC~NAB100 to a binary ONE (i.e., slgnal FICENAB000 is ~orced to a binary ZERO). ~his conditions the circuits of block 750-512 to apply signals ~NICLEV0100 through Z~IC~EV2100 as control ~ignal~ [ZCD0100 through [ZC~2100 to ZCD ~witch 750-306. This.~ause~ the first LDA
~; instruction to be electéd for loading into RIRA register 750-30~ by ZCD ~witch 7S0-306 ~i~e., ~ee waveform K).
Therea~ter, the LDA instruction is loaded into the ~BIR
: regi~ter of proc~ssor 700 on the T clock of the end o the third cycle in response to signal [CLKT100. Also, on th~ T clock of ~h~ previous cycle ~third ~ycle), the RAD~3-7 r~gister~ 750~301a through 750-301n were loaded from RICA register 750-308 via the ZIC position of ZADR0-7 addre~s selection switches 7S0-302a ~hrough 750-302n ~orm J~
On the 1/2 T clock uf the first half of the fourth cycle, the addre~s ~ignals applied ~y the RADR0-7 regis-ters to the eight cache levels cause eight words includ-ing the STA instruction to be read out to ZCD switch 7~0-306. At that tim~, the addre~s fro~ RICA registar 750~900 is in~rPmented by one and restored. Again, the siynals 7.NICLEV0100-210D from the lev~l 1 bit positions ~f RICA register 750-900 select the STA instruction word for loading into ~IRA register 750-308 (waveform K).

.

The STA in~txuction i~ then loaded into the RBIR regl~-tor on the T clock of the end of the fourth cycle.
A~ the end of the fourth cycle, all of the ~ADR0-7 registers 7S0-301a through 750-301n are loaded with ~le next instruction address from RICA regi~ter 750-900 ~owever, as s en ~rom E'igure 8, data words transferred by nlain memory 800, in response to a previous rea~ quad command, are ~tarting to be received by cache unit 750, he read quad command is assumed to have been issued by cacne 750 prior to its execution of the IFl command ~isoussed above as a result of a miss condition (i.e., block reque~ted not in cache). At that time, the block addre~ signals and level siqnals, in addition to other control signals, are stored in transi~ block buffer 1.5 750-102. That i~, write cache flag and read quad flag blt positions of transit blo k buffer 7~0-102 are forced to binary QNES. The block addre~s signal~
correspond to the read quad address applied to the ~ADO
lines 24-31 by processor 700. ~he level ~ignals TBR~0100-2100 written into transit block buffer 750-102 are obtained rom round robin register 750-504 as a consequence of a diractory assignment cycle o~ operation xequired because of having detected the mi~s condltion.
When ~he SIUl00 begins the tran~fer of data, the ~S cixcuit~ o~ blok 750~115 of Figure 4 force memory ~rite request signal MEMWRTREQ100 to a binary ONE.
That i~, the SIU100 forces the DPFS line to a binary ONE indicating that the first two word~ are being trans-ferx~d (waveform P). The SIU100 al~o force~ the ARDA
.~C line to a binary ONE to indicate that the reque~t~d re~d data i3 on the ~S lines. Al~o, the states of the A~A a~d DPFS line~ are clocked into the FARDA and FDPFS
flip~1Ops of block 750-115. The presence of signals 11b on the~e two flip-~lop~ to~ether wlth the wr~te sache fla~
~ nal belng ~ bin~ry ONE raRult ln the circuits o~
bloc~ 750-115 forcing signal MEMWRTRES)100 to a binary Oi~E. At the same time, the SIU applies signals to ~he ~IIFS linesl bits 2 and 3 condition the transit block buffer 750~102 to read out the address and level signal~ for writing ~he pair of data words into cache storage unit 750-300. Also, the contents of the control bit positions including the wrlte cache Plag bit are read out.
The ~MWRT~EQ si~nal when a binary ONX operates to enable decoder circuit 750-30300 of Figure 7b. Upon decoding the level signals TBLEV0100-2100 read out from buffer 750-102, decoder circuit 750-30300 force.s one 15 o~ the eight signals MEMLEV0100 through MEMLEV7100 to a bin~ry ONE. At the 4ame time, the complement siqnal of one of the eight signals is forced to a binary ZERO
(i.e., one of the signals MEt~LEV0000 through ~EMLEV7000~.
The result i~ that ~he appropriate one of the address 20 selection ZADR0-7 switches 750-302a thro~gh 750-302n i5 conditioned to select position 2 rather than position 1 (waveform R). It is only the address selection swltch - specified by the TB level signals that selects position 2. The r~maining address selection switches for the 25 other seven levels select position 1~ As explained herein, this as~ume-~ no conflict between the in~truction and memory data levels.
Therefore, as seen from Figure 8 (waveform R), the transit blocX addre~s on the T clock is loaded into one of the RADR0-7 ragi~ters while the instruction register address from RIRA register 750-900 i~ loaded into the remaining ~ADR registers (wav~orm J). This permit~
~e writing of the first memory data word loaded in'co the R~FSB reyi~ter 750-712 on ~he T clock to be written into cache unit 750-300 at the specifled level on the 1/2 T clock concurrent with acces~ing a~ instruction word from the r~maining sevel levels. The appropriate inQtruc-tion word i5 ~elected a~ an output from ZCD switch 750-306 under control o level 1 sign~l~ ZNICLEV0100-2100 from RICA register 750-900. Since the RDI~UF line on iO th~ last ~ cl~ck was a biTIary ONE, the LDA instruction word from ~CD switc:h 750~306 i~ loaded into RIRA regis-ter 750-308 on the 1/2 T clock (waveform K). On the ~ext T clock, the second LDA instruction i~ loaded into the RBIR r~gister of processor 700 (wavefonn F).
lS Since there are seven level~ available from whlch instructions can be acces~ed concurrent with writing memory data, th~ ~onflict~ are reduced ~ignlficantly.
However, when a conflic~ is detected by the comparator circuits of block~ 750-914 and 750-916, this causes the circuits of block 750~920 to hold up in~truction accessing~ Since processor 700 will not be pullin~
ins~ructions rrom cache 750 on every T clock, this has - little effec~ if any, on processor operation.
IYhen there is a conflict, signal CMPDATA/ICLEV100 .S .-iw.itclle~ to a binary ON~. ~his i~ shown by the dotted portion of waveform V of Figure ~. In greater detail, ~ seen from Figure 7d that the memory write request signal I~E~TREQ100 when foxced to a binary OME, one o~
the section.s of ~he comparator circuits of blocks ~,0 7.~0-912 and 750-914 forces slgnal CMPDATA/ICLEV100 ~o a bin~ry O~l~ and s.igna~ CMPDATA/XC~EV000 to a binary ZERO

l7~
~ , , when the transit block buffer level signal~ RTBLEV0100-2100 are ldentical to the instruction level 1 ~ignals ZI~ICL~Y0100-2100.
The signal CMPDATA/ICLEV100 switches the FIN~RDY
flip-flop 750-92150 to a binary ONE on a T clock during the secon~ half of the fourth cycle when processor 700 forces the RDIBUF line to a binary ONE. Th~ flip-flop 750-92150 when a binary ONE conditions AND/OR gate 750-92156 to switch signal IFETCH~DY000 to a binary ONE.
The x2sult is that the circuits of block 7~0-114 force the IBUFRDY line to a binary ZERO. This i~ indicated by the dotted portion of wavefo~m W in Figure 8. The signals CMPDATA/ICI.EV000 and FINHRDY000 inhibit the circuit~ of block 750~9~0 from incrementing the addre~s con~ents of RICA register 750-900 and strobing RIRA
rt~gis~er 750-308 ~i.e., inhibits generation of ~iqnal~
[RICA100, [RIRA100 and setting of FRDIBUF flip-flop).
The above conflict results in delay~ng the accessing of instructions ~til ths first 1/2 T cloc3c after the 20 four woxds of memory data have been written into cache unit 750-300. Thi~ iY illustra~ed by the dotted por-tions of the waveforlos H, I and ~C in Figure 8 . Thu~ ;, the c~econd I.DA instruction will not be loaded ihto the- pro-ce3sox' 5 R~IR register until 3 T clock ~ycleY later.
The remaining three wor~s of memory data are written into cache unit 750-300 in the manner previously de~cribed. Of course, where there is no conflict, each o~ the three woxds will be wr~tten into cache unit 750-300 concurrently with the pulling of instruction words fxom cache unit 7s0-300 (waYeforms R, S and J, X of Fiyure .g). ~ha~ ia, as long a~ the write cache flag cont:rol bit raad bUt from transit block buffer 750-102 l7cl is a ~lnary ONE, the data word is clocked from tlle ~DFS register 750-702 lnto the RDFSB regi~ter 750-712 on a next T clock signal and written into cache unit 7.50-300 on the following 1/2 T clock. These operations are repeated twice for each pair of read quad data words received from SIU100.
. Also, during a first T clock cycle (fourth cycle which corresponds ~o an I cycle) processor 700 begins executing the L~A instxuction as explained herein. This involves the formation of an address which is included in a read ~in~le command forwarded to cache 750 by pro-cessor section 704-4 of Figure 3e. The command is coded to specify a memory read quad operation for fetch-ing a 4 word block from memory 800. In ~reater detail, tAe generated addre~s loaded into the RADO register 704-46 serves as the command addre~s. Additionally, command bits 1-4 and . zono bits 5-8 are gen~rated by the circuits 704~118 of Flgure Sc and switch 704-40.
~he zone bits 5-8 are 3et to bina~y ONES, ~ince they are not used for read commands. Command bits 1-4 are forced to a command code of 0111 by the decoder circuit~ of ~ -block 704-118 (i.e., quad operation). The circuits of block 704-108 qenerate the cache command siqnals coded to speoify a read singla type command which are applied to the DMEM line~. The decoder 704-120 foxces the DREQC~C
line to a binary ONE. As seen from Figure 8, during the next T clock cycle 5, which corresponds to a C cycle, processox 700 ~ignal~ cache 750 of the cache reque~t by forcing the DREQCAC lin~ to a binary ONE (i.e., waveform 3() ~).
'~he addre~ contained within the read oommand i8 applied via ZDAD switch 750-530 as an input to ZADR0-7 l~o swi~che3 750-301a through 750-301n in addition to the directory circuits of block~ 750-500 and 750-502. As ~een from Figure 7c, durin the fir~t half of tha fifth cycle, AND/NAND gate 750-92051 and NAND gate 750-92052 S force signals ENBMEMLEV100 and EN~ADR1100 to binary ZEROS. The result is that the circuits of block 750-303 causa the pairs of control signals [ZADR00100, [ZADR01100, through [ZADR70100, [ZADR71100 to be binary ZEROS.
Accordingly, the ~ADR0-7 switche~ 750~302a through 750-302n select ZDAD ~witch 750-532 a~ an addres~ source.
As seen from Figure 8, the read command addres~ is loaded into the RADRO-7 registers 750-301a through 750-301n for application to all levels on a 1/2 T clock in .
response to signal [CLXHT100 ~i.e., waveform tl). When 15 a hit condition i~ detected by the circuits of block - 750-512, this cause~ the operand address word at the specified level to be read out from ZCD ~witch 750-306 during the second half of the T clock cycle as illustrated in Figure 8 (i.e., waveform I).
In greater detail, with reference to Figure 7c, it ~: is seen that the circuits of block 7S0~526 force signal GS~C11100 to a binary ONE during the 3~cond half of a T
: - clock cycle. The hit ~ignals ZHT1100 through ZHT7100 from c;rcuit3 750-546 through 750-552 are used to control Z5 ~.e operation of ZCD ~witch 750-306 in accordance with the re~ults of the ~earch operation ju~t performed. In the case of a~hit condition, when one af the signal~
ZHT1100 through ZHT7100 ie forced to a binary ONE and the hit detected lavel i~ used to generate signal~
~CD0100 through lZCD2100. This re~ult~ in the operand addre~e word from the level at whioh the hit occurred to b~ applied ~o the ZDI lineq via position 1 of ZDI switch . `~ 181 750-312. As seen from Figure 8, the comparison o~ bits 10-23 of the read command address, the encoding of the hit level signals when there is a hit and the enabli~g of the.
~CD switch 750-526 requires a full T clock cycle of operation.
The operand word applied to the ZDI lines is loaded into the processor's RDI data register 704-164 of Figure 3c in rasponse to T clock signal [CLKT100 (waveform I of Figure 8).
When a hit condition is not detected, the output signals . 10 applied to the ZDI lines are still loaded into RDI data register 704-164, but the processor 700 is prevented from ~urther processing or held via the CPSTOP line. When the requested information is obtainèd ~rom memory by cache unit 750, the contents O f RDI data register 704-lS4 are replaced at which time the D~TARECOV line is forced to a binary ONE and processor 700 is permitted to continue processing (i.e., the CPSTOPOOO line is forced to a binary ONE).
~Rhile it is to be seen that the read command address from processor 70~ was ]oaded into the RADR register 750-301 on the 1/2 T clock in response to signal CCLKHT100, other addresses also are loaded into the RADR register 750-301 during ~he o-ther 1/2 T clock times, but they are not meaningful. Hence J they are not shown in Figure 8.
~5 lt will be noted from Figure 8 that processor 700 prior ,,,. . l.~Z

to generating the read command eorces the RD~IBU~ line to a binary ONE a second time during the third cycle. This signals cache unit 750 that the processor 700 has taken the first LDA instruction on the previous T olock. Hence, during the first hal~ T of the fourth cycle, cache unit 750 re~ills the RIRA register 750-308 with -the next instruction.
This corresponds to the STA instruction in Figure 8.
In greater detail~ it is seen from ~igure 7c that the circuits of block 750-526 force signal ZCDICENAB100 to a binary O~E. This conditions -the circuits of block 750-512 to apply level signals ZNICLEVO100 through ZNICLEV2100 from RICA instruction register 750-900 as control signals ~ZCDO100 through ~ZCD2100 to ZCD switch 750-306. This causes the STA instruction at the location speci~ied by the address contents of RADR register 750-301 loaded on the previous T clock (waveform J) to be selected for loading into RIRA register 750-308 by ZCD switch 750-360 (i.e., waveform K). Thereafter, the LDA instruction is loaded into the RBIR regi.ster Oe processor 700 on the T clock in response to signal ~CLKT100 (i.e., waveform L).
The LnA i.nstruction remains in the RBIR register only ~or one clock period. Tllere.rore, the STA instruction is loaded into the RBIR register on the T clock as discussed a~ove.
Figure 8 ~llustrate.s the operation of an alternative 182a embodiment of the present invention. In this embodiment, instructions are always fetched during the first half o~ a T clock cycle. The writing of memory data occurs concurrently with the accessing of instructions when there is no conflict between levels.
However, in the case of a con~lict detected during -the first hal~ of the T clock cycle, memory data is written during the second half of the T clock cycle. The writing o~ memory data proceeds concurrently with the processor's accessing of operands when the levels are not the sæme. In the case where a processor read /

ZO

/

.. _ . ... . _ . . . . . .. .

~3 command ~p~cifies accessing an operand at the same l~vel in~o which the memory data is written, tha acces~ing of the operand is del~yed by at least one T clock until no conflict i8 presentO Of course, a processor write command will cause a conflict since the writing of data can only proceed throu~h tha æCDIN switch 750-304.
It will be appreciated that the alternate embodiment, requires additional clrcuits for storing the hit level : .slgnals, for det~ct~ng the conflict and for controlling ~he hold logic c~rcuit~ of block 750-116 and the operation of the data recovery clrcuits as explained herein.
The w~v~orms H and ~ illustrate the c~ce where a memory da~a address i3 loaded into a specified one of ~ 15 the R~DR0-7 regi~ter6 750-301a throuqh 750-301n wh~le the : processor read command addres3 is loaded into 3even of addre~3 r~gisters 750-301a throu~h 750-301n. That i9, the memory write request signal MEMWRTREQ100 i8 forced to a binary ONE during the second half of the fifth T clock cycle, cau~es one of the Z~DRO-7 addres3 ~el~ction switche~ 750-302a through 750-302n spe~if~ad by level ~ignal~ RTBLEV0100-2100 to switch from position 0 to - positlon 2. Thi~, in turn, load~ one vf the RADR0-7 regis~ers with th~ address rom transit block buffer 750-102. The remaining seven regi~ters are loaded with the read command addre~s from ZDA~ switch 750-530.
: On the T clock at the time when the operand ou~put from cache 750 applled to the ZDI line~ via ZDI switch 750-31~ i~ load~d into the processo~-'s RDI register 3~ lwa~ef~nm I3, a compari~on $8 made between the hit level and leYel into which memory data is being written. The -17g-, comparison i~ made by compari~on clrcuits such as those of block~ 750-912 and 750-914 of Pigure 7d. Anytime the comparison cir~uits detect that the hit level ~ignal~
resulting from the ~earch cycle of operation (i.e., sig- '7 nals ZCD0100-ZCD2100) are identical to the level si~nals RTBL~V0100-2100, they force output compare signal CMPDATA/ -OPERLEV to a binary ON~ (waveform X). This cond~tions the hold circuit~ of block 750-116 to force the CPSTOP000 - line to a b$nary ZERO (waveform Y). The true comparison, in effec~ cause~ the cache circuits to simulate a miss condition until the conflict of writing memory data and opexand accesses no longer is present.
As seen from waveforms H and I of Figure 8, the detect~on of a conflict-delays the accessing of thc operand until the wr.iting of memory data has been com-pl~ted, At ~hat tlme, the operand i5 acce6sed from cache unit 750-300 and strobed into RDI regi~ter of pxocessor 700 by the data recovery circuit~. At that time, processor 700 is rele~sed (i.e., the CPSTOP000 line is forced to a binary ONE).
It will be apprec~ated that when the memory wri~e request signal MEMWRTREQ100 i~ forcèd to a binary ONÉ
during the first half of a T clock cycle, the level ~ig nals ~T~LEV0100-2100 ~xom transit block buffer 750-102 ~S ar~ saved in a register for writing memory data during the ~econd half of a T clock cycle.

. Now, the de~crlp~ion of F~gure a w~ll be com-plet2d with refexona~ to the firs~c embodiment, Th~t 1~, . the STA ln~ruation c~u~e~ the processor 700 to g~nerate a second cache requ~t to cache unit 750. In greaS~r 5 detail, the STA in~truc~tlon requlres two prc:ce~sor cyclss ~or ~ompletl~n. Durlng the first cycle, processor 700 carrie~ out operatlon~ ~imllar to tho~e requlred ~or th~
IJDA inAtructlon whlch re~u~tY ln gen~rating 4he ~ddress.
Thi~ addre~ 1B included in the wrlte ~ingle comman~
10 whlch proo~aor 700 forw~rd~ to csehe unlt 750 ~nd the end o~ tho ~ir~t cache cycle. ~t that tlm~, proce~qsor 700 ~orc~ th~ D~QCAC line to a binary ONE (w~vafonn M~ .
~ 0n ~ro~n ~lguxe 8, the wri~e command addr~ss applled to th~ ~ADO~/RhDO lines 1~ lo~d~d into RADR
15 r~glat~r 750-301 rom posltion 1 OL~ ZADR ~witoh 750-302.
~' ~url~n~ ~h~ ~lr8~ h~l~ of the ~ix~h oyclo, when there i~
!. no ~.emory d~ta tr~0r, th~ clr~ult~ o~ bloc3c 750-92000 o~ Figurl3 7t ~oro~ ~lgnals ENBMEML~V100 ~nd ENPJ~Rli.00 to binary ~RO~. This cau~e~ th~ clrcult~ o~ blo~k 750-2û 303 to ~orce th~ .of slgnal~ ~ZADR00100, tZAD~0110O
through ~ADR7olûo~ tZADR71100 to blnary 2~0~.
Accord~ ly, X~DR0-7 ~wlt~hq~ 7S0-302a 'chrough 750-302n connect the ad~r~ cutput ~ ZDP~ ~witch 750-530 al3 th~ addr~ put to RADR0-7 regi~ter~ 750~3ûls through 25 750-301n. W~ the aommand wri~ addre~ ¢lo~ked ~-nto R~M0-7 ~gi~re Oll ~h~ 1~2 T olock in re~ponsa to ~ignal IC~XHT100 ~nd ~ppli~d ~o all o~ the l~vels ~
nothillg h~pen~ ~t ~ tlm~, ~lnce the direatory ~e~rch mu~t be p~rl~onned fo~ th~ wrlte command li~7 ~ no writ~
30 31gn~1~ are yQA~s~tet). The wrlt~ ~onunand ~ddr~s~ i9 ~,~ved ln ~ch~ RD~ rngl~ter 7S0-532 ~or w~iting th~

~b proce~or ~lata word during the next T clock cycle.
The write aon~nand ~ddress 1~ al~o applif~d to d~ rectorie 750-500 and 750-502 for carrying out a search cy~le of operation. A3 mentioned, the qearch S operation requlres a ~ull T clock cycle. As ~een from Fi~ure 8, the write command addre~s saved in the RD~ reg~t~r 750-532 is applied v~a positior 1 Qf~ ZD~D ~witoh 750-530 to the ZADRO-7 ~witches 750-3U2 during th~ fl~st hnlf of the seventh clock cycle.
Again, ZADRO-7 3witohes 750-30Z connect the address out-put of ZDAD Ywitch 750-530 as the addre3s input to I~DRO-7 regis~ers 750-301a through 750-301n. The write comm~nd address i~ again clocked into address registers 750-341a through 750-301n on the 1~2 q' clocl~ ln response to aignal ~ 3TlOQ.
Re~errlng to E'igure 7 e, lt i~ seen that during the second half of the ~eventh T clock cycle, ~he multi~
plexer circui t 7$0-9Z002 applies the hit level signal~
LEtl0100 through RHX~LEV2100 from ~e circu~ t~ of 29 block 750 S12 a~ inputs to register 75û-92006. Thase ~igna1s ar~ c10~ked into regis~er 750-92006, in re~pon~e.
~o 1/2 T clock ~igna1 ~CLKHT021, and applied to the in-. ~ puts of decoder c~rcuits 7$0-92008 ~hrough 750-92014.
At th~ ~am2 tlme, tl e zon~ ~8i~na18 ZONE0100 through ZONE-~5 3100 rom ~wil~ah 750-144 obta1ned from proces~or 700 ar~ al~o 10aded into regi~ter 750-9200~, durin~ the ~acond h~1 f of the cy~1e .
During the ~e~ond cy~1e of the STA instruction, p~oce3~0r 70û t~n0~erq ~he data word via the ~P,DO 1ine~
and the ~DO regi~t~r to caahe unit 750. At ~his time, ~he ~ircu~ t~ o~ ~10~3k 750 526 condition ZCD~N switch 750-30~ tc~ apply the proces~or data word via position 1 a~ an ` 1~
input to all of ~he level~ of cache ~torage unit 7~0-300. The decoder circuits of block 750-920000 force one of th~ wrlte signals of one of the ~ets of w~ite Rignal~ (2 . g. 3ignal WRT00100) for writing the data -.
word into the appropriate zone (waveform o).
As ~een from Figure 8, during the third cycle, pro-ce~sor 700 again force~ the RDIBUF line to a binary ON~
indicating that the STA instruction was loaded into the R~IR reg$ster~ During ~he first half o~ the fifth 10 cycle, the RDIBUF flip-flop of register 750-92024 set by the RDIBUF ~ignal cau~e3 the 6econd LDA in~truction, - ~tored at the loca~lon spe~ified by the conten~ of RA~R reg~ster 750-301, to be loaded into RIRA regi~ter 750-303 (waveform ~ hat i8 ~ the RDIBUF flip flop 15 CdU8Q~ signal ~A~EINST000 to be forc~d to a binary ZERO, which for~es signal lRIR~100 to a binary ONE.
The RADR0-7 regi~ters 750-301a throu~h 750-301n are loaded with an addre3~ from RICA in~truction register 750-900,durlng the ~econd half o~ the fourth cycle via ZIC
20 switch 750-906 and position 1 o ZADR switch 750-302 ; (waveform J). This addre~ i8 applied to the address : inputs of all level~ of cache storage unit 750-300.
Also, during the fir~t half of th~ fifth ~y~le, the addre~s contents of the RICA regi~ter 750-900 are incremented 25 by one and loaded bac~ into the register 750-900. ~he read out of the appropriate instruction from ZCD switch : 750-306 proceeds under the control of the level ~ignal~
ZNICLEV0100-2100 from switch 750-910 which are used to - genexate ~$gnals ~CD0100-2100.
While the RIRA reyi~ter 750-308 1~ loaded with the ~e~ond L~A in~tructlon, it i~ seen ~rom Figure 5 that it i~ not tran~erred to the RBIR regi~ter until the . ' .

.. . . . . . .. ... .. _ .

- `~

~ixth cycle (waveform F). The rea on is that the STA
in~truction, as mentionod previously, require~ two s.
Following ~he completion of the I cycle execution of the STA instruction, processor 700 forces the RDIBUF
line to a binary ONE (waveform E). A~ -~een from Figure 8, the second LDA lnstruction, followin~ its loading into the RBIR register, results in processor 700 forward-ing a second read comn~and to cache 750, as signalled by the forcing of the DREQCAC line to a binary ONE (wave-form G). In the manner previously de~cribecl, the read command addres~ from proces~or 700 is loaded into ~ADR0-7 reg~ ters 750-301a through 750-301n,during the ~ first half of th~ eighth cycle,in re ponse to signal : 15 ~CLKHT100 (wave~orm H). During the ~econd half of the cycle, the operand addre~s word, from the level at which the hit condition occurred, is loaded into th~ proces~or P~DI register via the ZDI lines.
Because bhe ~DIBUF line was forced to a binary ONE
during the sixth cycle, thi3 again cause~ a new in~truc-tion corresponding to the ~econd STA instruction to be loaded into RIRA register 750-308, durlng the first half of the sevsnth cycle (waveonm K). The STA instruction i~ loaded into the processor R~IR regIster on the T
cloc~ during the second half of the ~eventh cycl~ (wa~-form ~3.
. In the manner pr~viou~ly de~cribed, the proce 80r 700 generates a ~econd write cQmmand whlch i8 forwarded to cache unlt 754 durinq the nlnth cycl~ and signalled 30 by forcing the OREQCAC line to a binary OME (waveform M).
The wrlte conunand addre~ i6 loaded lnto the RADR0-7 , ~ . . .

v --~ 189 registers 750-301a through 750-301n from the ~AD0 lines and RDAD register 750~532 on the 1/2 T eloek,in response to signals ~CLKHT100 (waveform N), During the seeond half o~ the tenth eyele, the proeessor data word is written into caehe unit 750-300. Also, ~.he next instruetion is loaded into RIRA regis~er 750-308, during the first hal~ o~ the elghth cyele (wave~orm K).
From the foregoing, it is seen how the arrangement o~
the pre~erred embodiment enables a plurality o~ operations to take plaee simultaneously, and how the arrangement o~
the preferred embodimen~ minimizes the inter~erenee among the di~erent types of operations required to be per~ormed by a eache system. Aeeordinglyj this results in improved systems performanee in terms of e~fielency and hit ratio.
Also, it is seen how the arrangement o~ the pre~erred embodiment enables instruetions to be accessed ~rom eache ~torage unit 750-300 during the ~irst half of a T clock cycle and the writlng or read ou-t of proeessor operands into and ~rom caehe storage unit 750-300 during the second hal~ oi~ the same T eloek cyele.
It will be ~ppreelnted that in a system which has a hi~h hit ratio suoh as the preferred embodiment, eonslderably more instructlorls are aceessed from cache than memory data ~e:ing written into cneh~. Hence, the split cycle arrangement 2~ mlnimiY,es interferenee t-etween such instruction and processor oporand nccesses.

-19~-Also, the arrangement prevents interference between the ~riting of memory data and processor operand accesses.
As mentioned, during the first portion of each T clock cycle, when there is data to be ~ritten into cache storage unit 750-300, the circuits of block 75~-115 force the memory ~rite request signal to a binary ONE. This results from the ~IFS steering signals returned by main memory 800.
Bits 2 and 3 are used to select the address contents of one of the transit block buffer locations for read out into the RADR register 750-3010 Referring to Figure 7e, it is seen that signal ~EMWRTREQ100 from 750-115 causes AND/NAND gate 750-9205 to force signal ENBME~LEV100 to a binar~ ON~ and signal ENBMEMLEV000 to a binary ZERO. This causes AND gates 750-30302 and AND gate 750-30304 to force control signals C~ADRO1100 and C~ADRO0100 to a binary ONE and a binary Z~RO, respect~ively. The result is tha~ the ZADR switch 750-302 selects position 2 ~ZTBA) instead of position 1. Accordingly, the transit block buffer is connected as the address source for the RADR register 750-301.
On the T clock signal, the transit block buffer address is loaded into the RADR register. On the 1/2 T clock follo~ing that T clo~k, the memory data signals which are loaded into RDFSB register 750-712 are written into cache storage unit 750-300 via ZCDIN switch 750-304 at the address read out from buffer 750-102.

~.~

As seen from Figure 7e, the signal. MEMWRTREQ100 forces the bottom -three flip-:elops o~ register 750-92006 to binary ONES. This enables all of the decoder circuits 750-9200B
through 750-9201~ for operation. Accordingly, each of these circui.-ts decodes the level signals RTBI~VO100 through R'rUL,EY2100 and forces one of its outputs to a binary ONE.
This causes all four bytes Or the data word to be written i.nto cache unit 750-300. It will be appreciated that the rema.ining words of the data block are written into cache ~lO UDi.t 750-300 in the same manner during the first half of successive T clocls cyclo~s of opera-tion.
It wi~l. he noted tha-t in those instances where memory data is being received preventing ins-truction accesses, the circuits of block 750-920 prevent -the IRUFRDY line :from indicating a ready condi-tion. That is, -the signal MEMWRTR~Q100 ca~lses the inhi.b:it ins-truction ready EINEIRDY flip-~lop 750-92150 to be :forced -to a binary ONE. This causes AND/OR gate 750-92156 to force s:ignal IFRTC}IRDYOOO to a binary ONE. The result is th~-t si~nal IBUFRDYlOO, ~enerated by the circuits of block ~) 750-:ll5, is :force(l to a binary ZERO indicating a non-ready ccG~dit:ion.

';

Claims (39)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A cache unit for use with a data processing unit for providing fast access to information fetched from a main store coupled to said cache unit in response to commands received from said data processing unit, said cache unit comprising: a buffer store including a plurality of addressable word locations for storing said information address switch selection means having a number of inputs for receiving a corresponding number of addresses from a corresponding number of address sources and an output;
address register means coupled to said output and to said buffer store, said address register means for storing the address specify-ing the word location to be accessed during a cache cycle of operation; control circuit means coupled to said address switch selection means for generating coded control signals identifying which address source is connected to supply said address to said address register means; and, timing means for generating timing signals for defining a number of intervals of said cache cycle of operation, said timing means being coupled to said control means, said control means being conditioned by said timing means during one of said intervals to enable said address selection means to select an address for loading into said address register means from one of said address sources and said control means being conditioned during another one of said intervals to enable said address switch selection means to select an address for loading into said address register means from another one of said address sources for enabling the accessing of said information specified by both address sources during the same cache cycle without inter-ference.

2. The cache unit of claim 1 wherein said information includes data and instructions and said buffer store word locations are organized into a plurality of levels, and wherein said timing means generates first and second timing signals for defining first and second intervals corresponding to said number of intervals.

3. The cache unit of claim 2 wherein said levels are organized vertically for accessing information on a word basis.

4. The system of claim 2 wherein said timing means includes:
a clocked bistable element having a clock input terminal, a gate input terminal and at least one output terminal; first input means for receiving a first series of clock pulses for defining a time interval which is one-half the duration of said cache cycle, said first input means being connected to said clock input terminal;
and, said input means for receiving a definer clock pulse signal, said second input means being connected to said gate input terminal, said bistable element being conditioned by said clock pulses and said definer clock pulse signal to produce at said output terminal, a bistate signal whose first and second states define said first and second intervals of said cache cycle.

5. The cache unit of claim 2 wherein control means includes:
first gating means coupled to receive said first timing signal from said timing means and said gating means being operative to generate an output signal for enabling the loading of address information into said address register means during said first interval for accessing information from said levels of said buffer store during said second interval of said cache cycle; second gating means coupled to receive said second timing signal from said timing means, said second gating means being operative to generate an output signal for enabling the loading of address information into said address register means during said second interval for enabling access to information stored in said levels of said buffer store during said first interval of said cache cycle; and, said address switch selection means having control inputs connected to said first and second gating means, said address switch selection means being conditioned by said coded signals for enabling said address switch selection means to load said address register means with said addresses from said address sources during said first and second intervals of said same cache cycle of operation.

6. The cache unit of claim 5 wherein said one of said address sources includes: an instruction address register coupled to said one of said inputs of said address switch selection means, said instruction address register including a number of bit positions, a group of said bit positions for storing an address specifying a next word location within said levels of said buffer store from which an instruction word is to be accessed during said first interval of said cache cycle.

7. The cache unit of claim 6 wherein each of said commands includes a command code and an address and said another one of said address sources includes an input circuit means coupled to said processing unit for receiving said address of each said command and said input circuit means being connected to said another one of said inputs of said address switch selection means, said input circuit means being operative to apply said command address specifying a word location within each of said levels of said buffer store from which an operand word is to be fetched or into which an operand word is to be written during said second interval of said cache cycle.

8. The cache unit of claim 7 wherein further one of said address sources includes: a buffer for storing at least one address derived from a command which has a command code specifying a read type operation, said address specifying the word location within said buffer store into which the information requested from said main store by said command is to be written; and, means coupled to said buffer and to said address switch selection means, said means for applying said address to a further one of said inputs of said address switch selection means for loading into said address register means enabling the writing of said information into said buffer store during said first interval of said cache cycle.

9. The cache unit of claim 8 wherein said buffer is arranged to store a set of level signals specifying which one of said levels in which said requested information is to be written and said cache unit further including: input switch means includ-ing at least one set of input terminals coupled to receive inform-ation to be written into said buffer store during said cache cycle and a set of output terminals coupled to apply said information to each of said levels of said buffer store; and, write control circuit means comprising decoder means for receiving said set of level signals from said buffer, said decoder circuit being enabled in response to said set of level signals to generate a set of write control signals for writing said information into the location and level of said buffer store specified by said buffer during said first interval.

10. The cache unit of claim 9 wherein said unit further includes: an input data register coupled to receive data words from said main store transferred in response to one of said com-mands having a command code specifying a read type operation previously stored in said buffer, said input data register being coupled to said one set of input terminals of said input switch means for enabling said data words to be applied to said levels of said buffer store during said first intervals of said cache cycle for writing into the designated level.

11. The cache unit of claim 8 wherein said control means further includes third gating means for generating memory write enable signals enabling said requested information to be written in-to said buffer store during said first interval, said third gating means being connected to condition said first and second gating means for generating said coded control signals to cause said address switch selection means to switch from a first position to a second position for selecting said address from said buffer in place of said address from said instruction address register for loading into said address register means.

12. The cache unit of claim 11 wherein said unit further includes: instruction ready control circuit means for generating an output signal to said data processing unit for signalling when instructions are ready to be accessed from said buffer store; and, inhibit control means coupled to said third gating means and to said instruction ready control means, said inhibit control means being conditioned by said third gating means to inhibit said instruction ready control circuit means from generating said output signal when said requested information is being written into said buffer store during said first interval.

13. The cache unit of claim 10 wherein said third gating means generates first and second memory write enabling signals designated as ENBMEMLEV and respectively in accordance with the expressions:

and wherein signal MEMWRTREQ indicates that said requested information is to be written into said buffer store and signal FDN2HT defines said second interval, and said first and second gating means generates first and second coded control signals [ZADRO and respectively in accordance with the expressions:

and wherein signal ENBADR is a binary ONE during said second interval, for selecting an address from said instruction address register, said buffer and said input circuit means for loading into said address register means when signals [ZADRO, have the values 00, 01 and 10 respectively.

14. The cache unit of claim 12 wherein said control means further includes fourth gating means for generating an output signal for indicating when a predetermined type of command from said data processing unit was decoded during said first interval, said fourth gating means being coupled to said first and second gating means, said fourth gating means being operative in response to said pre-determined type of command to force signal ENBADR to a binary ONE
enabling said address switch selection means to select an address from said instruction address register means for loading into said address register means during said first interval for accessing an instruction from said levels of said buffer store during said second interval.

15. The cache unit of claim 13 wherein said predetermined type of command includes a command code specifying an operation for loading the address of a next block of instructions into said instruction address register means for enabling said data process-ing unit to access further instructions from said buffer store during subsequent cache cycles.

16. The cache unit of claim 2 wherein each of said commands includes a command code and an address and wherein each level of said buffer store contains a number of blocks of said word locations, each level and each block being defined by a level address and a block address respectively and said cache unit further including:
a directory having a plurality of locations corresponding in number to the number of levels in said buffer store and being addressable by said level addresses, each location of said directory storing block addresses of blocks of words within the associated level stored in said buffer store, said directory responsive to said level address corresponding to a low order portion of said command address to read out said block addresses corresponding to a high order portion of said command address; comparison means coupled to said directory for comparing said block addresses read out from said directory with the high order portion of said command address and generating hit detection signals indicative of whether or not the information being accessed is stored in said buffer store; and, directory level control means coupled to said timing means to said comparison means and to said buffer store, said directory level control means in response to said hit detection signals being operative to generate a set of hit level signals during said second interval of a next cache cycle for enabling the transfer of a requested operand word to said data processing unit specified by each command having a command code specifying a read type operation in accordance with the results of a directory search operation performed during the previous cache cycle without interfering with transferring instruction words required by said data processing unit.

17. The cache unit of claim 16 wherein said cache unit further includes: output multiposition switch means including a number of sets of input terminals corresponding to the number of levels, a plurality of output terminals and a set of control input terminals; and a number of conductor means, each coupling a different one of said number of sets of input terminals to said buffer store for receiving signals read out from a different one of said levels of said buffer store and said control input terminals being connected to receive said set of hit level signals, said multiposition switch means being conditioned by said set of hit level signals to apply to said output terminals said signals from one of said levels designated by said level signals as the operand word to be transferred to said data processing unit during said second interval of said next cache cycle.

18. The cache unit of claim 17 wherein said cache unit further includes: input switch means including at least one set of input terminals coupled to receive information to be written into said buffer store during said cache cycle and a set of output terminals coupled to apply said information to each of said levels of said buffer store; and, write control circuit means comprising:
decoder circuit means including first input means for receiving said set of hit level signals and second input means for receiving write control signals specifying those portions of said information applied from said input switch means to be written into said buffer store, said decoder circuit means being operative in response to said set of hit level signals to generate a set of write control signals for writing said information into the designated one of said levels of said buffer store during said intervals.

19. The cache unit of claim 18 wherein each of said commands whose command code specify a write operation further includes: a number of data words to be written into said main store, and wherein said input switch means includes another set of input terminals, said cache unit further including input conductor means coupled to said another set of input terminals for enabling said number of data words to be applied to all of said levels of said buffer store during said second interval of said cache cycle for writing therein when said hit detection signals indicate that the block of information words specified by said command resides in said buffer store.

20. A cache unit for use with a data processing unit for providing fast access to instructions and data fetched from a main store coupled to said cache unit in response to commands received from said data processing unit, said cache unit comprising: a buffer store including a plurality of addressable word locations organized into a plurality of levels for storing said data and instructions; multiposition address switch selection means having a number of sets of input terminals for receiving a corresponding number of sets of address signals from a correspond-ing number of address sources, a plurality of output terminals and a plurality of control input terminals; an address register coupled to said plurality of output terminals and to said buffer store, said address register for storing the address specifying the word location within said levels to be accessed during a cache cycle of operation; control circuit means coupled to said plurality of control input terminals of said multiposition address switch selection means, said control means generating coded control signals identifying which address source is connected to supply said address to said output terminals; and, split cycle timing means for generating timing signals for defining first and second intervals of said cache cycle of operation, said timing means being coupled to said control means, said control means being conditioned by said timing means during said first interval to enable said address selection means to select an address for loading into said address register applied to a first one of said sets of input terminals by a first one of said address sources and said control means being conditioned during said second interval to enable said address switch selection means to select an address for loading into said address register applied to a second one of said sets of input terminals applied by a second one of said address sources for enabling the performance of different types of operations without interference involving the accessing of data and instructions specified by said first and second address sources during the same cache cycle.

21. The cache unit of claim 20 wherein said levels are organized vertically for accessing information on a word basis.

22. The cache unit of claim 20 wherein control circuit means includes: first gating means coupled to receive a first timing signal from said timing means and said gating means being operative to generate an output signal for enabling the loading of address information into said address register during said first interval for accessing information from said levels of said buffer store during said second interval of said cache cycle;
second gating means coupled to receive a second timing signal from said timing means, said second gating means being operative to generate an output signal for enabling the loading of address information into said address register during said second interval for enabling access to information stored in said levels of said buffer store during said first interval of said cache cycle; and, said plurality of control input terminals of said address switch selection means being connected to said first and second gating means, said address switch selection means being conditioned by said coded signals for enabling the loading of said address register with said addresses from said address sources during said first and second intervals of said same cache cycle of operation.

23. The cache unit of claim 22 wherein each of said commands includes a command code and an address and said first one of said address sources includes: an input circuit means coupled to said processing unit for receiving said address of each said command and said input circuit means being connected to said first one of said sets of input terminals of said address switch selection means, said input circuit means being operative to apply said command address specifying a word location within each of said levels of said buffer store from which an operand word is to be fetched or into which an operand word is to be written during said second interval of said cache cycle.

24. The cache unit of claim 23 wherein said second one of said address sources includes: an instruction address register coupled to said second one of said sets of input terminals of said address switch selection means, said instruction address register including a number of bit positions, a group of said bit positions for storing an address specifying a next word location within said levels of said buffer store from which an instruction word is to be accessed during said first interval of said cache cycle.

25. The cache unit of claim 24 wherein further one of said address sources includes: a buffer for storing at least one address derived from a command which has a command code specifying a read type operation, said address specifying the word location within said buffer store into which the information requested from said main store by said command is to be written; and, means coupled to said buffer and to said address switch selection means, said means for applying said address to a third one of said sets of input terminals of said address switch selection means for loading into said address register enabling the writing of said information into said buffer store during said first interval of said cache cycle.

26. The cache unit of claim 25 wherein said control circuit.
means further includes third gating means for generating memory write enable signals enabling said requested information to be written into said buffer store during said first interval, said third gating means being connected to condition said first and second gating means for generating said coded control signals to cause said address switch selection means to switch from a first position to a second position for selecting said address from said buffer in place of said address from said instruction address register for loading into said address register.

27. The cache unit of claim 26 wherein said unit further includes: instruction ready control circuit means for generating an output signal to said data processing unit for signalling when instructions are ready to be accessed from said buffer store; and, inhibit control means coupled to said third gating means and to said instruction ready control means, said inhibit control means being conditioned by said third gating means to inhibit said instruction ready control circuit means from generating said output signal when said requested information is being written into said buffer store during said first interval.

28. The cache unit of claim 27 wherein said control circuit means further includes fourth gating means for generating an output signal for indicating when a predetermined type of command from said data processing unit was decoded during said first interval, said fourth gating means being coupled to said first and second gating means, said fourth gating means being operative in response to said predetermined type of command to generate a control signal for conditioning said address switch selection means to select an address from said instruction address register for loading into said address register during said first interval for accessing an instruction from said levels of said buffer store during said second interval.

29. The cache unit of claim 20 wherein each of said commands includes a command code and an address and wherein each level of said buffer store contains a number of blocks of said word locations, each level and each block being defined by a level address and a block address respectively and said cache unit further including: a directory having a plurality of locations corresponding in number to the number of levels in said buffer store and being addressable by said level addresses, each location of said directory storing block addresses of blocks of words within the associated level stored in said buffer store, said directory responsive to said level address corresponding to a low order portion of said command address to read out said block addresses corresponding to a high order portion of said command address;
comparison means coupled to said directory for comparing said block addresses read out from said directory with the high order portion of said command address and generating hit detection signals indicative of whether or not the information being accessed is stored in said buffer store; and, directory level control means coupled to said split cycle timing means to said comparison means and to said buffer store, said directory level control means in response to said hit detection signals being operative to generate a set of hit level signals during said second interval of a next cache cycle for enabling the transfer of a requested operand word to said data processing unit specified by each command having a command code specifying a read type operation in accordance with the results of a directory search operation performed during the previous cache cycle without inter-fering with transferring instruction words requested by said data processing unit.

30. A cache system for use with a data processing unit for providing fast access to instructions and data fetched from a main store coupled to said cache unit by a number of address sources in response to commands received from said data processing unit, said cache system comprising: a cache store including a plurality of addressable word locations organized into a plurality of levels for storing said data and instructions, said levels being arranged vertically for accessing information on a word basis; a multiposition address switch having a number of sets of input terminals for receiving a corresponding number of sets of address signals from said number of address sources, a plurality of output terminals and a plurality of control input terminals;
an address register coupled to said plurality of output terminals and to said cache store, said address register for storing the address specifying the location within said levels whose contents are to be accessed during a cache cycle of operation; control circuit means coupled to said multiposition address switch input control terminals for generating coded control signals identifying which one of said number of address sources is connected to supply said address to said output terminals; and, split cycle timing means for generating timing signals for defining first and second halves of said cache cycle of operation, said timing means being coupled to said control means, said control means being conditioned by said timing means during said first half to enable said address switch to select an address for loading into said address register applied to a first one of said sets of input terminals by a first one of said address sources for enabling access of data during said second half of said cache cycle and said control means being conditioned during said second half to enable said address switch to select an address for loading into said address register applied to a second one of said sets of input terminals by a second one of said address sources for enabl-ing the accessing of instructions during said first half of said cache cycle without interference.

31. The cache system of claim 30 wherein said split cycle timing means includes means for distributing to different sections of said cache system first and second sets of clock pulses having a 180° phase relationship for defining said first and second halves of said cache cycle.

32. The cache system of claim 30 wherein control circuit means includes: first gating means coupled to receive a first timing signal from said timing means and said gating means being operative to generate an output signal for enabling the loading of address information into said address register during said first half of said cache cycle for accessing information from said levels of said cache store during said second half of said cache cycle; second gating means coupled to receive a second timing signal from said timing means, said second gating means being operative to generate an output signal for enabling the loading of address information into said address register during said second interval for enabling access to information stored in said levels of said cache store during said first half of said cache cycle;

and, said address switch input control terminals being connected to said first and second gating means, said address switch being conditioned by said coded signals for enabling said address switch to load said address register with said addresses from said first and second address sources during said first and second halves of said same cache cycle of operation.

33. The cache system of claim 32 wherein each of said commands includes a command code and an address and said another one of said address sources includes: an input circuit means coupled to said processing unit for receiving said address of each said command and said input circuit means being connected to said first one of said sets of input terminals of said address switch, said input circuit means being operative to apply said command address specifying a word location within each of said levels of said cache store from which an operand word is to be fetched or into which an operand word is to be written during said second half of said cache cycle.

34. The cache system of claim 33 wherein said one of said address sources includes: an instruction address register coupled to said second one of said sets of input terminals of said address switch, said instruction address register including a number of bit positions, a group of said bit positions for storing an address specifying a next word location within said levels of said cache store from which an instruction word is to be accessed during said first half of said cache cycle.

35. The cache system of claim 34 wherein further one of said number of address sources includes: a buffer for storing at least one address derived from a command which has a command code specifying a read type operation, said address specifying the word location within said cache store into which the information requested from said main store by said command is to be written;
and, means coupled to said buffer and to said address switch, said means for applying said address to a further one of said sets of input terminals of said address switch for loading into said address register enabling the writing of said information into said cache store during said first half of said cache cycle.

36. The cache system of claim 35 wherein said control circuit means further includes third gating means for generating memory write enable signals enabling said requested information to be written into said cache store during said first half of said cache cycle, said third gating means being connected to condition said first and second gating means for generating said coded control signals to cause said address switch to switch from a first position to a second position for selecting said address from said buffer in place of said address from said instruction address register for loading into said address register.

37. The cache system of claim 36 wherein said system further includes: instruction ready control circuit means for generating an output signal to said data processing unit for signalling when instructions are ready to be accessed from said cache store; and, inhibit control means coupled to said third gating means and to said instruction ready control means, said inhibit control means being conditioned by said third gating means to inhibit said instruction ready control circuit means from generating said output signal when said requested information is being written into said cache store during said first half of said cache cycle.

38. The cache system of claim 37 wherein said control means further includes fourth gating means for generating an output signal for indicating when a predetermined type of command from said data processing unit was decoded during said first half of said cache cycle, said fourth gating means being coupled to said first and second gating means, said fourth gating means being operative in response to said predetermined type of command to generate a control signal for conditioning said address switch to select an address from said instruction address register for loading into said address register during said first half for accessing an instruction from said levels of said cache store during said second half of said cache cycle.

39. The cache system of claim 30 wherein each of said commands includes a command code and an address and wherein each level of said cache store contains a number of blocks of said word locations, each level and each block being defined by a level address and a block address respectively and said cache system further including: a directory having a plurality of locations corresponding in number to the number of levels in said buffer store and being addressable by said level addresses, each location of said directory storing block addresses of blocks of words within the associated level stored in said cache store, said directory responsive to said level address corresponding to a low order portion of said command address to read out said block addresses corresponding to a high order portion of said command address; comparison means coupled to said directory for comparing said block addresses read out from said directory with the high order portion of said command address and generating hit detection signals indicative of whether or not the information being accessed is stored in said cache store; and, directory level control means coupled to said split cycle timing means to said comparison means and to said cache store, said directory level control means in response to said hit detection signals being operative to generate a set of hit level signals during said second half of a next cache cycle for enabling the transfer of a requested operand word to said data processing unit specified by each command having a command code specifying a read type operation in accordance with the results of a directory search operation performed during the previous cache cycle without inter-fering with transferring instruction words requested by said data processing unit.