GB2068640A

GB2068640A - Wiring layers for semiconductor devices

Info

Publication number: GB2068640A
Application number: GB8102607A
Authority: GB
Original assignee: Nippon Electric Co Ltd
Current assignee: NEC Corp
Priority date: 1980-01-28
Filing date: 1981-01-28
Publication date: 1981-08-12
Also published as: JPS56105660A; GB2068640B

Abstract

In a semiconductor device wherein a semiconductor substrate 2 is bonded to a metal layer 19 at the bottom of a recess in a ceramic package 1 and includes a substrate biasing circuit, a first wiring layer 7, 10%, of silicon containing aluminum, or polycrystalline silicon, is connected directly to a source 3 or drain 3 of an insulated gate field effect transistor in the biasing circuit and extends on to a field insulating film 5 on the substrate surface, and a second wiring layer 11 of pure aluminium contacts the first wiring layer on the insulating film and is directly connected to a connecting section of a scribe line region 21 of the substrate. This pure aluminium wiring layer makes a more stable contact with the substrate than the materials used for the first wiring layer. <IMAGE>

Description

SPECIFICATION Improvements in or relating to semiconductor devices The present invention relates to semiconductor devices.

In recent years, progress in realising high density and high speed in semiconductor integrated circuit devices, especially in insulated gate field effect type integrated circuit devices, has been remarkable.

Accordingly, the performance required for the device itself on the production line is such that there are small deviations from desired values. Consequently, control of all the steps of diffusion, assembly and inspection has become an important problem.

One of the factors which governs the performance of these devices is known to be the threshold voltages of several kinds of MOS transistors forming the integrated circuit device, the performance largely depending upon the fluctuations of these voltages.

The threshold voltage of an MOS transistor is determined by various production factors, such as the thickness of a gate insulating film, the impurity concentration of the semiconductor substrate, the boundary surface level, etc., which are severally controlled in the manufacturing steps carried out on a wafer.

However, besides these factors, there are factors caused in the assembling step which influence the potential difference between the semiconductor substrate and the source region in the MOS transistor, and as a result cause the threshold voltage to be varied. The relation between the threshold voltage and the source-substrate potential difference is represented by the following formula: VT ~ A (Vs + B) - + C where VT is the threshold voltage, Vs is the potential difference between a substrate and a source region, and A, B and C are constants.Accordingly, even if control is effected over the various factors in the diffusion process for making an MOS integrated circuit device, so as to realize in the wafer state a desired threshold voltage determined by the circuit design, a desired circuit performance cannot be obtained if the substrate potential does not assume a desired value due to problems caused by the assembling step.

In an effort to solve these problems, the following two different methods have been employed. One is the method of providing an electrode for biasing a substrate along a scribe line. The other is the method of improving the electrical contact between the back surface of the semiconductor substrate and a package by mounting an integrated circuit chip on the package and thereby biasing the substrate of the chip from the side of the package via the back surface of the substrate. In practice, these methods are generally employed in combination.

In the second method, applying a bias potential from the back surface of the substrate, a bonding pad is provided on a substrate biasing wiring layer and is connected to a substrate bias generator circuit. The pad is connected to the package through a bonding wire and thereby the integrated circuit substrate mounted on the package is biased from its back surface. However, when using the second method, a stable substrate potential cannot be attained so readily. As a cause of the instability it has been proved that the eutectic state with Si largely depends upon the soldering material and the temperature employed in mounting the integrated circuit chip (substrate) on the package, and that there exists an instability in mass-production such that the contact resistance of the mount fluctuates widely from about 100 ohm to about 10 kohm.

On the other hand, in the first prior art method, in which a substrate biasing wiring layer connected to a substrate bias generator circuit is directly connected to a portion of the semiconductor substrate such as the scribe line region, sufficient bias potential cannot be applied through a surface of a semiconductor substrate. This is because, in the process developed in accordance with miniaturization of such devices as silicon-gate MOS integrated circuits, a silicon-containing aluminum metallic wiring, etc. has become an obstacle from the view point of ohmic connection.Namely, in the abovedescribed prior art method, the wiring layer to be connected to the source and drain region of an insulated gate field effect transistor in the substrate bias generator circuit has to be a silicon-containing aluminum layerforthe purpose of preventing shorting of the PN-junctions in the source and drain regions that may be caused by miniaturization of the device. However, with the prior art technique of directly connecting a wiring layer of such material to a mono-crystalline silicon substrate of one conductivity type, the contact resistance amounts to 100 to 500 ohm for a contact area of 5 Am x 1000 Rm.

It is an object of the present invention to provide an effective semiconductor device in which the above-mentioned shortcomings in the prior art are reduced or eliminated.

According to the present invention, the abovementioned object has been achieved on the basis of the discovery that in view of deviations in massproduction, good electrical properties can be obtained by employing a material that is different from an internal wiring and capable of making ohmic contact only at a biasing contact portion of a substrate surface.

According to the present invention, there is provided a semiconductor device comprising a semiconductor substrate of one conductivity type having a substrate bias generator circuit, an impurity region of the opposite conductivity type in said substrate bias generator circuit provided along a major surface of said semiconductor substrate, a field insulating film provided on said major surface of said semiconductor substrate, a first wiring layer made of siliconcontaining aluminum or polycrystalline silicon, connected directly to said impurity region of the opposite conductivity type and extending over said field insulating film, and a second wiring layer made of pure aluminum, contacted with said first wiring layer on said failed insulating film and connected directly to a region of said one conductivity type in said semiconductor substrate.The semiconductor device may further comprises a bonding pad provided on said second wiring layer at the contacting section between said first and second wiring layers, a package for mounting said semiconductor substrate therein, a conductor chip provided on said package, and a bonding wire for connecting said conductor chip to said bonding pad.

According to the present invention, there is also provided a semiconductor device comprising a semiconductor substrate of one conductivity type, said semiconductor substrate including a main area and a scribe line region surrounding said main area; a plurality of circuit elements provided in said main area and along a major surface of said semiconductor substrate; a field insulating film provided in said main area and on said major surface of said semiconductor substrate, said field insulating film surrounding substantially each of said circuit elements; an impurity region of the opposite conductivity type of one of said circuit elements provided in said main area and along said major surface; a first wiring layer made of silicon - containing aluminum or polycrystalline silicon connected directly to said impurity region of said opposite conductivity type and extending over said field insulating film; a second wiring layer made of pure aluminum, contacted with said first wiring layer on said field insulating film and connected directly to a connecting section in said semiconductor substrate.

The connection region is favorably positioned in the scribe line region, and the second wiring layer favorably surrounds the main area with the scribe line region.

According to the present invention, there is also provided a semiconductor device comprising a ceramic package having a recess portion and a high wall portion located along the periphery of said recess portion; a semiconductor substrate of one conductivity type having an impurity region of the opposite conductivity type formed along one major surface of said semiconductor substrate, said semiconductor substrate being bonded to a part of said recess portion via a metallized layer formed on the surface of said recess portion at its another major surface; a field insulating film provided on said one major surface, a first wiring layer made of siliconcontaining aluminum or polycrystalline silicon, connected directly to said impurity region and extending over said field insulating film; a second wiring layer made of pure aluminum, contacted with said first wiring layer on said field insulating film and connected directly to a connecting section of said semiconductor substrate, said second wiring layer having a bonding pad at the contacting section between said first and second wiring layers on said field insulating film; a conductor chip bonded to said recess portion via said metallized layer between said semiconductor substrate and said high wall portion; and a bonding wire for connecting said conductor chip to said bonding pad.

The invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure l is a plan view of a semiconductor device constructed according to a prior art technique; Figure 2 is a cross-section of a part of the device shown in Figure 1,drawn to an enlarged scale; Figure 3 is a plan view of a semiconductor device according to the present invention; Figure 4 is a cross-section of a part of the device shown in Figure 3, drawn to an enlarged scale; and Figure 5 is a cross-section of another device according to the present invention.

Figures 1 and 2 show semiconductor devices constructed according to the prior art technique, in which a semiconductor substrate (semiconductor chip) 2 having a plurality of circuits (not shown) each constructed of a large number of elements such as field effect transistors is soldered via a metallized layer 19 onto a surface 25 of a recess portion in a ceramic package 1. A plurality of bonding pads 22 connected to the respective circuits are in turn connected via bonding wires 24 to a plurality of external lead layers 23, respectively, provided on a high wall portion 26 located along the periphery of the recess portion of the ceramic package 1. Among the plurality of circuits, one is a substrate bias generator circuit 20, which is formed of a plurality of insulated gate field effect transistors.

According to the prior art technique illustrated in Figures 1 and 2, a silicon-containing aluminum wiring layer 10 connected to the source or drain regions 3 of the transistors in the substrate bias generator circuit 20 is directly in turn connected to an electrode provided on a connecting section 15 in a scribe line region 21. A method of employing a small chip 17 for substrate bias bonding and connecting a bonding pad 14 provided on a wiring layer 10 to this small chip 17 via a bonding wire 16, is also used in combination. However, since this method is a method of biasing a substrate through its back surface, a contact resistance would fluctuate largely depending upon a mounting condition of the substrate, and hence the substrate bias potential is not stable.On the other hand, in the former method, which a silicon-containing aluminum wiring layer 10 is directly connected to a connecting section 15 of a stribe line region 21,the bias potential has large deviation. Explaining this prior art technique in greater detail, N±type source and drain regions 3,3 of a transistor forming a substrate bias generator circuit 20, are provided in a P-type semiconductor substrate 2. On a channel region between the source and drain regions 3, 3 is provided a gate polycrystalline silicon electrode 6 via a gate insulating film, and to this electrode is connected an internal wiring metallic electrode 7. Between a scribe line region 21 and the source or drain region 3 is provided a thick field insulating film 5, and under this field insulating film 5 is provided a P±channel stopper region 4. In an integrated circuit chip manufactured so as to have a high density and to operate at a high speed, the source or drain region 3 formed in the surface of the device is a shallow diffused impurity region of about 0.5 Rm in thickness. Accordingly, for the purpose of preventing shorting at the connecting portion between the diffused region 3 and the metallic wiring caused by an alloying reaction between silicon and metal, either a silicon-containing aluminum layer or a multi-layer structure consisting of polycrystalline silicon and aluminum is employed for the wiring metallic electrode. As one method for biasing the substrate, a silicon-containing aluminum metal wiring 10 connected to a substrate bias generator circuit, is connected to directly the P-type semiconductor substrate 2 at a connecting section 15 in the scribe line region 21.However, the in the abovedescribed structure in which a silicon-containing aluminum layer or a polycrystalline silicon layer is connected to a P-type semiconductor substrate region, the contact resistance at this connecting section would largely fluctuate over 100 to 500 ohm for a contact area of 5 lim x 1000 Rm. In the structure shown in Figure 2, similarly to that shown in Figure 1 the back surface of the substrate is biased from the side of the package 1 via a thin bonding wire 16 which extends from a bonding pad 14 of the wiring layer 10 through an aperture formed in a device protective insulator layer 13.It is to be noted here that the thin bonding wire is scarecely connected to the package directly in view of the problems of mechanical strength and assembly, but generally the connection is often made via a small metallic chip 17.

Preferred embodiment 1: In a first preferred embodiment of the present invention illustrated in Figures 3 and 4, a plurality of circuits 32, 20 each constructed of a large number of circuit elements such as field effect transistors are formed in a main area 31 of the P-type semiconductor substrate 2 of 3.5 mm x 5.5 mm area. The main area 31 is encircled with a scribe line region 21 of the substrate 2. Each circuit element is substantially surrounded by a thick field insulating layer 5 in the main area. An aluminum containing a few percent of silicon is used for the internal metallic wirings 7 and 10' of the fieid effect transistor of a substrate bias generator circuit 20.The silicon-containing aluminum wiring layer 10' is connected directly to the source or drain region of the opposite conductivity type (N±type) of the field effect transistor of the substrate bias generator circuit 20 and extends on the field insulating film 5. A pure aluminum wiring layer 11 contacts with the silicon-containing aluminum wiring layer 10' on the field insulating film 5 and is connected directly to a P-type semiconductor substrate at a connecting section 35 in the scribe line region 21. The connecting section 35 that is the pure aluminum wiring layer 11 of 5 lim width surrounds the main area 31 of the substrate with the scribe region 21.Since pure aluminum makes contact with a a monocrystalline silicon semiconductor substrate as described above, the contact resistance takes a value lower than 10 ohm such as, for instance, about 5 ohm for a contact area of 5 ym x 1000 um, and thereby stable ohmic contact can be obtained. It is to be noded that in Figures 3 and 4 component parts having the same functions as those shown in Figures 1 and 2 are given like reference numerals. In the above-described structure according to the present invention, it becomes possible to stably apply a substrate bias potential from a substrate bias generator circuit to a substrate.

In one manufacturing process of the semiconductor device according to the first preferred embodiment, at first silicon-containing aluminum is deposited as by sputtering for use as an internal wiring metal, a region of the silicon-containing aluminum layer where ohmic connection is required is etched, thereafter pure aluminum is deposited on the etched region, and thereby patterning of the entire wiring is carried out. However, the above-described manufacturing process is no more than one example, but many other processes can be conceived, and it is only necessary that eventually the structure shown in Figures 3 and 4 is obtained.

In addition, another method of biasing the substrate could be employed in combination, in which a bonding pad 34 is provided at the aperture of the passivation film 13 such as C.V.D. silicon oxide film on the pure aluminum wiring layer 11 above the field insulating film 5, and this bonding pad 34 is connected to a small conductor chip 17 formed on a surface 25 of the recess portion of the ceramic package 1 via a metalized layer 19 for substrate bias bonding via a bonding thin wire 16 to apply a substrate bias to the back surface of the substrate 2.

Still further, a method of applying a substrate bias to the substrate via a metallized layer 19, and through another small chip 17', another bonding thin wire 16' and another bounding pad 34' provided on the substrate, could be employed in combination.

Preferred embodiment2: Another preferred embodiment of the present invention is illustrated in Figure 5. It isto be noted that in Figure 5 component parts having the same functions as those shown in Figures 1 to 4 are given like reference numerals. In this preferred embodiment, a double-layer structure consisting of a polycrystalline silicon layer 9 and a pure aluminum layer 8 or of a silicon-containing aluminum layer 9 and a pure aluminum layer 8, is employed for the internal metallic wiring, and in the internal metallic wiring extending from a substrate bias generator circuit 20 a double-layer structure of a pure aluminum layer 11 and a polycrystalline silicon or silicon-containing aluminum layer 12 is employed.But, at least a connecting section 35 with the semiconductor substrate is entirely composed of a single layer of pure aluminum 11, and thereby good ohmic connection with the substrate can be obtained.

The characteristic advantage of the abovedescribed structures of the semiconductor device according to the present invention is that since pure aluminum used for internal wiring is also used for ohmic connection with the substrate, the manufacturing process is simple and thus mass-productivity is excellent. Thus, according to the present invention, semiconductor devices having stable character- istics which are little affected by fluctuations upon assembly, can be obtained, and hence it has become possible to realize a high reliability. Moreover, it has become possible to mount a semiconductor chip even in a package of the type in which a mount surface has a floating structure such as a cerdip package, and hence cheap products having good productivity can be obtained.

Claims

1. A semiconductor device comprising a semiconductor substrate of one conductivity type having a substrate bias generator circuit, an impurity region of the opposite conductivity type in said substrate bias generator circuit provided along a major surface of said semiconductor substrate, a field insulating film provided on said major surface of said semiconductor substrate, a first wiring layer made of siliconcontaining aluminum or polycrystalline silicon, connected directly to said impurity region of the opposite conductivity type and extending over said field insulating film, and a second wiring layer made of pure aluminum, contacted with said first wiring layer on said field insulating film and connected directly to a region of said one conductivity type in said semiconductor substrate.

2. A semiconductor device of Claim 1, further comprising a bonding pad provided on said second wiring layer at the contacting section between said first and second wiring layers, a package for mounting said semiconductor substrate therein, a conductor chip provided on said package, and a bonding wire for connecting said conductor chip to said bonding pad.

3. A semiconductor device of Claim 1, in which said impurity region of the opposite conductivity type is one of source and drain regions of an insulated gate field effect transistor in said substrate bias generator circuit.

4. A semiconductor device comprising a semiconductor substrate of one conductivity type, said semiconductor substrate including a main area and a scribe line region surrounding said main area; a plurality of circuit elements provided in said main area and along a major surface of said semiconductor substrate; a field insulating film provided in said main area and on said major surface of said semiconductor substrate, said field insulating film surrounding substantially each of said circuit elements; an impurity region of the opposite conductiv ity type of one of said circuit elements provided in said main area and along said major surface; a first wiring layer made of silicon - containing aluminum or polycrystalline silicon connected directly to said impurity region of said opposite conductivity type and extending over said field insulating film; a second wiring layer made of pure aluminum, contacted with said first wiring layer on said field insulating film and connected directly to a connecting section in said semiconductor substrate.

5. A semiconductor device of Claim 4, in which said connecting section is positioned in said scribe line region.

6. A semiconductor device of Claim 4, in which said second wiring layer of pure aluminum surrounds said main area with said scribe line region.

7. A semiconductor device comprising a ceramic package having a recess portion and a high wall portion located along the periphery of said recess portion; a semiconductor substrate of one conduc tivitytype having an impurity region of the opposite conductivity type formed along one major surface of said semiconductor substrate, said semiconductor -substrate being bonded to a part of said recess portion via a metallized layer formed on the surface of said recess portion at its another major surface; a field insulating film provided on said one major surface; a first wiring layer made of siliconcontaining aluminum or polycrystalline silicon, connected directly to said impurity region and extending over said field insulating film; a second wiring layer made of pure aluminum, contacted with said first wiring layer on said field insulating film and connected directly to a connecting section of said semiconductor substrate, said second wiring layer having a bonding pad at the contacting section between said first and second wiring layers on said field insulating film; a conductor chip bonded to saiâ recess portion via said metallized layer between said semiconductor substrate and said high wall portion; and a bonding wire for connecting said conductor chip to said bonding pad.

8. A semiconductor device constructed, arranged and adapted to operate substantially as hereinbefore described with reference to, and as illustrated in, Figures 3 to 5 of the accompanying drawings.