GB2040633A - Electrical Oscillator Circuit - Google Patents

Abstract

An oscillating device suitable for an electronic timepiece and comprising two pairs of IGFETS (insulated gate field effect transistors) 13, 14 and 31, 34 which respectively form a primary and an auxiliary inverter. The gates of all the IGFETS are connected, via feedback circuitry including a quartz crystal, to the output of the primary inverter so as to cause oscillation. The auxiliary inverter is brought into operation in response to a large increase in load, or for starting up, by applying a suitable control voltage to a third pair of IGFETS 32, 33 which are arranged between those of the auxiliary inverter so as to control the current flow through them. <IMAGE>

Description

SPECIFICATION Electrical Oscillator Circuit This invention relates to oscillating devices having complementary field effect transistor inverters and feedback circuits, and more particularly to an improvement in reducing power dissipation and attaining stable oscillation under relatively wide voltage range of the power source in such oscillating devices.

In some uses of a quartz crystal oscillator, such as a wristwatch, it is required to minimise the electric power dissipation to elongate the actual life of the power source such as, for example, a silver oxide battery. It is also required, however, to obtain the stable oscillation in spite of the source voltage change due to the increase or decrease of the current dissipation from the battery under the gradual voltage decrease depending on the output voltage characteristics of the battery.

As is well-known in the art, in order to start up the oscillation a higher amplification factor is required and, accordingly, a higher mutual conductance, in the inverter than that required during a time thereafter in which oscillation continues. In the prior art, oscillating devices were designed to have amplification factors of constant value during the starting up period as well as during continuing oscillation. Accordingly, under continuing oscillating operation more electric current is used than that required to continue stable oscillation, because the higher the amplification factor, the more the current usage. Hence, there have been devised oscillating devices each having an auxiliary inverter which is connected, in parallel, to the primary inverter only during starting up of oscillation. A switching field effect transistor connects and disconnects one current-carrying terminal of the auxiliary inverter to the corresponding terminal of the primary inverter, and another switching field effect transistor connects and disconnects the other current-carrying terminal of the auxiliary inverter to the corresponding terminal of the primary inverter. Thus, the amplification factor, as a whole, can be increased only when both switching transistors are in the conductive state. This is disclosed in Japanese patent application laid open to the public inspection on 12th January, 1978 as 31 53/78. This development solved the basic problem but it has been found that the operating condition of the auxiliary inverter in this circuit is adversely affected by the insertion of the switching transistors, as easily understood from the following description. To avoid this drawback, more troublesome steps were required in the design and manufacture of the relevant integrated circuits.

As is known in the art, the mutual conductance of an inverter depends on the voltage supplied to the inverter. If the circuit design is made so as to achieve stable oscillation when the output voltage of the battery is dissipated to a certain low value, more current fiows than required for stable oscillation when the output voltage of the battery is still relatively high. This excess current shortens the life of the battery. If the circuit is designed to supply relatively small excess current, relatively high supply voltage is required to obtain stable operation, thus the useful life of the battery is shortened, especially when considering its output characteristics in conjunction with occasional voltage drop due to temporary energisation of a relatively large load such as, for example, sounding an alarm. On the other hand, if the circuit is designed to supply relatively large excess current, the excess current directly consumes energy of the battery. It has been necessary, therefore, to continue to search for oscillating devices capable of achieving stable operation under voltage changes of relatively wide ranges in the D.C.

source.

The present invention seeks to provide a semiconductor oscillating device which is capable of saving current dissipation and yet simple in design and manufacture.

The present invention also seeks to provide an oscillating device capable of performing stable oscillation under relatively wide voltage changes in the power source.

According to one aspect of the present invention, there is provided an oscillator including a first pair of insulated gate field effect transistors having channels of opposite conductive types, the channels being connected in series between a pair of power supply rails; a second pair of insulated gate field effect transistors also having channels of opposite conductive types and being connected in series with one another and in parallel with the first pair; the gates of all said transistors being connected together and being connected by feedback means to the junction of said first pair of transistors so as to cause a predetermined oscillation, and control means being connected between the said second pair of transistors so as to control the interaction of the said second pair of transistors with the said first pair of transistors.

According to a further aspect of the present invention, there is provided a first and a second voltage terminal adapted to be connected with a D.C. voltage supply of relatively small capacity; a first insulated gate field effect transistor having a channel of a first conductive type and connected between the first voltage terminal and an output terminal; a second insulated gate field effect transistor having a channel of a second conductive type opposite to the first conductive type and connected between the second voltage terminal and the output terminal, the first and second transistors being connected to form a primary inverter; third and fourth insulating gate field effect transistors having channels of first and second conductive types, respectively, the third and fourth transistors being connected for forming an auxiliary inverter; fifth and sixth insulated gate field effect transistors having channels of the first and second conductive types, respectively; the first terminal, the third transistor, the fifth transistor, the sixth transistor, the fourth transistor and the second terminal being connected in series along this order, and a node between the fifth and sixth transistors being connected to said output terminal; positive feedback means connected between the output terminal and a point connected commonly to gate electrodes of said first, second, third and fourth transistors for causing a predetermined oscillation; and means for controlling current flow through the fifth and sixth transistors to vary the interaction of the auxiliary inverter with the primary inverter.

One embodiment of the invention will now be described by way of example with reference to the accompanying drawings, in which Figure 1 is a circuit, partly in block diagrammatic form, of an oscillating device according to this invention, and Figure 2 is a block diagram of a watch in which the oscillating device shown in Figure 1 can be used.

A quartz crystal oscillating circuit, as known in the art, is included in Figure 1. In this circuit, an insulated gate field effect transistor (hereinafter referred to as an IGFET) 13 of the P-channel type is connected in series with an N-channel IGFET 1 4 between a plus or VDo terminal 11 and a minus or earth terminal 12 to form a primary inverter 1 5. The quartz crystal oscillating circuit also includes a feedback resistor in parallel with a series combination of a quartz crystal element 1 9 and a stabilisation resistor 20 connected between the gates of the IGFETS 13, 14 at a node 1 6 and the drains of the IGFETS at a node 1 7. The node 16 has an input 1 and the node 17 has an output 0. The known quartz crystal oscillating circuit is completed by two capacitors 21, 22 connected in series between the node 1 6 and a point between the resistor 20 and the quartz crystal 1 9 for adjusting the oscillation frequency and for stabilising the continuing oscillation.

Electric power is supplied from a small battery 23 which also energises a continuous load 24 comprising a frequency divider, a display device and the like. The battery 23 occasionally energises a relatively large load 25 such as an alarm sound device, a lamp and the like when a switch 26 is closed, whereby the output voltage (i.e. VDD) of the battery 23 decreases due to an internal resistance of the battery 23. For example, the wristwatch battery of one kind having standard voltage of 1.55 volts decreases its output voltage to be of about 1.2 volt when sounding the alarm or lighting the lamp.

Current dissipation of the crystal oscillator formed by the primary inverter 1 5 depends on the charging and discharging current of the series circuit of the IGFETS 1 3 and 14. The charging and discharging current of the capacitors 21 and 22 depends on so many factors that it is difficult to estimate such current. The most simple and useful way to estimate the current dissipation is to calculate the short current which means the current flowing through the IGFETS 1 3 and 14 under transient condition during which both of the IGFETS 1 3 and 14 are in the conductive state. Similarly the easiest way to consider the oscillating operation may be to focus on the mutual or transfer conductance Gm. This transfer conductance means the sum of the transfer conductances Gm of IGFETS 13 and 14. Assume now, respective threshold voltages of IGFETS 13 and 14 are VTHP and VTHN, and the conductance coefficients of the IGFETS 1 3 and 1 4 take the same value K. Then the short current SHORT and the mutual conductance Gm can be calculated from: sHoRT=1/4 K (VDD (IVTHPI+VTHN)} (1) Gm=2 K {VDD(IVTHPI+VTHN)} (2) wherein VDD is the source voltage.

Assume that the IGFETS 13 and 14 are designed such that the K takes relatively large value K1, enough to obtain relatively large Gm in order to be capable of oscillating under relatively low voltage, such as 1.2 volt, of the VDD. Since the output voltage of one typical battery changes from 1.55 volt (standard output voltage) to 1.2 volt during energisation of the large load 25, as already described, it is necessary to design the device to operate stably under the possible lowest voltage supply. This means, however, that such a device consumes larger excess current dissipation when relatively high voltage, such as 1.55 volt, is applied to it. It is noted that the 1SHORT is proportional to the second power of the {VDD(IVTHPI +VTHN) } According to this embodiment, two insulated gate field effect transistors (IGFETS) of P-channel type 31 and 32, and two IGFETS of N-channel type 33 and 34 are added to the quartz crystal oscillating circuit. The IGFETS 31 and 34, which have higher transfer conductances than that of the IGFETS 13 and 1 4, are arranged such that each gate thereof is commonly connected to node 16 of the gates of the IGFETS 1 3 and 14, and that each source thereof is connected to the respective source of the IGFETS 13 and 14 as shown. Arranged between the drains of the IGFETS 31 and 34 are the IGFETS 32 and 33 of relatively high transfer conductance to operate as switching circuit whereby overriding means are provided. The drains of IGFETS 32 and 33 are connected to the common connection node 17 of the drains of the IGFETS 13 and 14. The gates of the IGFETS 32 and 33 are subject to control signals A and B, generation of which are hereinafter set forth.

In operation, briefly speaking, an auxiliary inverter formed by the IGFETS 31 and 34 is connected in parallel with the primary inverter 1 5 formed by the IGFETS 1 3 and 14 when the switching IGFETS 32 and 33 are conductive state. Under this parallel operation of these two inverters, total current supplied from the battery 23 is the sum of the short current of the primary inverter 1 5 and of the auxiliary inverter formed by the IGFETS 31 and 34. This means that the virtual transfer conductance Gm becomes large when the IGFETS 32 and 33 are conductive. As is known in the art, IGFETS 32 and 33 become conductive when low and high level signals are applied to the gates A and B thereof, respectively, and non-conductive when high and low level signals are applied to the gates A and B, respectively.

In the conductive state of both IGFETS 32 and 33, there are, of course, slight voltage drops along source-drain paths of IGFETS 32 and 33. These voltage drops should be taken into account when transfer conductances of IGFETS 31 and 34 are selected during the system design. The transfer conductance of the IGFETS depends on the pattern of the integrated circuit design, for example, the larger the channel width, the larger the transfer conductance. This requirement can be easily solved.

It is noted that the threshold voltages IVTHPI and VTHN of the IGFETS 31 and 34, respectively, are not adversely affected by insertion of the IGFETS 32 and 33. This means that oscillating operation by the auxiliary inverter of the IGFETS 31 and 34 can be obtained without any adverse effect on the switching IGFETS 32 and 33. On the other hand, the threshold voltages IVTHPI and VTHN of the IGFETS 32 and 33, respectively, are adversely affected by the voltage drops along the source-drain paths of the IGFETS 31 and 34.

In more detail, the IGFETS 31 and 32 are formed on a common substrate which must have the same potential with VDD. There is a voltage drop VDRop in the IGFET 31 if it is conductive, hence a source of the IGFET 32 takes a potential of VDDVDROP. This means, the source of the IGFET 32 is biased negatively by DROP. Accordingly, the mutual conductance of the IGFET 32 in this particular circuit is virtually reduced. As for the IGFET 33, generally, the P-well or P-tab potential thereof is the same with the ground potential as known in the art. Thus, virtual reducing of mutual conductance similarly occurs. While it is possible to give a separate potential to the P-well for the IGFET 33 from the ground potential, this, however, requires more complicated pattern in the integrated circuits. Thus, it is preferable to make the IGFETS 33 and 34 on the same P-well diffused on the N-substrate which also contains the IGFETS 31 and 32.

It is also possible to compensate this adverse effect by changing the threshold voltages of the IGFETS 31 and 34 themselves; this changing of the threshold voltages, however, requires complications in manufacturing. Because the threshold voltage depends on the process in making the IGFETS, it is preferable to give the IGFETS 32 and 33 well-shaped control signals A and B.

In the prior devices disclosed in Japanese patent application laid open to public inspection as the number 3153/78, already mentioned, the IGFETS 32 and 33 are used to form an auxiliary inverter while the IGFETS 31 and 34 are used as switching transistors, hence the prior devices are subject to the drawbacks mentioned above.

On the contrary, according to this embodiment, the IGFETS 31 and 34 are used for making the auxiliary inverter, and the IGFETS 32 and 33 are used for switching, thus the above drawbacks are effectively avoided.

Assume now that the mutual conductance coefficients of the IGFETS 13 and 14 take the same value K1 (already described), that the mutual conductance coefficients of the switching IGFETS 32 and 33 are very large with respect to that of the IGFETS 31 and 34, and that the mutual conductance coefficients of the IGFETS 31 and 34 take the same value K2.

The short current I short (OFF) and the mutual conductance Gm (OFF) when the IGFETS 32 and 33 are non-conductive will be shown from the equations (1) and (2): I short (OFF)=1/4 K1 IVDD(IVTHPI+VTHN)} (3) Gm (OFF)=2.K1 VDD(lVTHP +VTHN)I (4) And the short current I short (ON) and the mutual conductance Gm (ON) when the IGFETS 32 and 33 are conductive will be shown from the equation (1) and (2): I short (ON)=1/4 (K1 +K2)VDD(IVThP}+VThN)I2 (5) Gm (ON)=2(K1 +K2){VDD (IVTHPI+VTHN)} (6) Further assume for simplicity that IVTHPI+VTHN=1.0 (volt), than I short (OFF), I short (ON), Gm (OFF) and Gm (ON) in cases when VDO takes 1.55 volt and 1.2 volt can be calculated as follows: V00=1.55[volt] VDD= 1.2 [volt] short (OFF): 0.075 K1 0.01 K1 short (ON): 0.075(K1+K2) 0.01 (Kl+K2) Gm(OFF): 1.1 K1 0.4K1 Gm (ON): 1.1 (K1+K2) 0.4(K1+K2) And then, if it is controlled such that the IGFETS 32 and 33 are non-conductive when VDD is larger than 1.2 volt (including 1.55 volt) and that the IGFETS 32 and 33 are conductive when Voo is not larger than 1.2 volt, the short current ratio P of those when Odd=1.55 (volt) and Odd=1.2 (volt), and the Gm ratio a of those when VDD=1.55 (volt) and Vow=1 .2 (volt) will be: ISHORT(OFF)] VDD=1 .55 0.075K1 7.5K1 = = (7) ISHORT(ONI] VDD=1'2 0.01 (K 1 +K2) K1+K2 Gm(OFF)]VDD=1.55 1.1K1 2.75K1 a= = Gm(ON)jV00=1 .2 0.4(K1 +K2) K1+K2 If we choose the condition a=1 which means that the Gm has the same value at VDD=1.55 [volt] and at Vow=1 .2 [volt], then p will be: 7.5K1 1 = 7.5 2.7 &num;2.7 K1+K2 2.75 This means that current dissipation at V,,=l .55 [volt] will be the value of that at Vow=1 .2 [volt] multiplied by 2.7.

If there is no auxiliary inverter oscillator, however, the short current ratio PA will be: 0.075 K1 APA= .-7.5 0.01 K1 This means that current dissipation at V,,=l .5 (volt) will be the value of that Vow=1 .2 (volt) multiplied by 7.5, if there is no auxiliary inverter.

From this particular calculation, the short current ratio decreases from 7.5 to 2.7 according to this embodiment. This illustrates that current dissipation can be saved largely in this embodiment. It is further understood that K2 is to be preferably larger value than K1.

Referring now to Figure 2, which shows a schematic diagram of a system of a watch for which the oscillating device in Figure 1 may be applied, a numeral 31 indicates the oscillating device. An output signal from the oscillating device 31 is given to a frequency dividing circuit 32. There are also provided a control unit 33 and a display unit 34. The control unit 33 includes a counter, a circuit for changing a count-up value of the counter, a time-setting circuit, a register circuit for holding data corresponding to a real time, a memory circuit for memorising an alarming time, an actuating circuit for sounding a buzzer and the like. The function of the control unit 33 depends on the function required for particular watches.

Referring again to Figure 1, circuits are classified into groups from a different point of view. As already mentioned, numeral 24 indicates the continuous load consuming relatively low electric power, and numeral 25 indicates the temporary load consuming relatively large power. The temporary large load is actuated usually by an actuation signal developed from the continuous small load 24 including control unit 33 shown in Figure 2, and the temporary large load may also manually be actuated. In order to obtain control signals A and B for the switching transistors 32 and 33, there are provided signal-generating units 27 and 28.

Concerning the signal-generating unit 27, a low level signal on a line 41 expressing the actuation of the load 25, which is given by the control unit including in the continuous load 24, causes A signal to be a low level and causes B signal to be a high level through an inverter 42. Thus the switching transistors 32 and 33 become conductive when the temporary large load is actuated so that the auxiliary inverter is connected to the primary inverter in parallel relationship whereby providing mutual conductance enough to obtain stable oscillation even though the D.C. voltage of the battery 23 reduces due for energisation of the large load 25.

Concerning the signal-generating unit 28, if manually operated contacts 43 are closed to actuate the large load 25, the A signal changes from high level to low level by function of a resistance 44 and, in turn, the B signal changes from low level to high level by means of an inverter 45.

Thus, the auxiliary inverter can be connected to the primary inverter automatically when a temporary large load is energised automatically or manually and also when oscillating operation starts up.

Although described above is a certain preferred embodiment, there may be modifications or changes within the scope of the appended claims or within the spirit of the invention. For example, the IGFETS 32 and 33 can be controlled to be variable impedance instead of switching operation. Then the mutual conductance Cm as a whole may take variable value. Further, another auxiliary inverter and overriding means thereof can be provided in parallel relationship with the primary inverter, and it is possible to connect, in stepwise manner, one auxiliary inverter to the primary inverter and then another auxiliary inverter to the primary inverter.

Claims (11)

Claims

1. An oscillating device comprising: first and a second voltage terminal adapted to be connected with a D.C. voltage supply of a relatively small capacity; a first insulated gate field effect transistor having a channel of a first conductive type and connected between the first voltage terminal and an output terminal; a second insulated gate field effect transistor having a channel of a second conductive type opposite to the first conductive type and connected between the second voltage terminal and the output terminal, the first and second transistors being connected to form a primary inverter; third and fourth insulating gate field effect transistors having channels of first and second conductive types, respectively, the third and fourth transistors being connected for forming an auxiliary inverter; fifth and sixth insulated gate field effect transistors having channels of the first and second conductive types, respectively; the first terminal, the third transistor, the fifth transistor, the sixth transistor, the fourth transistor and the second terminal being connected in series along this order, and a node between the fifth and sixth transistors being connected to said output terminal; positive feedback means connected between the output terminal and a point connected commonly to gate electrodes of said first, second, third and fourth transistors for causing a predetermined oscillation; and means for controlling current flow through the fifth and sixth transistors to vary the interaction of the auxiliary inverter with the primary inverter.

2. An oscillating device according to claim 1, wherein said fifth and sixth transistors are variable impedances responsive to said control means.

3. An oscillating device according to claim 1, wherein said fifth and sixth transistors are switching transistors.

4. An oscillating device according to claim 1, 2 or 3, wherein the mutual conductance of said auxiliary inverter is higher than that of said primary inverter.

5. An oscillating device according to any of claims 1 to 4, wherein said control means includes means responsive to current flow through a relatively large load connected across said D.C. voltage supply for actuating said fifth and sixth transistors.

6. An oscillating device according to any preceding claim, wherein said control means includes a manual switch.

7. An oscillating device including a first pair of insulated gate field effect transistors having channels of opposite conductive types, the channels being connected in series between a pair of power supply rails; a second pair of insulated gate field effect transistors also having channels of opposite conductive types and being connected in series with one another and in parallel with the first pair; the gates of all said transistors being connected together and being connected by feedback means to the junction of said first pair of transistors so as to cause a predetermined oscillation, and control means being connected between the said second pair of transistors so as to control the interaction of the said second pair of transistors with the said first pair of transistors.

8. An oscillating device as claimed in claim 7, in which the control means includes a third pair of insulated gate field effect transistors having channels of opposite types and being connected in series.

9. An oscillating device as claimed in claim 7 or claim 8, in which the said first pair of transistors forms a primary inverter and the said second pair of transistors forms a secondary inverter, and the mutual conductance of said auxiliary inverter is higher than that of said primary inverter.

10. An oscillating device as claimed in any one of claims 7 to 9, in which said control means includes switching means.

11. An oscillating device as claimed in any one of claims 7 to 10, in which said control means includes means responsive to the current flow through a relatively large load connected across said power supply rail, so as to actuate said third pair of transistors.

1 2. An oscillating device substantially as herein described with reference to the accompanying drawings. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~